CN115035862A

CN115035862A - Display panel driving method and display device

Info

Publication number: CN115035862A
Application number: CN202210744289.2A
Authority: CN
Inventors: 杨心澜; 王继国; 王世君; 刘屹; 台玉可; 齐胜美; 王洋; 魏旃; 丁腾飞; 梁海瑶; 吕广爽; 陈公达; 彭洲; 张盛丰
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Priority date: 2022-06-27
Filing date: 2022-06-27
Publication date: 2022-09-09

Abstract

According to the driving method of the display panel and the display device provided by the embodiment of the disclosure, the scanning stage and the touch stage are set in one display frame, so that the display panel can realize the function of performing display and touch in a time-sharing manner. In addition, in the next scanning stage after the touch stage is finished, a new register group is controlled to scan the coupled grid lines, so that the problem that in the prior art, scanning is started again after the shift register is paused in the middle of line-by-line scanning, and horizontal stripes are displayed can be avoided. And, this disclosed embodiment is through reserving scan time with other integrated functions, insert between the display scanning stage, avoid the electric leakage problem of long-time display level.

Description

Display panel driving method and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a driving method of a display panel and a display device.

Background

In displays such as Liquid Crystal Displays (LCDs) and Organic Light-Emitting diodes (OLEDs), a plurality of pixel cells are generally included. Each pixel unit may include: a plurality of differently colored sub-pixels. And controlling the corresponding brightness of each sub-pixel so as to mix the colors required to be displayed to display a color image.

Disclosure of Invention

The display panel driving method provided by the embodiment of the present disclosure includes: the display device comprises a plurality of grid lines, a grid driving circuit respectively coupled with the grid lines, and a plurality of frame starting signal lines coupled with the grid driving circuit; the grid driving circuit comprises a plurality of shift registers, wherein the driving output end of one shift register is coupled with one grid line, the shift registers are divided into M register groups, and different register groups are coupled with different frame starting signal lines; m is an integer greater than 1;

the driving method comprises the following steps:

dividing a display frame into M scanning stages and N touch control stages; in the mth scanning stage of the M scanning stages, loading a frame start signal to a frame start signal line coupled to the mth register group of the M register groups, loading different clock signals to the plurality of clock signal lines, controlling a shift register unit in the mth register group to output a gate scanning signal to a coupled gate line, and loading a cut-off control signal to a frame start signal line coupled to the remaining register groups;

setting one touch control stage in the N touch control stages between two adjacent scan stages of the M scan stages, wherein in the touch control stage, a touch control electrode in the display panel is scanned, a cut-off control signal is loaded to each frame starting signal line, and the cut-off control signal is loaded to each clock signal line; n is an integer greater than 0.

In some possible embodiments, one touch stage of the N touch stages is set between every two adjacent scan stages of the M scan stages.

In some possible embodiments, in two adjacent display frames, the two display frames include a first display frame and a second display frame, and a target touch phase is arranged between an mth scanning phase of the first display frame and a1 st scanning phase of the second display frame;

the target touch stage is one of the N touch stages of the second display frame; or, the target touch stage is one of the N touch stages of the first display frame.

In some possible embodiments, the shift registers in each register group are respectively coupled with the grid lines spaced by M-1 rows;

in the mth scanning stage, a frame start signal is loaded to a frame start signal line coupled to the mth register group, different clock signals are loaded to clock signal lines coupled to the mth register group, and the shift registers in the mth register group are controlled to scan the gate lines coupled to the shift registers at M-1 lines at intervals row by row.

In some possible embodiments, the clock signals corresponding to different register sets have the same period and the same timing.

The display device provided by the embodiment of the disclosure comprises:

a display panel, comprising: the display device comprises a plurality of grid lines, a grid driving circuit respectively coupled with the grid lines, and a plurality of frame starting signal lines coupled with the grid driving circuit; the grid driving circuit comprises a plurality of shift registers, wherein one shift register is coupled with one grid line and divides the shift registers into M register groups, and different register groups are coupled with different frame starting signal lines; m is an integer greater than 1;

a timing controller configured to divide one display frame into M scanning stages and N touch stages; in the mth scanning stage of the M scanning stages, loading a frame start signal to a frame start signal line coupled to the mth register group of the M register groups, loading different clock signals to the plurality of clock signal lines, controlling a shift register unit in the mth register group to output a gate scanning signal to a coupled gate line, and loading a cut-off control signal to a frame start signal line coupled to the remaining register groups; loading a cut-off control signal to each frame start signal line and loading the cut-off control signal to each clock signal line at each of the N touch control stages;

a touch driving circuit configured to set one of the N touch stages between two adjacent scan stages of the M scan stages, in which touch electrodes in the display panel are scanned; n is an integer greater than 0.

In some possible embodiments, the shift registers in each register group are respectively coupled to the gate lines spaced by M-1 rows;

the register group comprises at least two cascade groups, the shift registers in the same cascade group are arranged in a cascade mode, and the shift registers in the same cascade group are respectively coupled with grid lines at intervals of multiple rows.

In some possible embodiments, M is 2, each shift register in the first register group is respectively coupled to the gate lines of the odd-numbered rows, and each shift register in the second register group is respectively coupled to the gate lines of the even-numbered rows;

the first register group comprises a first cascade group and a second cascade group, the shift registers in the first cascade group are respectively coupled with the grid lines at intervals of 3 rows, and the shift registers in the second cascade group are respectively coupled with the grid lines at intervals of 3 rows;

the second register group comprises a third cascade group and a fourth cascade group, the shift registers in the third cascade group are respectively coupled with the grid lines at intervals of 3 rows, and the shift registers in the fourth cascade group are respectively coupled with the grid lines at intervals of 3 rows.

In some possible embodiments, the first register group is disposed at a first end of the plurality of gate lines, and the second register group is disposed at a second end of the plurality of gate lines;

or each shift register comprises a left shift register arranged at the first end of the same grid line and a right shift register arranged at the second end, and the left shift register and the right shift register coupled with the same grid line output the grid scanning signals at the same time;

or, the first cascaded set and the third cascaded set are disposed at first ends of the plurality of gate lines, and the second cascaded set and the fourth cascaded set are disposed at second ends of the plurality of gate lines;

or, the first register group and the second register group are both located at the same end of the plurality of gate lines.

In some possible embodiments, the display panel further includes: and different register groups are coupled with the same clock signal line.

In some possible embodiments, two adjacent gate lines are taken as a gate line group, and the shift registers corresponding to the same gate line group are coupled to the same clock signal line.

In some possible embodiments, the shift register includes: an output transistor and a clock selection circuit;

a gate of the output transistor is coupled to a first node, a second pole of the output transistor is coupled to the driving output, and a first pole of the output transistor is coupled to the clock selection circuit;

the clock selection circuit is configured to turn on a first pole of the output transistor with a clock signal terminal coupled to a corresponding clock signal line in response to a signal of a selection signal terminal.

In some possible embodiments, the display panel further includes a plurality of selection signal lines;

the selection signal end of each shift register in the same register group is coupled with the same selection signal line, and different register groups are coupled with different selection signal lines.

In some possible embodiments, the shift register further includes: the circuit comprises an input circuit, a reset circuit, at least one control circuit and pull-down circuits corresponding to the control circuits one to one;

the input circuit is configured to supply a signal of a first scan selection signal terminal to the first node in response to a signal of an input signal terminal;

the reset circuit is configured to supply a signal of a second scan selection signal terminal to the first node in response to a signal of a reset signal terminal;

the control circuit is configured to control the levels of signals of the first node and the corresponding second node to be opposite;

the pull-down circuit is configured to provide a signal of a reference signal terminal to the driving output terminal in response to a signal of the corresponding second node.

In some possible embodiments, the two control circuits are two, a first control circuit of the two control circuits is coupled to the first control signal terminal, and a second control circuit of the two control circuits is coupled to the second control signal terminal;

the plurality of selection signal lines include a first selection signal line and a second selection signal line; wherein a first control signal terminal of the first register set is coupled to the first selection signal line, and a second control signal terminal of the second register set is coupled to the second selection signal line.

Drawings

FIG. 1 is a schematic diagram of some structures of a display device in an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of some structures of a display panel according to an embodiment of the present disclosure;

FIG. 3 is a diagram illustrating some structures of a shift register according to an embodiment of the present disclosure;

FIG. 4 is another schematic diagram of a shift register according to an embodiment of the present disclosure;

FIG. 5 is a timing diagram of some signals in an embodiment of the present disclosure;

FIG. 6a is a schematic diagram of some structures of a gate driving circuit according to an embodiment of the present disclosure;

FIG. 6b is another schematic structural diagram of a gate driving circuit according to an embodiment of the disclosure;

FIG. 6c is a schematic diagram of another structure of a gate driving circuit according to an embodiment of the present disclosure;

FIG. 7a is a schematic diagram of still other structures of a gate driving circuit according to an embodiment of the present disclosure;

FIG. 7b is a schematic diagram of another structure of a gate driving circuit according to an embodiment of the present disclosure;

FIG. 7c is a schematic diagram of another structure of a gate driving circuit according to an embodiment of the present disclosure;

FIG. 7d is a schematic diagram of still other structures of a gate driving circuit in an embodiment of the present disclosure;

FIG. 8a is a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure;

FIG. 8b is a schematic diagram of another structure of a gate driving circuit according to an embodiment of the present disclosure;

FIG. 9 is a timing diagram of further signals in an embodiment of the disclosure;

FIG. 10 is another schematic structural diagram of a display panel according to an embodiment of the present disclosure;

FIG. 11a is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 11b is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 12 is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 13 is a schematic diagram of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 14a is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 14b is a schematic diagram of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 15 is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 16 is a schematic diagram of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 17 is a schematic diagram of still other structures of a display panel in an embodiment of the present disclosure;

fig. 18 is a schematic structural diagram of display panels in an embodiment of the disclosure.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. And the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and the like in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the sizes and shapes of the various figures in the drawings are not to scale, but are merely intended to illustrate the present disclosure. And like reference numerals refer to like or similar elements or elements having like or similar functions throughout.

Referring to fig. 1 and 2, the display device may include: the display device includes a display panel 100, a timing controller 200, and a touch driving circuit 300. The display panel 100 may include a plurality of pixel units arranged in an array, a plurality of gate lines GA (e.g., GA1, GA2, GA3, and GA4), a plurality of data lines DA (e.g., DA1, DA2, and DA3), a gate driving circuit 110, and a source driving circuit 120. The gate driving circuit 110 is coupled to the gate lines GA1, GA2, GA3, and GA4, and the source driving circuit 120 is coupled to the data lines DA1, DA2, and DA3, respectively. The timing controller 200 may input a clock signal to the gate driving circuit 110 through a Level Shift (Level Shift) circuit, and cause the gate driving circuit 110 to output a gate scan signal to the gate lines GA1, GA2, GA3, and GA4 coupled thereto, thereby scanning the gate lines GA1, GA2, GA3, and GA 4. The timing controller 200 inputs display data to the source driving circuit 120, so that the source driving circuit 120 inputs a data voltage to the data line according to the received display data, thereby charging the sub-pixel SPX, and inputting a corresponding data voltage to the sub-pixel SPX, thereby implementing a picture display function of the display frame. Illustratively, the number of the source driving circuits 120 may be set to 2, wherein one source driving circuit 120 is connected to half of the number of data lines, and the other source driving circuit 120 is connected to the other half of the number of data lines. Of course, the number of the source driving circuits 120 may also be 3, 4, or more, and the source driving circuits may be designed according to the requirements of the practical application, and are not limited herein.

Illustratively, each pixel unit includes a plurality of sub-pixels SPX. For example, the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that color mixing may be performed by red, green, and blue to realize color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that color display may be realized by performing color mixing of red, green, blue, and white. Of course, in practical applications, the light emitting color of the sub-pixels in the pixel unit may be determined according to practical application environments, and is not limited herein.

In some embodiments, referring to fig. 2, each sub-pixel SPX includes a transistor 01 and a pixel electrode 02 therein. One row of sub-pixels SPX corresponds to one gate line, and one column of sub-pixels SPX corresponds to one data line. A gate electrode of the transistor 01 is electrically connected to a corresponding gate line, a source electrode of the transistor 01 is electrically connected to a corresponding data line, and a drain electrode of the transistor 01 is electrically connected to the pixel electrode 02.

In some embodiments, the pixel array structure of the present disclosure may also be a dual-gate structure, that is, two gate lines are disposed between two adjacent rows of pixels, and this arrangement may reduce half of the data lines, that is, include data lines between two adjacent rows of pixels, and include no data lines between two adjacent rows of pixels, where the specific pixel arrangement structure and the data lines are not included, and the arrangement of the scan lines is not limited.

It should be noted that the display panel in the embodiment of the present disclosure may be a liquid crystal display panel. Illustratively, a liquid crystal display panel generally includes upper and lower substrates facing each other, and liquid crystal molecules encapsulated between the upper and lower substrates. When a picture is displayed, a voltage difference exists between the data voltage loaded on the pixel electrode of each sub-pixel and the common electrode voltage on the common electrode, and the voltage difference can form an electric field, so that liquid crystal molecules are deflected under the action of the electric field. The electric fields with different intensities enable the deflection degree of liquid crystal molecules to be different, so that the transmittance of the sub-pixels is different, the sub-pixels can realize the brightness of different gray scales, and further, the picture display is realized.

To achieve different application scenarios, the display panel may set a number of different refresh frequencies. For example, in some application scenarios, in order to save power consumption, the display panel needs to display in a down-conversion mode, for example: from 60HZ to 30 HZ. In other scenarios, for example: when a high frequency game is executed, it is necessary to increase the frequency of the display panel, for example: the picture is smoother by increasing from 60HZ to 90HZ or 120 HZ. Therefore, in order to be suitable for different scenes, the display panel may change the display frequency, i.e., dynamic frame rate display.

In the embodiment of the present disclosure, the display panel is further provided with a plurality of touch electrodes (the specific values of the touch electrodes can be determined according to the requirements of practical applications). Illustratively, the touch electrode may be a self-capacitance touch electrode, so that a self-capacitance technology may be adopted to implement a touch function. The touch electrode can also be a mutual capacitance touch electrode, so that a mutual capacitance technology can be adopted to realize a touch function. The touch electrode can also be a pressure-sensitive capacitive touch electrode, so that a pressure-sensitive capacitive technology can be adopted to realize a touch function.

In the embodiment of the present disclosure, the touch electrode may be disposed between the upper substrate and the lower substrate of the pair of cells of the display panel in an embedded manner. Illustratively, the common electrode may be multiplexed as a touch electrode. The touch driving circuit 300 is electrically connected to each touch electrode, respectively, to scan the touch electrodes in the display panel, thereby implementing a touch function.

In some embodiments of the present disclosure, the gate driving circuit may include a plurality of shift registers, and a driving output terminal GO of one shift register is coupled to one gate line. Illustratively, as shown in fig. 3, the shift register may include: the input circuit 1, the reset circuit 2, at least one control circuit, a pull-down circuit corresponding to the control circuit one by one, the output transistor M0, and the clock selection circuit 5. Wherein the input circuit 1 is configured to provide the signal of the first scan selection signal terminal VDS to the first node N1 in response to the signal of the input signal terminal INP. The reset circuit 2 is configured to supply a signal of the second scan selection signal terminal VSD to the first node N1 in response to a signal of the reset signal terminal. The control circuit is configured to control the levels of the signals of the first node N1 and the corresponding second node N2 to be opposite. The pull-down circuit is configured to provide a signal of the reference signal terminal VREF to the driving output terminal GO in response to a signal of the corresponding second node. The gate of the output transistor M0 is coupled to the first node N1, the second pole of the output transistor M0 is coupled to the driving output GO, and the first pole of the output transistor M0 is coupled to the clock selection circuit 5. The clock selection circuit 5 is configured to turn on the first pole of the output transistor M0 with the clock signal terminal CK coupled to the corresponding clock signal line in response to a signal of the selection signal terminal CKX.

In some embodiments of the present disclosure, as shown in fig. 3, the shift register may include: a control circuit and a pull-down circuit. The input circuit 1 includes a first transistor M1. A control electrode of the first transistor M1 is coupled to the input signal terminal INP, a first electrode of the first transistor M1 is coupled to the first scan selection signal terminal VDS, and a second electrode of the first transistor M1 is coupled to the first node N1. The reset circuit 2 includes a second transistor M2. A control electrode of the second transistor M2 is coupled to the reset signal terminal, a first electrode of the second transistor M2 is coupled to the second scan selection signal terminal VSD, and a second electrode of the second transistor M2 is coupled to the first node N1. The control circuit 3 includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. A control electrode and a first electrode of the third transistor M3 are coupled to the control signal terminal VN, a second electrode of the third transistor M3 is coupled to a control electrode of the fifth transistor M5, a first electrode of the fifth transistor M5 is coupled to the control signal terminal VN, and a second electrode of the fifth transistor M5 is coupled to the second node N2. A control electrode of the fourth transistor M4 is coupled to the first node N1, a first electrode of the fourth transistor M4 is coupled to the reference signal terminal VREF, and a second electrode of the fourth transistor M4 is coupled to a control electrode of the fifth transistor M5. A control electrode of the sixth transistor M6 is coupled to the first node N1, a first electrode of the sixth transistor M6 is coupled to the reference signal terminal VREF, and a second electrode of the sixth transistor M6 is coupled to the second node N2. A control electrode of the seventh transistor M7 is coupled to the second node, a first electrode of the seventh transistor M7 is coupled to the reference signal terminal VREF, a second electrode of the seventh transistor M7 is coupled to the second node N2, and the seventh transistor M7 pulls down the first node under the control of the second node. The pull-down circuit includes an eighth transistor M8, a control electrode of the eighth transistor M8 is coupled to the second node N2, a first electrode of the eighth transistor M8 is coupled to the reference signal terminal VREF, a second electrode of the eighth transistor M8 is coupled to the driving output, and the eighth transistor M8 pulls down the driving output GO under the control of the second node. The clock selection circuit 5 includes a ninth transistor M9, a control electrode of the ninth transistor M9 is coupled to the selection signal terminal CKX, a first electrode of the eighth transistor M8 is coupled to a first electrode of the output transistor M0, and a second electrode of the ninth transistor M9 is coupled to the corresponding clock signal terminal CK.

In some embodiments of the present disclosure, as shown in fig. 3, the shift register may further include: a first capacitor C1, a tenth transistor M10, and an eleventh transistor M11. A first electrode plate of the first capacitor C1 is coupled to the first node N1, and a second electrode plate of the first capacitor C1 is coupled to the driving output GO. A control electrode of the tenth transistor M10 is coupled to the frame reset signal terminal STVO, a first electrode of the tenth transistor M10 is coupled to the reference signal terminal VREF, and a second electrode of the tenth transistor M10 is coupled to the first node N1. A control electrode of the eleventh transistor M11 is coupled to the frame reset signal terminal STVO, a first electrode of the eleventh transistor M11 is coupled to the reference signal terminal VREF, and a second electrode of the eleventh transistor M11 is coupled to the driving output terminal GO, i.e., the tenth transistor M10 and the eleventh transistor M11 are respectively used for noise reduction of the first node and the driving output terminal under the control of the STVO.

In some embodiments of the present disclosure, as shown in fig. 4, the shift register may include: 2 control circuits and 2 pull-down circuits. Wherein the 2 control circuits comprise a first control circuit 3-1 and a second control circuit 3-2. The 2 pull-down circuits include a first pull-down circuit 4-1 and a second pull-down circuit 4-2. The first control circuit 3-1 is coupled to the first node N1, the 1 st second node N2-1 and the first control signal terminal VN-1, and includes a1 st third transistor M3-1, a1 st fourth transistor M4-1, a1 st fifth transistor M5-1, a1 st sixth transistor M6-1 and a1 st seventh transistor M7-1. The second control circuit 3-2 is coupled to the first node N1, the 2 nd second node N2-2 and the second control signal terminal VN-2, and includes a2 nd third transistor M3-2, a2 nd fourth transistor M4-2, a2 nd fifth transistor M5-2, a2 nd sixth transistor M6-2 and a2 nd seventh transistor M7-2.

The first pull-down circuit 4-1 is coupled to the 1 st second node N2-1 and includes a1 st eighth transistor M8-1.

The second pull-down circuit 4-2 is coupled to the 2 nd second node N2-2 and includes a2 nd eighth transistor M8-2. The specific connection method can refer to the connection method described above, and is not described herein again.

The control electrode may be a gate electrode, a first electrode is a source electrode, and a second electrode is a drain electrode. Alternatively, the control electrode may be its gate, the first electrode its drain, and the second electrode its source. The N-type transistors are turned on under the control of a high-level signal and turned off under the control of a low-level signal. The P-type transistors are turned on under the control of a low level signal and turned off under the control of a high level signal.

In some embodiments of the present disclosure, taking the shift register shown in fig. 4 as an example, the shift register shown in fig. 4 operates in a corresponding signal timing diagram in the nth frame Fn, as shown in fig. 5. Wherein INP represents a signal of the input signal terminal INP, CK represents a signal of the clock signal terminal CK, ga represents a gate scan signal of the driving output terminal GO, re represents a signal of the reset signal terminal, and STVO represents a signal of the frame reset signal terminal STVO. Illustratively, the driving output terminal GO is coupled to a corresponding gate line. The active level of the gate scanning signal ga may control the transistors in the pixels coupled to the corresponding gate lines to be turned on, and the inactive level may control the transistors in the pixels coupled to the corresponding gate lines to be turned off. Illustratively, the transistors in the shift register are N-type transistors, the active level of the gate scanning signal ga may be high, the inactive level may be low, and the signal vref is a fixed voltage with a low level. Alternatively, the transistors in the shift register may be P-type transistors, the active level of the gate scanning signal ga may be low, the inactive level may be high, and the signal vref may be a fixed voltage of high. And is not limited herein.

It should be noted that, in the shift register provided by the embodiment of the present disclosure, the first transistor M1 and the second transistor M2 are symmetrically designed, and functions can be interchanged, so that the shift register provided by the embodiment of the present disclosure can implement bidirectional scanning. In the forward direction scanning, the first transistor M1 is used as an input transistor, and the second transistor M2 is used as a reset transistor. Further, taking the active level of the gate scanning signal ga as a high level and the inactive level as a low level as an example, the signal of the first scanning control terminal VDS is a fixed voltage of a high level, and the signal of the second scanning control terminal VSD is a fixed voltage of a low level. In the reverse scanning, the second transistor M2 is used as an input transistor, and the first transistor M1 is used as a reset transistor. Further, taking the example that the active level of the gate scanning signal ga is high and the inactive level is low, the signal of the first scanning control terminal VDS is a fixed voltage of low level, and the signal of the second scanning control terminal VSD is a fixed voltage of low level.

In some embodiments of the present disclosure, the display panel may further include a plurality of clock signal lines and a plurality of frame start signal lines, and the plurality of clock signal lines and the plurality of frame start signal lines are respectively coupled to the gate driving circuit. In this way, a corresponding clock signal can be input to the gate driving circuit through the clock signal line, and the clock signal is input to the clock signal terminal of the shift register, so that the shift register outputs a gate scanning signal to the coupled gate lines. For example, as shown in fig. 6a, the display panel may include 4 clock signal lines CKS 1-CKS 4, and the 4 clock signal lines CKS 1-CKS 4 are coupled to the gate driving circuit 110. It should be noted that fig. 6a only illustrates 4 clock signal lines, and in practical applications, the specific number of clock signal lines may be determined according to practical application requirements, and is not limited herein, for example, another number of clock signal lines that is an integer multiple of 2 may also be used, such as 2, 6, 8, 10, 12, and so on.

In some embodiments of the present disclosure, the frame reset signal terminal STVO of each shift register is coupled to the same frame reset signal line, so that the shift registers can be reset uniformly, and optionally, the first node and the driving output terminal GO are reset.

In some embodiments of the present disclosure, the plurality of shift registers are divided into M register groups, and different register groups are coupled to different frame start signal lines; m is an integer greater than 1. Optionally, the shift registers in each register group are respectively coupled to the gate lines spaced by M-1 rows. The register group comprises at least two cascade groups, the shift registers in the same cascade group are arranged in a cascade mode, and the shift registers in the same cascade group are respectively coupled with the grid lines at intervals of multiple rows. Illustratively, M may be 2, 3, 4, 5, 6 or more, and is not limited herein. The following description will be given by taking M as 2.

Illustratively, M ═ 2, as shown in fig. 7a to 8b, the plurality of shift registers are divided into 2 register groups: a first register set ZGOA1 and a second register set ZGOA 2. The first register group ZGOA1 includes shift registers SR1, SR3, SR5, SR7, the second register group ZGOA2 includes shift registers SR2, SR4, SR6, SR8, and each shift register in the first register group ZGOA1 is coupled to a gate line of an odd-numbered row (GA 1, GA3, GA5, GA7), and each shift register in the second register group ZGOA2 is coupled to a gate line of an even-numbered row (GA 2, GA4, GA6, GA 8). Further, the first register group ZGOA1 is coupled to the start-of-frame signal line STV1, the input signal terminal INP of the shift register included in the first register group ZGOA1 is coupled to the start-of-frame signal line STV1, optionally, the input signal terminal INP of the first shift register included in the first register group ZGOA1 is coupled to the start-of-frame signal line STV1, where the coupling may refer to direct electrical connection or indirect electrical connection (i.e., other circuit components are disposed therebetween), which is not limited herein, the second register group ZGOA2 is coupled to the start-of-frame signal line STV2, the input signal terminal INP of the shift register included in the second register group ZGOA2 is coupled to the start-of-frame signal line STV2, and optionally, the input signal terminal INP of the first shift register included in the second register group ZGOA2 is coupled to the start-of-frame signal line STV 1. And a driving output terminal GO of the shift register SR1 is coupled to the gate line GA1, a driving output terminal GO of the shift register SR2 is coupled to the gate line GA2, a driving output terminal GO of the shift register SR3 is coupled to the gate line GA3, a driving output terminal GO of the … … shift register SR7 is coupled to the gate line GA7, and a driving output terminal GO of the shift register SR8 is coupled to the gate line GA 8.

In some embodiments of the present disclosure, different register groups are coupled to the same clock signal line, and thus the number of clock signal lines can be reduced, for example, 8 clock signal lines need to be arranged in the prior art, but 4 clock signal lines can be arranged in the present invention to achieve the same practical effect, thereby reducing the frame. For example, the first register group ZGOA1 is coupled to the first clock signal line CKS1 to the fourth clock signal line CKS4, the second register group ZGOA2 is also coupled to the first clock signal line CKS1 to the fourth clock signal line CKS4, and referring to fig. 6b, the shift registers SR1 and SR2 are connected to the same clock signal line CKS 1. Illustratively, as shown in FIGS. 7a to 8b, the clock signal terminal CK of the 8k-7 th stage shift register SR8k-7 is coupled to the first clock signal line CKS1, the clock signal terminal CK of the 8k-5 th stage shift register SR8k-5 is coupled to the second clock signal line CKS2, the clock signal terminal CK of the 8k-3 th stage shift register SR8k-3 is coupled to the third clock signal line CKS3, the clock signal terminal CK of the 8k-1 th stage shift register SR8k-1 is coupled to the fourth clock signal line CKS4, the clock signal terminal CK of the 8k-6 th stage shift register SR8k-6 is coupled to the first clock signal line CKS1, the clock signal terminal CK of the 8k-4 th stage shift register SR8k-4 is coupled to the second clock signal line CKS2, the clock signal terminal CK of the 8 k-k-2 th stage shift register SR8k-2 is coupled to the third clock signal line CKS3, the clock signal terminal CK of the 8 k-th stage shift register SR8k is coupled to the fourth clock signal line CKS 4. K is an integer greater than 0.

For example, as shown in fig. 6a to 8b, two adjacent gate lines are taken as a gate line group, and the shift registers corresponding to the same gate line group are coupled to the same clock signal line. For example, the gate lines GA1 and GA2 are a gate line set, and the clock signal terminal CK of the first stage shift register SR1 and the second stage shift register SR2 are coupled to the first clock signal line CKs 1. The gate lines GA3 and GA4 are a set of gate lines, and the clock signal terminal CK of the third stage shift register SR3 and the fourth stage shift register SR4 are coupled to the second clock signal line CKs 2. The gate lines GA5 and GA6 are a gate line group, and the clock signal terminal CK of the fifth stage shift register SR5 and the sixth stage shift register SR6 are coupled to the second clock signal line CKs 2. The same reasoning can be followed for the rest, and will not be described herein.

Illustratively, as shown in fig. 6c, 7a to 8b, the first register group ZGOA1 includes a first cascade group ZJL1 and a second cascade group ZJL 2. The shift registers in the first cascaded set ZJL1 are respectively coupled to the gate lines spaced by 3 rows, and the shift registers in the second cascaded set ZJL2 are respectively coupled to the gate lines spaced by 3 rows. The first cascaded set ZJL1 and the second cascaded set ZJL2 are both coupled to the frame start signal line STV 1. The first cascaded set ZJL1 includes shift registers SR1 and SR5, and the input signal terminal INP of the shift register SR1 is coupled to the frame start signal line STV1, and the input signal terminal INP of the shift register SR5 is coupled to the driving output GO of the shift register SR 1. The driving output terminal GO of the shift register SR5 is coupled to the reset signal terminal RE of the shift register SR 1. The second cascaded set ZJL2 includes shift registers SR3 and SR7, and the input signal terminal INP of the shift register SR3 is coupled to the frame start signal line STV1, and the input signal terminal INP of the shift register SR7 is coupled to the driving output terminal GO of the shift register SR 3. The driving output terminal GO of the shift register SR7 is coupled to the reset signal terminal RE of the shift register SR 3.

Illustratively, as shown in fig. 7a to 8b, the second register group ZGOA2 includes a third cascade group ZJL3 and a fourth cascade group ZJL4, and the shift registers in the third cascade group ZJL3 are respectively coupled to the gate lines spaced by 3 rows, and the shift registers in the fourth cascade group ZJL4 are respectively coupled to the gate lines spaced by 3 rows. Wherein the third and fourth concatenated groups ZJL3 and ZJL4 are both coupled to the frame start signal line STV 2. The third cascade group ZJL3 includes shift registers SR2 and SR6, and the input signal terminal INP of the shift register SR2 is coupled to the frame start signal line STV2, and the input signal terminal INP of the shift register SR6 is coupled to the driving output terminal GO of the shift register SR 2. The driving output terminal GO of the shift register SR6 is coupled to the reset signal terminal RE of the shift register SR 2. The fourth cascaded set ZJL4 includes shift registers SR4 and SR8, and the input signal terminal INP of the shift register SR4 is coupled to the frame start signal line STV2, and the input signal terminal INP of the shift register SR8 is coupled to the driving output terminal GO of the shift register SR 4. The driving output terminal GO of the shift register SR8 is coupled to the reset signal terminal RE of the shift register SR 4.

In some embodiments of the present disclosure, as shown in fig. 7a, a first register group ZGOA1 may be disposed at a first end of the plurality of gate lines, and a second register group ZGOA2 may be disposed at a second end of the plurality of gate lines. Illustratively, the first register group ZGOA1 is disposed on the left side of the plurality of gate lines, the second register group ZGOA2 is disposed on the right side of the plurality of gate lines, and the first register group ZGOA1 and the second register group ZGOA2 drive different gate lines, respectively.

In some embodiments of the present disclosure, as shown in fig. 7b, the first and second register groups ZGOA1 and ZGOA2 may be located at the same end of the plurality of gate lines. Illustratively, the first register set ZGOA1 and the second register set ZGOA2 may both be located to the left of the plurality of gate lines.

In some embodiments of the present disclosure, as shown in fig. 7c, each shift register may also include a left shift register disposed at a first end of the same gate line and a right shift register disposed at a second end, and the left shift register and the right shift register coupled to the same gate line output the gate scan signal at the same time. Illustratively, two first stage shift registers SR1 are provided, one being a left shift register SR1 and the other being a right shift register SR 1. And the left shift register SR1 and the right shift register SR1 simultaneously input the gate scan signal to the gate line GA 1. Two second-stage shift registers SR2 are also provided, one being a left-side shift register SR2 and the other being a right-side shift register SR 2. And the left shift register SR2 and the right shift register SR2 simultaneously input the gate scan signal to the gate line GA 2. Two third stage shift registers SR3 are also provided, one being a left side shift register SR3 and the other being a right side shift register SR 3. And the left shift register SR3 and the right shift register SR3 simultaneously input gate scan signals to the gate line GA 3. The same reasoning can be followed for the rest, and will not be described herein.

In some embodiments of the present disclosure, as shown in fig. 7d, 8a and 8b, the first and third cascade groups ZJL1 and ZJL3 may be disposed at the first end of the gate lines, and the second and fourth cascade groups ZJL2 and ZJL4 may be disposed at the second end of the gate lines. Illustratively, the first and third cascade groups ZJL1 and ZJL3 are disposed at the left side of the plurality of gate lines, and the second and fourth cascade groups ZJL2 and ZJL4 are disposed at the right side of the plurality of gate lines. Specifically, referring to fig. 7d and fig. 8a, the first cascaded set ZJL1 includes shift registers SR1 and SR 5. The second cascaded set ZJL2 includes shift registers SR3, SR 7. Referring to fig. 7d and fig. 8b, the third cascade group ZJL3 includes shift registers SR2 and SR 6. The fourth cascaded group ZJL4 includes shift registers SR4, SR 8.

In some embodiments of the present disclosure, the display panel further includes a plurality of selection signal lines; the selection signal terminal CKX of each shift register in the same register set is coupled to the same selection signal line, and different register sets are coupled to different selection signal lines. Illustratively, M-2, as shown in fig. 8a and 8b, the plurality of selection signal lines includes a first selection signal line CXS1 and a second selection signal line CXS 2. The selection signal terminal CKX of each shift register in the first register group ZGOA1 is coupled to the first selection signal line CXS1, and the selection signal terminal CKX of each shift register in the second register group ZGOA2 is coupled to the second selection signal line CXS 2.

In some embodiments of the present disclosure, as shown in fig. 4, fig. 7b, fig. 8a and fig. 8b, the first control signal terminal VN-1 and the select signal terminal CKX of each shift register (i.e. the odd-numbered shift registers) in the first register group ZGOA1 are coupled to the first select signal line CXS1 for inputting the same control signal. The second control signal terminal VN-2 and the selection signal terminal CKX of each shift register (i.e., the even-numbered shift register) in the second register group ZGOA2 are coupled to the second selection signal line CXS2 for inputting the same control signal. When the first selection signal line CXS1 is loaded with an active level (e.g., high level) and the second selection signal line CXS2 is loaded with an inactive level (e.g., low level), scanning of the gate lines of odd rows can be realized. When the first selection signal line CXS1 is loaded with an inactive level (e.g., low level) and the second selection signal line CXS2 is loaded with an active level (e.g., high level), scanning of even-numbered row gate lines can be realized.

For example, as shown in fig. 6b, 6c and 7b, the control signal terminal VN and the select signal terminal CKX of each shift register (i.e. odd number of shift registers) in the first register group ZGOA1 are coupled to the first select signal line CXS1 for inputting the same control signal. The control signal terminal VN and the selection signal terminal CKX of each shift register (i.e. the even shift register) in the second register group ZGOA2 are coupled to the second selection signal line CXS2 for inputting the same control signal. When the first selection signal line CXS1 is loaded with an active level (e.g., high level) and the second selection signal line CXS2 is loaded with an inactive level (e.g., low level), scanning of the gate lines of odd rows can be realized. When the first selection signal line CXS1 is loaded with an inactive level (e.g., low level) and the second selection signal line CXS2 is loaded with an active level (e.g., high level), scanning of even-numbered row gate lines can be realized. The structure of the shift register in fig. 6c is illustrated in fig. 3.

Some embodiments of the present disclosure provide a driving method, including: dividing a display frame into M scanning stages and N touch control stages; in the mth scanning stage of the M scanning stages, loading a frame start signal to a frame start signal line coupled to the mth register group of the M register groups, loading different clock signals to a plurality of clock signal lines, controlling a shift register unit in the mth register group to output a grid scanning signal to a coupled grid line, and loading a cut-off control signal to a frame start signal line coupled to the rest register groups; setting one touch control stage in N touch control stages between two adjacent scan stages of the M scan stages, scanning a touch control electrode in the display panel in the touch control stage, loading a cut-off control signal to each frame starting signal line, and loading a cut-off control signal to each clock signal line; n is an integer greater than 0.

In the driving method provided by the embodiment of the present disclosure, the scanning stage and the touch stage are set in one display frame, so that the display panel can realize the function of performing display and touch in a time-sharing manner. In addition, in the next scanning stage after the touch stage is finished, a new register group is controlled to scan the coupled grid lines, so that the problem that in the prior art, scanning is started again after the shift register is paused in the middle of line-by-line scanning, and horizontal stripes are displayed can be avoided. And, this disclosed embodiment is through reserving scan time with other integrated functions, insert between the display scanning stage, avoid the electric leakage problem of long-time display level.

In some embodiments of the present disclosure, one touch stage of the N touch stages may be set between every two adjacent scan stages of the M scan stages. Optionally, in two adjacent display frames, the two display frames include a first display frame and a second display frame, and a target touch stage is disposed between an mth scanning stage of the first display frame and a1 st scanning stage of the second display frame. The target touch stage is one of the N touch stages of the second display frame. For example, as shown in fig. 9, the g-th display frame F _ g has two touch phases tu1_ g and tu2_ g, and tu1_ g is the target touch phase in the g-th display frame F _ g. The g +1 th display frame F _ g +1 has two touch phases tu1_ g +1 and tu2_ g +1, wherein tu1_ g +1 is the target touch phase in the g +1 th display frame F _ g + 1. Of course, the target touch stage is one of the N touch stages of the first display frame, and is not limited herein.

In some embodiments of the present disclosure, in the mth scanning phase, a frame start signal is loaded to a frame start signal line coupled to the mth register group, a different clock signal is loaded to a clock signal line coupled to the mth register group, and each shift register in the mth register group is controlled to scan a gate line coupled to the mth register group every M-1 lines.

Illustratively, the clock signals corresponding to different register groups have the same period and the same time sequence.

For example, taking M ═ 2 and N ═ 2 (of course, N may be set to other values, but is not limited thereto), as shown in fig. 9, CKS1_1 represents a clock signal on the first clock line CKS1, CKS2_1 represents a clock signal on the second clock line CKS2, CKS3_1 represents a clock signal on the third clock line CKS3, CKS4_1 represents a clock signal on the fourth clock line CKS4, stv1_1 represents a signal on the first frame start signal line, and stv2_1 represents a signal on the second frame start signal line. GA1_1 represents a gate scan signal inputted to the gate line GA1 from the driving output GO of the first stage shift register SR1, GA3_1 represents a gate scan signal inputted to the gate line GA3 from the driving output GO of the third stage shift register SR3, GA5_1 represents a gate scan signal inputted to the gate line GA5 from the driving output GO of the fifth stage shift register SR5, GA7_1 represents a gate scan signal inputted to the gate line GA7 from the driving output GO of the seventh stage shift register SR7, GA2_1 represents a gate scan signal inputted to the gate line GA2 from the driving output GO of the second stage shift register SR2, GA4_1 represents a gate scan signal inputted to the gate line GA4 from the driving output GO of the seventh stage shift register SR4, GA6_1 represents a gate scan signal inputted to the gate line GA6 from the driving output GO of the sixth stage shift register SR6, and GA8_1 represents a gate scan signal inputted to the gate line GA8 from the driving output GO of the eighth stage shift register SR 8.

And, the g-th display frame F _ g includes 2 scanning stages and 2 touch stages. Wherein, the g-th display frame F _ g comprises 2 scanning stages: a1 st scan phase sm1_ g and a2 nd scan phase sm2_ g. The g-th display frame F _ g includes 2 touch stages: the 1 st touch phase tu1_ g and the 2 nd touch phase tu2_ g. The 1 st touch phase tu1_ g precedes the 1 st scan phase sm1_ g, and the 2 nd touch phase tu2_ g is located between the 1 st scan phase sm1_ g and the 2 nd scan phase sm2_ g. The g +1 th display frame F _ g +1 includes 2 scanning stages and 2 touch stages. Wherein, the g +1 th display frame F _ g +1 includes 2 scanning stages: a1 st scan phase sm1_ g +1 and a2 nd scan phase sm2_ g + 1. The g +1 th display frame F _ g +1 includes 2 touch phases: the 1 st touch phase tu1_ g +1 and the 2 nd touch phase tu2_ g + 1. The 1 st touch phase tu1_ g +1 is located between the 2 nd scan phase sm2_ g and the 1 st scan phase sm1_ g +1, and the 2 nd touch phase tu2_ g +1 is located between the 1 st scan phase sm1_ g +1 and the 2 nd scan phase sm2_ g + 1.

In the g-th display frame F _ g, in the 1 st touch phase tu1_ g, the touch electrodes in the display panel are scanned, and the first frame start signal line and the second frame start signal line are respectively loaded with the low-level off control signal, and the first clock signal line CKS1 to the fourth clock signal line CKS4 are respectively loaded with the low-level off control signal, so that the shift registers in each register group keep outputting the low-level signals. And loading a frame reset signal on the frame reset signal line to control each shift register to reset.

In the 1 st scanning period sm1_ g, the first frame start signal line is applied with a high-level frame start signal, and the second frame start signal line is applied with a low-level off control signal. The first selection signal line CXS1 is supplied with an on control signal at a high level, and the second selection signal line CXS2 is supplied with an off control signal at a low level, so that the ninth transistor M9 of each shift register in the first register can be turned on, and the ninth transistor M9 of each shift register in the second register can be turned off. Signals CKS1_1 to CKS4_1 are applied to the first clock signal line CKS1 to the fourth clock signal line CKS4, respectively, and gate scan signals GA1_1, GA3_1, GA5_1, and GA7_1 are output to the gate lines GA1, GA3, GA5, and GA7 coupled to the shift register units in the first register group ZGOA 1. While the second register set ZGOA2 is controlled to keep outputting a low signal.

In the 2 nd touch phase tu2_ g, the touch electrodes in the display panel are scanned, and the low-level off control signal is respectively applied to the first frame start signal line and the second frame start signal line, the low-level off control signal is respectively applied to the first clock signal line CKS1 to the fourth clock signal line CKS4, and the low-level off control signal is applied to the first selection signal line CXS1 and the second selection signal line CXS2, so that the shift registers in the register groups keep outputting low-level signals.

In the 2 nd scanning period sm2_ g, the frame start signal at the high level is applied to the second frame start signal line, and the off control signal at the low level is applied to the first frame start signal line. The second selection signal line CXS2 is supplied with an on control signal at a high level, and the first selection signal line CXS1 is supplied with an off control signal at a low level, so that the ninth transistor M9 of each shift register in the second register can be turned on, and the ninth transistor M9 of each shift register in the first register can be turned off. Signals CKS1_1 to CKS4_1 are applied to the first clock signal line CKS1 to the fourth clock signal line CKS4, respectively, and gate scan signals GA2_1, GA4_1, GA6_1, and GA8_1 are output to the gate lines GA2, GA4, GA6, and GA8 coupled to the shift register units in the second register group ZGOA 2. And controls the first register group ZGOA1 to keep outputting a low signal.

In the g +1 th display frame F _ g +1, in the 1 st touch phase tu1_ g +1, the touch electrodes in the display panel are scanned, and the low-level off control signal is applied to each of the first frame start signal line and the second frame start signal line, the low-level off control signal is applied to each of the first clock signal line CKS1 to the fourth clock signal line CKS4, and the low-level off control signal is applied to each of the first selection signal line CXS1 and the second selection signal line CXS2, so that each of the shift registers in each of the register groups keeps outputting a low-level signal. And loading a frame reset signal to the frame reset signal line to control each shift register to reset.

In the 1 st scanning period sm1_ g +1, the first frame start signal line is applied with the frame start signal of the high level, and the second frame start signal line is applied with the off control signal of the low level. The first selection signal line CXS1 is supplied with an on control signal at a high level, and the second selection signal line CXS2 is supplied with an off control signal at a low level, so that the ninth transistor M9 of each shift register in the first register can be turned on, and the ninth transistor M9 of each shift register in the second register can be turned off. Signals CKS1_1 to CKS4_1 are applied to the first clock signal line CKS1 to the fourth clock signal line CKS4, respectively, and gate scan signals GA1_1, GA3_1, GA5_1, and GA7_1 are output to the gate lines GA1, GA3, GA5, and GA7 coupled to the shift register units in the first register group ZGOA 1. While the second register set ZGOA2 is controlled to keep outputting a low signal.

In the 2 nd touch phase tu2_ g +1, the touch electrodes in the display panel are scanned, and the low-level off control signal is applied to the first frame start signal line and the second frame start signal line, respectively, the low-level off control signal is applied to the first clock signal line CKS1 to the fourth clock signal line CKS4, respectively, and the low-level off control signal is applied to the first selection signal line CXS1 and the second selection signal line CXS2, so that the shift registers in the register groups keep outputting low-level signals.

In the 2 nd scanning period sm2_ g +1, the frame start signal of the high level is applied to the second frame start signal line, and the off control signal of the low level is applied to the first frame start signal line. The second selection signal line CXS2 is applied with an on control signal of a high level, and the first selection signal line CXS1 is applied with an off control signal of a low level, so that the ninth transistor M9 of each shift register in the second register can be turned on, and the ninth transistor M9 of each shift register in the first register can be turned off. Signals CKS1_1 to CKS4_1 are applied to the first clock signal line CKS1 to the fourth clock signal line CKS4, respectively, and gate scan signals GA2_1, GA4_1, GA6_1, and GA8_1 are output to the gate lines GA2, GA4, GA6, and GA8 coupled to the shift register units in the second register group ZGOA 2. And controls the first register group ZGOA1 to keep outputting a low signal.

It should be noted that, in the embodiment of the present disclosure, two register sets may be switched to work separately in one display frame to provide a segmented scanning time for touch, that is, the touch scanning frequency may be 2 times of the display scanning frequency, that is, the display panel may implement a display scanning frequency of 60Hz +120Hz or a display scanning frequency of 120Hz +240Hz, and the like. In addition, the embodiment of the disclosure can avoid the problem of horizontal stripes of brightness difference of the uplink and downlink sub-pixels caused by suspending the scanning of the shift register in the display process. Of course, the touch scan frequency may also be 3 times the display scan frequency, that is, the display panel may realize a display scan frequency of 60Hz + a touch scan frequency of 180Hz, and the like. The touch scanning frequency may also be 4 times of the display scanning frequency, that is, the display panel may implement a display scanning frequency of 60Hz + a touch scanning frequency of 240Hz, and the like.

In some embodiments of the present disclosure, as shown in fig. 10, one column of sub-pixels is of the same color, and the red sub-pixel column, the green sub-pixel column, and the blue sub-pixel column are sequentially and repeatedly arranged. For example, red subpixel columns R11 to R81, green subpixel columns G11 to G81, blue subpixel columns B11 to B81, red subpixel columns R12 to R82, green subpixel columns G12 to G82, and blue subpixel columns B12 to B82. Moreover, a row of sub-pixels SPX is correspondingly coupled to a gate line, and a column of sub-pixels SPX is correspondingly coupled to a data line. For example, as shown in fig. 9 to 11B, in the g-th display frame F _ g, when the gate scan signals applied to the gate lines GA1, GA3, GA5, and GA7 are at a high level in the 1 st scan phase sm1_ g, the data lines DA1 to DA6 are applied with corresponding data voltages, so that the sub-pixels R11 to B12, R31 to B32, R51 to B52, and R71 to B72 may be input with the corresponding data voltages. In the 2 nd scan phase sm2_ g, the polarity of the data voltage is inverted once, and when the gate scan signals applied to the gate lines GA2, GA4, GA6, and GA8 are at a high level, the data voltages are applied to the data lines DA1 to DA6, respectively, so that the sub-pixels R21 to B22, R41 to B42, R61 to B62, and R81 to B82 can input the corresponding data voltages. In this way, the polarity of each sub-pixel in the g-th display frame F _ g is made to be in a dot inversion manner as shown in fig. 11 a. In the g +1 th display frame F _ g +1, when the gate scan signals applied to the gate lines GA1, GA3, GA5, and GA7 are at a high level in the 1 st scan stage sm1_ g +1, the data lines DA1 to DA6 are applied with corresponding data voltages, respectively, so that the subpixels R11 to B12, R31 to B32, R51 to B52, and R71 to B72 can input the corresponding data voltages. In the 2 nd scan phase sm2_ g +1, the polarity of the data voltage is inverted once, and when the gate scan signals applied to the gate lines GA2, GA4, GA6, and GA8 are at a high level, the data voltages are applied to the data lines DA1 to DA6, respectively, so that the sub-pixels R21 to B22, R41 to B42, R61 to B62, and R81 to B82 can input the corresponding data voltages. The polarities of the sub-pixels in the g +1 th display frame F _ g +1 are inverted in a dot inversion manner as shown in fig. 11 b. In fig. 11a and 11b, "+" represents positive polarity and "-" represents negative polarity. Compare like this when progressive scanning grid line, need in a display frame the mode of overturning data voltage many times, this disclosed embodiment can only need in a display frame with data voltage's polarity upset once, can realize some upset effects, can reduce the consumption.

In other embodiments of the present disclosure, as shown in fig. 12, a column of sub-pixels is of the same color, and the red sub-pixel column, the green sub-pixel column, and the blue sub-pixel column are sequentially and repeatedly arranged. For example, red subpixel columns R11 to R81, green subpixel columns G11 to G81, blue subpixel columns B11 to B81, red subpixel columns R12 to R82, green subpixel columns G12 to G82, and blue subpixel columns B12 to B82. In addition, one row of sub-pixels SPX is correspondingly coupled to one gate line, and one column of sub-pixels SPX corresponds to two data lines. In the same column of sub-pixels, the sub-pixels in odd rows are coupled to the data line on the left side of the column of sub-pixels, and the sub-pixels in even rows are coupled to the data line on the right side of the column of sub-pixels. For example, as shown in fig. 9 and fig. 11a to 12, in the g-th display frame F _ g, when the gate scan signals applied to the gate lines GA1, GA3, GA5, and GA7 are at a high level in the 1 st scan phase sm1_ g, the data lines DA1 to DA7 are applied with corresponding data voltages, respectively, so that the sub-pixels R11 to B12, R31 to B32, R51 to B52, and R71 to B72 may input the corresponding data voltages. In the 2 nd scan phase sm2_ g, the polarity of the data voltage is inverted once, and when the gate scan signals applied to the gate lines GA2, GA4, GA6, and GA8 are at a high level, the data voltages are applied to the data lines DA1 to DA7, respectively, so that the sub-pixels R21 to B22, R41 to B42, R61 to B62, and R81 to B82 can input the corresponding data voltages. In this way, the polarity of each sub-pixel in the g-th display frame F _ g is made to be in a dot inversion manner as shown in fig. 11 a. In the g +1 th display frame F _ g +1, when the gate scan signals applied to the gate lines GA1, GA3, GA5, and GA7 are at a high level in the 1 st scan stage sm1_ g +1, the data lines DA1 to DA7 are applied with corresponding data voltages, respectively, so that the subpixels R11 to B12, R31 to B32, R51 to B52, and R71 to B72 can input the corresponding data voltages. In the 2 nd scan phase sm2_ g +1, the polarity of the data voltage is inverted once, and when the gate scan signals applied to the gate lines GA2, GA4, GA6, and GA8 are at a high level, the data voltages are applied to the data lines DA1 to DA7, respectively, so that the sub-pixels R21 to B22, R41 to B42, R61 to B62, and R81 to B82 can input the corresponding data voltages. The polarities of the sub-pixels in the g +1 th display frame F _ g +1 are inverted in a dot inversion manner as shown in fig. 11 b. In fig. 11a and 11b, "+" represents positive polarity, and "-" represents negative polarity. Compare like this when progressive scanning grid line, need in a display frame the mode of overturning data voltage many times, this disclosed embodiment can only need in a display frame with data voltage's polarity upset once, can realize some upset effects, can reduce the consumption. In addition, in each scanning stage, each data line only charges the sub-pixels with the same color, so that the problem of the color mixing picture Fine Pitch Mura can be avoided.

In still other embodiments of the present disclosure, as shown in fig. 13, a column of sub-pixels has the same color, and the red sub-pixel column, the green sub-pixel column, and the blue sub-pixel column are sequentially and repeatedly arranged. For example, red subpixel columns R11 to R41, green subpixel columns G11 to G41, blue subpixel columns B11 to B41, red subpixel columns R12 to R42, green subpixel columns G12 to G42, and blue subpixel columns B12 to B42. Moreover, one row of the sub-pixels SPX corresponds to two Gate lines (i.e., Dual gates), and two adjacent columns of the sub-pixels SPX correspond to one data line. And the sub-pixels in the two adjacent columns of sub-pixels are coupled with the corresponding data lines. And aiming at two sub-pixels coupled with the same data line in the same row, the left sub-pixel is coupled with the grid line positioned above the row, and the right sub-pixel is coupled with the grid line positioned below the row. For example, as shown in fig. 9 and 13 to 14B, in the g-th display frame F _ g, in the 1 st scan phase sm1_ g, the polarity of the data voltage is inverted once, and when the gate scan signals applied to the gate lines GA1, GA3, GA5, and GA7 are at a high level, the data voltages are applied to the data lines DA1 to DA3, respectively, so that the sub-pixels R11 to R41, R12 to R42, and B12 to B42 can be input with the corresponding data voltages. In the 2 nd scan phase sm2_ G, when the gate scan signals applied to the gate lines GA2, GA4, GA6 and GA8 are at a high level, corresponding data voltages are applied to the data lines DA1 to DA3, respectively, so that the sub-pixels G11 to G41, B11 to B41 and G12 to G42 may input the corresponding data voltages. In this way, the polarity of each sub-pixel in the g-th display frame F _ g is made to be in a column inversion manner as shown in fig. 14 a. In the g +1 th display frame F _ g +1, the polarity of the data voltage is inverted once in the 1 st scan stage sm1_ g +1, and when the gate scan signals applied to the gate lines GA1, GA3, GA5, and GA7 are at a high level, the data voltages are applied to the data lines DA1 to DA3, respectively, so that the sub-pixels R11 to R41, R12 to R42, and B12 to B42 can input the corresponding data voltages. In the 2 nd scan phase sm2_ G +1, when the gate scan signals applied to the gate lines GA2, GA4, GA6, and GA8 are at a high level, the data lines DA1 to DA3 are applied with corresponding data voltages, respectively, so that the sub-pixels G11 to G41, B11 to B41, and G12 to G42 can input the corresponding data voltages. The polarities of the sub-pixels in the g +1 th display frame F _ g +1 are inverted in a dot inversion manner as shown in fig. 14 b. In fig. 14a and 14b, "+" represents positive polarity and "-" represents negative polarity. Compared with the mode of repeatedly turning the data voltage in one display frame when the grid line is scanned line by line, the column turning effect can be realized only by turning the polarity of the data voltage once in one display frame, and the power consumption can be reduced. In addition, in each scanning stage, each data line only charges the same color sub-pixel, the data lines do not need to be turned from positive to negative to 0V in monochrome color mixing, turning between the positive and the negative is changed into from 0V to positive or from 0V to negative, pre-charging Margin is increased, the display panel with the Dual Gate structure is better in low-temperature performance, and the problem of vertical stripes of the display panel with the Dual Gate structure in monochrome color mixing can be solved.

In some other embodiments of the present disclosure, the register groups may also be divided into 3 groups, which may also enable the display panel shown in fig. 13 to achieve the dot inversion effect. Moreover, the touch scanning frequency is 3 times of the display scanning frequency, that is, the display panel can realize the display scanning frequency of 60Hz + the touch scanning frequency of 180 Hz.

In still other embodiments of the present disclosure, as shown in fig. 15, a row of sub-pixels is of the same color, and the red sub-pixel row, the green sub-pixel row and the blue sub-pixel row are sequentially and repeatedly arranged. For example, red subpixel columns R11 to R41, green subpixel columns G11 to G41, blue subpixel columns B11 to B41, red subpixel columns R12 to R42, green subpixel columns G12 to G42, and blue subpixel columns B12 to B42. Moreover, one row of the sub-pixels SPX corresponds to two Gate lines (i.e., Dual gates), and two adjacent columns of the sub-pixels SPX correspond to two data lines. The plurality of sub-pixels in the display panel may be divided into a plurality of sub-pixel groups, and each sub-pixel group may include two sub-pixels adjacent in the same row. And one sub-pixel in the sub-pixel group is electrically connected with one of the two corresponding grid lines, and the other sub-pixel is electrically connected with the other of the two corresponding grid lines. And a column of sub-pixel groups may be disposed between every two adjacent data lines, and for the two adjacent data lines, one data line is connected to the odd-numbered row of the column of sub-pixel groups disposed between the two data lines, and the other data line is connected to the even-numbered row of the column of sub-pixel groups disposed between the two data lines. It can also be said that two adjacent columns of sub-pixels are disposed between two adjacent data lines. This can reduce the power consumption of the source driver circuit. For example, as shown in fig. 9, 11a, 11B and 15, in the g-th display frame F _ g, when the gate scan signals applied to the gate lines GA1, GA3, GA5 and GA7 are at a high level in the 1 st scan phase sm1_ g, the data lines DA1 to DA4 are applied with corresponding data voltages, so that the sub-pixels R11 to R41, R12 to R42 and B12 to B42 can be input with corresponding data voltages. In the 2 nd scan phase sm2_ G, when the gate scan signals applied to the gate lines GA2, GA4, GA6, and GA8 are at a high level, the data lines DA1 to DA4 are applied with corresponding data voltages, so that the sub-pixels G11 to G41, B11 to B41, and G12 to G42 can input the corresponding data voltages. In this way, the polarity of each sub-pixel in the g-th display frame F _ g is made to be in a dot inversion manner as shown in fig. 11 a. In the g +1 th display frame F _ g +1, when the gate scan signals applied to the gate lines GA1, GA3, GA5, and GA7 are at a high level in the 1 st scan stage sm1_ g +1, the data lines DA1 to DA4 are applied with the corresponding data voltages, respectively, so that the sub-pixels R11 to R41, R12 to R42, and B12 to B42 can input the corresponding data voltages. In the 2 nd scan phase sm2_ G +1, when the gate scan signals applied to the gate lines GA2, GA4, GA6, and GA8 are at a high level, the data lines DA1 to DA4 are applied with corresponding data voltages, respectively, so that the sub-pixels G11 to G41, B11 to B41, and G12 to G42 can input the corresponding data voltages. The polarities of the sub-pixels in the g +1 th display frame F _ g +1 are inverted in a dot inversion manner as shown in fig. 11 b. Compare like this when progressive scanning grid line, need in a display frame the mode of overturning data voltage many times, this disclosed embodiment can only need in a display frame with data voltage's polarity upset once, can realize some upset effects, can reduce the consumption. And, odd row grid lines charge the red sub-pixel, even row grid lines charge the blue-green color mixture of green sub-pixel and blue sub-pixel, it needs 0V to positive or negative polarity inversion, but there is no continuous pre-charging. Taking a blue-green mixed-color picture (i.e., the blue sub-pixel and the green sub-pixel are lighted, and the red sub-pixel is black) as an example, the prior art has a scheme that the gate lines GA1 to GA8 are scanned line by line, and the blue sub-pixels B12, B23 and the green sub-pixel G23 are precharged continuously, which causes the adjacent green sub-pixel and the blue sub-pixel to be slightly lighted, resulting in a serious vertical stripe of the picture. In the technical solution of the embodiment of the present disclosure, the odd-numbered rows of gate lines are scanned line by line in the 1 st scanning stage, so that the data line DA3 can charge the blue sub-pixels B12 and B32. In the 2 nd scanning stage, the gate lines of the even rows are scanned line by line, so that the data line DA3 charges the green sub-pixel G12, the blue sub-pixel B21, the green sub-pixel G32 and the blue sub-pixel B41 without continuous pre-charging, thereby improving the brightness uniformity of the display screen.

In still other embodiments of the present disclosure, as shown in fig. 16, a row of sub-pixels is the same color, and the red sub-pixel row, the green sub-pixel row, and the blue sub-pixel row are repeatedly arranged in sequence. For example, red subpixel rows R11 to R16, green subpixel rows G11 to G16, blue subpixel rows B11 to B16, red subpixel rows R21 to R26, green subpixel rows G21 to G26, blue subpixel rows B21 to B26, red subpixel rows R31 to R36, and green subpixel rows G31 to G36. And, a row of sub-pixels SPX is correspondingly coupled to a gate line, and a column of sub-pixels SPX is correspondingly coupled to a data line. For example, as shown in fig. 9, 11a, 11B and 16, in the G-th display frame F _ G, when the gate scan signals applied to the gate lines GA1, GA3, GA5 and GA7 are at a high level in the 1 st scan stage sm1_ G, the data lines DA1 to DA6 are applied with corresponding data voltages, respectively, so that the sub-pixels R11 to R16, B11 to B16, G21 to G26 and R31 to R36 can be input with corresponding data voltages. In the 2 nd scan phase sm2_ G, the polarity of the data voltage is inverted once, and when the gate scan signals applied to the gate lines GA2, GA4, GA6, and GA8 are at a high level, the data voltages are applied to the data lines DA1 to DA6, respectively, so that the sub-pixels G11 to G16, R21 to R26, B21 to B26, and G31 to G36 can be inputted with the corresponding data voltages. In this way, the polarity of each sub-pixel in the g-th display frame F _ g is reversed in dot inversion as shown in fig. 11 a. In the G +1 th display frame F _ G +1, when the gate scan signals applied to the gate lines GA1, GA3, GA5, and GA7 are at a high level in the 1 st scan stage sm1_ G +1, the data lines DA1 to DA6 are applied with corresponding data voltages, respectively, so that the sub-pixels R11 to R16, B11 to B16, G21 to G26, and R31 to R36 can input the corresponding data voltages. In the 2 nd scan phase sm2_ G +1, the polarity of the data voltage is inverted once, and when the gate scan signals applied to the gate lines GA2, GA4, GA6 and GA8 are at a high level, corresponding data voltages are applied to the data lines DA1 to DA6, so that the sub-pixels G11 to G16, R21 to R26, B21 to B26 and G31 to G36 can input corresponding data voltages. The polarity of each sub-pixel in the g +1 th display frame F _ g +1 is reversed in dot inversion as shown in fig. 11 b. Compare like this when progressive scanning grid line, need in a display frame the mode of overturning data voltage many times, this disclosed embodiment can only need in a display frame with data voltage's polarity upset once, can realize some upset effects, can reduce the consumption. Moreover, the problem of displaying the horizontal stripes can be avoided.

In some other embodiments of the present disclosure, the register groups may also be divided into 6, and at this time, the number of the frame start signal lines is set to 6, that is, 6 different frame start signals need to be input, so that the display panel shown in fig. 16 can also achieve the dot inversion effect. Moreover, the touch scanning frequency is 6 times of the display scanning frequency, that is, the display panel can realize the display scanning frequency of 60Hz + the touch scanning frequency of 360 Hz. The register groups can also be divided into 3, and at the moment, the number of the frame starting signal lines is set to be 3, namely 3 different frame starting signals are required to be input, and the polarities of adjacent columns in the same row are different, so that the cross striation problem can be improved. Further, this also allows the display panel shown in fig. 16 to achieve an effect similar to dot inversion. Moreover, the touch scanning frequency is 3 times of the display scanning frequency, that is, the display panel can realize the display scanning frequency of 60Hz + the touch scanning frequency of 180 Hz.

In still other embodiments of the present disclosure, as shown in fig. 17, a row of sub-pixels is the same color, and the red, green, and blue rows of sub-pixels are repeatedly arranged in sequence. For example, red subpixel rows R11 to R16, green subpixel rows G11 to G16, blue subpixel rows B11 to B16, red subpixel rows R21 to R26, green subpixel rows G21 to G26, blue subpixel rows B21 to B26, red subpixel rows R31 to R36, and green subpixel rows G31 to G36. In addition, one row of sub-pixels SPX is correspondingly coupled to one gate line, and one column of sub-pixels SPX is correspondingly coupled to two data lines. In the same column of sub-pixels, the sub-pixels in odd rows are coupled to the data line on the left side of the column of sub-pixels, and the sub-pixels in even rows are coupled to the data line on the right side of the column of sub-pixels. For example, as shown in fig. 9, 11a, 11B and 17, in the G-th display frame F _ G, when the gate scan signals applied to the gate lines GA1, GA3, GA5 and GA7 are at a high level in the 1 st scan phase sm1_ G, the data lines DA1 to DA7 are applied with corresponding data voltages, so that the sub-pixels R11 to R16, B11 to B16, G21 to G26 and R31 to R36 may input corresponding data voltages. In the 2 nd scan phase sm2_ G, the polarity of the data voltage is inverted once, and when the gate scan signals applied to the gate lines GA2, GA4, GA6, and GA8 are at a high level, the data voltages are applied to the data lines DA1 to DA7, respectively, so that the sub-pixels G11 to G16, R21 to R26, B21 to B26, and G31 to G36 can be inputted with the corresponding data voltages. In this way, the polarity of each sub-pixel in the g-th display frame F _ g is made to be in a dot inversion manner as shown in fig. 11 a. In the G +1 th display frame F _ G +1, when the gate scan signals applied to the gate lines GA1, GA3, GA5, and GA7 are at a high level in the 1 st scan stage sm1_ G +1, the data lines DA1 to DA7 are applied with corresponding data voltages, respectively, so that the sub-pixels R11 to R16, B11 to B16, G21 to G26, and R31 to R36 can input the corresponding data voltages. In the 2 nd scan phase sm2_ G +1, the polarity of the data voltage is inverted once, and when the gate scan signals applied to the gate lines GA2, GA4, GA6, and GA8 are at a high level, the data voltages are applied to the data lines DA1 to DA7, respectively, so that the sub-pixels G11 to G16, R21 to R26, B21 to B26, and G31 to G36 can input the corresponding data voltages. The polarities of the sub-pixels in the g +1 th display frame F _ g +1 are inverted in a dot inversion manner as shown in fig. 11 b. Compare like this when progressive scanning grid line, need in a display frame the mode of overturning data voltage many times, this disclosed embodiment can only need in a display frame with data voltage's polarity upset once, can realize some upset effects, can reduce the consumption. Moreover, the problem of displaying the horizontal stripes can be avoided.

In still other embodiments of the present disclosure, the register groups may be divided into 3, at this time, the frame start signal lines are set to 3, that is, 3 different frame start signals need to be input, that is, the frame start signals stv1_1, stv2_1 and stv3_1 control the timing, so that a similar dot inversion effect can be achieved, the frame start signal stv1_1 controls one register group to drive the gate lines GA1 and GA4, so that the red subpixels R11 and R22 have the same positive polarity, the red subpixels R12 and R23 have the same negative polarity, the next frame is turned positive and negative, the adjacent red subpixels in the same column can achieve positive and negative polarity alternation, and two adjacent subpixels in the same row have different polarities. For example, the polarity of the first column of subpixels in the previous frame is: + -, the polarity of the first column of sub-pixels in the next frame is- + -. Therefore, with three frame start signals, the display panel shown in fig. 17 can also be made to achieve an effect similar to dot inversion. The frame start signal line and the frame start signal are reduced compared to the architecture of the display panel shown in fig. 16. Moreover, the touch scanning frequency is 3 times of the display scanning frequency, that is, the display panel can realize the display scanning frequency of 60Hz + the touch scanning frequency of 180 Hz.

In still other embodiments of the present disclosure, as shown in fig. 18, a selection control circuit MUX may be further disposed between the driving output terminal of the gate driving circuit and the gate line, so that the gate driving circuit and the selection control circuit MUX are combined to implement interlaced display. Specifically, the selection control circuit MUX may control the grouping of gate lines, for example, the selection control circuit MUX includes a selection control transistor coupled to each gate line, a first pole of the selection control transistor is coupled to the driving output terminal of the shift register, a second pole of the selection control transistor is coupled to the corresponding gate line, and a control pole of the selection control transistor is coupled to the control terminal of the selection gate line. And taking the odd-numbered grid lines as a group and the even-numbered grid lines as a group, coupling the control electrodes of the selection control transistors corresponding to the odd-numbered grid lines with the control end of the same selection grid line, and coupling the control electrodes of the selection control transistors corresponding to the even-numbered grid lines with the control end of the same selection grid line. When only the odd-numbered gate lines are scanned, the selection control transistors corresponding to the odd-numbered gate lines can be controlled to be turned on, and the selection control transistors corresponding to the even-numbered gate lines are controlled to be turned off. When only even-numbered gate lines are scanned, the selection control transistors corresponding to the even-numbered gate lines can be controlled to be turned on, and the selection control transistors corresponding to the odd-numbered gate lines are controlled to be turned off.

It should be noted that, the timing controller is configured to divide a display frame into M scanning phases and N touch phases; in the mth scanning stage of the M scanning stages, loading a frame start signal to a frame start signal line coupled to the mth register group of the M register groups, loading different clock signals to a plurality of clock signal lines, controlling a shift register unit in the mth register group to output a grid scanning signal to a coupled grid line, and loading a cut-off control signal to a frame start signal line coupled to the rest register groups; and loading a cut-off control signal to each frame starting signal line and loading a cut-off control signal to each clock signal line at each of the N touch control stages. The working principle and the specific implementation of the timing controller are the same as those in the above embodiments, and therefore, the working process of the timing controller can be implemented by referring to the specific implementation of the driving method in the above embodiments, and is not described herein again.

It should be noted that the touch driving circuit is configured to set one touch stage of the N touch stages between two adjacent scan stages of the M scan stages, and in the touch stage, scan the touch electrodes in the display panel; n is an integer greater than 0. The working principle and the specific implementation of the timing controller are the same as those in the above embodiments, and therefore, the working process of the touch driving circuit can be implemented by referring to the specific implementation of the driving method in the above embodiments, and is not described herein again.

In specific implementation, in the embodiment of the present disclosure, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein nor should they be construed as limiting the present disclosure.

According to the driving method of the display panel and the display device provided by the embodiment of the disclosure, the scanning stage and the touch stage are set in one display frame, so that the display panel realizes the functions of displaying and touching in a time-sharing manner. In addition, because a new register group is controlled to scan the coupled grid lines in the next scanning stage after the touch control stage is finished, the problem that the horizontal stripes are displayed because the scanning of the shift register is stopped in the middle and then started in the line-by-line scanning in the prior art can be avoided. The embodiment of the disclosure reserves scanning time for other integrated functions, and inserts the scanning time between display scanning stages, thereby avoiding the electric leakage problem of displaying the level for a long time.

As will be appreciated by one skilled in the art, embodiments of the present disclosure may be provided as a method, system, or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and so forth) having computer-usable program code embodied therein.

The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the present disclosure.

It will be apparent to those skilled in the art that various changes and modifications may be made to the disclosed embodiments without departing from the spirit and scope of the disclosed embodiments. Thus, if such modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to encompass such modifications and variations.

Claims

1. A driving method of a display panel, the display panel comprising: the display device comprises a plurality of grid lines, a grid driving circuit respectively coupled with the grid lines, and a plurality of frame starting signal lines coupled with the grid driving circuit; the grid driving circuit comprises a plurality of shift registers, wherein the driving output end of one shift register is coupled with one grid line, the shift registers are divided into M register groups, and different register groups are coupled with different frame starting signal lines; m is an integer greater than 1;

the driving method comprises the following steps:

2. The method for driving a display panel according to claim 1, wherein one of the N touch phases is set between every two adjacent scan phases of the M scan phases.

3. The method according to claim 1, wherein, in two adjacent display frames, the two display frames include a first display frame and a second display frame, and a target touch phase is provided between an mth scanning phase of the first display frame and a1 st scanning phase of the second display frame;

4. The method according to any of claims 1 to 3, wherein the shift registers in each of the register groups are respectively coupled to the gate lines spaced by M-1 rows;

5. The method according to claim 4, wherein the clock signals corresponding to different register sets have the same period and the same timing.

6. A display device, comprising:

7. The display device according to claim 6, wherein the shift registers in each of the register groups are respectively coupled to gate lines spaced by M-1 rows;

8. The display device of claim 7, wherein M is 2, each shift register in a first register group is coupled to a gate line of an odd-numbered row, and each shift register in a second register group is coupled to a gate line of an even-numbered row;

the second register group includes a third cascade group and a fourth cascade group, and the shift registers in the third cascade group are respectively coupled with the grid lines spaced by 3 rows, and the shift registers in the fourth cascade group are respectively coupled with the grid lines spaced by 3 rows.

9. The display device of claim 8, wherein the first register group is disposed at a first end of the plurality of gate lines and the second register group is disposed at a second end of the plurality of gate lines;

10. The display device according to any one of claims 6 to 9, wherein the display panel further comprises: and different register groups are coupled with the same clock signal line.

11. The display device according to claim 10, wherein two adjacent gate lines are taken as a gate line group, and the shift registers corresponding to the same gate line group are coupled to the same clock signal line.

12. The display device according to any one of claims 6 to 9, wherein the shift register includes: an output transistor and a clock selection circuit;

a gate of the output transistor is coupled to a first node, a second pole of the output transistor is coupled to the driving output terminal, and a first pole of the output transistor is coupled to the clock selection circuit;

13. The display device according to claim 12, wherein the display panel further comprises a plurality of selection signal lines;

14. The display device according to claim 13, wherein the shift register further comprises: the circuit comprises an input circuit, a reset circuit, at least one control circuit and pull-down circuits corresponding to the control circuits one to one;

the reset circuit is configured to provide a signal of a second scan selection signal terminal to the first node in response to a signal of a reset signal terminal;

15. The display device according to claim 14, wherein the number of the control circuits is two, a first control circuit of the two control circuits is coupled to a first control signal terminal, and a second control circuit of the two control circuits is coupled to a second control signal terminal;