WO2023241220A1 - Control method and control apparatus for flat panel detector, and flat panel detection apparatus - Google Patents

Abstract

A control method and control apparatus for a flat panel detector, and a flat panel detection apparatus. In the method, shift registers are divided into cascaded groups, different cascaded groups are coupled to different frame start signal lines and different clock signal lines, and according to different reading modes, the cascaded groups may be controlled to implement different working states in the different reading modes. Moreover, in a first reading mode, the effects of row-by-row scanning and row-by-row reading can be realized. In a second reading mode, the effects of multi-row simultaneous scanning and multi-row simultaneous reading can be realized, thereby improving the collection frame frequency while reducing the reading time.

Description

Control method, control device and flat panel detection device for flat panel detector

Cross-references to related applications

This disclosure requires the priority of a Chinese patent application submitted to the China Patent Office on June 16, 2022, with the application number 202210682748.9 and the application name "Control method, control device and flat panel detection device for flat-panel detectors", and its entire content is approved by This reference is incorporated into this disclosure.

Technical field

The present disclosure relates to the field of detection technology, and in particular to a control method, a control device and a flat panel detection device for a flat panel detector.

Background technique

X-ray photography utilizes the short wavelength and easy penetrability of X-rays, as well as the different absorption characteristics of X-rays by different tissues, to image by detecting the intensity of X-rays transmitted through objects. As the core component of the X-ray imaging system, the Flat Panel Detector (FPD) is responsible for converting X-rays into electrical signals and recording the images, which can be displayed on the monitor or stored for subsequent reading.

Contents of the invention

The control method, control device and flat panel detector provided by the embodiments of the present disclosure can reduce the reading time.

Embodiments of the present disclosure provide a control method for a flat panel detector. The flat panel detector includes: a plurality of gate lines, a plurality of data lines arranged insulated and intersecting with the gate lines, and a plurality of data lines formed by the plurality of gate lines and the plurality of gate lines. A detection unit defined by each data line, a gate drive circuit coupled to each of the gate lines, a plurality of frame start signal lines and a plurality of clock signal lines coupled to the gate drive circuit; the gate The pole driving circuit includes a plurality of shift registers, one shift register is coupled to a gate line, the plurality of shift registers are divided into multiple cascade groups, and the shift registers in the same cascade group are arranged in cascade , and different cascade groups are coupled to different frame start signal lines and different clock signal lines;

The driving method includes:

When using the first reading mode, within one frame scanning time, different frame start signals are loaded on each of the frame start signal lines, and different clock signals are loaded on each of the clock signal lines to control each of the The cascade group works sequentially, scans the plurality of gate lines line by line, and collects the detection signals on each of the data lines respectively when the gate lines are scanned, and determines the one-to-one target corresponding to each of the detection units. Detecting signals; wherein each shift register in the same cascade group scans the coupled gate lines line by line;

When the second reading mode is adopted, within one frame scanning time, the same frame start signal is loaded to the frame start signal line coupled to at least part of the cascade group, and the same frame start signal is loaded to the frame start signal line coupled to at least part of the cascade group. The clock signal line is loaded with the same clock signal, controls at least part of the cascade group to work simultaneously, scans adjacent gate lines among the plurality of gate lines simultaneously, and collects the data when the gate lines are scanned. The detection signal on the data line determines the one-to-one target detection signal of the detection unit group; wherein the detection unit group includes a detection unit coupled to a gate line scanned at the same time and coupled to at least one of the data lines, And each shift register in the same cascade group scans the coupled gate lines line by line.

In some possible implementations, the plurality of shift registers are divided into N cascade groups, and each shift register in the same cascade group is coupled to gate lines spaced N-1 rows apart; N is an integer greater than 1;

The frame start signal lines coupled to at least part of the cascade groups are loaded with the same frame start signal, and the clock signal lines coupled to at least part of the cascade groups are loaded with the same clock signal to control at least part of the cascade groups. The cascade group works simultaneously and scans adjacent multiple gate lines among the multiple gate lines at the same time, including:

Taking at least two adjacent gate lines as a gate line group, for one gate line group, load the same frame start signal to the frame start signal line corresponding to the cascade group coupled to the gate line group, and The clock signal line corresponding to the cascade group coupled to the gate line group is loaded with the same clock signal, and the cascade group coupled to the gate line group is controlled to work simultaneously, and the gate lines in the gate line group are simultaneously scanning.

In some possible implementations, two adjacent gate line groups are coupled to different cascade groups. For the first gate line group and the second gate line group of the two adjacent gate line groups, , for the frame start signal corresponding to the cascade group coupled to the first gate line group and the cascade group coupled to the second gate line group The lines are loaded with different frame start signals, and the clock signal lines corresponding to the cascade group coupled to the first gate line group and the cascade group coupled to the second gate line group are loaded with different The clock signal controls the sequential operation of the cascade group coupled to the first gate line group and the cascade group coupled to the second gate line group. The second raster line group is scanned in sequence.

In some possible implementations, two adjacent gate line groups are coupled to the same cascade group, the same frame start signal is loaded on the frame start signal lines corresponding to all the cascade groups, and the same frame start signal is loaded on all the frame start signal lines corresponding to the cascade groups. The clock signal line corresponding to the cascade group is loaded with the same clock signal, controlling all the cascade groups to work simultaneously, and scanning all gate lines in the same gate line group simultaneously.

In some possible implementations, N=4, the plurality of clock signal lines include the first to eighth clock signal lines, and the plurality of frame start signal lines include the first to eighth frame start signal lines. Frame 4 start signal line;

The plurality of cascade groups include a 1st cascade group to a 4th cascade group; wherein the 1st cascade group is coupled to the 4k-3rd gate line, and the 2nd cascade group is coupled to the 4k-th gate line. -2 gate lines are coupled, the 3rd cascade group is coupled with the 4k-2nd gate line, the 4th cascade group is coupled with the 4kth gate line, k is an integer greater than 0; and , the first cascade group is coupled to the first clock signal line, the fifth clock signal line, and the first frame start signal line respectively, and the second cascade group is coupled to the second clock signal line, the sixth clock signal line, respectively. The signal line is coupled to the second frame start signal line. The third cascade group is coupled to the third clock signal line, the seventh clock signal line and the third frame start signal line respectively. The fourth cascade group The groups are respectively coupled to the fourth clock signal line, the eighth clock signal line and the fourth frame start signal line;

When two adjacent gate line groups are coupled to different cascade groups, the first gate line group is coupled to the first cascade group and the second cascade group, and the second gate line group is coupled to the first cascade group and the second cascade group. The gate line group is coupled to the third cascade group and the fourth cascade group, and the same frame start signal is loaded on the first frame start signal line and the second frame start signal line. , the first clock signal line and the second clock signal line are loaded with the same clock signal, the fifth clock signal line and the sixth clock signal line are loaded with the same clock signal; the third clock signal line is loaded with the same clock signal; The frame start signal line and the fourth frame start signal line are loaded with the same frame start signal, the third clock signal line and the fourth clock signal line are loaded with the same clock signal, and the seventh clock signal line is loaded with the same clock signal. The clock signal line and the eighth clock signal line are loaded with the same clock signal;

When two adjacent gate line groups are coupled to the same cascade group, each of the gate line groups is coupled to the first to fourth cascade groups, and for the first frame The start signal line to the fourth frame start signal line are loaded with the same frame start signal, the first clock signal line to the fourth clock signal line are loaded with the same clock signal, and the fifth clock signal line is loaded with the same clock signal. The signal line to the eighth clock signal line is loaded with the same clock signal.

In some possible implementations, the effective level of the frame start signal loaded by the frame start signal line corresponding to the cascade group coupled to the first gate line group is higher than that of the cascade group coupled to the second gate line group. The effective level of the frame start signal loaded on the frame start signal line corresponding to the cascade group is advanced by 1/4 clock cycle;

The clock signal loaded by the clock signal line corresponding to the cascade group coupled to the first gate line group and the clock signal loaded by the clock signal line corresponding to the cascade group coupled to the second gate line group are the same, and the duty cycle of the clock signal loaded by the clock signal line corresponding to the cascade group coupled to the first gate line group is 25%.

In some possible implementations, when using the second reading mode, based on the rule of simultaneously collecting detection signals on m adjacent m data lines to obtain a target detection signal, the one-to-one corresponding detection unit group is determined. Target detection signal; wherein, 2≤m≤M; M is the number of gate lines scanned simultaneously; the detection unit group includes detection units coupled to the gate lines scanned simultaneously and coupled to the m data lines .

In some possible implementations, the cascade group coupled to the odd-numbered gate lines is disposed at the first end of the plurality of gate lines, and the cascade group coupled to the even-numbered gate lines is disposed at the first end of the plurality of gate lines. The second end of the grid line.

A control device for a flat panel detector provided by an embodiment of the present disclosure. The flat panel detector includes: a plurality of gate lines, a plurality of data lines arranged insulated and intersecting with the gate lines, and a plurality of data lines formed by the plurality of gate lines and the plurality of gate lines. A detection unit defined by each data line, a gate drive circuit coupled to each of the gate lines, a plurality of frame start signal lines and a plurality of clock signal lines coupled to the gate drive circuit; the gate The pole driving circuit includes a plurality of shift registers, one shift register is coupled to a gate line, the plurality of shift registers are divided into multiple cascade groups, and the shift registers in the same cascade group are arranged in cascade , and each of the cascade groups is coupled to different frame start signal lines and different clock signal lines;

The control device includes:

The driving circuit is configured to load different frame start signals to each of the frame start signal lines and load different clocks to each of the clock signal lines within one frame scanning time when the first reading mode is adopted. The signal controls each of the cascade groups to work sequentially and scan the plurality of gate lines line by line; when using the second reading mode, within one frame scanning time, at least part of the frames coupled to the cascade groups are scanned. The same frame start signal is loaded on the start signal line, and the same clock signal is loaded on the clock signal line coupled to at least part of the cascade group, and the at least part of the cascade group is controlled to work simultaneously, and the plurality of gate lines are loaded with the same clock signal. Multiple adjacent gate lines are scanned simultaneously; wherein each shift register in the same cascade group scans the coupled gate lines line by line;

The acquisition circuit is configured to collect the detection signals on each of the data lines respectively when the gate line is scanned when the first reading mode is used, and determine the one-to-one target detection of each of the detection units. signal; when using the second reading mode, during the gate line scanning, the detection signal on the data line is collected, and the target detection signal corresponding to the detection unit group is determined one-to-one; wherein, the detection unit group It includes a detection unit coupled to the simultaneously scanned gate lines and coupled to at least one of the data lines.

In some possible implementations, the plurality of shift registers are divided into N cascade groups, and the shift registers in the same cascade group are respectively coupled to gate lines spaced N-1 rows apart; N is greater than an integer of 1;

The driving circuit is further configured to: use at least two adjacent gate lines as a gate line group, and for one gate line group, load the frame start signal line corresponding to the cascade group coupled to the gate line group. The same frame start signal, and the same clock signal is loaded on the clock signal line corresponding to the cascade group coupled to the gate line group, and the cascade group coupled to the gate line group is controlled to work at the same time. The raster lines in the raster line group are scanned simultaneously.

The flat panel detection device provided by the embodiment of the present disclosure includes a flat panel detector and the above-mentioned flat panel detector control device.

Description of the drawings

Figure 1 is a schematic structural diagram of a flat panel detection device in an embodiment of the present disclosure;

Figure 2 is a schematic structural diagram of a flat-panel detector in an embodiment of the present disclosure;

Figure 3 is a schematic structural diagram of a shift register in an embodiment of the present disclosure;

Figure 4a is some signal timing diagrams in embodiments of the present disclosure;

Figure 4b is another signal timing diagram in an embodiment of the present disclosure;

Figure 4c is another signal timing diagram in an embodiment of the present disclosure;

Figure 5 is a schematic structural diagram of a gate drive circuit in an embodiment of the present disclosure;

Figure 6 is another structural schematic diagram of a gate drive circuit in an embodiment of the present disclosure;

Figure 7a is another structural schematic diagram of a gate drive circuit in an embodiment of the present disclosure;

Figure 7b is another structural schematic diagram of a gate drive circuit in an embodiment of the present disclosure;

Figure 7c is another structural schematic diagram of a gate drive circuit in an embodiment of the present disclosure;

Figure 7d is another structural schematic diagram of a gate drive circuit in an embodiment of the present disclosure;

Figure 8 is some flowcharts of control methods in embodiments of the present disclosure;

Figure 9 is another signal timing diagram in an embodiment of the present disclosure;

Figure 10 is another signal timing diagram in an embodiment of the present disclosure;

Figure 11a is another structural schematic diagram of a flat panel detector in an embodiment of the present disclosure;

Figure 11b is another structural schematic diagram of a flat panel detector in an embodiment of the present disclosure;

Figure 12 is another signal timing diagram in an embodiment of the present disclosure;

Figure 13a is another structural schematic diagram of a flat panel detector in an embodiment of the present disclosure;

Figure 13b is another structural schematic diagram of a flat panel detector in an embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. And the embodiments and features in the embodiments of the present disclosure may be combined with each other without conflict. Based on the described embodiments of the present disclosure, those of ordinary skill in the art can make All other embodiments obtained fall within the scope of the present disclosure.

Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the usual meaning understood by a person with ordinary skill in the art to which this disclosure belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprising" mean that the elements or things appearing before the word include the elements or things listed after the word and their equivalents, without excluding other elements or things. Words such as "coupled" or "connected" are not limited to physical or mechanical coupling, but may include electrical coupling, whether direct or indirect.

It should be noted that the sizes and shapes of the figures in the drawings do not reflect true proportions and are only intended to illustrate the present disclosure. And the same or similar reference numbers throughout represent the same or similar elements or elements with the same or similar functions.

Referring to FIGS. 1 and 2 , the flat panel detection device may include a flat panel detector 100 and a flat panel detector control device 200 . The flat panel detector 100 may include: a plurality of gate lines GA (for example, GA1, GA2, GA3, GA4), and a plurality of data lines DA that are insulated and intersected with the gate lines GA (for example, GA1, GA2, GA3, GA4). (for example, DA1, DA2, DA3), a detection unit arranged in an array defined by a plurality of gate lines GA (for example, GA1, GA2, GA3, GA4) and a plurality of data lines DA (for example, DA1, DA2, DA3) SPX, and the gate driving circuit 110 coupled to each gate line GA1, GA2, GA3, and GA4 respectively. The control device 200 may include: a driving circuit 210 and a collection circuit 220. The driving circuit 210 is coupled to the gate driving circuit 110, and the acquisition circuit 220 is coupled to the data lines DA1, DA2, and DA3 respectively.

As shown in FIG. 2 , each detection unit SPX includes a transistor 11 and a photodetector 12 . Among them, one row of detection units SPX corresponds to one gate line, and one column of detection units SPX corresponds to one data line. The gate of the transistor 11 is coupled to the corresponding gate line, the source of the transistor 11 is coupled to the corresponding data line, and the drain of the transistor 11 is coupled to the photodetector 12. It should be noted that in this disclosure, the specific detection The unit arrangement structure and data lines, and the arrangement of scan lines are not limited. For example, the flat panel detector in the embodiment of the present disclosure may be an X-ray flat panel detector. In practical applications, the photodetector 12 may include a scintillator and a photodiode. The scintillator absorbs X-rays and converts them into visible light. The electric diode converts the visible light generated by the scintillator into an electrical signal. When the drive circuit 210 controls the gate drive circuit 110 to scan the gate line, the transistor 11 coupled to the gate line is turned on, so that the electrical signal converted by the photodiode can be The input to the data line is through the turned-on transistor 11. The acquisition circuit 220 can collect signals on the data line and generate a target detection signal, so that imaging can be performed based on the generated target detection signal.

In some embodiments of the present disclosure, the gate driving circuit may include multiple shift registers, and one shift register is coupled to one gate line. For example, as shown in FIG. 3 , the shift register may include: switching transistors M1 to M15 and a storage capacitor CST. Furthermore, the shift register is coupled to the input signal terminal IP, the reset signal terminal RE, the clock signal terminal CLK, the reference voltage terminal VREF, the first scan control terminal VDS, the second scan control terminal VSD, the first conversion control terminal VDD1, the second The conversion control terminal VDD2, the noise reduction control terminal GCL, the driving output terminal GOUT, the first node N1, the second node N2 and the third node N3. The signal timing diagram corresponding to the operation of the shift register shown in Figure 3 in the nth frame Fn can be implemented in various ways. In some examples, the signal timing diagram corresponding to the operation of the shift register shown in Figure 3 in the nth frame Fn can be shown in Figure 4a. The specific working process is basically the same as that in the related art, and will not be described again here. In other examples, the signal timing diagram corresponding to the operation of the shift register shown in Figure 3 in the nth frame Fn can also be shown in Figure 4b. The specific working process is basically the same as that in the related art and will not be described here. Repeat. In some examples, the signal timing diagram corresponding to the operation of the shift register shown in Figure 3 in the nth frame Fn can also be shown in Figure 4c. The specific working process is basically the same as that in related technologies and will not be described here. Repeat. It should be noted that this disclosure only takes the structure of the shift register shown in FIG. 3 as an example. In practical applications, the shift register can also adopt other structures, which is not limited here.

It should be noted that, as shown in Figures 4a to 4c, TS represents the scanning stage, and BT represents the blanking time stage. ip represents the signal of the input signal terminal IP, ck_1~ck_3 respectively represents the clock signal of the clock signal terminal CLK, ga_1~ga_3 respectively represents the gate scan signal of the drive output terminal GOUT, re represents the signal of the reset signal terminal RE, and vds represents the first The signal of the scan control terminal VDS, vsd represents the signal of the second scan control terminal VSD, vdd1 represents the signal of the first conversion control terminal VDD1, vdd2 represents the signal of the second conversion control terminal VDD2, and gcl represents the noise reduction control terminal The signal of GCL, vref represents the signal of the reference voltage terminal VREF. Among them, in Figures 4a to 4c, the clock cycles of the clock signals ck_1 to ck_3 are different. Taking the clock cycle of the clock signal ck_3 as T as an example, the clock cycle of the clock signal ck_2 can be 2T, and the clock cycle of the clock signal ck_1 can be 4T. Of course, in actual applications, the clock periods of the clock signals ck_2 and ck_3 can also be set to other values, which are not limited here.

For example, the driving output terminal GOUT of each shift register is coupled to a gate line in a one-to-one correspondence. The valid levels of the gate scanning signals ga_1 to ga_3 can control the transistors in the detection units coupled to the corresponding gate lines to be turned on, and the invalid levels can control the transistors in the detection units coupled to the corresponding gate lines to be turned off. For example, the switching transistors M1 to M15 are N-type transistors, the effective levels of the gate scanning signals ga_1 to ga_3 can be high level, the inactive levels can be low level, and the signal vref can be a low level fixed voltage. Alternatively, the switching transistors M1 to M15 are P-type transistors, the effective level of the gate scanning signals ga_1 to ga_3 may be low level, the inactive level may be high level, and the signal vref may be a high-level fixed voltage. No limitation is made here.

It should be noted that in the above-mentioned shift register provided by the embodiment of the present disclosure, the switching transistors M1 and M2 are symmetrically designed, and the switching transistors M5 and M6 are symmetrically designed, which can realize functional interchange. Therefore, the above-mentioned shift register provided by the embodiment of the present disclosure is symmetrically designed. Bidirectional scanning is possible. During forward scanning, the switching transistors M1 and M5 are used as input transistors, and the switching transistors M2 and M6 are used as reset transistors. Moreover, taking the effective level of the gate scanning signals ga_1 to ga_3 as high level and the inactive level as low level as an example, the signal vds of the first scanning control terminal VDS is a high-level fixed voltage, and the second scanning control terminal The signal vsd at terminal VSD is a low-level fixed voltage. During reverse scanning, the switching transistors M2 and M6 are used as input transistors, and the switching transistors M1 and M5 are used as reset transistors. Moreover, taking the effective level of the gate scanning signals ga_1 to ga_3 as a high level and the inactive level as a low level as an example, the signal vds of the first scanning control terminal VDS is a low-level fixed voltage, and the second scanning control terminal The signal vsd at terminal VSD is a low-level fixed voltage.

In specific implementation, the signal vdd1 of the first conversion control terminal VDD1 and the signal vdd2 of the second conversion control terminal VDD2 may be high-level and low-level switching pulse signals respectively, and the signal vdd1 of the first conversion control terminal VDD1 and the signal vdd2 of the second conversion control terminal VDD2 may be high-level and low-level switching pulse signals respectively. The level of the signal vdd2 of the second conversion control terminal VDD2 is opposite. Alternatively, the signal vdd1 of the first conversion control terminal VDD1 and the signal vdd2 of the second conversion control terminal VDD2 may also be DC signals respectively. Moreover, when the first conversion control terminal VDD1 is loaded with a high-level DC signal, the second conversion control terminal VDD2 is loaded with no signal or a low-level DC signal. When the second conversion control terminal VDD2 is loaded with a high-level DC signal, the first conversion control terminal VDD1 is loaded with no signal or a low-level DC signal. For example, in the first stage, the signal vdd1 of the first conversion control terminal VDD1 is a high-level signal, and the signal vdd2 of the second conversion control terminal VDD2 is a low-level signal. In the second stage, the signal vdd1 of the first conversion control terminal VDD1 is a low-level signal, and the signal vdd2 of the second conversion control terminal VDD2 is a high-level signal. For example, the maintenance duration of the first phase can be made the same as the maintenance duration of the second phase. For example, the maintenance duration of the first stage and the maintenance duration of the second stage are respectively set to the duration of one frame, the duration of multiple frames, 2s, 1h, or 24h, etc., which are not limited here. Moreover, the first and second phases can be sequenced according to actual applications. For example, the work process in the first phase can be executed first, and then the work process in the second phase can be executed. Alternatively, the work process in the second stage may be executed first, and then the work process in the first stage may be executed.

In some embodiments of the present disclosure, the flat panel detector may further include a plurality of clock signal lines and a plurality of frame start signal lines, and the plurality of clock signal lines and the plurality of frame start signal lines are respectively coupled to the gate drive circuit. catch. In this way, a corresponding clock signal can be input to the gate driving circuit through the clock signal line, and the clock signal is input to the clock signal terminal of the shift register, so that the shift register outputs a gate scanning signal to the coupled gate line. For example, as shown in FIG. 5 , the flat panel detector may include 8 clock signal lines CK1˜CK8 and 4 frame start signal lines STV1˜STV4. Among them, the eight clock signal lines CK1 to CK8 and the four frame start signal lines STV1 to STV4 are respectively coupled to the gate driving circuit 110 . Furthermore, CK1 serves as the first clock signal line, CK2 serves as the second clock signal line, CK3 serves as the third clock signal line, CK4 serves as the fourth clock signal line, CK5 serves as the fifth clock signal line, and CK6 serves as the sixth clock signal line. CK7 serves as the seventh clock signal line, and CK8 serves as the eighth clock signal line. STV1 is used as the start signal line of the first frame, STV2 is used as the start signal line of the second frame, STV3 is used as the start signal line of the third frame, and STV4 is used as the start signal line of the fourth frame. It should be noted that Figure 5 only takes 8 clock signal lines and 4 frame start signal lines as an example. In actual applications, the clock signal The specific number of clock signal lines and frame start signal lines can be determined according to the actual application requirements and is not limited here. For example, it can also be other numbers of clock signal lines and frame start signal lines that are an integer multiple of 2, such as 2, 4 , 6, 10, 12 and other numbers of clock signal lines and frame start signal lines.

In some embodiments of the present disclosure, the shift register in the gate driving circuit is divided into multiple cascade groups. Shift register cascade settings in the same cascade group. Furthermore, different cascade groups are coupled to different frame start signal lines. Furthermore, multiple shift registers are divided into multiple register groups, and the same register group is coupled to the same clock signal line. And between the gate lines coupled to two adjacent shift registers in the same register group, there is at least one gate line coupled to other register groups. For example, multiple shift registers are divided into N cascade groups, and each shift register in the same cascade group is coupled to gate lines spaced by N-1 rows; N is an integer greater than 1. Taking the gate lines GA1 to GA24, the clock signal lines CK1 to CK8 and the frame start signal lines STV1 to STV4 as an example, as shown in Figures 6 to 7d, the gate drive circuit 110 includes shift registers SR1 to SR24. The driving output terminal GOUT of SR1 is coupled to the gate line GA1, the driving output terminal GOUT of the shift register SR2 is coupled to the gate line GA2, the driving output terminal GOUT of the shift register SR3 is coupled to the gate line GA3,... shift register The driving output terminal GOUT of SR23 is coupled to the gate line GA23, and the driving output terminal GOUT of the shift register SR24 is coupled to the gate line GA24. Taking N=4 as an example, the shift registers SR1 to SR24 are divided into four cascade groups: the first cascade group ZSR1 to the fourth cascade group ZSR4. Among them, the first cascade group ZSR1 is coupled to the first frame start signal line STV1, the second cascade group ZSR2 is coupled to the second frame start signal line STV2, and the third cascade group ZSR3 is coupled to the third frame start signal line STV2. The signal line STV3 is coupled, and the fourth cascade group ZSR4 is coupled with the fourth frame start signal line STV4. Moreover, the first cascade group ZSR1 is coupled to the first clock signal line CK1 and the fifth clock signal line CK5, the second cascade group ZSR2 is coupled to the second clock signal line CK2 and the sixth clock signal line CK6, and the third cascade group ZSR2 is coupled to the second clock signal line CK2 and the sixth clock signal line CK6. The cascade group ZSR3 is coupled to the third clock signal line CK3 and the seventh clock signal line CK7, and the fourth cascade group ZSR4 is coupled to the fourth clock signal line CK4 and the eighth clock signal line CK8. And, the first cascade group is coupled to the 4k-3 gate line, the second cascade group is coupled to the 4k-2 gate line, and the third cascade group is coupled to the 4k-2 gate line. , the 4th cascade group is coupled to the 4kth gate line. k is an integer greater than 0.

Exemplarily, as shown in Figure 6 and Figure 7a, the first cascade group ZSR1 includes a shift register SR1, SR5, SR9, SR13, SR17 and SR21. The input signal terminal IP of the shift register SR1 is coupled to the first frame start signal line STV1, the drive output terminal GOUT of the shift register SR1 is coupled to the input signal terminal IP of the shift register SR5, and the drive output of the shift register SR5 The terminal GOUT is coupled to the reset signal terminal RE of the shift register SR1. The driving output terminal GOUT of the shift register SR5 is coupled to the input signal terminal IP of the shift register SR9, and the driving output terminal GOUT of the shift register SR9 is coupled to the reset signal terminal RE of the shift register SR5. The rest can be deduced in the same way and will not be elaborated here. Furthermore, the clock signal terminals of the shift registers SR1, SR9, and SR17 are all coupled to the first clock signal line CK1. The clock signal terminals of the shift registers SR5, SR13, and SR21 are all coupled to the fifth clock signal line CK5.

For example, as shown in Figures 6 and 7b, the second cascade group ZSR2 includes shift registers SR2, SR6, SR10, SR14, SR18 and SR22. The input signal terminal IP of the shift register SR2 is coupled to the second frame start signal line STV2, the drive output terminal GOUT of the shift register SR2 is coupled to the input signal terminal IP of the shift register SR6, and the drive output of the shift register SR6 The terminal GOUT is coupled to the reset signal terminal RE of the shift register SR2. The driving output terminal GOUT of the shift register SR6 is coupled to the input signal terminal IP of the shift register SR10, and the driving output terminal GOUT of the shift register SR10 is coupled to the reset signal terminal RE of the shift register SR6. The rest can be deduced in the same way and will not be elaborated here. Furthermore, the clock signal terminals of the shift registers SR2, SR10, and SR18 are all coupled to the second clock signal line CK2. The clock signal terminals of the shift registers SR6, SR14, and SR22 are all coupled to the sixth clock signal line CK6.

For example, as shown in Figures 6 and 7c, the third cascade group ZSR3 includes shift registers SR3, SR7, SR11, SR15, SR19 and SR23. The input signal terminal IP of the shift register SR3 is coupled to the third frame start signal line STV3. The drive output terminal GOUT of the shift register SR3 is coupled to the input signal terminal IP of the shift register SR7. The drive output of the shift register SR7 The terminal GOUT is coupled to the reset signal terminal RE of the shift register SR3. The driving output terminal GOUT of the shift register SR7 is coupled to the input signal terminal IP of the shift register SR11. The driving output terminal GOUT of the shift register SR11 is coupled to the reset signal terminal RE of the shift register SR7. The rest can be deduced in the same way and will not be elaborated here. Moreover, the clock signal terminals of the shift registers SR3, SR11, and SR19 are all connected to the third The clock signal line CK3 is coupled. The clock signal terminals of the shift registers SR7, SR15, and SR23 are all coupled to the seventh clock signal line CK7.

For example, as shown in Figures 6 and 7d, the fourth cascade group ZSR4 includes shift registers SR4, SR8, SR12, SR16, SR20 and SR24. The input signal terminal IP of the shift register SR4 is coupled to the fourth frame start signal line STV4, the drive output terminal GOUT of the shift register SR4 is coupled to the input signal terminal IP of the shift register SR8, and the drive output of the shift register SR8 The terminal GOUT is coupled to the reset signal terminal RE of the shift register SR4. The driving output terminal GOUT of the shift register SR8 is coupled to the input signal terminal IP of the shift register SR12, and the driving output terminal GOUT of the shift register SR12 is coupled to the reset signal terminal RE of the shift register SR8. The rest can be deduced in the same way and will not be elaborated here. Furthermore, the clock signal terminals of the shift registers SR4, SR12, and SR20 are all coupled to the fourth clock signal line CK4. The clock signal terminals of the shift registers SR8, SR16, and SR24 are all coupled to the eighth clock signal line CK8.

In some embodiments of the present disclosure, the cascade group coupled to the odd-numbered gate lines may be disposed at the first end of the plurality of gate lines, and the cascade group coupled to the even-numbered gate lines may be disposed at the plurality of gate lines. The second end of the grid line. For example, as shown in FIG. 6 , the cascade group coupled to the odd-numbered gate lines can be arranged on the left side of the plurality of gate lines, and the cascade group coupled to the even-numbered gate lines can be arranged on the left side of the plurality of gate lines. The right side of the grid line. That is, the first cascade group ZSR1 and the third cascade group ZSR3 are arranged on the left side of the plurality of gate lines, and the second cascade group ZSR2 and the fourth cascade group ZSR4 are arranged on the left side of the plurality of gate lines.

Shift registers in gate drive circuits in the related art are usually in a row-by-row cascade relationship. Therefore, it can only collect the target detection signal of the detection unit line by line. However, in the field of FPXD (Flat Panel X-ray Detector, X-ray flat panel detector), especially in dynamic DR (Digital Radiation, digital radiation) or CBCT (Cone beam CT, cone beam CT) applications, in order to improve the acquisition Frame rate, to quickly locate lesions, will use the Binning operation, that is, the resolution is reduced by merging multiple rows and columns to read, thereby reducing the reading time and increasing the acquisition frame rate. The gate drive circuit provided by the embodiment of the present disclosure divides the shift register into cascade groups, and the different cascade groups are coupled to different frame start signal lines and different clock signal lines, so that the gate drive circuit can be controlled according to different read modes. Each cascade group achieves different working states in different reading modes. And, in the first reading mode, It can achieve the effect of progressive scanning and line-by-line reading. In the second reading mode, the effect of simultaneous scanning and reading of multiple lines can be achieved, thereby reducing the reading time and increasing the acquisition frame rate.

In some embodiments of the present disclosure, the control method of the flat-panel detector, as shown in Figure 8, may include the following steps:

S10. When using the first reading mode, within one frame scanning time, load different frame start signals to each frame start signal line, load different clock signals to each clock signal line, and control the order of each cascade group. Work, scan multiple raster lines line by line, and collect the detection signals on each data line respectively during the raster line scanning, and determine the target detection signal corresponding to each detection unit; among them, each unit in the same cascade group The shift register scans the coupled gate lines row by row. For example, in the first reading mode, each cascade group outputs the first gate scanning signal to the plurality of gate lines line by line, so as to realize the line-by-line scanning of the plurality of gate lines. Optionally, the effective levels of each first gate scanning signal are maintained for the same duration. Optionally, the effective level of the loaded clock signal in the first read mode is used to output the effective level of the first gate scanning signal. Optionally, the effective levels of the clock signals loaded in the first read mode have the same maintenance period. Optionally, the clock cycles of the clock signals loaded in the first reading mode are the same.

For example, in the first read mode, the signal timing diagram corresponding to the gate driving circuit shown in FIG. 6 is shown in FIG. 9 . Among them, in the first reading mode, ck1_1 represents the clock signal input to the first clock signal line CK1, ck2_1 represents the clock signal input to the second clock signal line CK2, and ck3_1 represents the clock signal input to the third clock signal line CK3. clock signal, ck4_1 represents the clock signal input to the fourth clock signal line CK4, ck5_1 represents the clock signal input to the fifth clock signal line CK5, ck6_1 represents the clock signal input to the sixth clock signal line CK6, ck7_1 represents the clock signal input to the seventh clock signal line CK7, and ck8_1 represents the clock signal input to the eighth clock signal line CK8. stv1_1 represents the frame start signal input to the first frame start signal line STV1, stv2_1 represents the frame start signal input to the second frame start signal line STV2, stv3_1 represents the input to the third frame start signal line STV3 The frame start signal on, stv4_1 represents the frame start signal input to the 4th frame start signal line STV4.

Furthermore, the signal ga1_1 represents the first gate scanning signal output by the gate drive circuit 110 to the gate line GA1, and the signal ga2_1 represents the first gate signal output by the gate drive circuit 110 to the gate line GA2. Scan signal,... signal ga22_1 represents the first gate scanning signal output by the gate driving circuit 110 to the gate line GA22, signal ga23_1 represents the first gate scanning signal output by the gate driving circuit 110 to the gate line GA23, signal ga24_1 represents the first gate scanning signal output by the gate driving circuit 110 to the gate line GA24. Furthermore, taking the high level as the effective level of the first gate scanning signal as an example, the shift register SR1 outputs the first high level of the clock signal ck1_1 to the gate line GA1 to generate the first gate scanning signal. High level in ga1_1. The shift register SR2 outputs the first high level of the clock signal ck2_1 to the gate line GA2 to generate the high level of the first gate scanning signal ga2_1. The shift register SR3 outputs the first high level of the clock signal ck3_1 to the gate line GA3 to generate the high level of the first gate scanning signal ga3_1. The shift register SR4 outputs the first high level of the clock signal ck4_1 to the gate line GA4 to generate the high level of the first gate scanning signal ga4_1. The shift register SR5 outputs the first high level of the clock signal ck5_1 to the gate line GA5 to generate the high level of the first gate scanning signal ga5_1. The shift register SR6 outputs the first high level of the clock signal ck6_1 to the gate line GA6 to generate the high level of the first gate scanning signal ga6_1. The shift register SR7 outputs the first high level of the clock signal ck7_1 to the gate line GA7 to generate the high level of the first gate scanning signal ga7_1. The shift register SR8 outputs the first high level of the clock signal ck8_1 to the gate line GA8 to generate the high level of the first gate scanning signal ga8_1. The shift register SR9 outputs the second high level of the clock signal ck1_1 to the gate line GA9 to generate the high level of the first gate scanning signal ga9_1. The shift register SR10 outputs the second high level of the clock signal ck2_1 to the gate line GA10 to generate the high level of the first gate scanning signal ga10_1. The shift register SR11 outputs the second high level of the clock signal ck3_1 to the gate line GA11 to generate a high level in the first gate scanning signal ga11_1. The shift register SR12 outputs the second high level of the clock signal ck4_1 to the gate line GA12 to generate the high level of the first gate scanning signal ga12_1. The shift register SR13 outputs the second high level of the clock signal ck5_1 to the gate line GA13 to generate the high level of the first gate scanning signal ga13_1. The shift register SR14 outputs the second high level of the clock signal ck6_1 to the gate line GA14 to generate the high level of the first gate scanning signal ga14_1. The shift register SR15 outputs the second high level of the clock signal ck7_1 to the gate line GA15 to generate the first gate scan High level in signal ga15_1. The shift register SR16 outputs the second high level of the clock signal ck8_1 to the gate line GA16 to generate the high level of the first gate scanning signal ga16_1. The rest can be deduced in the same way and will not be elaborated here.

That is to say, the high-level maintenance duration of each clock signal ck1_1 to ck8_1 is the same, and the clock period of each clock signal ck1_1 to ck8_1 is the same. Moreover, the high level of the clock signals ck1_1 to ck8_1 can be their effective levels, and the low level can be their invalid pulses. Of course, when the shift register outputs the low level of the clock signal to generate the low level signal that controls the conduction of the transistor in the first gate scan signal, the low level of the clock signal can be used as its effective level, and the high level level as its invalid pulse.

As shown in Figure 2 and Figure 9, in practical applications, the scintillator absorbs X-rays and converts them into visible light. The photodiode converts the visible light generated by the scintillator into electrical signals. The first gate scanning signals ga1_1~ga24_1 are When the level is high, that is, when the gate lines GA1 to GA24 are scanned, the transistors 11 coupled to the gate lines GA1 to GA24 are turned on. For example, when the first gate scanning signal ga1_1 is high level, that is, when the gate line GA1 is scanned, the transistor 11 in each detection unit coupled to the gate line GA1 is turned on, so that the electrical signal converted by the photodiode can be The turned-on transistor 11 is input to the data lines DA1 to DA3. The collection circuit 220 can collect signals on the data lines DA1 to DA3 and generate target detection signals corresponding to each detection unit in the first row. After that, when the first gate scanning signal ga2_1 is high level, that is, when the gate line GA2 is scanned, the transistor 11 in each detection unit coupled to the gate line GA2 is turned on, so that the electrical signal converted by the photodiode can be The turned-on transistor 11 is input to the data lines DA1 to DA3. The collection circuit 220 can collect signals on the data lines DA1 to DA3 and generate target detection signals corresponding to each detection unit in the second row. The rest are the same, and so on, so I won’t go into details here. In this way, the target detection signal corresponding to each detection unit can be obtained, so that imaging can be performed based on the target detection signal corresponding to each detection unit.

S20. When using the second reading mode, within one frame scanning time, load the same frame start signal to the frame start signal line coupled to at least part of the cascade group, and load the same frame start signal to the frame start signal line coupled to at least part of the cascade group. The clock signal line is loaded with the same clock signal, controls at least part of the cascade group to work at the same time, scans multiple adjacent gate lines among the multiple gate lines at the same time, and collects the detection signal on the data line while scanning the gate lines to determine The target detection signal corresponding to the detection unit group one-to-one; wherein, the detection unit group includes the A detection unit is coupled to a gate line and coupled to at least one data line, and each shift register in the same cascade group scans the coupled gate line line by line. For example, in the second reading mode, each cascade group outputs a second gate scanning signal to the plurality of gate lines to achieve simultaneous scanning of adjacent gate lines among the plurality of gate lines. Optionally, the effective levels of each second gate scanning signal are maintained for the same duration. Optionally, the effective level of the loaded clock signal in the second read mode is used to output the effective level of the second gate scanning signal. Optionally, the effective level of the loaded clock signal in the second read mode has the same maintenance period. Optionally, the clock cycles of the clock signals loaded in the second reading mode are the same.

In some embodiments of the present disclosure, the same frame start signal is loaded on the frame start signal line coupled to at least part of the cascade group, and the same clock signal is loaded on the clock signal line coupled to at least part of the cascade group, and the control At least some of the cascade groups work at the same time, and scan multiple adjacent gate lines among multiple gate lines at the same time, including: taking at least two adjacent gate lines as a gate line group, and for a gate line group, pair and gate lines The frame start signal line corresponding to the group-coupled cascade group is loaded with the same frame start signal, and the clock signal line corresponding to the cascade group coupled to the gate line group is loaded with the same clock signal to control the gate line group The coupled cascade groups work simultaneously, and the gate lines in the gate line group are scanned simultaneously. For example, the number of gate lines in the same gate line group may be N/A. A is an integer, and 1≤A<N, N/A is an integer. For example, when N=4, A=2 or A=1. When A=2, the number of gate lines in the same gate line group can be 2, and the second gate scanning signals loaded by these two gate lines are the same, so that the two gate lines can be driven at the same time. When A=1, the number of gate lines in the same gate line group can be 4, and the second gate scanning signals loaded on these 4 gate lines are the same, so that these 4 gate lines can be driven at the same time. Of course, in actual applications, it can be determined according to the needs of actual applications, and is not limited here.

In some embodiments of the present disclosure, two adjacent gate line groups are coupled to different cascade groups. For the first gate line group and the second gate line group in the two adjacent gate line groups, The frame start signal lines corresponding to the cascade group coupled to the first gate line group and the cascade group coupled to the second gate line group are loaded with different frame start signals, and the frame start signals are loaded with the first gate line The clock signal lines corresponding to the group-coupled cascade group and the cascade group coupled to the second gate line group are loaded with different clock signals to control the cascade group coupled to the first gate line group and the cascade group coupled to the second gate line group. The cascade groups coupled to the two gate line groups work sequentially, scanning the first gate line group and the second gate line group in sequence. For example, the number of gate lines in the first gate line group is the same as the number of gate lines in the second gate line group. The sum of the numbers can be equal to the number of cascade groups. For example, when the number of gate lines in the first gate line group and the number of gate lines in the second gate line group are both 2 gate lines, the first gate line group and the first cascade group ZSR1 and the second level The cascade group ZSR2 is coupled, and the second gate line group is coupled to the third cascade group ZSR3 and the fourth cascade group ZSR4. Moreover, the same frame start signal is loaded to the first frame start signal line and the second frame start signal line, and the same frame start signal is loaded to the third frame start signal line and the fourth frame start signal line. The frame start signal loaded on the first frame start signal line is different from the frame start signal loaded on the third frame start signal line. And, the first clock signal line and the second clock signal line are loaded with the same clock signal, the fifth clock signal line and the sixth clock signal line are loaded with the same clock signal, and the third clock signal line and the fourth clock signal line are loaded with the same clock signal. The same clock signal is loaded, and the same clock signal is loaded to the seventh clock signal line and the eighth clock signal line. Different clock signals are applied to the first clock signal line, the third clock signal line, the fifth clock signal line, and the seventh clock signal line.

In some embodiments of the present disclosure, the clock signal loaded by the clock signal line corresponding to the cascade group coupled to the first gate line group and the clock loaded by the clock signal line corresponding to the cascade group coupled to the second gate line group The clock cycles of the signals are the same, and the duty cycle of the clock signal loaded by the clock signal line corresponding to the cascade group coupled to the first gate line group is 25%. For example, as shown in Figure 10, in the second read mode, ck1_2 represents the clock signal input to the first clock signal line CK1, ck2_2 represents the clock signal input to the second clock signal line CK2, and ck3_2 represents the input The clock signal to the third clock signal line CK3, ck4_2 represents the clock signal input to the fourth clock signal line CK4, ck5_2 represents the clock signal input to the fifth clock signal line CK5, ck6_2 represents the clock signal input to the sixth clock signal For the clock signal on line CK6, ck7_2 represents the clock signal input to the seventh clock signal line CK7, and ck8_2 represents the clock signal input to the eighth clock signal line CK8. Among them, the clock cycles of the clock signals ck1_2 to ck8_2 are the same and the duty cycle is 25%. And, the clock signals ck1_2 and ck2_2 are the same, the clock signals ck3_2 and ck4_2 are the same, the clock signals ck5_2 and ck6_2 are the same, and the clock signals ck7_2 and ck8_2 are the same. Furthermore, the clock signals ck1_2, ck3_2, ck5_2, and ck7_2 are different.

In some embodiments of the present disclosure, the effective level of the frame start signal loaded by the frame start signal line corresponding to the cascade group coupled to the first gate line group is higher than that of the cascade group coupled to the second gate line group. The effective level of the frame start signal loaded on the corresponding frame start signal line is advanced by 1/4 clock cycle. For example, as shown in Figure As shown in 10, in the second reading mode, stv1_2 represents the frame start signal input to the first frame start signal line STV1, stv2_2 represents the frame start signal input to the second frame start signal line STV2, stv3_2 represents the frame start signal input to the third frame start signal line STV3, stv4_2 represents the frame start signal input to the fourth frame start signal line STV4. Among them, the frame start signals stv1_2 and stv2_2 are the same, the frame start signals stv3_2 and stv4_2 are the same, and the effective level of the frame start signal stv1_2 (such as high level) is higher than the effective level of the frame start signal stv3_2 (such as high level). flat) 1/4 clock cycle in advance (this clock cycle is the clock cycle of clock signal ck1_2).

Furthermore, the signal ga1_2 represents the second gate scanning signal output by the gate driving circuit 110 to the gate line GA1, the signal ga2_2 represents the second gate scanning signal output by the gate driving circuit 110 to the gate line GA2, ... the signal ga22_2 represents the second gate scanning signal output by the gate driving circuit 110 to the gate line GA22, the signal ga23_2 represents the second gate scanning signal output by the gate driving circuit 110 to the gate line GA23, and the signal ga24_2 represents the gate driving circuit 110 The second gate scan signal is output to gate line GA24. Furthermore, taking the high level as the effective level of the second gate scanning signal as an example, the shift register SR1 outputs the first high level of the clock signal ck1_2 to the gate line GA1 to generate the second gate scanning signal. High level in ga1_2. The shift register SR2 outputs the first high level of the clock signal ck2_2 to the gate line GA2 to generate a high level in the second gate scanning signal ga2_2. The shift register SR3 outputs the first high level of the clock signal ck3_2 to the gate line GA3 to generate the high level of the second gate scanning signal ga3_2. The shift register SR4 outputs the first high level of the clock signal ck4_2 to the gate line GA4 to generate the high level of the second gate scanning signal ga4_2. The shift register SR5 outputs the first high level of the clock signal ck5_2 to the gate line GA5 to generate the high level of the second gate scanning signal ga5_2. The shift register SR6 outputs the first high level of the clock signal ck6_2 to the gate line GA6 to generate the high level of the second gate scanning signal ga6_2. The shift register SR7 outputs the first high level of the clock signal ck7_2 to the gate line GA7 to generate a high level in the second gate scanning signal ga7_2. The shift register SR8 outputs the first high level of the clock signal ck8_2 to the gate line GA8 to generate the high level of the second gate scanning signal ga8_2. The shift register SR9 outputs the second high level of the clock signal ck1_2 to the gate line GA9 to generate the high level of the second gate scanning signal ga9_2. shift register The controller SR10 outputs the second high level of the clock signal ck2_2 to the gate line GA10 to generate the high level of the second gate scanning signal ga10_2. The shift register SR11 outputs the second high level of the clock signal ck3_2 to the gate line GA11 to generate the high level of the second gate scanning signal ga11_2. The shift register SR12 outputs the second high level of the clock signal ck4_2 to the gate line GA12 to generate the high level of the second gate scanning signal ga12_2. The shift register SR13 outputs the second high level of the clock signal ck5_2 to the gate line GA13 to generate the high level of the second gate scanning signal ga13_2. The shift register SR14 outputs the second high level of the clock signal ck6_2 to the gate line GA14 to generate the high level of the second gate scanning signal ga14_2. The shift register SR15 outputs the second high level of the clock signal ck7_2 to the gate line GA15 to generate the high level of the second gate scanning signal ga15_2. The shift register SR16 outputs the second high level of the clock signal ck8_2 to the gate line GA16 to generate the high level of the second gate scanning signal ga16_2. The rest can be deduced in the same way and will not be elaborated here.

That is to say, the high-level maintenance duration of each clock signal ck1_2 to ck8_2 is the same, and the clock period of each clock signal ck1_2 to ck8_2 is the same. Moreover, the high level of the clock signals ck1_2 to ck8_2 can be their effective levels, and the low level of the clock signals ck1_2 to ck8_2 can be their invalid pulses. Of course, when the shift register outputs the low level of the clock signal to generate the low level signal that controls the conduction of the transistor in the second gate scan signal, the low level of the clock signal can be used as its effective level, and the high level level as its invalid pulse.

In some examples, when the second reading mode is used, the one-to-one corresponding target detection signal of the detection unit group can be determined based on the rule that each data line is collected separately to obtain a target detection signal. The detection unit group includes detection units coupled to simultaneously scanned gate lines and coupled to one data line. Illustratively, as shown in Figure 2, Figure 10 and Figure 11a, in practical applications, the scintillator absorbs X-rays and converts them into visible light, and the photodiode converts the visible light generated by the scintillator into electrical signals. When the polar scanning signals ga1_2 to ga24_2 are at a high level, that is, when the gate lines GA1 to GA24 are scanned, the transistors 11 coupled to the gate lines GA1 to GA24 are turned on. For example, when the second gate scanning signals ga1_2 and ga2_2 are high level at the same time, that is, when the gate lines GA1 and GA2 are scanned at the same time, the transistors 11 in each detection unit coupled to the gate lines GA1 and GA2 are turned on at the same time, then The transistors 11 in the detection units of the first and second rows in the same column are turned on at the same time, which allows The detection signals in the first and second row detection units in the same column are input to the coupled data lines, so that the detection signals in the two detection units are combined into one target detection signal, that is, the first detection signal in the same column. The row and second row of detection units are used as a detection unit group ZSPX. And, when the second gate scanning signals ga3_2 and ga4_2 are high level at the same time, that is, when the gate lines GA3 and GA4 are scanned simultaneously, the transistors 11 in each detection unit coupled to the gate lines GA3 and GA4 are turned on at the same time, Then the transistors 11 in the third and fourth row detection units in the same column are turned on at the same time, which allows the detection signals in the third and fourth row detection units in the same column to be input to the coupled data lines, Thus, the detection signals in the two detection units are combined into one target detection signal, that is, the detection units in the third row and the fourth row in the same column serve as a detection unit group ZSPX. The rest are the same, and so on, so I won’t go into details here. In this way, the signals of two adjacent detection units in each column can be collected simultaneously, and the target detection signals corresponding to each detection unit group ZSPX can be obtained, so that imaging can be performed based on the target detection signals corresponding to each detection unit group ZSPX. This reduces the resolution in the column direction to 1/2 of the original, increases the acquisition frame rate, reduces the reading time, and is conducive to quickly locating the location of the lesion.

In some examples, when using the second reading mode, the one-to-one corresponding target detection signal of the detection unit group can also be determined based on the rule of simultaneously collecting detection signals on m adjacent m data lines to obtain a target detection signal. ; Where, 2≤m≤M; M is the number of gate lines scanned simultaneously; the detection unit group includes detection units coupled to the gate lines scanned simultaneously and coupled to m data lines. For example, as shown in Figure 2, Figure 10 and Figure 11b, when m=2, in practical applications, the scintillator absorbs X-rays and converts them into visible light, and the photodiode converts the visible light generated by the scintillator into electrical signals. , when the second gate scanning signals ga1_2 to ga24_2 are high level, that is, when the gate lines GA1 to GA24 are scanned, the transistors 11 coupled to the gate lines GA1 to GA24 are turned on. For example, when the second gate scanning signals ga1_2 and ga2_2 are high level at the same time, that is, when the gate lines GA1 and GA2 are scanned at the same time, the transistors 11 in each detection unit coupled to the gate lines GA1 and GA2 are turned on at the same time, then The transistors 11 in the first and second row detection units in the same column are turned on at the same time, which enables the first and second row detection units in the first column and the first and second row detection units in the second column to be turned on at the same time. The detection signals in are all input to the coupled data lines, thereby combining the detection signals on the two data lines into one target detection signal, that is, the first and second row detection units in the first column and the second column The first and second rows in The detection unit is used as a detection unit group ZSPX. And, the detection signals in the first and second row detection units in the third column and the first and second row detection units in the fourth column are input to the coupled data lines, so that the two pieces of data are The detection signals on the line are combined into a target detection signal, that is, the detection units in the first row and the second row in the third column and the detection units in the first row and the second row in the fourth column serve as a detection unit group ZSPX. And, the detection signals in the first and second row detection units in the fifth column and the first and second row detection units in the sixth column are input to the coupled data lines, so that the two pieces of data are The detection signals on the line are combined into a target detection signal, that is, the first and second row detection units in the fifth column and the first and second row detection units in the sixth column serve as a detection unit group ZSPX. And, the detection signals in the first and second row detection units in the seventh column and the first and second row detection units in the eighth column are input to the coupled data lines, so that the two pieces of data are The detection signals on the line are combined into a target detection signal, that is, the first and second row detection units in the seventh column and the first and second row detection units in the eighth column serve as a detection unit group ZSPX.

Moreover, when the second gate scanning signals ga3_2 and ga4_2 are high level at the same time, that is, when the gate lines GA3 and GA4 are scanned simultaneously, the transistors 11 in each detection unit coupled to the gate lines GA3 and GA4 are turned on at the same time, then The transistors 11 in the first and second row detection units in the same column are turned on at the same time, which allows the third and fourth row detection units in the first column and the third and fourth row detection units in the second column to be turned on at the same time. The detection signals in are all input to the coupled data lines, thereby combining the detection signals on the two data lines into one target detection signal, that is, the detection units in the third and fourth rows in the first column and the second column The detection units in the third and fourth rows are used as a detection unit group ZSPX. And, the detection signals in the third and fourth row detection units in the third column and the third and fourth row detection units in the fourth column are input to the coupled data lines, thereby converting the two data The detection signals on the line are combined into a target detection signal, that is, the detection units in the third row and the fourth row in the third column and the detection units in the third row and the fourth row in the fourth column serve as a detection unit group ZSPX. And, the detection signals in the third and fourth row detection units in the fifth column and the third and fourth row detection units in the sixth column are input to the coupled data lines, thereby converting the two data The detection signals on the line are combined into a target detection signal, that is, the detection units in the third row and the fourth row in the fifth column and the detection units in the third row and the fourth row in the sixth column serve as a detection unit group ZSPX. And, make the third and fourth rows in the seventh column detect single The detection signals in the unit and the third and fourth row detection units in the eighth column are input to the coupled data lines, thereby combining the detection signals on the two data lines into one target detection signal, that is, the seventh The detection units in the third row and the fourth row in the column and the detection units in the third row and the fourth row in the eighth column serve as a detection unit group ZSPX. The rest are the same, and so on, so I won’t go into details here. In this way, the signals of two adjacent detection units in two adjacent columns (that is, detection units in two rows and two columns) can be collected at the same time, and the target detection signal corresponding to each detection unit group ZSPX can be obtained one-to-one, so as to realize the integration of M rows *M columns of detection units are used as a scanning area to obtain the target detection signal corresponding to each scanning area, so that imaging can be performed based on the target detection signal corresponding to each detection unit group ZSPX. As a result, the resolution in both the column and row directions is reduced to 1/2 of the original, the acquisition frame rate is increased, the reading time is reduced, and it is conducive to quickly locating the location of the lesion.

Embodiments of the present disclosure provide other control methods for flat panel detectors, which are modified from the implementations in the above embodiments. Only the differences between this embodiment and the above-mentioned embodiment will be described below, and the similarities will not be described again.

In some embodiments of the present disclosure, two adjacent gate line groups are coupled to the same cascade group, the same frame start signal is loaded on the frame start signal lines corresponding to all cascade groups, and the same frame start signal is loaded on all cascade groups. The corresponding clock signal line is loaded with the same clock signal, controlling all cascade groups to work simultaneously, and scanning all gate lines in the same gate line group simultaneously. For example, the number of gate lines in the same gate line group is equal to the number of cascade groups. For example, when two adjacent gate line groups are coupled to the same cascade group, the number of gate lines in the gate line group is 4 gate lines, and each gate line group is connected to the first cascade group ZSR1 to the fourth level. Group ZSR4 coupling. Furthermore, the same frame start signal is loaded on the first frame start signal line to the fourth frame start signal line. And, the same clock signal is loaded on the first to fourth clock signal lines, and the same clock signal is loaded on the fifth to eighth clock signal lines. Moreover, the clock signals loaded on the first clock signal line and the fifth clock signal line are different.

In some embodiments of the present disclosure, when two adjacent gate line groups are coupled to the same cascade group, the clock cycle of the clock signal loaded on the first clock signal line and the clock signal loaded on the fifth clock signal line The same, the levels are opposite, and the duty cycle of the clock signal loaded on the first clock signal line is 50%. For example, as shown in Figure 12, in the second read mode, ck1_3 represents the input to the first clock signal The clock signal on line CK1, ck2_3 represents the clock signal input to the second clock signal line CK2, ck3_3 represents the clock signal input to the third clock signal line CK3, ck4_3 represents the clock input to the fourth clock signal line CK4 signal, ck5_3 represents the clock signal input to the fifth clock signal line CK5, ck6_3 represents the clock signal input to the sixth clock signal line CK6, ck7_3 represents the clock signal input to the seventh clock signal line CK7, ck8_3 represents the input to the clock signal on the eighth clock signal line CK8. Among them, the clock cycles of the clock signals ck1_3 to ck8_3 are the same and the duty cycle is 50%. Furthermore, the clock signals ck1_3 to ck4_3 are the same, the clock signals ck5_3 and ck8_3 are the same, and the levels of the clock signals ck1_3 and ck8_3 are opposite.

For example, as shown in Figure 12, in the second reading mode, stv1_3 represents the frame start signal input to the first frame start signal line STV1, and stv2_3 represents the frame start signal input to the second frame start signal line STV2. Frame start signal, stv3_3 represents the frame start signal input to the third frame start signal line STV3, stv4_3 represents the frame start signal input to the fourth frame start signal line STV4. Among them, the frame start signals stv1_3~stv4_3 are the same.

Furthermore, the signal ga1_3 represents the second gate scanning signal output by the gate driving circuit 110 to the gate line GA1, the signal ga2_3 represents the second gate scanning signal output by the gate driving circuit 110 to the gate line GA2, ... the signal ga22_3 represents the second gate scanning signal output by the gate driving circuit 110 to the gate line GA22, the signal ga23_3 represents the second gate scanning signal output by the gate driving circuit 110 to the gate line GA23, and the signal ga24_3 represents the gate driving circuit 110 The second gate scan signal is output to gate line GA24. Furthermore, taking the high level as the effective level of the second gate scanning signal as an example, the shift register SR1 outputs the first high level of the clock signal ck1_3 to the gate line GA1 to generate the second gate scanning signal. High level in ga1_3. The shift register SR2 outputs the first high level of the clock signal ck2_3 to the gate line GA2 to generate the high level of the second gate scanning signal ga2_3. The shift register SR3 outputs the first high level of the clock signal ck3_3 to the gate line GA3 to generate the high level of the second gate scanning signal ga3_3. The shift register SR4 outputs the first high level of the clock signal ck4_3 to the gate line GA4 to generate a high level in the second gate scanning signal ga4_3. The shift register SR5 outputs the first high level of the clock signal ck5_3 to the gate line GA5 to generate a high level in the second gate scanning signal ga5_3. Shift register SR6 will The first high level of the clock signal ck6_3 is output to the gate line GA6 to generate the high level of the second gate scanning signal ga6_3. The shift register SR7 outputs the first high level of the clock signal ck7_3 to the gate line GA7 to generate a high level in the second gate scanning signal ga7_3. The shift register SR8 outputs the first high level of the clock signal ck8_3 to the gate line GA8 to generate a high level in the second gate scanning signal ga8_3. The shift register SR9 outputs the second high level of the clock signal ck1_3 to the gate line GA9 to generate the high level of the second gate scanning signal ga9_3. The shift register SR10 outputs the second high level of the clock signal ck2_3 to the gate line GA10 to generate the high level of the second gate scanning signal ga10_3. The shift register SR11 outputs the second high level of the clock signal ck3_3 to the gate line GA11 to generate the high level of the second gate scanning signal ga11_3. The shift register SR12 outputs the second high level of the clock signal ck4_3 to the gate line GA12 to generate the high level of the second gate scanning signal ga12_3. The shift register SR13 outputs the second high level of the clock signal ck5_3 to the gate line GA13 to generate the high level of the second gate scanning signal ga13_3. The shift register SR14 outputs the second high level of the clock signal ck6_3 to the gate line GA14 to generate the high level of the second gate scanning signal ga14_3. The shift register SR15 outputs the second high level of the clock signal ck7_3 to the gate line GA15 to generate the high level of the second gate scanning signal ga15_3. The shift register SR16 outputs the second high level of the clock signal ck8_3 to the gate line GA16 to generate the high level of the second gate scanning signal ga16_3. The rest can be deduced in the same way and will not be elaborated here.

That is to say, the high-level sustaining time of each clock signal ck1_3 to ck8_3 is the same, and the clock period of each clock signal ck1_3 to ck8_3 is the same. Moreover, the high level of the clock signals ck1_3 to ck8_3 can be their effective level, and the low level can be their invalid pulse. Of course, when the shift register outputs the low level of the clock signal to generate the low level signal that controls the conduction of the transistor in the second gate scan signal, the low level of the clock signal can be used as its effective level, and the high level level as its invalid pulse.

In some examples, when using the second reading mode, the one-to-one corresponding target detection signal of the detection unit group can also be determined based on the rule of simultaneously collecting detection signals on m adjacent m data lines to obtain a target detection signal. ; Where, 2≤m≤M; M is the number of gate lines scanned simultaneously; the detection unit group includes detection units coupled to the gate lines scanned simultaneously and coupled to m data lines. Show For example, as shown in Figure 2, Figure 12 and Figure 13a, when m=2, in practical applications, the scintillator absorbs X-rays and converts them into visible light, and the photodiode converts the visible light generated by the scintillator into electrical signals. , when the second gate scanning signals ga1_3 to ga24_3 are high level, that is, when the gate lines GA1 to GA24 are scanned, the transistors 11 coupled to the gate lines GA1 to GA24 are turned on. For example, when the second gate scanning signals ga1_3 to ga4_3 are at high level at the same time, that is, when the gate lines GA1 to GA4 are scanned simultaneously, the transistors 11 in each detection unit coupled to the gate lines GA1 to GA4 are turned on at the same time, then The transistors 11 in the first to fourth row detection units in the same column are turned on at the same time, which can make the first to fourth row detection units in the first column and the first to fourth row detection units in the second column The detection signals in are all input to the coupled data lines, so that the detection signals on the two data lines are combined into one target detection signal, that is, the detection units in the first row to the fourth row in the first column and the second column The detection units in the first and second rows are used as a detection unit group ZSPX. And, the detection signals in the first to fourth row detection units in the third column and the first to fourth row detection units in the fourth column are all input to the coupled data lines, so that the two pieces of data are The detection signals on the line are combined into a target detection signal, that is, the detection units in the first row to the fourth row in the third column and the detection units in the first row to the fourth row in the fourth column serve as a detection unit group ZSPX. And, the detection signals in the first to fourth row detection units in the fifth column and the first to fourth row detection units in the sixth column are all input to the coupled data lines, so that the two data The detection signals on the line are combined into a target detection signal, that is, the detection units in the first row to the fourth row in the fifth column and the detection units in the first row to the fourth row in the sixth column serve as a detection unit group ZSPX. And, the detection signals in the first to fourth row detection units in the seventh column and the first to fourth row detection units in the eighth column are all input to the coupled data lines, so that the two pieces of data are The detection signals on the line are combined into a target detection signal, that is, the detection units in the first to fourth rows in the seventh column and the detection units in the first to fourth rows in the eighth column serve as a detection unit group ZSPX.

Moreover, when the second gate scanning signals ga5_3 and ga8_3 are high level at the same time, that is, when the gate lines GA5 to GA8 are scanned simultaneously, the transistors 11 in each detection unit coupled to the gate lines GA5 to GA8 are turned on at the same time, then The transistors 11 in the detection units in the fifth to eighth rows in the same column are turned on at the same time, which can enable the detection in the detection units in the fifth to eighth rows in the first column and the detection units in the fifth to eighth rows in the second column. The signals are input to the coupled data lines, so that the detection signals on these two data lines are The detection signals are combined into a target detection signal, that is, the detection units in the fifth to eighth rows in the first column and the detection units in the fifth to eighth rows in the second column serve as a detection unit group ZSPX. And, the detection signals in the fifth to eighth row detection units in the third column and the fifth to eighth row detection units in the fourth column are input to the coupled data lines, thereby connecting the two data lines The detection signals are combined into a target detection signal, that is, the detection units in the fifth to eighth rows in the third column and the detection units in the fifth to eighth rows in the fourth column serve as a detection unit group ZSPX. And, the detection signals in the detection units in the fifth row to the eighth row in the fifth column and the detection units in the fifth row to the eighth row in the sixth column are all input to the coupled data lines, so that the two data lines The detection signals are combined into a target detection signal, that is, the detection units in the fifth row to the eighth row in the fifth column and the detection units in the fifth row to the eighth row in the sixth column serve as a detection unit group ZSPX. And, the detection signals in the fifth to eighth row detection units in the seventh column and the fifth to eighth row detection units in the eighth column are input to the coupled data lines, thereby connecting the two data lines The detection signals are combined into a target detection signal, that is, the detection units in the fifth to eighth rows in the seventh column and the detection units in the fifth to eighth rows in the eighth column serve as a detection unit group ZSPX. The rest are the same, and so on, so I won’t go into details here. In this way, the signals of two adjacent detection units in two adjacent columns can be collected at the same time, and the target detection signals corresponding to each detection unit group ZSPX can be obtained, so that imaging can be performed based on the target detection signals corresponding to each detection unit group ZSPX. . As a result, the resolution in the column direction is reduced to 1/4 of the original, the acquisition frame rate is increased, the reading time is reduced, and it is conducive to quickly locating the location of the lesion.

For example, as shown in Figure 2, Figure 12 and Figure 13b, when m=4, in practical applications, the scintillator absorbs X-rays and converts them into visible light, and the photodiode converts the visible light generated by the scintillator into electrical signals. , when the second gate scanning signals ga1_3 to ga24_3 are high level, that is, when the gate lines GA1 to GA24 are scanned, the transistors 11 coupled to the gate lines GA1 to GA24 are turned on. For example, when the second gate scanning signals ga1_3 to ga4_3 are at high level at the same time, that is, when the gate lines GA1 to GA4 are scanned simultaneously, the transistors 11 in each detection unit coupled to the gate lines GA1 to GA4 are turned on at the same time, then The transistors 11 in the first to fourth row detection units in the same column are turned on at the same time, which can cause the first to fourth row detection units in the first column to the first row to fourth row detection units in the fourth column. The detection signals in are all input to the coupled data lines, thereby combining the detection signals on the two data lines into one The target detection signal, that is, the detection units in the first row to the fourth row in the first column to the detection units in the first row to the fourth row in the fourth column serve as a detection unit group ZSPX. And, the detection signals in the first to fourth row detection units in the fifth column to the first to fourth row detection units in the eighth column are all input to the coupled data lines, so that the two pieces of data are The detection signals on the line are combined into a target detection signal, that is, the detection units in the first to fourth rows in the fifth column to the detection units in the first row to the fourth row in the eighth column serve as a detection unit group ZSPX.

Moreover, when the second gate scanning signals ga5_3 and ga8_3 are high level at the same time, that is, when the gate lines GA5 to GA8 are scanned simultaneously, the transistors 11 in each detection unit coupled to the gate lines GA5 to GA8 are turned on at the same time, then The transistors 11 in the detection units of the fifth to eighth rows in the same column are turned on at the same time, which can enable the detection of the detection units in the fifth to eighth rows of the first column to the fifth to eighth rows of the fourth column. The signals are all input to the coupled data lines, so that the detection signals on the two data lines are combined into a target detection signal, that is, the detection units in the fifth row to the eighth row in the first column to the fifth row to the fourth column. The eighth row of detection units is used as a detection unit group ZSPX. And, the detection signals in the detection units in the fifth to eighth rows in the fifth column to the fifth to eighth rows in the eighth column are all input to the coupled data lines, so that the two data lines The detection signals are combined into a target detection signal, that is, the detection units in the fifth row to the eighth row in the fifth column to the detection units in the fifth row to the eighth row in the eighth column serve as a detection unit group ZSPX. The rest are the same, and so on, so I won’t go into details here. In this way, the signals of four adjacent detection units in four adjacent columns (that is, detection units in four rows and four columns) can be collected at the same time, and the target detection signal corresponding to each detection unit group ZSPX can be obtained one-to-one, so as to realize the detection of M rows. *M columns of detection units are used as a scanning area to obtain the target detection signal corresponding to each scanning area, so that imaging can be performed based on the target detection signal corresponding to each detection unit group ZSPX. As a result, the resolution in both the column and row directions is reduced to 1/4 of the original, the acquisition frame rate is increased, the reading time is reduced, and it is conducive to quickly locating the location of the lesion.

In some embodiments of the present disclosure, the clock period of the clock signal loaded on the clock signal line in the first acquisition mode is greater than the clock period of the clock signal loaded on the clock signal line in the second acquisition mode. For example, in the first acquisition mode, the clock cycles of the clock signals ck1_1 to ck8_1 loaded on the clock signal line are 4T. In the second acquisition mode, the clock signal loaded on the clock signal line The clock period of ck1_2~ck8_2 is 2T, and the clock period of clock signals ck1_3~ck8_3 is T.

An embodiment of the present disclosure also provides a control device for a flat-panel detector, as shown in Figure 1 , including: a driving circuit 210 and a collection circuit 220. Wherein, the driving circuit 210 is configured to load different frame start signals to each frame start signal line and load different clock signals to each clock signal line within one frame scanning time when the first reading mode is adopted. Control each cascade group to work sequentially and scan multiple gate lines line by line; when using the second reading mode, load the same frame start signal line coupled to at least part of the cascade group within one frame scanning time. The frame start signal, and loading the same clock signal to the clock signal lines coupled to at least some of the cascade groups, controlling at least some of the cascade groups to work simultaneously, and scanning multiple adjacent gate lines among the multiple gate lines at the same time; wherein , each shift register in the same cascade group scans the coupled gate lines line by line. The acquisition circuit 220 is configured to, when using the first reading mode, collect the detection signals on each data line respectively during gate line scanning, and determine the one-to-one corresponding target detection signal of each detection unit; when using the second reading mode, In the mode, during gate line scanning, the detection signals on the data lines are collected to determine the target detection signals corresponding to the detection unit group; wherein, the detection unit group includes a detection unit coupled to the gate lines scanned at the same time and connected to at least one data line. Coupled detection unit.

In some embodiments of the present disclosure, multiple shift registers are divided into N cascade groups, and the shift registers in the same cascade group are respectively coupled to gate lines spaced by N-1 rows; N is an integer greater than 1. The driving circuit is further configured to: use at least two adjacent gate lines as a gate line group, and for one gate line group, load the same frame start signal line corresponding to the cascade group coupled to the gate line group. start signal, and load the same clock signal to the clock signal line corresponding to the cascade group coupled to the gate line group, control the cascade group coupled to the gate line group to work at the same time, and scan the gate lines in the gate line group simultaneously .

It should be noted that the working principle and specific implementation of the control device are the same as the principles and implementation of the control method in the above embodiment. Therefore, the working process of the control device can be implemented with reference to the specific implementation of the control method in the above embodiment. , which will not be described in detail here.

Embodiments of the present disclosure also provide a flat-panel detection device, including a flat-panel detector and a control device for the above-mentioned flat-panel detector provided by embodiments of the present disclosure. The principle of solving the problem of the flat panel detection device is similar to that of the control device of the flat panel detector mentioned above. Therefore, the implementation of the flat panel detection device can be referred to the implementation of the control device of the flat panel detector, and the repetitive parts will not be repeated here. It should be noted that for Other essential components of the flat panel detection device are all understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used to limit the present disclosure.

Those skilled in the art will appreciate that embodiments of the present disclosure may be provided as methods, systems, or computer program products. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment that combines software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each process and/or block in the flowchart illustrations and/or block diagrams, and combinations of processes and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine, such that the instructions executed by the processor of the computer or other programmable data processing device produce a use A device for realizing the functions specified in one process or multiple processes of the flowchart and/or one block or multiple blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable memory that causes a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction means, the instructions The device implements the functions specified in a process or processes of the flowchart and/or a block or blocks of the block diagram.

These computer program instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operating steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby executing on the computer or other programmable device. Instructions provide steps for implementing the functions specified in a process or processes of a flowchart diagram and/or a block or blocks of a block diagram.

Although the preferred embodiments of the present disclosure have been described, those skilled in the art will be able to make additional changes and modifications to these embodiments once the basic inventive concepts are apparent. Therefore, it is intended that the appended claims be construed to include the preferred embodiments and all changes and modifications that fall within the scope of this disclosure.

Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without depart from the spirit and scope of the disclosed embodiments. In this way, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and equivalent technologies, the present disclosure is also intended to include these modifications and variations.

Claims (11)

1. A control method for a flat panel detector, wherein the flat panel detector includes: a plurality of gate lines, a plurality of data lines arranged insulated and intersecting with the gate lines, and a plurality of data lines formed by the plurality of gate lines and the plurality of data lines. A line-defined detection unit, a gate drive circuit coupled to each of the gate lines, a plurality of frame start signal lines and a plurality of clock signal lines coupled to the gate drive circuit; the gate drive The circuit includes multiple shift registers, one shift register is coupled to a gate line, the multiple shift registers are divided into multiple cascade groups, the shift registers in the same cascade group are arranged in cascade, and Different cascade groups are coupled to different frame start signal lines and different clock signal lines;

   The driving method includes:

   When using the first reading mode, within one frame scanning time, different frame start signals are loaded on each of the frame start signal lines, and different clock signals are loaded on each of the clock signal lines to control each of the The cascade group works sequentially, scans the plurality of gate lines line by line, and collects the detection signals on each of the data lines respectively when the gate lines are scanned, and determines the one-to-one target corresponding to each of the detection units. Detecting signals; wherein each shift register in the same cascade group scans the coupled gate lines line by line;

   When the second reading mode is adopted, within one frame scanning time, the same frame start signal is loaded to the frame start signal line coupled to at least part of the cascade group, and the same frame start signal is loaded to the frame start signal line coupled to at least part of the cascade group. The clock signal line is loaded with the same clock signal, controls at least part of the cascade group to work simultaneously, scans adjacent gate lines among the plurality of gate lines simultaneously, and collects the data when the gate lines are scanned. The detection signal on the data line determines the one-to-one target detection signal of the detection unit group; wherein the detection unit group includes a detection unit coupled to a gate line scanned at the same time and coupled to at least one of the data lines, And each shift register in the same cascade group scans the coupled gate lines line by line.
2. The control method of the flat panel detector according to claim 1, wherein the plurality of shift registers are divided into N cascade groups, and each shift register in the same cascade group is separated by N-1 rows. gate line coupling; N is an integer greater than 1;

   The frame start signal lines coupled to at least part of the cascade groups are loaded with the same frame start signal, and the clock signal lines coupled to at least part of the cascade groups are loaded with the same clock signal to control the At least some of the cascade groups work simultaneously to simultaneously scan adjacent multiple gate lines among the multiple gate lines, including:

   Taking at least two adjacent gate lines as a gate line group, for one gate line group, load the same frame start signal to the frame start signal line corresponding to the cascade group coupled to the gate line group, and The clock signal line corresponding to the cascade group coupled to the gate line group is loaded with the same clock signal, and the cascade group coupled to the gate line group is controlled to work simultaneously, and the gate lines in the gate line group are simultaneously scanning.
3. The control method of the flat panel detector according to claim 2, wherein the two adjacent grid line groups are coupled to different cascade groups. For the first grid line in the two adjacent grid line groups, group and the second gate line group, loading different frame start signal lines corresponding to the cascade group coupled to the first gate line group and the cascade group coupled to the second gate line group. a frame start signal, and load different clock signals on the clock signal lines corresponding to the cascade group coupled to the first gate line group and the cascade group coupled to the second gate line group, Control the cascade group coupled to the first gate line group and the cascade group coupled to the second gate line group to work sequentially, for the first gate line group and the second gate line group The raster line groups are scanned in sequence.
4. The control method of the flat panel detector according to claim 2, wherein the cascade groups coupled to two adjacent gate line groups are the same, and the same frame is loaded to the frame start signal lines corresponding to all the cascade groups. start signal, and load the same clock signal to the clock signal lines corresponding to all the cascade groups, control all the cascade groups to work at the same time, and scan all the gate lines in the same gate line group at the same time.
5. The control method of a flat panel detector according to claim 3 or 4, wherein N=4, the plurality of clock signal lines include a first clock signal line to an eighth clock signal line, and the plurality of frame start signals The lines include the first frame start signal line to the fourth frame start signal line;

   The plurality of cascade groups include a 1st cascade group to a 4th cascade group; wherein the 1st cascade group is coupled to the 4k-3rd gate line, and the 2nd cascade group is coupled to the 4k-th gate line. -2 gate lines are coupled, the 3rd cascade group is coupled with the 4k-2nd gate line, the 4th cascade group is coupled with the 4kth gate line, k is an integer greater than 0; and , the first cascade group is coupled to the first clock signal line, the fifth clock signal line, and the first frame start signal line respectively, and the second cascade group is coupled to the second clock signal line, the sixth clock signal line, respectively. The signal line is coupled to the second frame start signal line, and the third cascade group is respectively connected to the third clock signal line, The seventh clock signal line and the third frame start signal line are coupled, and the fourth cascade group is coupled to the fourth clock signal line, the eighth clock signal line, and the fourth frame start signal line respectively;

   When two adjacent gate line groups are coupled to different cascade groups, the first gate line group is coupled to the first cascade group and the second cascade group, and the second gate line group is coupled to the first cascade group and the second cascade group. The gate line group is coupled to the third cascade group and the fourth cascade group, and the same frame start signal is loaded on the first frame start signal line and the second frame start signal line. , the first clock signal line and the second clock signal line are loaded with the same clock signal, the fifth clock signal line and the sixth clock signal line are loaded with the same clock signal; the third clock signal line is loaded with the same clock signal; The frame start signal line and the fourth frame start signal line are loaded with the same frame start signal, the third clock signal line and the fourth clock signal line are loaded with the same clock signal, and the seventh clock signal line is loaded with the same clock signal. The clock signal line and the eighth clock signal line are loaded with the same clock signal;

   When two adjacent gate line groups are coupled to the same cascade group, each of the gate line groups is coupled to the first to fourth cascade groups, and for the first frame The start signal line to the fourth frame start signal line are loaded with the same frame start signal, the first clock signal line to the fourth clock signal line are loaded with the same clock signal, and the fifth clock signal line is loaded with the same clock signal. The signal line to the eighth clock signal line is loaded with the same clock signal.
6. The control method of the flat panel detector according to claim 5, wherein the effective level of the frame start signal loaded by the frame start signal line corresponding to the cascade group coupled to the first gate line group is greater than the The effective level of the frame start signal loaded on the frame start signal line corresponding to the cascade group coupled to the second gate line group is advanced by 1/4 clock cycle;

   The clock signal loaded by the clock signal line corresponding to the cascade group coupled to the first gate line group and the clock signal loaded by the clock signal line corresponding to the cascade group coupled to the second gate line group are the same, and the duty cycle of the clock signal loaded by the clock signal line corresponding to the cascade group coupled to the first gate line group is 25%.
7. The control method of a flat panel detector according to any one of claims 1 to 4, wherein when the second reading mode is adopted, a target is obtained based on the simultaneous collection of detection signals on m adjacent m data lines. The rules for detecting signals determine the one-to-one target detection signals of the detection unit group; where, 2≤m≤M; M is the number of gate lines scanned simultaneously; the detection unit group includes the A detection unit coupled to the gate lines and coupled to the m data lines.
8. The control method of a flat panel detector according to any one of claims 1 to 4, wherein the cascade group coupled to the odd-numbered gate lines is disposed at the first end of the plurality of gate lines and connected to the even-numbered gate lines. A cascade group of gate line couplings is provided at the second end of the plurality of gate lines.
9. A control device for a flat panel detector, wherein the flat panel detector includes: a plurality of gate lines, a plurality of data lines arranged insulated and intersecting with the gate lines, and a plurality of data lines formed by the plurality of gate lines and the plurality of data lines. A line-defined detection unit, a gate drive circuit coupled to each of the gate lines, a plurality of frame start signal lines and a plurality of clock signal lines coupled to the gate drive circuit; the gate drive The circuit includes multiple shift registers, one shift register is coupled to a gate line, the multiple shift registers are divided into multiple cascade groups, the shift registers in the same cascade group are arranged in cascade, and Each of the cascade groups is coupled to a different frame start signal line and a different clock signal line;

   The control device includes:

   The driving circuit is configured to load different frame start signals to each of the frame start signal lines and load different clocks to each of the clock signal lines within one frame scanning time when the first reading mode is adopted. The signal controls each of the cascade groups to work sequentially and scan the plurality of gate lines line by line; when using the second reading mode, within one frame scanning time, at least part of the frames coupled to the cascade groups are scanned. The same frame start signal is loaded on the start signal line, and the same clock signal is loaded on the clock signal line coupled to at least part of the cascade group, and the at least part of the cascade group is controlled to work simultaneously, and the plurality of gate lines are loaded with the same clock signal. Multiple adjacent gate lines are scanned simultaneously; wherein each shift register in the same cascade group scans the coupled gate lines line by line;

   The acquisition circuit is configured to collect the detection signals on each of the data lines respectively when the gate line is scanned when the first reading mode is used, and determine the one-to-one target detection of each of the detection units. signal; when using the second reading mode, during the gate line scanning, the detection signal on the data line is collected, and the target detection signal corresponding to the detection unit group is determined one-to-one; wherein, the detection unit group It includes a detection unit coupled to the simultaneously scanned gate lines and coupled to at least one of the data lines.
10. The control device of the flat panel detector according to claim 9, wherein the plurality of shift The registers are divided into N cascade groups, and the shift registers in the same cascade group are respectively coupled to gate lines spaced by N-1 rows; N is an integer greater than 1;

    The driving circuit is further configured to: use at least two adjacent gate lines as a gate line group, and for one gate line group, load the frame start signal line corresponding to the cascade group coupled to the gate line group. The same frame start signal, and the same clock signal is loaded on the clock signal line corresponding to the cascade group coupled to the gate line group, and the cascade group coupled to the gate line group is controlled to work at the same time. The raster lines in the raster line group are scanned simultaneously.
11. A flat panel detection device, which includes a flat panel detector and a control device for the flat panel detector as claimed in claim 9 or 10.