JP2014241458A - Solid state image sensor and camera system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state image sensor and a camera system capable of transmitting digital array data obtained by AD conversion to a signal processing circuit of a subsequent stage while suppressing increase in power consumption and reduction in data rate without using a sense amplifier circuit.SOLUTION: A pixel signal read-out part comprises: a holding part which holds digital signals obtained by an AD conversion part; and bus wirings for outputting the digital data held by the holding part to a transmission part. The transmission part shares a plurality of the bus wirings of a small scale as a single group, and selects and transmits the digital signals on group-by-group basis.

Description

  The present technology relates to a solid-state imaging device represented by a CMOS (Complimentary Metal Oxide Semiconductor) image sensor and a camera system.

On the other hand, the CMOS image sensor has an FD (Floating Diffusion) amplifier for each pixel, and its output selects a single row in the pixel array and reads them in the column direction at the same time. The output type is mainstream.
This is because it is difficult to obtain a sufficient driving capability with an FD amplifier arranged in a pixel, and therefore it is necessary to lower the data rate, and parallel processing is advantageous.

  Various pixel signal readout (output) circuits for column parallel output type CMOS image sensors have been proposed. One of the most advanced forms is a type in which an analog-digital conversion device (hereinafter abbreviated as ADC (Analog digital converter)) is provided for each column and a pixel signal is extracted as a digital signal.

That is, as a means for reading out pixel signals at high speed in a CMOS image sensor, the output signal lines of the pixels arranged in a two-dimensional manner are shared for each column, and a readout circuit is provided for each column and driven simultaneously. There is a method of performing large-scale parallel processing.
Here, in a system that performs analog-to-digital (AD) conversion in the readout circuit of each column and transmits the digital signal to the subsequent digital signal processing circuit at high speed, the digital output signal of the large-scale array is transmitted at high speed. Means are needed.
As a general means, there is a method in which an output signal line is shared through a switch and read by a sense amplifier circuit.
In this technique, a signal is read out by exclusive control in which only the output switch to be read is turned on and the others are turned off, and the switches are sequentially controlled at high speed to sequentially read the data in each column.
A specific configuration example of this type of column-parallel ADC-mounted CMOS image sensor will be described (for example, see Patent Document 1 and Non-Patent Document 1).

  FIG. 1 is a block diagram illustrating a configuration example of a column parallel ADC-mounted CMOS image sensor using a sense amplifier in a data transfer system.

  The solid-state imaging device 10 includes a pixel array unit 11 as an imaging unit, a vertical scanning circuit 12, a horizontal scanning circuit 13, a timing control circuit 14, a column ADC group 15, a reference voltage generation circuit 16, and a sense amplifier circuit (S / A). 17 and a digital signal processing circuit 18.

The pixel array unit 11 includes unit pixels 11A including photodiodes and in-pixel amplifiers arranged in a matrix (matrix).
In the solid-state imaging device 10, as a control circuit for sequentially reading out signals from the pixel array unit 11, a timing control circuit 14 that generates an internal clock, a vertical scanning circuit 12 that controls row address and row scanning, a column address and column scanning, and the like. A horizontal column scanning circuit 13 for controlling the above is arranged.

The column ADC group 15 includes an AD conversion unit 15-1, a memory 15-2, and a switch 15-3 arranged for each output signal line 19 of each column.
The AD conversion unit 15-1 compares a ramp waveform RAMP obtained by changing the reference voltage generated by the reference voltage generation circuit 16 in a staircase pattern with an analog signal obtained from the unit pixel 11A via the signal line 19. A comparator is provided corresponding to each column of the array.
Further, the AD conversion unit 15-1 has an asynchronous up / down counter (hereinafter referred to as a counter) having a function of receiving an output of the comparator and a clock and performing an up / down count (or down count) and holding a count value. .
The output of the counter of the AD conversion unit 15-1 is held in the memory 15-2, and the output of the memory 15-2 is connected to the corresponding data transfer line 20 via the switch 15-3.
A sense amplifier circuit 17 corresponding to the data transfer line 20 is connected to the data transfer line 20, and a digital signal processing circuit 18 is disposed at the output of the sense amplifier circuit 17.

The counter having a function as a holding circuit of the AD conversion unit 15-1 is initially in, for example, an up-count (or down-count) state, performs a reset count, and performs an up-count operation when the output of the corresponding comparator is inverted. Stops and the count value is held.
At this time, the initial value of the counter is an arbitrary value of the AD conversion gradation, for example, 0. During the reset count period, the reset component ΔV of the unit pixel 11A is read out.
Thereafter, the counter enters a down-count (or up-count) state, performs data count corresponding to the incident light quantity, and when the output of the corresponding comparator is inverted, the count value corresponding to the comparison period is held in the memory 15-2. The
The counter value held in the memory 15-2 is scanned by the horizontal scanning circuit 13 and input as a digital signal to the digital signal processing circuit 18 through the data transfer line 20 and the sense amplifier circuit 17.

  The horizontal scanning circuit 13 is activated, for example, when a start pulse and a master clock are supplied, and drives the corresponding switch 15-3 in synchronization with the drive clock corresponding to the master clock to latch the memory 15-2. Data is read by the data transfer line 20.

In the solid-state imaging device 10 having such a configuration, the following processing is performed within one horizontal unit period (1H).
That is, in 1H, the first reading from the unit pixel 11A in any row to the signal line 19 is P-phase reading PR, and the first comparison in the comparator is P-phase comparison PC. Then, each operation is continuously performed by setting the second reading as the D-phase reading DR, the comparison in the comparator as the D-phase comparison DC, and the post-processing after the D-phase processing as the D-phase post-processing DAP.

  Timing control of these P-phase readout PR, P-phase comparison PC, D-phase readout DR, D-phase comparison DC, and D-phase post-processing DAP is performed in the timing control circuit 14.

JP-A-2005-278135

W. Yang et al. (W. Yang et. Al., “An Integrated 800x600 CMOS Image System,” ISSCC Digest of Technical Papers, pp. 304-305, Feb., 1999)

  By the way, with the progress of microfabrication technology for semiconductor processes, CMOS transistors have become smaller and the power supply voltage has been lowered to operate at high speed and with low power consumption.

  However, there is a problem such as off-leakage, and the threshold voltage of the transistor itself is not lowered, and there is a problem that the operating voltage margin of an analog circuit such as a sense amplifier is reduced as the power supply voltage is lowered.

In addition, in the case where complicated random access is not required and it is only necessary to sequentially access in order, a method of propagating the digital output signals of each column through the shift register 21 as shown in FIG.
However, this requires a high-speed clock signal to be applied to the majority of the shift resist flip-flop circuits (FF) 15-4 in all the columns, resulting in a problem that current consumption becomes very large.

  The present technology provides a solid-state imaging device capable of transmitting digital array data after AD conversion to a subsequent signal processing circuit without using a sense amplifier circuit and suppressing an increase in power consumption and a decrease in data rate And providing a camera system.

  A solid-state imaging device according to a first aspect of the present technology includes a pixel array unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix, and a pixel signal is read from the pixel array unit in units of a plurality of pixels. A pixel AD converter that performs analog-to-digital conversion every time, a pixel signal readout unit that outputs a digital signal, and a transmission unit that transmits the digital signal output from the pixel signal readout unit. The reading unit includes a holding unit that holds a digital signal from the AD conversion unit, and a bus wiring for outputting the digital data held in the holding unit to the transmission unit. The bus wiring is shared as a group.

  The solid-state imaging device according to the second aspect of the present technology includes a pixel array unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix, and reads out pixel signals from the pixel array unit in units of a plurality of pixels. A column AD conversion unit that performs analog-digital conversion for each column, a pixel signal reading unit that outputs a digital signal, and a transmission unit that transmits the digital signal output from the pixel signal reading unit, The pixel signal readout unit is arranged for each column and includes a plurality of holding units that hold digital signals from the AD conversion unit. The plurality of holding units on a scale smaller than the entire column are grouped, and the group is A plurality of sub-groups are formed together in a plurality of units, and the plurality of sub-groups are combined to form at least one main group. Arranged bus lines for transmitting selectively the transmitter digital signals held in the holding section of each column, respectively, the transmission unit is configured to share a plurality of the bus lines in the sub-group basis.

  A camera system according to a third aspect of the present technology includes a solid-state imaging device and an optical system that forms a subject image on the solid-state imaging device, and the solid-state imaging device includes a plurality of pixels that perform photoelectric conversion. A pixel signal that outputs a digital signal, including a pixel array unit arranged in a matrix and a column AD conversion unit that reads out a pixel signal from the pixel array unit in units of a plurality of pixels and performs analog-digital conversion for each column A reading unit; and a transmission unit that transmits a digital signal output from the pixel signal reading unit. The pixel signal reading unit includes a holding unit that holds a digital signal from the AD conversion unit, and a holding unit. Bus wiring for outputting the held digital data to the transmission unit, and the transmission unit shares the plurality of bus wirings as one group.

  A camera system according to a fourth aspect of the present technology includes a solid-state imaging device and an optical system that forms a subject image on the solid-state imaging device, and the solid-state imaging device includes a plurality of pixels that perform photoelectric conversion. A pixel signal reading unit that includes a pixel unit arranged in a matrix and a column AD conversion unit that reads out pixel signals from the pixel unit in units of a plurality of pixels and performs analog-digital conversion for each column, and outputs a digital signal And a transmission unit that transmits the digital signal output from the pixel signal readout unit, wherein the pixel signal readout unit is arranged for each column, and holds a digital signal by the AD conversion unit A plurality of the holding units on a scale smaller than the entire column as one group, and the groups are grouped into a plurality of units to form a plurality of subgroups. The loops are grouped to form at least one main group, and for each of the groups, a bus wiring for selectively transmitting the digital signal held in the holding unit of each column to the transmission unit is arranged, and the transmission unit Share a plurality of bus lines in units of subgroups.

  According to the present technology, digital array data after AD conversion can be transmitted to a subsequent signal processing circuit while suppressing an increase in power consumption and a decrease in data rate without using a sense amplifier circuit.

It is a block diagram which shows the example of a structure of the column parallel ADC mounting CMOS image sensor which used the sense amplifier for the data transfer system. It is a block diagram which shows the structural example of the column parallel ADC mounting CMOS image sensor which used the shift register instead of the sense amplifier for the data transfer system. It is a figure which shows the 1st structural example of the column parallel ADC mounting CMOS image sensor (solid-state image sensor) which concerns on this embodiment. It is a figure which shows the operation | movement outline | summary of the transmission circuit in the CMOS image sensor (solid-state image sensor) of FIG. It is a figure which shows the 2nd structural example of the CMOS image sensor (solid-state image sensor) mounted with column parallel ADC which concerns on this embodiment. It is a figure which shows the operation | movement outline | summary of the transmission circuit in the CMOS image sensor (solid-state image sensor) of FIG. It is a figure which shows an example of the laminated structure of the CMOS image sensor (solid-state image sensor) which concerns on this embodiment. It is a figure which shows the example of circuit arrangement | positioning of two chips | tips where the CMOS image sensor (solid-state image sensor) which concerns on this embodiment is laminated | stacked. It is a figure which shows the example of circuit arrangement | positioning which arrange | positioned all the circuits of FIG. 1 on one chip as a comparative example. It is a figure showing an example of the composition of the camera system to which the solid-state image sensing device concerning an embodiment of this art is applied.

Hereinafter, embodiments of the present technology will be described with reference to the drawings.
The description will be given in the following order.
1. 1. First configuration example of solid-state imaging device 2. Second configuration example of solid-state imaging device 3. Laminated structure of solid-state imaging device Configuration example of camera system

<1. First Configuration Example of Solid-State Image Sensor>
FIG. 3 is a diagram showing a first configuration example of the column parallel ADC-mounted CMOS image sensor (solid-state imaging device) according to the present embodiment.

The CMOS image sensor (solid-state imaging device) 100 includes a pixel array unit 110, a vertical scanning circuit 120, a timing control circuit 130, a column ADC group 140, a reference voltage generation circuit 150, a transmission circuit 160, and a digital signal processing circuit 170. .
The vertical scanning circuit 120, the timing control circuit 130, the column ADC group 140, the reference voltage generation circuit 150, and the digital signal processing circuit 170 form a pixel signal reading unit.

The pixel array unit 110 is configured by unit pixels 110A including photoelectric conversion elements (photodiodes) and in-pixel amplifiers arranged in a matrix (matrix).
The pixel array unit 110 reads the pixel signal VSL to the output signal line LSGN in units of a plurality of pixels.
In the CMOS image sensor 100, the following circuit is arranged as a control circuit for sequentially reading out signals from the pixel array unit 110.
That is, a timing control circuit 130 that generates an internal clock, a vertical scanning circuit 120 that controls row addresses and row scanning, and a digital processing circuit 170 that controls column addresses and column scanning are arranged.

The column ADC group 140 includes an AD conversion unit 141 (−0 to −N) arranged for each output signal line LSGN of each column, a memory 142 (−0 to −N) as a holding unit, and a bus wiring 143 (− 0 to -N).
The memory 142 (−0 to −N) arranged for each column includes a number of memories corresponding to the number of bits of the resolution (about 8 to 16 bits) of the AD conversion unit 141.
The bus wiring 143 arranged for each column transmits the digital signals held in all the memories corresponding to the resolution to the transmission circuit 160.

As described above, the AD conversion unit 141 has an AD conversion function with a resolution of about 8 bits to 16 bits.
The AD conversion unit 141 compares each ramp waveform RAMP obtained by changing the reference voltage generated by the reference voltage generation circuit 150 in a stepped manner with an analog signal obtained from the unit pixel 110A via the signal line LSGN. Comparators provided corresponding to the columns are included.
Further, the AD conversion unit 141 has an asynchronous up / down counter (hereinafter referred to as a counter) having a function of receiving an output of the comparator and a clock and performing an up / down count (or down count) and holding a count value.
The outputs of the counters of the AD conversion unit 141 are held in the memory 142, and the outputs of all the memories 142 corresponding to the resolution are transmitted to the transmission circuit 160 via the bus wiring 143 (-0 to -N).

The counter of the AD conversion unit 141 is initially in, for example, an up-count (or down-count) state, performs a reset count, stops the up-count operation when the output of the corresponding comparator is inverted, and holds the count value. .
At this time, the initial value of the counter is an arbitrary value of the AD conversion gradation, for example, 0. During the reset count period, the reset component ΔV of the unit pixel 110A is read out.
Thereafter, the counter enters a down count (or up count) state, performs data count corresponding to the incident light quantity, and when the output of the corresponding comparator is inverted, the count value corresponding to the comparison period is held in the memory 142.
The counter value held in the memory 142 is transmitted to the transmission circuit 160 via the bus wiring 143.

In the CMOS image sensor 100 having such a configuration, the following processing is performed within one horizontal unit period (1H).
That is, in 1H, the first reading from the unit pixel 110A in any row to the signal line LSGN is P-phase reading PR, and the first comparison in the comparator is P-phase comparison PC. Then, each operation is continuously performed by setting the second reading as the D-phase reading DR, the comparison in the comparator as the D-phase comparison DC, and the post-processing after the D-phase processing as the D-phase post-processing DAP.
Timing control of these P-phase readout PR, P-phase comparison PC, D-phase readout DR, D-phase comparison DC, and D-phase post-processing DAP is performed in the timing control circuit 130.

The transmission circuit 160 periodically shares a plurality of bus wirings (columns) 143 as a group on a scale smaller than the entire column N, selects a digital signal in units of group GRP, and transmits the digital signal to the digital signal processing circuit 170. .
In the example of FIG. 3, the bus wiring 140-0 of the column CLM0 and the bus wiring 143-1 of the column CLM1 are set as a group GRP0.
The bus wiring 140-2 of the column CLM2 and the bus wiring 143-3 of the column CLM3 are set as a group GRP1.
The bus wiring 140-4 of the column CLM4 and the bus wiring 143-5 of the column CLM5 are set as a group GRP2.
In the example of FIG. 3, two columns are set as one group, but three or more columns can be set as one group.

The transmission circuit 160 is arranged corresponding to each group GRP0, and individually receives the digital signals of the plurality of bus wirings of the group GRP according to the selection signal S (-0, -1, ... -N / 2). A plurality of first selectors 161 (−0, −1,..., −N / 2) that are independently selected are included.
The transmission circuit 160 includes a second selector 162 that selects a plurality of digital signals selected by the plurality of first selectors 161 according to the selection signal SA and outputs the selected digital signals to the digital signal processing circuit.
Further, the transmission circuit 160 regenerates the output of each first selector 161 (−0, −1,... −N / 2) to the clock CK (−0, −1,... −N / 2). A plurality of resynchronization circuits 163 (−0, −1,..., −N / 2) that are synchronized and output to the second selector 162 are included.
The resynchronization circuit 163 includes a flip-flop FF.

  Each of the first selectors 161 and the resynchronization circuits 163 corresponding to the first selectors 161 includes a selection signal S (−0, −1,... −N / 2) and a clock CK (−0, −1). ,..., -N / 2).

As described above, the CMOS image sensor 100 according to this embodiment includes only a so-called CMOS logic circuit without using an analog signal processing circuit such as a sense amplifier.
The outputs of the respective columns (columns) are grouped as a group GRP through the first selector 161 in a certain number of units. Similarly, the outputs of the first selector 161 are collected in units of a certain number via the second selector 162 in the next stage.
In this way, the selectors are picked up in a pyramid shape, and finally the signal lines are gathered up to one system or the number of signal processing systems of the digital signal processing circuit 170.

If the setup time margin is insufficient, a resynchronization circuit 163 constituted by a resynchronization flip-flop circuit FF is inserted at the output of the first selector 161 as appropriate.
As a result, the number of selector inputs and the number of stages and the resynchronization circuit 163 are adjusted according to the required reading speed, and the number of resynchronization circuits 163 is minimized.
Here, the selector control circuit and the resynchronization circuit need only drive the circuit of the series connected to the output of the column to be read.
For example, a lot of clock enablers are used to control the branch of the clock and realize it. Thereby, an increase in power consumption is suppressed.

4A to 4G are diagrams showing an outline of the operation of the transmission circuit in the CMOS image sensor (solid-state imaging device) of FIG.
4A shows the group output selected by the selection signal SA of the second selector 162, FIG. 4B shows the selection signal S0 of the first selector 161-0, and FIG. 4C shows the first output. The clock CK0 to the resynchronization circuit 163-0 arranged at the output part of the selector 161-0 is shown.
4D shows the selection signal S1 of the first selector 161-1 and FIG. 4E shows the clock CK1 to the resynchronization circuit 163-1 arranged at the output part of the first selector 161-1. ing.
FIG. 4F shows the selection signal S2 of the first selector 161-2, and FIG. 4G shows the clock CK2 to the resynchronization circuit 163-2 arranged at the output section of the first selector 161-2. ing.

For example, when accessing data from column (column) n to column (column) n + a, first, the selection signal S of the first selector 161 and the clock of the resynchronization circuit 163 are activated. The selection signal S is sequentially controlled.
Here, a is the number of inputs to the first selector 161 in the first stage, and FIGS. 3 and 4 are examples in which a = 2.
Next, when accessing data from column (row) n + a + 1 to column (row) n + 2a, the clock of the previous system is stopped and the clock of the system circuit to be accessed is made active.

Similarly, the clock of the selector in the subsequent stage is driven only during the period of data processing.
In addition, by increasing the number of first selectors 161 that are activated simultaneously in the first stage, it is possible to reduce the data rate and increase the timing margin. In other words, it can also be used for increasing the number of simultaneous accesses for the purpose of improving the data rate.

<2. Second Configuration Example of Solid-State Image Sensor>
FIG. 5 is a diagram illustrating a second configuration example of the column-parallel ADC-mounted CMOS image sensor (solid-state imaging device) according to the present embodiment.

  The CMOS image sensor 100A in FIG. 5 is different in the formation of a column group and the configuration of a transmission circuit 160A corresponding thereto.

In the circuit of the CMOS image sensor 100 in FIG. 3, digital data output from the readout circuit of each column has a bit number corresponding to the resolution (about 8 to 16 bits) of the AD conversion unit 141.
For this reason, output signal wirings corresponding to the number of bits are required in each column (column), but because of the circuit width limitation of each column (mainly determined by the pixel size in the CMOS image sensor), that many wirings are required. May cause a physical problem that it is difficult to place the.
FIG. 5 shows a circuit for solving this problem.
In FIG. 5, a circuit portion different from FIG. 3 is shown in detail.

In the CMOS image sensor 100A of FIG. 5, a plurality of columns of memories (holding units) 142 having a smaller scale than the entire column are set as one group GRP.
As in the case of FIG. 3, each column includes a number of memories 142 corresponding to the number of bits corresponding to the resolution of the AD conversion unit 141.
In the CMOS image sensor 100A, the group GRP is grouped in a plurality of units to form a plurality of subgroups SGRP, and the plurality of subgroups SGRP are grouped to form at least one main group MGRP.

In the example of FIG. 5, four columns of memory (holding units) 142 are grouped into one group.
Specifically, the columns CLM0 to CLM3 are set as a group GRP10, and the columns CLM4 to CLM7 are set as a group GRP11.
Further, the columns CLM8 to CLM11 are group GRP12, and the columns CLM12 to CLM15 are group GRP13.
Columns CLM16 to CLM19 are group GRP14, columns CLM20 to CLM23 are group GRP15, columns CLM24 to CLM27 are group GRP16, and columns CLM29 to CLM31 are group GRP17.

In the example of FIG. 5, the first subgroup SGRP10 is formed by four groups GRP10 to GRP13, and the second subgroup SGRP11 is formed by four groups GRP14 to GRP17.
The main group MGRP10 is formed by the first subgroup SGRP10 and the second subgroup SGRP11.
Although not shown, the main group MGRP11... Composed of other columns is configured in the same manner as the main group GRP10.

In the CMOS image sensor 100A, for each of the groups GRP10 to GRP17, bus wirings 143 to 10-17 for selectively transmitting digital signals held in the plurality of memories 142 of each column to the transmission circuit 160A are arranged. .
The bus wirings 143-10 to 17 transmit the digital signals held in all the memories 142 to the transmission circuit 160A for each column in each group GRP10 to GRP17.
The transmission circuit 160A periodically shares a plurality of bus wirings in units of subgroups SGRP10 and SGRP11, selects a digital signal in units of subgroups, and transmits the digital signal to the digital signal processing circuit 170A.

A plurality of memories 142 of each column CLM10 to CLM31 of each group GRP10 to GRP17 are connected to bus wirings 143 to 10 to 143-17 via switches 144 that are turned on / off by selection signals S0 to S3 and S4 to S7.
In the first subgroup SGRP10, the selection signal S from the digital signal processing circuit 170A is supplied with the selection signals S0 to S3 latched by the synchronization circuit 164-10 which is composed of FF and is synchronized with the clock CK10.
In the second subgroup SGRP11, the selection signal S from the digital signal processing circuit 170A is supplied with the selection signals S4 to S7 latched by the synchronization circuit 164-11 which is composed of FF and is synchronized with the clock CK11.

In the first subgroup SGRP10, the column switch CLM0 of the group GRP10, the column CLM4 of the group GRP11, the column CLM8 of the group GRP12, and the memory switch 144 of the column CLM12 of the group GRP13 are selected by the selection signal S0.
Then, the data in the memory 142 in the column CLM0 is transferred to the bus wiring 143-10, and the data in the memory 142 in the column CLM4 is transferred to the bus wiring 143-11. Similarly, data in the memory 142 in the column CLM8 is transferred to the bus wiring 143-12, and data in the memory 142 in the column CLM12 is transferred to the bus wiring 143-13.

In the first subgroup SGRP10, the column switch CLM1 of the group GRP10, the column CLM5 of the group GRP11, the column CLM9 of the group GRP12, and the memory switch 144 of the column CLM13 of the group GRP13 are selected by the selection signal S1.
Then, the data in the memory 142 in the column CLM1 is transferred to the bus wiring 143-10, and the data in the memory 142 in the column CLM5 is transferred to the bus wiring 143-11. Similarly, the data in the memory 142 in the column CLM9 is transferred to the bus wiring 143-12, and the data in the memory 142 in the column CLM13 is transferred to the bus wiring 143-13.

In the first subgroup SGRP10, the memory switch 144 of the column CLM2 of the group GRP10, the column CLM6 of the group GRP11, the column CLM10 of the group GRP12, and the column CLM14 of the group GRP13 is selected by the selection signal S2.
Then, the data in the memory 142 in the column CLM2 is transferred to the bus wiring 143-10, and the data in the memory 142 in the column CLM6 is transferred to the bus wiring 143-11. Similarly, data in the memory 142 in the column CLM10 is transferred to the bus wiring 143-12, and data in the memory 142 in the column CLM14 is transferred to the bus wiring 143-13.

In the first subgroup SGRP10, the memory switch 144 of the column CLM3 of the group GRP10, the column CLM7 of the group GRP11, the column CLM11 of the group GRP12, and the column CLM15 of the group GRP13 is selected by the selection signal S3.
Then, the data in the memory 142 in the column CLM3 is transferred to the bus wiring 143-10, and the data in the memory 142 in the column CLM7 is transferred to the bus wiring 143-11. Similarly, the data in the memory 142 in the column CLM11 is transferred to the bus wiring 143-12, and the data in the memory 142 in the column CLM15 is transferred to the bus wiring 143-13.

In the second subgroup SGRP11, the memory switch 144 of the column CLM16 of the group GRP14, the column CLM20 of the group GRP15, the column CLM24 of the group GRP16, and the column CLM28 of the group GRP17 is selected by the selection signal S4.
Then, the data in the memory 142 in the column CLM16 is transferred to the bus wiring 143-14, and the data in the memory 142 in the column CLM20 is transferred to the bus wiring 143-15. Similarly, the data in the memory 142 in the column CLM24 is transferred to the bus wiring 143-16, and the data in the memory 142 in the column CLM28 is transferred to the bus wiring 143-17.

In the second subgroup SGRP11, the memory switch 144 of the column CLM17 of the group GRP14, the column CLM21 of the group GRP15, the column CLM25 of the group GRP16, and the column CLM29 of the group GRP17 is selected by the selection signal S5.
Then, the data in the memory 142 in the column CLM17 is transferred to the bus wiring 143-14, and the data in the memory 142 in the column CLM21 is transferred to the bus wiring 143-15. Similarly, the data in the memory 142 in the column CLM25 is transferred to the bus wiring 143-16, and the data in the memory 142 in the column CLM29 is transferred to the bus wiring 143-17.

In the second subgroup SGRP11, the memory switch 144 of the column CLM18 of the group GRP14, the column CLM22 of the group GRP15, the column CLM26 of the group GRP16, and the column CLM30 of the group GRP17 is selected by the selection signal S6.
Then, the data in the memory 142 in the column CLM18 is transferred to the bus wiring 143-14, and the data in the memory 142 in the column CLM22 is transferred to the bus wiring 143-15. Similarly, the data in the memory 142 in the column CLM26 is transferred to the bus wiring 143-16, and the data in the memory 142 in the column CLM30 is transferred to the bus wiring 143-17.

In the second subgroup SGRP11, the memory switch 144 of the column CLM19 of the group GRP14, the column CLM23 of the group GRP15, the column CLM27 of the group GRP16, and the column CLM31 of the group GRP17 is selected by the selection signal S7.
The data in the memory 142 in the column CLM19 is transferred to the bus wiring 143-14, and the data in the memory 142 in the column CLM23 is transferred to the bus wiring 143-15. Similarly, data in the memory 142 in the column CLM27 is transferred to the bus wiring 143-16, and data in the memory 142 in the column CLM31 is transferred to the bus wiring 143-17.

The transmission circuit 160A includes a plurality of first selectors 161-10 and 160-11 that are arranged corresponding to each of the subgroups SGRP10 and SGRP11 and select digital signals of a plurality of bus lines of the subgroups SGRP10 and SGRP11.
The first selector 161-10 is connected to the bus wirings 143-10 to 13-13 of the first subgroup SGRP10.
The second selector 161-11 is connected to the bus wirings 143-14 to 17-17 of the second subgroup SGRP11.

The transmission circuit 160A includes a second selector 162A that selects a plurality of digital signals selected by the plurality of first selectors 161-10 and 161-11 and outputs the selected digital signal to the digital signal processing circuit 170A.
The transmission circuit 160A then resynchronizes the outputs of the first selectors 160-10 and 161-11 with the clock CK10 and outputs the resynchronization circuits to the second selector 162A. 11 is included.

The digital signal selected by the first selector 161-10 is re-synchronized by the resynchronization circuit 163-10, and the digital signal processing circuit passes through the first bus BS10 and the first selector SL10 of the second selector 162A. 170A.
The digital signal selected by the first selector 161-11 is resynchronized by the resynchronization circuit 163-11, and the digital signal processing circuit passes through the second bus BS11 and the second selector SL11 of the second selector 162A. 170A.

  Each first selector 161 and the resynchronization circuit 163 corresponding to the first selector 161 are individually driven and controlled by the selection signal S and the clock CK.

Further, in the CMOS image sensor 100A, the bus wirings 143-10 to 17-17 are held in a state in which the signal is determined by the data held in the memory of any column in the corresponding group GRP10 to GRP17 even after the reading is completed. Is done.
This prevents each of the bus wirings 143-10 to 17 from following and becoming high impedance HiZ, thereby preventing indefinite information output.

  The digital signal processing circuit 170A of the CMOS image sensor 100A includes a rearrangement unit 171 that rearranges the read digital signals in units of main groups MGRP.

  As described above, in the CMOS image sensor 100A of FIG. 5, the bus wiring 143 for outputting the output signal of each column (column) is shared by a plurality of columns for each bit via the switch 144, and the number of output wirings is shared ( Column) Decrease by a fraction.

  FIG. 6 is a diagram showing an outline of the operation of the transmission circuit in the CMOS image sensor (solid-state imaging device) of FIG.

As described above, the CMOS image sensor 100A in FIG. 5 is an example in which the number of shared columns (rows) is four and the number of simultaneous accesses is eight.
A scan circuit for controlling an access column is provided in a group GRP in a column (column) unit sharing the output bus wiring 143, and data in each column in the share is sequentially accessed.
Since the number shared here is small and the load is small, the sense amplifier circuit used when reading by sharing in all the columns (rows) is not required, and the signal can be directly output by the logic circuit.
Further, as described above, since the data rate of the shared wiring section can be reduced without increasing the data rate of the entire system by increasing the number of circuits that are accessed simultaneously, the problem of timing margin can be solved.

Here, as described above, when a plurality of columns are accessed simultaneously, the output order of the finally aggregated data is different from the order of the column numbers.
For this reason, when it is necessary to perform processing in the order of columns (rows), it is necessary to rearrange data in the digital signal processing circuit 170 at the subsequent stage.
For rearrangement, a memory of “number of shared columns” × “number of simultaneous accesses” is required.

<3. Layered structure of solid-state image sensor>
FIG. 7 is a diagram illustrating an example of a stacked structure of the solid-state imaging device according to the present embodiment.

A CMOS image sensor (solid-state imaging device) 200 shown in FIG. 3 has a stacked structure of a first chip (upper chip) 210 and a second chip (lower chip) 220.
The first chip 210 and the second chip 220 to be stacked are electrically connected by vias (TCV) formed in the first chip 210.
The CMOS image sensor (solid-state imaging device) 200 is formed as a semiconductor device having a laminated structure that is cut out by dicing after bonding at a wafer level.

FIG. 8 is a diagram showing a circuit arrangement example of two chips on which the CMOS image sensor (solid-state imaging device) according to this embodiment is stacked.
FIG. 9 is a diagram showing a circuit arrangement example in which all the circuits of FIG. 1 are arranged on one chip as a comparative example.

In the stacked structure of upper and lower two chips, the first chip 210 is configured by an analog chip (sensor chip) in which a pixel array unit 110 including a plurality of pixels and a vertical (V) scanning circuit 120 are arranged in an illegitimate shape.
The second chip 120 includes a column ADC 140 that converts an analog signal transferred from the first chip 210 via a TCV (Through Contact VIA) and a logic chip (digital chip) including a digital signal processing circuit (logic circuit) 170. Is done.
The bonding pad BPD and the input / output circuit are formed in the second chip 220, and the opening OPN for wire bonding to the second chip 220 is formed in the first chip 210.
The electrical connection between the first chip 210 and the second chip 220 is made, for example, through a via (TCV).
The TCV (via) is arranged at the chip end or between the pad (PAD) and the circuit area.
For example, the control signal and the power supply TCV are mainly concentrated at the four corners of the chip, and the signal wiring area of the first chip 210 can be reduced.
By reducing the number of wiring layers of the first chip 210 and increasing the power line resistance and increasing IR-Drop, the first chip 210 can be used by using the wiring of the second chip 220 by effectively arranging the TCV. It is possible to reinforce power supply noise countermeasures and stable supply.

  As described above, in the stacked CMOS image sensor 200 of FIGS. 7 and 8, unlike the comparative example of FIG. 9, each column circuit of the column ADC group 140 (A) and the digital signal processing circuit 170 (A) are adjacently connected. However, there is an advantage that the chip size is not directly affected.

As described above, according to this embodiment, an analog circuit such as a sense amplifier is not required. Then, according to the present embodiment, a large-scale digital array data signal can be transferred to a subsequent stage only with a CMOS logic circuit, while solving the problems of low power consumption driving, high-speed data rate compatibility, and physical limitations of the wiring area. Can be transmitted to the digital signal processing circuit.
In the case of a stacked type, there is an advantage that even if each column of the column ADC group and the digital signal processing circuit are adjacently connected, the chip size is not directly affected.

  A solid-state imaging device having such an effect can be applied as an imaging device for a digital camera or a video camera.

<4. Configuration example of camera system>
FIG. 10 is a diagram illustrating an example of a configuration of a camera system to which the solid-state imaging device according to the embodiment of the present technology is applied.

As shown in FIG. 10, the camera system 300 includes an imaging device 310 to which the CMOS image sensors (solid-state imaging devices) 100 and 200 according to the present embodiment can be applied.
Furthermore, the camera system 300 includes an optical system that guides incident light (images a subject image) to the pixel region of the imaging device 310, for example, a lens 420 that forms incident light (image light) on the imaging surface.
The camera system 300 includes a drive circuit (DRV) 330 that drives the imaging device 310 and a signal processing circuit (PRC) 340 that processes an output signal of the imaging device 310.

  The drive circuit 330 includes a timing generator (not shown) that generates various timing signals including a start pulse and a clock pulse that drive a circuit in the imaging device 310, and drives the imaging device 310 with a predetermined timing signal. .

Further, the signal processing circuit 340 performs predetermined signal processing on the output signal of the imaging device 310.
The image signal processed by the signal processing circuit 340 is recorded on a recording medium such as a memory. The image information recorded on the recording medium is hard copied by a printer or the like. The image signal processed by the signal processing circuit 340 is displayed as a moving image on a monitor including a liquid crystal display.

  As described above, by mounting the above-described solid-state imaging devices 100 and 200 as the imaging device 310 in an imaging device such as a digital still camera, a highly accurate camera with low power consumption can be realized.

In addition, this technique can take the following structures.
(1) a pixel array unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix;
A pixel signal readout unit that reads out a pixel signal from the pixel array unit in units of a plurality of pixels and includes a column AD conversion unit that performs analog-digital conversion for each column, and outputs a digital signal;
A transmission unit for transmitting a digital signal output from the pixel signal readout unit,
The pixel signal readout unit is
A holding unit for holding a digital signal by the AD conversion unit;
A bus wiring for outputting the digital data held in the holding unit to the transmission unit, and
The transmission unit is
A solid-state imaging device that shares a plurality of the above-mentioned bus wirings as one group.
(2) Each holding unit of the pixel signal readout unit is
Including a number of memories corresponding to the number of bits corresponding to the resolution of the AD converter,
The above bus wiring
The solid-state imaging device according to (1), wherein digital signals held in all memories are transmitted to the transmission unit.
(3) The transmission unit
A plurality of first selectors arranged corresponding to each group, for selecting digital signals of a plurality of bus wires in the group;
The solid-state imaging device according to (1) or (2), further including: a second selector that selects a plurality of digital signals selected by the plurality of first selectors and outputs the selected digital signals to the digital signal processing unit.
(4) The solid-state imaging device according to (3), including a plurality of resynchronization circuits that resynchronize outputs of the plurality of first selectors with a clock and output the same to the second selector.
(5) The solid-state imaging device according to (4), wherein the first selector and the resynchronization circuit corresponding to the first selector are individually driven and controlled.
(6) a digital signal processing unit that processes a digital signal output from the pixel signal reading unit and transmitted;
The transmission unit is
The solid-state imaging device according to any one of (1) to (5), wherein a digital signal is selected in a group unit and transmitted to the digital signal processing unit.
(7) a first chip;
A second chip,
The first chip and the second chip have a laminated structure bonded together,
The first chip is
At least the pixel array section is disposed;
The second chip is
At least the pixel signal readout unit and the digital signal processing unit are arranged,
The wiring between the first chip and the second chip is
The solid-state imaging device according to (6), wherein the solid-state imaging device is connected through a via formed in the first chip.
(8) a pixel array unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix;
A pixel signal readout unit that reads out a pixel signal from the pixel array unit in units of a plurality of pixels and includes a column AD conversion unit that performs analog-digital conversion for each column, and outputs a digital signal;
A transmission unit for transmitting a digital signal output from the pixel signal readout unit,
The pixel signal readout unit is
A plurality of holding units that are arranged for each column and hold digital signals by the AD conversion unit,
A plurality of the holding units having a smaller scale than the entire column are grouped together, and the groups are grouped into a plurality of units to form a plurality of subgroups, and the plurality of subgroups are grouped to form at least one main group. ,
For each group, a bus wiring for selectively transmitting a digital signal held in the holding unit of each column to the transmission unit is arranged,
The transmission unit is
A solid-state imaging device that shares the plurality of bus wirings in units of the subgroups.
(9) The pixel signal readout unit
Each holding unit includes a number of memories corresponding to the number of bits corresponding to the resolution of the AD conversion unit,
The data in the memory in each column of each group is transferred to the corresponding bus wiring in response to the selection signal,
The above bus wiring
The solid-state imaging device according to (9), wherein a digital signal held in all memories is transmitted to the transmission unit for each column in each group.
(10) The transmission unit is
A plurality of first selectors arranged corresponding to each of the subgroups for selecting digital signals of a plurality of bus wirings of the subgroup;
The solid-state imaging device according to (8) or (9), further including: a second selector that selects a plurality of digital signals selected by the plurality of first selectors and outputs the selected digital signal to the digital signal processing unit.
(11) The solid-state imaging device according to (10), including a plurality of resynchronization circuits that resynchronize outputs of the plurality of first selectors with a clock and output the same to the second selector.
(12) The solid-state imaging device according to (11), wherein the first selector and the resynchronization circuit corresponding to the first selector are individually driven and controlled.
(13) Each bus wiring is
The solid-state imaging device according to any one of (8) to (12), wherein the signal is held in a state where the signal is fixed by the data held in the memory in any column in the corresponding group.
(14) The digital signal processing unit
The solid-state imaging device according to any one of (8) to (13), including a rearrangement unit that rearranges the read digital signals in units of the main group.
(15) a digital signal processing unit that processes the digital signal output from the pixel signal reading unit and transmitted;
The transmission unit is
The solid-state imaging device according to any one of (8) to (14), wherein a digital signal is selected in units of subgroups and transmitted to the digital signal processing unit.
(16) a first chip;
A second chip,
The first chip and the second chip have a laminated structure bonded together,
The first chip is
At least the pixel array section is disposed;
The second chip is
At least the pixel signal readout unit and the digital signal processing unit are arranged,
The wiring between the first chip and the second chip is
The solid-state imaging device according to any one of (8) to (15), which is connected through a via formed in the first chip.
(17) a solid-state imaging device;
An optical system for forming a subject image on the solid-state imaging device,
The solid-state imaging device is
A pixel array unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix;
A pixel signal readout unit that reads out a pixel signal from the pixel array unit in units of a plurality of pixels and includes a column AD conversion unit that performs analog-digital conversion for each column, and outputs a digital signal;
A transmission unit for transmitting a digital signal output from the pixel signal readout unit,
The pixel signal readout unit is
A holding unit for holding a digital signal by the AD conversion unit;
A bus wiring for outputting the digital data held in the holding unit to the transmission unit, and
The transmission unit is
A camera system that shares a plurality of bus wirings as a group.
(18)
A solid-state image sensor;
An optical system for forming a subject image on the solid-state imaging device,
The solid-state imaging device is
A pixel unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix;
A pixel signal readout unit that reads out a pixel signal from the pixel unit in units of a plurality of pixels and includes a column AD conversion unit that performs analog-digital conversion for each column, and outputs a digital signal;
A transmission unit for transmitting a digital signal output from the pixel signal readout unit,
The pixel signal readout unit is
A plurality of holding units that are arranged for each column and hold digital signals by the AD conversion unit,
A plurality of the holding units having a smaller scale than the entire column are grouped together, and the groups are grouped into a plurality of units to form a plurality of subgroups, and the plurality of subgroups are grouped to form at least one main group. ,
For each group, a bus wiring for selectively transmitting a digital signal held in the holding unit of each column to the transmission unit is arranged,
The transmission unit is
A camera system sharing a plurality of the bus wirings in units of the subgroups.

  DESCRIPTION OF SYMBOLS 100 ... Solid-state imaging device (CMOS image sensor), 110 ... Pixel array part, 110 ... Row selection circuit, 130 ... Timing control circuit, 140 ... ADC group, 141 ... AD conversion 142, memory (holding unit), 143, bus wiring, 150, reference voltage generation circuit, 160, transmission circuit, 161, first selector, 162, second. 163... Resynchronization circuit, 170... Digital signal processing circuit, 200... Solid-state image sensor, 210... First chip (analog chip), 220. , Digital chip), 300 ... camera system, 310 ... imaging device, 320 ... lens, 330 ... drive circuit, 340 ... signal processing circuit.

Claims (18)

A pixel array unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix;
A pixel signal readout unit that reads out a pixel signal from the pixel array unit in units of a plurality of pixels and includes a column AD conversion unit that performs analog-digital conversion for each column, and outputs a digital signal;
A transmission unit for transmitting a digital signal output from the pixel signal readout unit,
The pixel signal readout unit is
A holding unit for holding a digital signal by the AD conversion unit;
A bus wiring for outputting the digital data held in the holding unit to the transmission unit, and
The transmission unit is
A solid-state imaging device that shares a plurality of the above-mentioned bus wirings as one group. Each holding unit of the pixel signal readout unit is
Including a number of memories corresponding to the number of bits corresponding to the resolution of the AD converter,
The above bus wiring
The solid-state imaging device according to claim 1, wherein digital signals held in all memories are transmitted to the transmission unit. The transmission unit is
A plurality of first selectors arranged corresponding to each group, for selecting digital signals of a plurality of bus wires in the group;
The solid-state imaging device according to claim 1, further comprising: a second selector that selects a plurality of digital signals selected by the plurality of first selectors and outputs the selected digital signals to the digital signal processing unit. The solid-state imaging device according to claim 3, further comprising a plurality of resynchronization circuits that resynchronize outputs of the plurality of first selectors with a clock and output the second selectors to the second selector. The solid-state imaging device according to claim 4, wherein the first selector and the resynchronization circuit corresponding to the first selector are individually driven and controlled. A digital signal processing unit that processes a digital signal output from the pixel signal reading unit and transmitted;
The transmission unit is
The solid-state imaging device according to claim 1, wherein digital signals are selected in groups and transmitted to the digital signal processing unit. A first chip;
A second chip,
The first chip and the second chip have a laminated structure bonded together,
The first chip is
At least the pixel array section is disposed;
The second chip is
At least the pixel signal readout unit and the digital signal processing unit are arranged,
The wiring between the first chip and the second chip is
The solid-state imaging device according to claim 6, wherein the solid-state imaging device is connected through a via formed in the first chip. A pixel array unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix;
A pixel signal readout unit that reads out a pixel signal from the pixel array unit in units of a plurality of pixels and includes a column AD conversion unit that performs analog-digital conversion for each column, and outputs a digital signal;
A transmission unit for transmitting a digital signal output from the pixel signal readout unit,
The pixel signal readout unit is
A plurality of holding units that are arranged for each column and hold digital signals by the AD conversion unit,
A plurality of the holding units having a smaller scale than the entire column are grouped together, and the groups are grouped into a plurality of units to form a plurality of subgroups, and the plurality of subgroups are grouped to form at least one main group. ,
For each group, a bus wiring for selectively transmitting a digital signal held in the holding unit of each column to the transmission unit is arranged,
The transmission unit is
A solid-state imaging device that shares the plurality of bus wirings in units of the subgroups. The pixel signal readout unit is
Each holding unit includes a number of memories corresponding to the number of bits corresponding to the resolution of the AD conversion unit,
The data in the memory in each column of each group is transferred to the corresponding bus wiring in response to the selection signal,
The above bus wiring
The solid-state imaging device according to claim 9, wherein digital signals held in all memories are transmitted to the transmission unit for each column in each group. The transmission unit is
A plurality of first selectors arranged corresponding to each of the subgroups for selecting digital signals of a plurality of bus wirings of the subgroup;
The solid-state imaging device according to claim 8, further comprising: a second selector that selects a plurality of digital signals selected by the plurality of first selectors and outputs the selected digital signals to the digital signal processing unit. The solid-state imaging device according to claim 10, further comprising: a plurality of resynchronization circuits that resynchronize outputs of the plurality of first selectors with a clock and output the same to the second selector. The solid-state imaging device according to claim 11, wherein the first selector and the resynchronization circuit corresponding to the first selector are individually driven and controlled. Each bus wiring above
The solid-state imaging device according to claim 8, wherein the signal is held in a state where the signal is determined by the data held in the memory in any column in the corresponding group. The digital signal processor is
The solid-state imaging device according to claim 8, further comprising a rearrangement unit that rearranges the read digital signals in units of the main group. A digital signal processing unit that processes a digital signal output from the pixel signal reading unit and transmitted;
The transmission unit is
The solid-state imaging device according to claim 8, wherein a digital signal is selected in units of subgroups and transmitted to the digital signal processing unit. A first chip;
A second chip,
The first chip and the second chip have a laminated structure bonded together,
The first chip is
At least the pixel array section is disposed;
The second chip is
At least the pixel signal readout unit and the digital signal processing unit are arranged,
The wiring between the first chip and the second chip is
The solid-state imaging device according to claim 15, wherein the solid-state imaging device is connected through a via formed in the first chip. A solid-state image sensor;
An optical system for forming a subject image on the solid-state imaging device,
The solid-state imaging device is
A pixel array unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix;
A pixel signal readout unit that reads out a pixel signal from the pixel array unit in units of a plurality of pixels and includes a column AD conversion unit that performs analog-digital conversion for each column, and outputs a digital signal;
A transmission unit for transmitting a digital signal output from the pixel signal readout unit,
The pixel signal readout unit is
A holding unit for holding a digital signal by the AD conversion unit;
A bus wiring for outputting the digital data held in the holding unit to the transmission unit, and
The transmission unit is
A camera system that shares a plurality of bus wirings as a group. A solid-state image sensor;
An optical system for forming a subject image on the solid-state imaging device,
The solid-state imaging device is
A pixel unit in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix;
A pixel signal readout unit that reads out a pixel signal from the pixel unit in units of a plurality of pixels and includes a column AD conversion unit that performs analog-digital conversion for each column, and outputs a digital signal;
A transmission unit for transmitting a digital signal output from the pixel signal readout unit,
The pixel signal readout unit is
A plurality of holding units that are arranged for each column and hold digital signals by the AD conversion unit,
A plurality of the holding units having a smaller scale than the entire column are grouped together, and the groups are grouped into a plurality of units to form a plurality of subgroups, and the plurality of subgroups are grouped to form at least one main group. ,
For each group, a bus wiring for selectively transmitting a digital signal held in the holding unit of each column to the transmission unit is arranged,
The transmission unit is
A camera system sharing a plurality of the bus wirings in units of the subgroups.