CN115116398A

CN115116398A - Display panel driving method and display device

Info

Publication number: CN115116398A
Application number: CN202210836796.9A
Authority: CN
Inventors: 文超平; 陈旭; 朱景辉; 孙语琳; 刘洋; 王海宏; 古宏刚
Original assignee: Nanjing Boe Display Technology Co ltd; BOE Technology Group Co Ltd
Current assignee: Nanjing Boe Display Technology Co ltd; BOE Technology Group Co Ltd
Priority date: 2022-07-15
Filing date: 2022-07-15
Publication date: 2022-09-27

Abstract

The driving method of the display panel and the display device provided by the embodiment of the disclosure divide the plurality of shift registers into a plurality of cascade groups, wherein the color of the sub-pixels corresponding to the gate lines coupled to the shift registers in the same cascade group is the same, the shift registers in the same cascade group are arranged in a cascade manner, and different cascade groups are coupled to different signal transmission lines. When the first driving mode is adopted, different control signals are loaded on each signal transmission line in a display frame, each cascade group is controlled to work sequentially, each shift register in the same cascade group scans the coupled grid lines line by line, and the grid lines are scanned line by line. And when the second driving mode is adopted, in one display frame, loading control signals to the signal transmission lines coupled with the set cascade group, controlling each shift register in the set cascade group to scan the coupled grid lines line by line, and loading stop signals to the signal transmission lines coupled with the other cascade groups except the set cascade group in the plurality of cascade groups.

Description

Display panel driving method and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a driving method of a display panel and a display device.

Background

In displays such as Liquid Crystal Displays (LCDs) and Organic Light-Emitting diodes (OLEDs), a plurality of pixel cells are generally included. Each pixel unit may include: a plurality of differently colored sub-pixels. And controlling the corresponding brightness of each sub-pixel so as to mix the colors required to be displayed to display a color image.

Disclosure of Invention

The display panel driving method provided by the embodiment of the present disclosure includes: the pixel structure comprises a plurality of sub-pixels with different colors, a plurality of grid lines, a grid driving circuit respectively coupled with the grid lines and a plurality of signal transmission lines coupled with the grid driving circuit; the color of the sub-pixels in the same row is the same, the sub-pixels in one row are coupled to one grid line, the grid driving circuit comprises a plurality of shift registers, the driving output end of one shift register is coupled to one grid line, the shift registers are divided into a plurality of cascade groups, the color of the sub-pixels corresponding to the grid lines coupled to the shift registers in the same cascade group is the same, the shift registers in the same cascade group are arranged in a cascade mode, and different cascade groups are coupled to different signal transmission lines;

the driving method comprises the following steps:

when a first driving mode is adopted, different control signals are loaded on each signal transmission line in a display frame, each cascade group is controlled to work sequentially, each shift register in the same cascade group scans coupled grid lines line by line, and the grid lines are scanned line by line;

and when a second driving mode is adopted, in one display frame, taking one of the cascade groups as a set cascade group, loading a control signal to the signal transmission line coupled with the set cascade group, controlling each shift register in the set cascade group to scan the coupled grid lines line by line, and loading a cut-off signal to the signal transmission lines coupled with the other cascade groups except the set cascade group in the plurality of cascade groups.

In some examples, the plurality of signal transmission lines includes a plurality of clock signal lines; the clock signal lines are divided into a plurality of clock line groups, and each clock line group comprises at least two clock signal lines; one of the cascaded sets is coupled to a clock signal line in one of the clock line sets;

the control signal comprises a clock signal.

In some examples, the display panel further comprises: a first frame start signal line;

the plurality of cascade groups are coupled to the same first frame start signal line.

In some examples, the plurality of signal transmission lines further includes a plurality of second frame start signal lines;

the plurality of cascade groups are coupled with the plurality of second frame starting signal lines in a one-to-one correspondence manner;

the control signal comprises a frame start signal.

In some examples, when the second driving mode is adopted, in one display frame, a frame start signal is applied to the second frame start signal line coupled to the set cascade group, a cut-off signal is applied to the second frame start signal lines coupled to the remaining cascade groups, a clock signal is applied to each clock signal line, and each shift register in the set cascade group is controlled to scan the coupled gate lines line by line.

In some examples, when the second driving mode is adopted, in one display frame, a frame start signal is loaded to the second frame start signal line to which the set cascade group is coupled, and an off signal is loaded to the second frame start signal lines to which the other cascade groups are coupled, a clock signal is loaded to the clock signal line to which the set cascade group is coupled, each shift register in the set cascade group is controlled to scan the coupled gate lines line by line, and an off signal is loaded to the clock signal line to which the other cascade groups except the set cascade group are coupled.

In some examples, when the second driving mode is adopted, in one display frame, a frame start signal is loaded to each of the second frame start signal lines, a clock signal is loaded to the clock signal lines coupled to the set cascade group, each shift register in the set cascade group is controlled to scan the coupled gate lines line by line, and a cut-off signal is loaded to the clock signal lines coupled to the other cascade groups except the set cascade group in the plurality of cascade groups.

In some examples, the plurality of different color sub-pixels includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel, and the first color sub-pixel row, the second color sub-pixel row, and the third color sub-pixel row are repeatedly arranged in sequence along a column direction;

the number of the plurality of cascaded sets is three, the cascaded set corresponding to the first color sub-pixel in the three cascaded sets is defined as a first cascaded set, the cascaded set corresponding to the second color sub-pixel is defined as a second cascaded set, and the cascaded set corresponding to the third color sub-pixel is defined as a third cascaded set;

the set cascade group is one of the first cascade group, the second cascade group and the third cascade group.

In some examples, when the second driving mode is adopted, in each of a plurality of consecutive display frames, the set cascade group is a cascade group corresponding to a same color sub-pixel;

or, when the second driving mode is adopted, in a plurality of consecutive display frames, the set cascade group is a cascade group sequentially repeated according to the cascade group corresponding to the first color sub-pixel, the cascade group corresponding to the second color sub-pixel, and the cascade group corresponding to the third color sub-pixel.

In some examples, the display panel further comprises a plurality of data lines; wherein a column of sub-pixels is coupled to one of the data lines;

the driving method further includes:

when the grid line is scanned, corresponding data voltage is input to the data line, and the corresponding sub-pixel is charged.

In some examples, the display panel further includes source driving circuits respectively coupled to the plurality of data lines;

the source driving circuit is configured to input a corresponding data voltage to the data line to charge the corresponding sub-pixel when the gate line is scanned.

In some examples, the display panel further includes a plurality of detection units, a detection input signal line, and a detection control signal line; wherein a control terminal of the detection unit is coupled to the detection control signal line, an input terminal of the detection unit is coupled to the detection input signal line, and an output terminal of one of the detection units is coupled to one of the data lines;

the driving method further includes:

and when a third driving mode is adopted, in a display frame, taking one of the plurality of cascade groups as a set cascade group, loading a control signal to the signal transmission line coupled with the set cascade group, controlling each shift register in the set cascade group to scan the coupled grid lines line by line, loading a stop signal to the signal transmission lines coupled with the other cascade groups except the set cascade group in the plurality of cascade groups, loading a start signal to the detection control signal line, and loading a detection voltage to the detection input signal line to charge the corresponding sub-pixel.

An embodiment of the present disclosure also provides a display device, including:

a display panel, comprising: the pixel structure comprises a plurality of sub-pixels with different colors, a plurality of grid lines, a grid driving circuit respectively coupled with the grid lines and a plurality of signal transmission lines coupled with the grid driving circuit; the color of the sub-pixels in the same row is the same, the sub-pixels in one row are coupled to one grid line, the grid driving circuit comprises a plurality of shift registers, the driving output end of one shift register is coupled to one grid line, the shift registers are divided into a plurality of cascade groups, the color of the sub-pixels corresponding to the grid lines coupled to the shift registers in the same cascade group is the same, the shift registers in the same cascade group are arranged in a cascade mode, and different cascade groups are coupled to different signal transmission lines;

the time schedule controller is configured to load different control signals to each signal transmission line in the plurality of signal transmission lines in a display frame when a first driving mode is adopted, control each cascaded set to work in sequence, control each shift register in the same cascaded set to scan coupled grid lines line by line, and scan the plurality of grid lines line by line; and when a second driving mode is adopted, in a display frame, taking one of the cascade groups as a set cascade group, loading a control signal to the signal transmission line coupled with the set cascade group, controlling each shift register in the set cascade group to scan the coupled grid lines line by line, and loading a cut-off signal to the signal transmission lines coupled with the other cascade groups except the set cascade group in the cascade groups.

Drawings

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present disclosure;

fig. 2a is a schematic structural diagram of a display panel according to an embodiment of the disclosure;

fig. 2b is another schematic structural diagram of a display panel according to an embodiment of the disclosure;

fig. 3 is a flowchart of a driving method provided by an embodiment of the disclosure;

FIG. 4 is a diagram illustrating some structures of a shift register according to an embodiment of the present disclosure;

FIG. 5 is a timing diagram of some of the signals provided by the disclosed embodiments;

fig. 6 is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

fig. 7a is a schematic structural diagram of a display panel according to an embodiment of the disclosure;

fig. 7b is a schematic structural diagram of a display panel according to an embodiment of the disclosure;

fig. 7c is a schematic view of still other structures of the display panel according to the embodiment of the disclosure;

FIG. 8 is a timing diagram of further signals provided by embodiments of the present disclosure;

FIG. 9a is a timing diagram of some further signals provided by the disclosed embodiments;

FIG. 9b is a timing diagram of some further signals provided by the disclosed embodiments;

FIG. 9c is a timing diagram of some further signals provided by the disclosed embodiments;

fig. 10 is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

fig. 11a is a schematic view of still other structures of a display panel according to an embodiment of the disclosure;

fig. 11b is a schematic view of still other structures of the display panel according to the embodiment of the disclosure;

fig. 11c is a schematic view of still other structures of the display panel according to the embodiment of the disclosure;

FIG. 12 is a timing diagram of further signals provided by embodiments of the present disclosure;

FIG. 13a is a timing diagram of some further signals provided by the disclosed embodiments;

FIG. 13b is a timing diagram of some further signals provided by the disclosed embodiments;

FIG. 13c is a timing diagram of some further signals provided by the disclosed embodiments;

fig. 14 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. And the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the sizes and shapes of the various figures in the drawings are not to scale, but are merely intended to illustrate the present disclosure. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

Referring to fig. 1 and 2a, the display device may include: the display panel 100 and the timing controller 200. The display panel 100 may include a plurality of pixel units arranged in an array, a plurality of gate lines GA (e.g., GA1, GA2, GA3, and GA4), a plurality of data lines DA (e.g., DA1, DA2, and DA3), a gate driving circuit 110, and a source driving circuit 120. The gate driving circuit 110 is coupled to the gate lines GA1, GA2, GA3, and GA4, respectively, and the source driving circuit 120 is coupled to the data lines DA1, DA2, and DA3, respectively. The timing controller 200 may input a clock signal to the gate driving circuit 110 through a Level Shift (Level Shift) circuit, and cause the gate driving circuit 110 to output signals to the gate lines GA1, GA2, GA3, and GA4 coupled thereto, so as to scan the gate lines GA1, GA2, GA3, and GA 4. The timing controller 200 inputs display data to the source driving circuit 120, so that the source driving circuit 120 inputs a data voltage to the data line according to the received display data, thereby charging the sub-pixel SPX, and inputting a corresponding data voltage to the sub-pixel SPX, thereby implementing a picture display function of the display frame. For example, the source driving circuits 120 may be arranged in 2, wherein one source driving circuit 120 is connected to half of the number of data lines, and the other source driving circuit 120 is connected to the other half of the number of data lines. Of course, the number of the source driving circuits 120 may also be 3, 4, or more, and the source driving circuits may be designed according to the requirements of the practical application, and are not limited herein.

Illustratively, each pixel unit includes a plurality of sub-pixels SPX of different colors. For example, the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that color mixing may be performed by red, green, and blue to realize color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that color display may be realized by performing color mixing of red, green, blue, and white. Of course, in practical applications, the light emitting color of the sub-pixels in the pixel unit may be determined according to practical application environments, and is not limited herein.

In some embodiments, as shown in fig. 2a, each sub-pixel SPX includes a transistor 01 and a pixel electrode 02 therein. The sub-pixels SPX in one row correspond to a gate line, and the sub-pixels SPX in one column correspond to a data line. A gate electrode of the transistor 01 is electrically connected to a corresponding gate line, a source electrode of the transistor 01 is electrically connected to a corresponding data line, and a drain electrode of the transistor 01 is electrically connected to the pixel electrode 02. Certainly, in practical applications, the pixel array structure of the present disclosure may also be a dual-gate structure, that is, two gate lines are disposed between two adjacent rows of pixels, and this arrangement may reduce half of the data lines, that is, include data lines between two adjacent rows of pixels, and some adjacent rows of pixels do not include data lines, and the specific pixel arrangement structure and the data lines are not limited in the arrangement manner of the scan lines.

It should be noted that the display panel in the embodiment of the present disclosure may be a liquid crystal display panel. Illustratively, a liquid crystal display panel generally includes upper and lower substrates facing each other, and liquid crystal molecules encapsulated between the upper and lower substrates. When a picture is displayed, a voltage difference exists between the data voltage loaded on the pixel electrode of each sub-pixel and the common electrode voltage on the common electrode, and the voltage difference can form an electric field, so that liquid crystal molecules are deflected under the action of the electric field. The electric fields with different intensities enable the deflection degree of liquid crystal molecules to be different, so that the transmittance of the sub-pixels is different, the sub-pixels can realize the brightness of different gray scales, and further, the picture display is realized.

In some embodiments of the present disclosure, as shown in fig. 2b, the color of the sub-pixels in the same row is the same, i.e. the sub-pixels in a row are the same color. For example, the plurality of sub-pixels of different colors includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, and the first color sub-pixel row, the second color sub-pixel row and the third color sub-pixel row are sequentially and repeatedly arranged along the column direction. Illustratively, the first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel, and then the red sub-pixel row, the green sub-pixel row, and the blue sub-pixel row are repeatedly arranged in sequence. For example, red subpixel rows R11 to R16, green subpixel rows G11 to G16, blue subpixel rows B11 to B16, red subpixel rows R21 to R26, green subpixel rows G21 to G26, blue subpixel rows B21 to B26, red subpixel rows R31 to R36, green subpixel rows G31 to G36, and blue subpixel rows B31 to B36. Since three sub-pixels in the same pixel unit in the conventional display panel are controlled by three data lines and one gate line. In the display panel in the embodiment of the present disclosure, three sub-pixels in the same pixel unit are controlled by one data line and three gate lines, so that the number of data lines is reduced to one third of the original number, the number of source driving circuits can be reduced, and the overall module cost is reduced; and the drawing space is saved, the lower frame of the display panel can be reduced, and the display panel can meet the high specification requirement of a narrower frame.

In the display panel provided by the embodiment of the application, one data line is connected with red, green and blue sub-pixels, when a red monochromatic picture, a green monochromatic picture or a blue monochromatic picture is displayed, because signals on one data line need to continuously jump, data drive is displayed as heavy load on the monochromatic picture, and therefore the power consumption of the monochromatic picture is too large, and the defects of uneven display and the like appear under the condition that the sub-pixels are not charged sufficiently. Especially, in a display panel applied to an embedded touch technology, heavy-load driving of a monochrome picture causes coupling of a common electrode, and aggravates problems such as horizontal stripe detection.

Based on this, the embodiment of the present disclosure provides a driving method of a display panel, as shown in fig. 3, including the following steps:

and S10, when the first driving mode is adopted, loading different control signals to each signal transmission line in the plurality of signal transmission lines in one display frame, controlling each cascade group to work sequentially, and controlling each shift register in the same cascade group to scan the coupled grid lines line by line and scan the plurality of grid lines line by line.

And S20, when the second driving mode is adopted, in one display frame, one of the cascade groups is used as a set cascade group, a control signal is loaded to the signal transmission line coupled with the set cascade group, each shift register in the set cascade group is controlled to scan the coupled grid lines line by line, and a cut-off signal is loaded to the signal transmission lines coupled with the other cascade groups except the set cascade group in the plurality of cascade groups.

Some embodiments of the present disclosure provide a driving method, in which a plurality of shift registers are divided into a plurality of cascade groups, the color of the sub-pixels corresponding to the gate lines coupled to the shift registers in the same cascade group is the same, and the shift registers in the same cascade group are arranged in a cascade manner, and different cascade groups are coupled to different signal transmission lines. Therefore, the shift registers in the same cascade group can drive the grid lines coupled with the same color sub-pixels, and the shift registers in the same cascade group can control the transistors in the same color sub-pixels to be conducted. And enabling the shift registers in the different cascaded sets to drive the grid lines coupled with the sub-pixels with different colors, so that the shift registers in the different cascaded sets can control the conduction of the transistors in the sub-pixels with different colors, and the sub-pixels with different colors can be driven independently. When the first driving mode is adopted, different control signals are loaded on each signal transmission line in a plurality of signal transmission lines in one display frame, each cascade group is controlled to work sequentially, each shift register in the same cascade group scans the coupled grid lines line by line, and the plurality of grid lines are scanned line by line, so that each line of sub-pixels can be driven line by line in one display frame. When the second driving mode is adopted, in one display frame, one of the plurality of cascade groups is used as a set cascade group, a control signal is loaded on the signal transmission line coupled with the set cascade group, each shift register in the set cascade group is controlled to scan the coupled grid lines line by line, and a cut-off signal is loaded on the signal transmission lines coupled with the other cascade groups except the set cascade group in the plurality of cascade groups, so that the sub-pixels with the same color can be driven in one display frame.

In some embodiments of the present disclosure, when the gate line is scanned, a corresponding data voltage is further input to the data line, so that the corresponding sub-pixel is charged.

In some embodiments of the present disclosure, the gate driving circuit may include a plurality of shift registers, and a driving output terminal GO of one shift register is coupled to one gate line. Illustratively, as shown in fig. 4, the shift register may include: switching transistors M1-M18 and a storage capacitor C1. The shift register is coupled to the input signal terminal IP, the reset signal terminal RE, the first frame reset signal terminal SRE1, the second frame reset signal terminal SRE2, the clock signal terminal CLK, the first reference voltage terminal VGL, the second reference voltage terminal LVGL, the first switching control terminal VDDO, the second switching control terminal VDDE, the cascade output terminal CO, the driving output terminal GO, the first node PU, the second node PD1, and the third node PD 2. The operation of the shift register shown in fig. 4 corresponds to a signal timing diagram in each display frame, as shown in fig. 5. Wherein, Fn represents the nth display frame, Fn + a represents the nth + a display frame, TS represents the scanning phase, and BT represents the blank Time (Blanking Time) phase. IP represents a signal of the input signal terminal IP, CLK represents a clock signal of the clock signal terminal CLK, GO represents a signal of the driving output terminal GO, RE represents a signal of the reset signal terminal RE, VDDO represents a signal of the first switching control terminal VDDO, and vddE represents a signal of the second switching control terminal vddE. Wherein a may be 1, 2, 3, 4 or other values, which are not limited herein. In specific implementation, the specific working process of the shift register shown in fig. 4 and the signal timing diagram shown in fig. 5 is basically the same as that in the prior art, and is not described herein again. It should be noted that the present disclosure is only described by taking the structure of the shift register shown in fig. 4 as an example, and in practical applications, the shift register may also adopt other structures, which is not limited herein.

Illustratively, the driving output terminal GO of each shift register is coupled to one gate line in a one-to-one correspondence. The active level of the signal go can control the transistors in the sub-pixels coupled to the corresponding gate lines to be turned on, and the inactive level can control the transistors in the sub-pixels coupled to the corresponding gate lines to be turned off. Illustratively, the transistors in the sub-pixels are N-type transistors, the active level of the signal go may be a high level, the inactive level is a low level, the first reference voltage terminal VGL and the second reference voltage terminal LVGL are both fixed voltages of a low level, and the voltage of the second reference voltage terminal LVGL is less than the voltage of the first reference voltage terminal VGL. Alternatively, the transistors in the sub-pixels are P-type transistors, the active level of the signal go may be a low level, the inactive level is a high level, the first reference voltage terminal VGL and the second reference voltage terminal LVGL are both fixed voltages of a high level, and the voltage of the second reference voltage terminal LVGL is higher than the voltage of the first reference voltage terminal VGL.

In some embodiments of the present disclosure, the display panel may further include a plurality of clock signal lines, and the plurality of clock signal lines are respectively coupled to the gate driving circuits. In this way, a corresponding clock signal can be input to the gate driving circuit through the clock signal line, and the clock signal is input to the clock signal terminal of the shift register, so that the shift register outputs signals to the coupled gate lines. For example, as shown in fig. 6, the display panel may include 6 clock signal lines CKS 1-CKS 6, and the 6 clock signal lines CKS 1-CKS 6 are coupled to the gate driving circuit 110. It should be noted that fig. 6 only illustrates 6 clock signal lines, and in practical applications, the specific number of clock signal lines may be determined according to practical application requirements, and is not limited herein, and for example, the specific number may be another number of clock signal lines which is an integral multiple of 2, such as 2, 4, 8, 10, 12, and the like.

In some embodiments of the present disclosure, the first frame reset signal terminals SRE1 of the shift registers of different stages are all coupled to the same first frame reset signal line, so that the shift registers can be reset uniformly. And the second frame reset signal terminals SRE2 of the shift registers of each stage are all coupled to the same second frame reset signal line, so that the shift registers can be reset uniformly.

In some embodiments of the present disclosure, the plurality of shift registers are divided into a plurality of cascaded groups, the color of the sub-pixels corresponding to the gate lines coupled to the shift registers in the same cascaded group is the same, and the shift registers in the same cascaded group are arranged in a cascaded manner. Therefore, the shift registers in the same cascaded group can drive the grid lines coupled with the same color sub-pixels, and the shift registers in the same cascaded group can control the transistors in the same color sub-pixels to be conducted. And enabling the shift registers in the different cascaded sets to drive the grid lines coupled with the sub-pixels with different colors, so that the shift registers in the different cascaded sets can control the conduction of the transistors in the sub-pixels with different colors, and the sub-pixels with different colors can be driven independently. Illustratively, taking an example that the plurality of sub-pixels of different colors includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel, the first color sub-pixel corresponds to one cascaded group, the second color sub-pixel also corresponds to one cascaded group, and the third color sub-pixel also corresponds to one cascaded group, then the plurality of cascaded groups is three, and the cascaded group corresponding to the first color sub-pixel in the three cascaded groups is defined as a first cascaded group, the cascaded group corresponding to the second color sub-pixel is defined as a second cascaded group, and the cascaded group corresponding to the third color sub-pixel is defined as a third cascaded group.

Illustratively, as shown in fig. 6 to 7c, the plurality of shift registers are divided into 3 cascaded sets: a first cascaded group ZGOA1, a second cascaded group ZGOA2, and a third cascaded group ZGOA 3. The first cascaded group ZGOA1 comprises shift registers SR1, SR4 and SR7, the second cascaded group ZGOA2 comprises shift registers SR2, SR5 and SR8, and the third cascaded group ZGOA3 comprises shift registers SR3, SR6 and SR 9. That is, the shift registers in the first cascaded set ZGOA1 are respectively coupled to the gate lines coupled to the red subpixels (i.e., GA1, GA4, GA7), the shift registers in the second cascaded set ZGOA2 are respectively coupled to the gate lines coupled to the green subpixels (i.e., GA2, GA5, GA8), and the shift registers in the third cascaded set ZGOA3 are respectively coupled to the gate lines coupled to the blue subpixels (i.e., GA3, GA6, GA 9).

Exemplarily, as shown in fig. 6 to 7c, the display panel further includes: a first frame start signal line STV 1; a plurality of concatenated groups are coupled to the same first start-of-frame signal line STV 1. Namely, the first cascaded group ZGOA1, the second cascaded group ZGOA2 and the third cascaded group ZGOA3 are all coupled to the first frame start signal line STV 1. The input signal terminal IP of the shift register SR1 of the first cascade ZGOA1 is coupled to the first start-of-frame signal line STV1STV 1. An input signal terminal IP of the shift register SR4 is coupled to the cascade output terminal CO of the shift register SR1, and a reset signal terminal RE of the shift register SR1 is coupled to the cascade output terminal CO of the shift register SR 4. An input signal terminal IP of the shift register SR7 is coupled to the cascade output terminal CO of the shift register SR4, and a reset signal terminal RE of the shift register SR4 is coupled to the cascade output terminal CO of the shift register SR 7. The driving output terminal GO of the shift register SR1 is coupled to the gate line GA1, the driving output terminal GO of the shift register SR4 is coupled to the gate line GA4, and the driving output terminal GO of the shift register SR7 is coupled to the gate line GA 7.

And the input signal terminal IP of the shift register SR2 of the second cascade ZGOA2 is coupled to the first start-of-frame signal line STV1STV 1. An input signal terminal IP of the shift register SR5 is coupled to the cascade output terminal CO of the shift register SR2, and a reset signal terminal RE of the shift register SR2 is coupled to the cascade output terminal CO of the shift register SR 5. An input signal terminal IP of the shift register SR8 is coupled to the cascade output terminal CO of the shift register SR5, and a reset signal terminal RE of the shift register SR5 is coupled to the cascade output terminal CO of the shift register SR 8. The driving output terminal GO of the shift register SR2 is coupled to the gate line GA2, the driving output terminal GO of the shift register SR5 is coupled to the gate line GA5, and the driving output terminal GO of the shift register SR8 is coupled to the gate line GA 8.

And the input signal terminal IP of the shift register SR3 of the third cascade group ZGOA3 is coupled to the first start-of-frame signal line STV1STV 1. An input signal terminal IP of the shift register SR6 is coupled to the cascade output terminal CO of the shift register SR3, and a reset signal terminal RE of the shift register SR3 is coupled to the cascade output terminal CO of the shift register SR 6. An input signal terminal IP of the shift register SR9 is coupled to the cascade output terminal CO of the shift register SR6, and a reset signal terminal RE of the shift register SR6 is coupled to the cascade output terminal CO of the shift register SR 9. The driving output terminal GO of the shift register SR3 is coupled to the gate line GA3, the driving output terminal GO of the shift register SR6 is coupled to the gate line GA6, and the driving output terminal GO of the shift register SR9 is coupled to the gate line GA 9.

In some embodiments of the present disclosure, different cascaded sets are coupled to different signal transmission lines, the plurality of signal transmission lines include a plurality of clock signal lines, the plurality of clock signal lines are divided into a plurality of clock line groups, each clock line group includes at least two clock signal lines; one cascade group is coupled to a clock signal line in one clock line group, and the control signal includes a clock signal. Illustratively, different clock signal lines carry clock signals of different timings, and different cascaded sets couple different clock signal lines. For example, the first cascaded group ZGOA1 is coupled to clock signal lines CKS1 to CKS2, the second cascaded group ZGOA2 is coupled to clock signal lines CKS3 to CKS4, and the third cascaded group ZGOA3 is coupled to clock signal lines CKS5 to CKS 6. Illustratively, as shown in FIG. 6 to FIG. 7c, the clock signal terminal CLK of the shift register SR8k-5 of the 6k-5 th stage is coupled to the clock signal line CKS1, the clock signal terminal CLK of the shift register SR8k-5 of the 6k-4 th stage is coupled to the clock signal line CKS2, the clock signal terminal CLK of the shift register SR8k-5 of the 6k-3 th stage is coupled to the clock signal line CKS3, the clock signal terminal CLK of the shift register SR8k-5 of the 6k-2 th stage is coupled to the clock signal line CKS4, the clock signal terminal CLK of the shift register SR8k-5 of the 6k-1 th stage is coupled to the clock signal line CKS5, the clock signal terminal CLK of the shift register SR8k-5 of the 6k stage is coupled to the clock signal line CKS6, and k is an integer greater than 0.

In some embodiments of the present disclosure, a portion of the cascade groups may be disposed at a first end of the plurality of gate lines, and another portion of the cascade groups may be disposed at a second end of the plurality of gate lines. For example, the first cascaded set ZGOA1 and the first cascaded set ZGOA1 are disposed at a first end of the plurality of gate lines and the second cascaded set ZGOA2 is disposed at a second end of the plurality of gate lines.

In some embodiments of the present disclosure, all the cascade groups may also be disposed at the same end of the plurality of gate lines. For example, the first cascaded group ZGOA1 to the third cascaded group ZGOA3 may be all located at the same end of the plurality of gate lines. Illustratively, the first through third cascaded sets ZGOA1 through ZGOA3 may all be located on the left side of the plurality of gate lines.

In some embodiments of the present disclosure, each shift register may also include a left shift register disposed at a first end of the same gate line and a right shift register disposed at a second end, and the left shift register and the right shift register coupled to the same gate line output signals simultaneously. Illustratively, two first stage shift registers SR1 are provided, one being a left shift register SR1 and the other being a right shift register SR 1. And the left shift register SR1 and the right shift register SR1 simultaneously input signals to the gate line GA 1. Two second-stage shift registers SR2 are also provided, one is the left shift register SR2, and the other is the right shift register SR 2. And the left shift register SR2 and the right shift register SR2 simultaneously input signals to the gate line GA 2. Two third stage shift registers SR3 are also provided, one being a left side shift register SR3 and the other being a right side shift register SR 3. And the left shift register SR3 and the right shift register SR3 simultaneously input signals to the gate line GA 3. The same reasoning can be followed for the rest, and will not be described herein.

When the structures shown in fig. 6 to fig. 7c are taken as examples of the gate driving circuit in the display panel provided by the embodiment of the present disclosure, a corresponding signal timing diagram is shown in fig. 8 when the first driving mode is adopted. Wherein, CKS1_1 represents the clock signal on the clock signal line CKS1, CKS2_1 represents the clock signal on the clock signal line CKS2, CKS3_1 represents the clock signal on the clock signal line CKS3, CKS4_1 represents the clock signal on the clock signal line CKS4, CKS5_1 represents the clock signal on the clock signal line CKS5, CKS6_1 represents the clock signal on the clock signal line CKS6, and STV1_1 represents the signal on the first frame start signal line STV 1. GA1_1 represents a signal input from the driving output terminal GO of the first stage shift register SR1 to the gate line GA1, GA2_1 represents a signal input from the driving output terminal GO of the second stage shift register SR2 to the gate line GA2, GA3_1 represents a signal input from the driving output terminal GO of the third stage shift register SR3 to the gate line GA3, GA4_1 represents a signal input from the driving output terminal GO of the fourth stage shift register SR4 to the gate line GA4, GA5_1 represents a signal input from the driving output terminal GO of the fifth stage shift register SR5 to the gate line GA5, GA6_1 represents a signal input from the driving output terminal GO of the sixth stage shift register SR6 to the gate line GA6, GA7_1 represents a signal input from the driving output terminal GO of the seventh stage shift register SR7 to the gate line GA7, and GA7_1 represents a signal input from the driving output terminal GO _ 72 of the eighth stage shift register SR7 to the gate line GA 7. When the first driving mode is adopted, in one display frame, signals CKS1_1 to CKS6_1 are loaded on clock signal lines CKS1 to CKS6 respectively, signals GA1_1, GA4 and GA7 output signals GA1_1, GA4_1 and GA7_1 from the shift register units in the first cascaded group ZGOA1 coupled to the gate lines GA1, GA4 and GA7, signals GA2_1, GA5_1 and GA8_1 from the shift register units in the second cascaded group ZGOA2 coupled to the gate lines GA2, GA5 and GA8 output signals GA2_1, GA5_1 and GA8_1, and signals GA3, GA6 and GA9 output signals GA3_1, GA6_1 and GA9_1 from the shift register units in the third cascaded group ZGOA3 coupled to the gate lines GA 3. And when scanning the grid line, the source electrode driving circuit also inputs corresponding data voltage to each data line to charge the corresponding sub-pixel, even if each sub-pixel is charged, thereby adopting red, green and blue color mixing to realize color display.

In some embodiments of the present disclosure, the cascade group is set to one of the first cascade group, the second cascade group, and the third cascade group when the second driving mode is adopted. That is, one cascade group is controlled to operate in one display frame. Illustratively, when the second driving mode is adopted, in each of the plurality of consecutive display frames, the cascade group is set to a cascade group corresponding to the same color sub-pixel. For example, when the second driving mode is adopted, the first cascade group operation is controlled in each of a plurality of consecutive display frames, so that the display panel displays a first-color monochrome picture (for example, a red monochrome picture). Alternatively, when the second driving mode is adopted, the second cascade group is controlled to operate in each of a plurality of consecutive display frames, so that the display panel displays a second color monochrome picture (e.g., a green monochrome picture). Alternatively, when the second driving mode is adopted, the third cascade operation is controlled in each of a plurality of consecutive display frames, so that the display panel displays a third color monochrome picture (e.g., a blue monochrome picture).

Illustratively, when the second driving mode is adopted, the cascade group is set to a cascade group sequentially repeated according to the cascade group corresponding to the first color sub-pixel, the cascade group corresponding to the second color sub-pixel, and the cascade group corresponding to the third color sub-pixel in a plurality of consecutive display frames. For example, in three adjacent display frames of a plurality of consecutive display frames, the first display frame controls the first cascade operation to make the display panel display a first color monochrome picture (e.g., a red monochrome picture), the second display frame controls the second cascade operation to make the display panel display a second color monochrome picture (e.g., a green monochrome picture), and the third display frame controls the third cascade operation to make the display panel display a third color monochrome picture (e.g., a blue monochrome picture).

In the gate driving circuit in the display panel provided by the embodiment of the present disclosure, taking the structure shown in fig. 6 to 7c as an example, when the second driving mode is adopted, the display panel is driven to display a red monochrome picture, and a corresponding signal timing diagram is shown in fig. 9 a. Wherein CKS1_2 represents the clock signal on the clock signal line CKS1, CKS2_2 represents the clock signal on the clock signal line CKS2, CKS3_2 represents the clock signal on the clock signal line CKS3, CKS4_2 represents the clock signal on the clock signal line CKS4, CKS5_2 represents the clock signal on the clock signal line CKS5, CKS6_2 represents the clock signal on the clock signal line CKS6, and STV1_2 represents the signal on the first frame start signal line STV 1. GA1_2 represents a signal input from the driving output terminal GO of the first stage shift register SR1 to the gate line GA1, GA2_2 represents a signal input from the driving output terminal GO of the second stage shift register SR2 to the gate line GA2, GA3_2 represents a signal input from the driving output terminal GO of the third stage shift register SR3 to the gate line GA3, GA4_2 represents a signal input from the driving output terminal GO of the fourth stage shift register SR4 to the gate line GA4, GA5_2 represents a signal input from the driving output terminal GO of the fifth stage shift register SR5 to the gate line GA5, GA6_2 represents a signal input from the driving output terminal GO of the sixth stage shift register SR6 to the gate line GA6, GA7_2 represents a signal input from the driving output terminal GO of the seventh stage shift register SR7 to the gate line GA7, and GA7_2 represents a signal input from the driving output terminal GO _ 72 of the eighth stage shift register SR7 to the gate line GA 7. When the second driving mode is adopted, the clock signal lines CKS1 to CKS2 are loaded with the clock signals CKS1_2 to CKS2_2, the clock signal lines CKS3 to CKS6 are loaded with low-level cut-off signals, the shift register units in the first cascade group ZGOA1 are controlled to output low-level cut-off signals GA2_2, GA5_2 and GA5_2 to the gate lines GA1, GA4 and GA6 5 coupled thereto and output signals GA1_2, GA4_2 and GA7_2 to the gate lines GA2, GA7 and GA8 coupled thereto, and the shift register units in the second cascade group ZGOA2 are controlled to output low-level cut-off signals GA5_2, GA5_2 and GA5_2 to the gate lines GA5, GA5 coupled thereto and GA5 in the third cascade group ZGOA 5. And when scanning the grid line, the source electrode driving circuit also inputs corresponding data voltage to each data line, so that the corresponding red sub-pixel is charged, even if each red sub-pixel is charged, and the display of a red single-color picture is realized.

When the gate driving circuit in the display panel provided by the embodiment of the present disclosure takes the structure shown in fig. 6 to fig. 7c as an example, and the second driving mode is adopted, the display panel is driven to display a green monochromatic image, and the corresponding signal timing diagram is shown in fig. 9 b. Wherein, CKS1_2 represents the clock signal on the clock signal line CKS1, CKS2_2 represents the clock signal on the clock signal line CKS2, CKS3_2 represents the clock signal on the clock signal line CKS3, CKS4_2 represents the clock signal on the clock signal line CKS4, CKS5_2 represents the clock signal on the clock signal line CKS5, CKS6_2 represents the clock signal on the clock signal line CKS6, and STV1_2 represents the signal on the first frame start signal line STV 1. GA1_2 represents a signal input from the driving output terminal GO of the first stage shift register SR1 to the gate line GA1, GA2_2 represents a signal input from the driving output terminal GO of the second stage shift register SR2 to the gate line GA2, GA3_2 represents a signal input from the driving output terminal GO of the third stage shift register SR3 to the gate line GA3, GA4_2 represents a signal input from the driving output terminal GO of the fourth stage shift register SR4 to the gate line GA4, GA5_2 represents a signal input from the driving output terminal GO of the fifth stage shift register SR5 to the gate line GA5, GA6_2 represents a signal input from the driving output terminal GO of the sixth stage shift register SR6 to the gate line GA6, GA7_2 represents a signal input from the driving output terminal GO of the seventh stage shift register SR7 to the gate line GA7, and GA7_2 represents a signal input from the driving output terminal GO _ 72 of the eighth stage shift register SR7 to the gate line GA 7. When the second driving mode is adopted, the clock signals CKS3_2 to CKS4_2 are loaded to the clock signal lines CKS3 to CKS4, the cut-off signals with low levels are loaded to the clock signal lines CKS1 to CKS2 and CKS5 to CKS6, the shift register units in the first cascade group ZGOA1 are controlled to output the cut-off signals GA1_2, GA1_2 and GA1_2 with low levels to the coupled gate lines GA1, GA4 and GA7, the shift register units in the second cascade group ZGOA1 are controlled to output the signals GA1_2, GA1_2 and GA1_2 to the coupled gate lines GA1, GA1 and GA1, and the shift register units in the third cascade group ZGOA1 are controlled to output the cut-off signals GA1_2, GA1_1 and GA1_1 with low levels to the coupled gate lines GA1, GA1 and GA 1. And when scanning the grid line, the source electrode driving circuit also inputs corresponding data voltage to each data line, so that the corresponding green sub-pixel is charged, even if each green sub-pixel is charged, and the display of green single-color pictures is realized.

In the gate driving circuit in the display panel provided by the embodiment of the present disclosure, taking the structures shown in fig. 6 to 7c as an example, when the second driving mode is adopted, the display panel is driven to display a red monochrome picture, and a corresponding signal timing diagram is shown in fig. 9 c. Wherein CKS1_2 represents the clock signal on the clock signal line CKS1, CKS2_2 represents the clock signal on the clock signal line CKS2, CKS3_2 represents the clock signal on the clock signal line CKS3, CKS4_2 represents the clock signal on the clock signal line CKS4, CKS5_2 represents the clock signal on the clock signal line CKS5, CKS6_2 represents the clock signal on the clock signal line CKS6, and STV1_2 represents the signal on the first frame start signal line STV 1. GA1_2 represents a signal input from the driving output terminal GO of the first stage shift register SR1 to the gate line GA1, GA2_2 represents a signal input from the driving output terminal GO of the second stage shift register SR2 to the gate line GA2, GA3_2 represents a signal input from the driving output terminal GO of the third stage shift register SR3 to the gate line GA3, GA4_2 represents a signal input from the driving output terminal GO of the fourth stage shift register SR4 to the gate line GA4, GA5_2 represents a signal input from the driving output terminal GO of the fifth stage shift register SR5 to the gate line GA5, GA6_2 represents a signal input from the driving output terminal GO of the sixth stage shift register SR6 to the gate line GA6, GA7_2 represents a signal input from the driving output terminal GO of the seventh stage shift register SR7 to the gate line GA7, and GA7_2 represents a signal input from the driving output terminal GO _ 72 of the eighth stage shift register SR7 to the gate line GA 7. When the second driving mode is adopted, the clock signal lines CKS5 to CKS6 are loaded with the clock signals CKS5_2 to CKS6_2, the clock signal lines CKS1 to CKS4 are loaded with low-level cut-off signals, the shift register units in the first cascade group ZGOA1 are controlled to output low-level signals GA9_2, GA4_2 and GA7_2 to the coupled gate lines GA1, GA4 and GA 28, the shift register units in the second cascade group ZGOA2 are controlled to output low-level cut-off signals GA2_2, GA5_2 and GA5_2 to the coupled gate lines GA2, GA7 and GA8, and the shift register units in the third cascade group ZGOA 5 are controlled to output signals GA5_2, GA5_2 and 5_2 to the coupled gate lines GA 5. And when scanning the grid line, the source driving circuit also inputs corresponding data voltage to each data line, so that the corresponding blue sub-pixel is charged, even if each blue sub-pixel is charged, and the display of the blue single-color picture is realized.

In summary, in the driving method provided by the embodiment of the disclosure, since the three colors of the red sub-pixel, the green sub-pixel, and the blue sub-pixel can be independently controlled by different clock line groups and different cascade groups, when the display panel displays the red monochrome image, the green monochrome image, and the blue monochrome image, the clock signal output of the other two clock line groups is cancelled, and the other two clock line groups are kept in the low level state. The conversion of data voltage from heavy load driving to light load driving under a single-color picture can be realized, the power consumption of a display panel for displaying a red single-color picture, a green single-color picture and a blue single-color picture is reduced, the charging rate is improved, and the problem of detecting horizontal stripes is reduced.

The embodiments of the present disclosure provide other schematic structural diagrams of a display panel, as shown in fig. 10, which are modified from the embodiments in the foregoing embodiments. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

In some embodiments of the present disclosure, as shown in fig. 10, the plurality of signal transmission lines further includes a plurality of second frame start signal lines. The plurality of cascade groups are coupled with the plurality of second frame start signal lines in a one-to-one correspondence manner, and the control signal comprises a frame start signal. That is, the plurality of signal transmission lines further include a plurality of clock signal lines and a plurality of second frame start signal lines. The control signals include a clock signal and a frame start signal.

When the structures shown in fig. 10 to 11c are taken as examples of the gate driving circuit in the display panel provided by the embodiment of the present disclosure, a corresponding signal timing diagram is shown in fig. 12 when the first driving mode is adopted. Wherein CKS1_1 represents the clock signal on the clock signal line CKS1, CKS2_1 represents the clock signal on the clock signal line CKS2, CKS3_1 represents the clock signal on the clock signal line CKS3, CKS4_1 represents the clock signal on the clock signal line CKS4, CKS5_1 represents the clock signal on the clock signal line CKS5, CKS6_1 represents the clock signal on the clock signal line CKS6, STV2_1 represents the signal on the second frame start signal line STV2, STV3_1 represents the signal on the second frame start signal line STV3, and STV4_1 represents the signal on the second frame start signal line STV 4. The reference numeral "GA 1_ 1" represents a signal input from the driving output terminal GO of the first stage shift register SR1 to the gate line GA1, the reference numeral "GA 2_ 1" represents a signal input from the driving output terminal GO of the second stage shift register SR2 to the gate line GA2, the reference numeral "GA 3_ 1" represents a signal input from the driving output terminal GO of the third stage shift register SR3 to the gate line GA3, the reference numeral "GA 4_ 1" represents a signal input from the driving output terminal GO of the fourth stage shift register SR4 to the gate line GA4, the reference numeral "GA 5_ 1" represents a signal input from the driving output terminal GO of the fifth stage shift register SR5 to the gate line GA5, the reference numeral "GA 6_ 1" represents a signal input from the driving output terminal GO of the sixth stage shift register SR6 to the gate line GA6, the reference numeral "GA 7_ 1" represents a signal input from the driving output terminal GO 7 of the seventh stage shift register SR7 to the gate line GA7, the reference numeral "GO 7" GO _1 "represents a signal input from the driving output terminal GO 7 of the eighth stage shift register SR7 to the gate line GA 7. When the first driving mode is adopted, in one display frame, signals CKS1_1 to CKS6_1 are loaded on clock signal lines CKS1 to CKS6 respectively, signals GA1_1, GA4 and GA7 output signals GA1_1, GA4_1 and GA7_1 from the shift register units in the first cascaded group ZGOA1 coupled to the gate lines GA1, GA4 and GA7, signals GA2_1, GA5_1 and GA8_1 from the shift register units in the second cascaded group ZGOA2 coupled to the gate lines GA2, GA5 and GA8 output signals GA2_1, GA5_1 and GA8_1, and signals GA3, GA6 and GA9 output signals GA3_1, GA6_1 and GA9_1 from the shift register units in the third cascaded group ZGOA3 coupled to the gate lines GA 3. And when scanning the grid line, the source electrode driving circuit also inputs corresponding data voltage to each data line to charge the corresponding sub-pixel, even if each sub-pixel is charged, thereby adopting red, green and blue color mixing to realize color display.

In some embodiments of the present disclosure, when the second driving mode is adopted, in one display frame, a frame start signal is applied to the second frame start signal line to which the set cascade group is coupled, and a cut-off signal is applied to the second frame start signal lines to which the other cascade groups are coupled, a clock signal is applied to each clock signal line, and each shift register in the set cascade group is controlled to scan the coupled gate lines line by line.

In the gate driving circuit in the display panel provided by the embodiment of the present disclosure, taking the structure shown in fig. 10 to 11c as an example, when the second driving mode is adopted, the display panel is driven to display a red monochrome picture, and a corresponding signal timing diagram is shown in fig. 13 a. Wherein CKS1_2 represents the clock signal on the clock signal line CKS1, CKS2_2 represents the clock signal on the clock signal line CKS2, CKS3_2 represents the clock signal on the clock signal line CKS3, CKS4_2 represents the clock signal on the clock signal line CKS4, CKS5_2 represents the clock signal on the clock signal line CKS5, CKS6_2 represents the clock signal on the clock signal line CKS6, STV2_2 represents the signal on the second frame start signal line STV2, STV3_2 represents the signal on the second frame start signal line STV3, and STV4_2 represents the signal on the second frame start signal line STV 4. GA1_2 represents a signal input from the driving output terminal GO of the first stage shift register SR1 to the gate line GA1, GA2_2 represents a signal input from the driving output terminal GO of the second stage shift register SR2 to the gate line GA2, GA3_2 represents a signal input from the driving output terminal GO of the third stage shift register SR3 to the gate line GA3, GA4_2 represents a signal input from the driving output terminal GO of the fourth stage shift register SR4 to the gate line GA4, GA5_2 represents a signal input from the driving output terminal GO of the fifth stage shift register SR5 to the gate line GA5, GA6_2 represents a signal input from the driving output terminal GO of the sixth stage shift register SR6 to the gate line GA6, GA7_2 represents a signal input from the driving output terminal GO of the seventh stage shift register SR7 to the gate line GA7, and GA7_2 represents a signal input from the driving output terminal GO _ 72 of the eighth stage shift register SR7 to the gate line GA 7. When the second driving mode is adopted, the clock signals CKS1_2 to CKS6_2 are loaded to the clock signal lines CKS1 to CKS6, the frame start signal is loaded to the second frame start signal line STV2, the cut-off signals are loaded to the second frame start signal lines STV3 to STV4, the shift register units in the first cascade group ZGOA1 are controlled to output signals GA1_2, GA4_2 and GA7_2 to the gate lines GA1, GA4 and GA7 coupled to the gate lines GA1, GA4 and GA7, the shift register units in the second cascade group ZGOA2 are controlled to output low-level cut-off signals GA2_2, GA2_2 and GA2_2 to the gate lines GA2, GA2 and GA2 coupled to the shift register units in the third cascade group ZGOA2, and the low-level cut-off signals GA2, GA2_2 and GA2_2 are controlled to the shift register units in the third cascade group ZGOA 2. And when scanning the grid line, the source electrode driving circuit also inputs corresponding data voltage to each data line, so that the corresponding red sub-pixel is charged, even if each red sub-pixel is charged, and the display of a red single-color picture is realized.

In the gate driving circuit in the display panel provided by the embodiment of the present disclosure, taking the structure shown in fig. 10 to 11c as an example, when the second driving mode is adopted, the display panel is driven to display a green monochromatic picture, and a corresponding signal timing diagram is shown in fig. 13 b. Wherein CKS1_2 represents the clock signal on the clock signal line CKS1, CKS2_2 represents the clock signal on the clock signal line CKS2, CKS3_2 represents the clock signal on the clock signal line CKS3, CKS4_2 represents the clock signal on the clock signal line CKS4, CKS5_2 represents the clock signal on the clock signal line CKS5, CKS6_2 represents the clock signal on the clock signal line CKS6, STV2_2 represents the signal on the second frame start signal line STV2, STV3_2 represents the signal on the second frame start signal line STV3, and STV4_2 represents the signal on the second frame start signal line STV 4. GA1_2 represents a signal input from the driving output terminal GO of the first stage shift register SR1 to the gate line GA1, GA2_2 represents a signal input from the driving output terminal GO of the second stage shift register SR2 to the gate line GA2, GA3_2 represents a signal input from the driving output terminal GO of the third stage shift register SR3 to the gate line GA3, GA4_2 represents a signal input from the driving output terminal GO of the fourth stage shift register SR4 to the gate line GA4, GA5_2 represents a signal input from the driving output terminal GO of the fifth stage shift register SR5 to the gate line GA5, GA6_2 represents a signal input from the driving output terminal GO of the sixth stage shift register SR6 to the gate line GA6, GA7_2 represents a signal input from the driving output terminal GO of the seventh stage shift register SR7 to the gate line GA7, and GA7_2 represents a signal input from the driving output terminal GO _ 72 of the eighth stage shift register SR7 to the gate line GA 7. When the second driving mode is adopted, the clock signals CKS1_2 to CKS6_2 are loaded to the clock signal lines CKS1 to CKS6, the frame start signal is loaded to the second frame start signal line STV3, the cut-off signals are loaded to the second frame start signal lines STV2 and STV4, the shift register units in the first cascade group ZGOA1 are controlled to output low-level cut-off signals GA1_2, GA4_2 and GA7_2 to the gate lines GA1, GA4 and GA7 coupled to the gate lines, the shift register units in the second cascade group ZGOA2 are controlled to output signals GA2_2, GA2_2 and GA2_2 to the gate lines GA2 and GA2 coupled to the second cascade group ZGOA2, and the shift register units in the third cascade group ZGOA2 are controlled to output low-level cut-off signals GA2, GA _2 and GA2_ 2. And when scanning the grid line, the source electrode driving circuit also inputs corresponding data voltage to each data line, so that the corresponding green sub-pixel is charged, even if each green sub-pixel is charged, and the display of green single-color pictures is realized.

In the gate driving circuit in the display panel provided by the embodiment of the present disclosure, taking the structure shown in fig. 10 to 11c as an example, when the second driving mode is adopted, the display panel is driven to display a red monochrome picture, and a corresponding signal timing diagram is shown in fig. 13 c. Wherein CKS1_2 represents the clock signal on the clock signal line CKS1, CKS2_2 represents the clock signal on the clock signal line CKS2, CKS3_2 represents the clock signal on the clock signal line CKS3, CKS4_2 represents the clock signal on the clock signal line CKS4, CKS5_2 represents the clock signal on the clock signal line CKS5, CKS6_2 represents the clock signal on the clock signal line CKS6, STV2_2 represents the signal on the second frame start signal line STV2, STV3_2 represents the signal on the second frame start signal line STV3, and STV4_2 represents the signal on the second frame start signal line STV 4. GA1_2 represents a signal input from the driving output terminal GO of the first stage shift register SR1 to the gate line GA1, GA2_2 represents a signal input from the driving output terminal GO of the second stage shift register SR2 to the gate line GA2, GA3_2 represents a signal input from the driving output terminal GO of the third stage shift register SR3 to the gate line GA3, GA4_2 represents a signal input from the driving output terminal GO of the fourth stage shift register SR4 to the gate line GA4, GA5_2 represents a signal input from the driving output terminal GO of the fifth stage shift register SR5 to the gate line GA5, GA6_2 represents a signal input from the driving output terminal GO of the sixth stage shift register SR6 to the gate line GA6, GA7_2 represents a signal input from the driving output terminal GO of the seventh stage shift register SR7 to the gate line GA7, and GA7_2 represents a signal input from the driving output terminal GO _ 72 of the eighth stage shift register SR7 to the gate line GA 7. When the second driving mode is adopted, the clock signals CKS1_2 to CKS6_2 are loaded to the clock signal lines CKS1 to CKS6, the frame start signal is loaded to the second frame start signal line STV4, the cut-off signals are loaded to the second frame start signal lines STV2 to STV3, the shift register units in the first cascade group ZGOA1 are controlled to output signals GA1_2, 86ga 28 _2 and GA7_2 with low levels to the gate lines GA1, GA4 and GA7 which are coupled, the shift register units in the second cascade group ZGOA2 are controlled to output signals GA2, GA2 and GA2 which are coupled with low levels, the cut-off signals GA2_2, GA2_2 and GA2_2, and the shift register units in the third cascade group ZGOA2 are controlled to output signals GA2, GA2_2, GA _2 and 2_ 2. And when scanning the grating, the source drive circuit also inputs corresponding data voltage to each data line, so that the corresponding blue sub-pixel is charged, even if each blue sub-pixel is charged, thereby realizing the display of the blue single-color picture.

In other embodiments of the present disclosure, when the second driving mode is adopted, in one display frame, a frame start signal is applied to the second frame start signal line to which the set cascade group is coupled, and a stop signal is applied to the second frame start signal lines to which the other cascade groups are coupled, a clock signal is applied to the clock signal line to which the set cascade group is coupled, each shift register in the set cascade group is controlled to scan the coupled gate lines line by line, and a stop signal is applied to the clock signal lines to which the other cascade groups except the set cascade group are coupled in the plurality of cascade groups. For example, taking the structures shown in fig. 10 to 11c as examples, the manner of loading the signal on the second frame start signal line can refer to fig. 13a to 13c, which is not described herein again. As an example of the structures shown in fig. 10 to 11c, the manner of loading the signal on the clock signal line can be referred to fig. 9a to 9c, which is not described herein again.

In still other embodiments of the present disclosure, when the second driving mode is adopted, in one display frame, a frame start signal is loaded to each second frame start signal line, a clock signal is loaded to a clock signal line to which the set cascade group is coupled, each shift register in the set cascade group is controlled to scan the coupled gate lines line by line, and a cut-off signal is loaded to a clock signal line coupled to the other cascade groups except the set cascade group in the plurality of cascade groups. For example, taking the structures shown in fig. 10 to fig. 11c as examples, the manner of loading the signal on the second frame start signal line may refer to fig. 12, which is not described herein again. As an example of the structures shown in fig. 10 to 11c, the manner of loading the signal on the clock signal line can be referred to fig. 9a to 9c, which is not described herein again.

The embodiments of the present disclosure provide still other schematic structural diagrams of a display panel, as shown in fig. 14, which are modified from the embodiments in the foregoing embodiments. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

In some embodiments of the present disclosure, as shown in fig. 14, the display panel further includes a plurality of detection units 300, a detection input signal line, and a detection control signal line SW; the control terminal of the detecting unit 300 is coupled to the detection control signal line SW, the input terminal of the detecting unit 300 is coupled to the detection input signal line, and the output terminal of one detecting unit 300 is coupled to one data line. Illustratively, as shown in fig. 14, the data lines DA1 to DA6 are respectively coupled to one detecting unit 300 in a one-to-one correspondence. Alternatively, the detection unit 300 includes a detection transistor MS, a control terminal of the detection transistor MS is used as a control terminal of the detection unit 300, a first terminal of the detection transistor MS is used as an input terminal of the detection unit 300, and a second terminal of the detection transistor MS is used as an output terminal of the detection unit 300. The detection control signal line SW is one, and the control terminals of all the detection transistors are coupled to the detection control signal line SW. Two input signal lines are detected: a first detection input signal line DO and a second detection input signal line DE, a first terminal of a part of the detection transistors being coupled to the first detection input signal line DO, and a first terminal of the remaining part of the detection transistors being coupled to the second detection input signal line DE. Alternatively, the data line corresponding to the sensing transistor coupled to the first sensing input signal line DO and the data line corresponding to the sensing transistor coupled to the second sensing input signal line DE are alternately arranged. For example, the data line corresponding to the sensing transistor coupled to the first sensing input signal line DO is an odd-numbered data line, and the data line corresponding to the sensing transistor coupled to the second sensing input signal line DE is an even-numbered data line.

In some embodiments of the present disclosure, the driving method further includes: when the third driving mode is adopted, in one display frame, one of the plurality of cascade groups is used as a set cascade group, a control signal is loaded on the signal transmission line coupled with the set cascade group, each shift register in the set cascade group is controlled to scan the coupled grid lines line by line, a cut-off signal is loaded on the signal transmission lines coupled with the other cascade groups except the set cascade group in the plurality of cascade groups, a start signal is loaded on the detection control signal line SW, and a detection voltage is loaded on the detection input signal line, so that the corresponding sub-pixel is charged.

The structure of the gate driving circuit of the display panel shown in fig. 14 can be as shown in fig. 6. Illustratively, as shown in conjunction with fig. 6 and 14, the signal transmission line includes a clock signal line. When the third driving mode is adopted, the corresponding signal timing diagrams may be as shown in fig. 9a to 9 c. When the third driving mode is adopted, the process of controlling the shift register in the first cascaded set to the third cascaded set to work may refer to the above embodiments, and will not be described herein. When scanning the gate line, the detection control signal line SW is applied with an on signal, and the first detection input signal line DO and the second detection input signal line DE are applied with detection voltages, respectively, so that the detection voltages are input to the data lines, and the corresponding sub-pixels are charged.

The structure of the gate driving circuit of the display panel shown in fig. 14 can be as shown in fig. 10. Illustratively, as shown in conjunction with fig. 10 and 14, the signal transmission line includes a clock signal line and a frame start signal line. When the third driving mode is adopted, the corresponding signal timing charts may be as shown in fig. 13a to 13 c. When the third driving mode is adopted, the process of controlling the shift register in the first cascaded set to the third cascaded set to work may refer to the above embodiments, and will not be described herein. When scanning the gate line, the detection control signal line SW is applied with an on signal, and the first detection input signal line DO and the second detection input signal line DE are applied with detection voltages, respectively, so that the detection voltages are input to the data lines, and the corresponding sub-pixels are charged.

Based on the same concept, embodiments of the present disclosure also provide a display device, including: display panel and time schedule controller. Wherein, the display panel includes: the pixel structure comprises a plurality of sub-pixels with different colors, a plurality of grid lines, a grid driving circuit respectively coupled with the grid lines and a plurality of signal transmission lines coupled with the grid driving circuit; the color of the same row of sub-pixels is the same, one row of sub-pixels is coupled with one grid line, the grid drive circuit comprises a plurality of shift registers, the drive output end of one shift register is coupled with one grid line, the plurality of shift registers are divided into a plurality of cascade groups, the color of the grid line coupled with the shift register in the same cascade group is the same corresponding to the color of the sub-pixel, the shift registers in the same cascade group are arranged in a cascade mode, and different cascade groups are coupled with different signal transmission lines.

The time schedule controller is configured to load different control signals to each signal transmission line in the plurality of signal transmission lines in a display frame when a first driving mode is adopted, control each cascade group to work in sequence, control each shift register in the same cascade group to scan the coupled grid lines line by line, and scan the plurality of grid lines line by line; when the second driving mode is adopted, in one display frame, one of the plurality of cascade groups is used as a set cascade group, a control signal is loaded on the signal transmission line coupled with the set cascade group, each shift register in the set cascade group is controlled to scan the coupled grid lines line by line, and a cut-off signal is loaded on the signal transmission lines coupled with the other cascade groups except the set cascade group in the plurality of cascade groups.

It should be noted that the working principle and the specific implementation of the display device are the same as the principle and the implementation of the driving method of the display panel in the above embodiment, and therefore, the working method of the display device can be implemented by referring to the specific implementation of the driving method in the above embodiment, and is not described again here.

In specific implementation, in the embodiment of the present disclosure, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein nor should they be construed as limiting the present disclosure.

According to the driving method of the display panel and the display device provided by the embodiment of the disclosure, the scanning stage and the touch stage are set in one display frame, so that the display panel can realize the function of performing display and touch in a time-sharing manner. In addition, because a new cascade group is controlled to scan the coupled grid lines in the next scanning stage after the touch stage is finished, the problem that the display horizontal stripes occur due to the fact that scanning is started after the shift register is paused in the middle during line-by-line scanning in the prior art can be avoided. And, this disclosed embodiment is through reserving scan time with other integrated functions, insert between the display scanning stage, avoid the electric leakage problem of long-time display level.

As will be appreciated by one skilled in the art, embodiments of the present disclosure may be provided as a method, system, or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and so forth) having computer-usable program code embodied therein.

The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the disclosure.

It will be apparent to those skilled in the art that various changes and modifications may be made to the disclosed embodiments without departing from the spirit and scope of the disclosed embodiments. Thus, if such modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to encompass such modifications and variations.

Claims

1. A driving method of a display panel, the display panel comprising: the pixel structure comprises a plurality of sub-pixels with different colors, a plurality of grid lines, a grid driving circuit respectively coupled with the grid lines and a plurality of signal transmission lines coupled with the grid driving circuit; the color of the same row of sub-pixels is the same, one row of sub-pixels is coupled with one grid line, the grid driving circuit comprises a plurality of shift registers, the driving output end of one shift register is coupled with one grid line, the plurality of shift registers are divided into a plurality of cascade groups, the color of the grid line coupled with the shift register in the same cascade group, which corresponds to the sub-pixel, is the same, the shift registers in the same cascade group are arranged in a cascade mode, and different cascade groups are coupled with different signal transmission lines;

the driving method comprises the following steps:

when a first driving mode is adopted, different control signals are loaded to each signal transmission line in the plurality of signal transmission lines in one display frame, each cascade group is controlled to work sequentially, each shift register in the same cascade group scans coupled grid lines line by line, and the plurality of grid lines are scanned line by line;

2. The driving method of a display panel according to claim 1, wherein the plurality of signal transmission lines include a plurality of clock signal lines; the plurality of clock signal lines are divided into a plurality of clock line groups, and each clock line group comprises at least two clock signal lines; one of the cascaded sets is coupled to a clock signal line in one of the clock line sets;

the control signal comprises a clock signal.

3. The method of driving a display panel according to claim 2, wherein the display panel further comprises: a first frame start signal line;

4. The driving method of the display panel according to claim 2, wherein the plurality of signal transmission lines further include a plurality of second frame start signal lines;

the control signal comprises a frame start signal.

5. The method according to claim 4, wherein in the second driving mode, in one display frame, the second frame start signal line coupled to the set cascade group is loaded with a frame start signal, the second frame start signal lines coupled to the remaining cascade groups are loaded with a cut-off signal, each clock signal line is loaded with a clock signal, and each shift register in the set cascade group is controlled to scan the coupled gate lines line by line.

6. The method for driving a display panel according to claim 4, wherein when the second driving mode is adopted, in one display frame, a frame start signal is applied to the second frame start signal line to which the set cascade group is coupled, and an off signal is applied to the second frame start signal lines to which the remaining cascade groups are coupled, a clock signal is applied to the clock signal lines to which the set cascade group is coupled, each shift register in the set cascade group is controlled to scan the coupled gate lines line by line, and an off signal is applied to the clock signal lines to which the remaining cascade groups other than the set cascade group are coupled among the plurality of cascade groups.

7. The method according to claim 4, wherein when the second driving mode is used, in one display frame, a frame start signal is applied to each of the second frame start signal lines, a clock signal is applied to the clock signal line coupled to the set cascade group, each shift register in the set cascade group is controlled to scan the coupled gate lines line by line, and an off signal is applied to the clock signal lines coupled to the rest of the cascade groups except the set cascade group.

8. The method according to any one of claims 1 to 7, wherein the plurality of different color sub-pixels include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel, and the first color sub-pixel row, the second color sub-pixel row, and the third color sub-pixel row are sequentially and repeatedly arranged in a column direction;

9. The method for driving a display panel according to claim 8, wherein in the second driving mode, in each of a plurality of consecutive display frames, the set cascade group is a cascade group corresponding to the same color sub-pixel;

10. The method of driving a display panel according to any one of claims 1 to 7, wherein the display panel further includes a plurality of data lines; wherein a column of sub-pixels is coupled to one of the data lines;

the driving method further includes:

11. The method according to claim 10, wherein the display panel further comprises source driver circuits respectively coupled to the plurality of data lines;

12. The driving method of a display panel according to claim 10, wherein the display panel further comprises a plurality of detection units, a detection input signal line, and a detection control signal line; wherein a control terminal of the detection unit is coupled to the detection control signal line, an input terminal of the detection unit is coupled to the detection input signal line, and an output terminal of one of the detection units is coupled to one of the data lines;

the driving method further includes:

13. A display device, comprising:

a display panel, comprising: the pixel structure comprises a plurality of sub-pixels with different colors, a plurality of grid lines, a grid driving circuit respectively coupled with the grid lines and a plurality of signal transmission lines coupled with the grid driving circuit; the color of the same row of sub-pixels is the same, one row of sub-pixels is coupled with one grid line, the grid driving circuit comprises a plurality of shift registers, the driving output end of one shift register is coupled with one grid line, the plurality of shift registers are divided into a plurality of cascade groups, the color of the grid line coupled with the shift register in the same cascade group, which corresponds to the sub-pixel, is the same, the shift registers in the same cascade group are arranged in a cascade mode, and different cascade groups are coupled with different signal transmission lines;