CN109166548B - Liquid crystal display with wide and narrow viewing angle switching - Google Patents
Liquid crystal display with wide and narrow viewing angle switching Download PDFInfo
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 38
- 101000805729 Homo sapiens V-type proton ATPase 116 kDa subunit a 1 Proteins 0.000 claims description 7
- 101000854879 Homo sapiens V-type proton ATPase 116 kDa subunit a 2 Proteins 0.000 claims description 7
- 101000854873 Homo sapiens V-type proton ATPase 116 kDa subunit a 4 Proteins 0.000 claims description 7
- 102100020737 V-type proton ATPase 116 kDa subunit a 4 Human genes 0.000 claims description 7
- 239000003990 capacitor Substances 0.000 claims description 3
- 101100113692 Caenorhabditis elegans clk-2 gene Proteins 0.000 claims description 2
- 230000000007 visual effect Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 22
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 18
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 14
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 13
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 13
- 102100040856 Dual specificity protein kinase CLK3 Human genes 0.000 description 12
- 101000749304 Homo sapiens Dual specificity protein kinase CLK3 Proteins 0.000 description 12
- 102100040858 Dual specificity protein kinase CLK4 Human genes 0.000 description 8
- 101000749298 Homo sapiens Dual specificity protein kinase CLK4 Proteins 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 4
- 230000004075 alteration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 244000144985 peep Species 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
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Abstract
The invention provides a liquid crystal display with wide and narrow visual angles switched, which comprises a time schedule controller, a grid driver and a source driver, wherein the time schedule controller is used for controlling the time schedule controller to be switched; the time schedule controller provides a first group of clock signals and a second group of clock signals; the gate driver provides gate signals for the gate lines in the odd-numbered rows according to the first group of clock signals and provides gate signals for the gate lines in the even-numbered rows according to the second group of clock signals; when the source driver is in the narrow viewing angle display mode, the source driver provides corresponding data signals to enable every four adjacent odd-even columns of pixel units corresponding to every two rows of gate lines to display an image data point with the second resolution, and the pixel units in the odd-numbered columns are driven by the first group of gamma voltages, and the pixel units in the even-numbered columns are driven by the second group of gamma voltages. The liquid crystal display with the wide and narrow viewing angles, disclosed by the invention, can be switched to a full high definition FHD (head-up display) resolution picture when being switched from a wide viewing angle display mode to a narrow viewing angle display mode, so that the requirement of a user on high display quality can be met.
Description
Technical Field
The invention relates to the field of liquid crystal display, in particular to a liquid crystal display with wide and narrow visual angles switched.
Background
Liquid Crystal Displays (LCDs) have many advantages such as being light and thin, saving energy, and having no radiation, and thus have gradually replaced conventional Cathode Ray Tube (CRT) displays. Liquid crystal displays are widely used in high definition digital televisions, desktop computers, Personal Digital Assistants (PDAs), notebook computers, mobile phones, digital cameras, and other electronic devices.
At present, in order to meet the requirements of people on the liquid crystal display in corresponding occasions, the liquid crystal display comprises different viewing angle display modes, namely a wide viewing angle display mode and a narrow viewing angle display mode, and under the occasion that peep prevention is needed, the liquid crystal display needs to switch the wide viewing angle display mode in the viewing angle display modes to the narrow viewing angle display mode.
However, the conventional lcd cannot change the resolution of the image while switching the viewing angle display mode. On the other hand, if the lcd is driven at 120Hz in the narrow viewing angle display mode, and the lcd cannot drive an Ultra High-Definition (UHD) picture, for example, an UHD picture, at a refresh rate of 120Hz, it is impossible to simultaneously switch to the UHD picture when switching from the wide viewing angle display mode to the narrow viewing angle display mode. In order to meet the requirement of high display quality of users, a technical solution for changing the resolution of the image while switching to the narrow viewing angle display mode of the liquid crystal display is required.
Disclosure of Invention
In view of the above, the present invention is directed to a liquid crystal display with wide and narrow viewing angles, which can solve the problem of switching to full High definition (fhd) screen when switching from wide viewing angle display mode to narrow viewing angle display mode.
The invention provides a liquid crystal display with wide and narrow visual angle switching, which comprises a time schedule controller, a control module, a switching output module and the liquid crystal display with wide and narrow visual angle switching. The timing controller provides a first group of clock signals and a second group of clock signals, the first group of clock signals and the second group of clock signals both comprise n clock signals which are evenly spaced by a phase difference in sequence, the phase difference of corresponding clock signals of the first group of clock signals and the second group of clock signals is 1/2 phase differences in a wide viewing angle display mode, and the phase difference of corresponding clock signals of the first group of clock signals and the second group of clock signals is the same in a narrow viewing angle display mode, wherein n is an even number which is greater than 1, one phase difference is T/n, and T is the period of the clock signals; the gate driver provides gate signals to the gate lines of the odd rows according to the first group of clock signals to open the pixel units of the odd rows on the display panel, and provides gate signals to the gate lines of the even rows according to the second group of clock signals to open the pixel units of the even rows; the source electrode driver provides corresponding data signals for the data lines connected with each pixel unit so as to charge the opened pixel units; the source driver provides corresponding data signals in the wide viewing angle display mode to enable each pixel unit to display an image data point with a first resolution, the source driver provides corresponding data signals in the narrow viewing angle display mode to enable each pixel unit of every four adjacent odd-even columns corresponding to every two rows of gate lines to display an image data point with a second resolution, the pixel units of odd columns are driven by a first group of gamma voltages, and the pixel units of even columns are driven by a second group of gamma voltages.
Preferably, the source driver, in the narrow viewing angle display mode, makes every four adjacent odd-even columns of pixel units corresponding to every two rows of gate lines receive data signals corresponding to odd-numbered rows of video signals in an odd-numbered frame and receive data signals corresponding to even-numbered rows of video signals in an even-numbered frame.
Preferably, the gate driver includes a plurality of gate driving units, the gate driving units of odd rows receive the first set of clock signals, and the gate driving units of even rows receive the second set of clock signals.
Preferably, n is 4.
Preferably, the 4 clock signals of the first set of clock signals are a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, respectively, the first clock signal being one phase difference earlier than the second clock signal, the second clock signal being one phase difference earlier than the third clock signal, the third clock signal being one phase difference earlier than the fourth clock signal; the 4 clock signals of the second set of clock signals are a fifth clock signal, a sixth clock signal, a seventh clock signal, and an eighth clock signal, respectively, the fifth clock signal being one phase difference earlier than the sixth clock signal, the sixth clock signal being one phase difference earlier than the seventh clock signal, and the seventh clock signal being one phase difference earlier than the eighth clock signal.
Preferably, the duty cycles of the clock signals of the first set of clock signals and the second set of clock signals are both 50%.
Preferably, the timing controller outputs the first trigger signal to the gate driving units of the first 2 odd-numbered rows and outputs the second trigger signal to the gate driving units of the first 2 even-numbered rows.
Preferably, the first trigger signal is earlier than the first clock signal by a phase difference, and the second trigger signal is earlier than the fifth clock signal by a phase difference.
Preferably, one of the gate driving units of the gate driver includes first to sixteenth switching elements, wherein the first switching element includes a first path terminal, a second path terminal and a first control terminal, the first path terminal receives the first pulse signal, and the first control terminal receives the second pulse signal; the second switch element comprises a third path end, a fourth path end and a second control end, the third path end receives the first clock signal, the second control end is connected with the second path end of the first switch element, the fourth path end is connected with the second control end through a first capacitor, and the fourth path end outputs the grid signal; the third switching element comprises a fifth path end, a sixth path end and a third control end, the fifth path end is connected with the second path end of the first switching element, the third control end receives a third pulse signal, and the sixth path end receives the second clock signal; the fourth switching element comprises a seventh path end, an eighth path end and a fourth control end, the seventh path end receives the first clock signal, the fourth control end is connected with the second path end of the first switching element, and the eighth path end outputs the current-stage transmission signal; the fifth switch element comprises a ninth path end, a tenth path end and a fifth control end, and the ninth path end and the fifth control end receive the first timing signal; the sixth switching element comprises an eleventh path end, a tenth path end and a sixth control end, the eleventh path end receives the reference low voltage, the sixth control end is connected with the second path end of the first switching element, and the tenth path end is connected with the tenth path end of the fifth switching element; the seventh switching element comprises a tenth path end, a tenth path end and a seventh control end, wherein the seventh control end receives the first timing signal, and the thirteenth path end receives the reference low voltage;
the eighth switching element comprises a fifteenth path end, a sixteenth path end and an eighth control end, the fifteenth path end is connected with the second path end of the first switching element, the sixteenth path end receives the reference low voltage, and the eighth control end is connected with the tenth path end of the fifth switching element; the ninth switch element comprises a seventeenth path end, an eighteenth path end and a ninth control end, the seventeenth path end is connected with the fourth path end of the second switch element, the ninth control end is connected with the tenth path end of the fifth switch element, and the eighteenth path end receives the reference low voltage; the tenth switching element comprises a nineteenth path end, a twentieth path end and a tenth control end, the nineteenth path end is connected with the eighth path end of the fourth switching element, the tenth control end is connected with the tenth path end of the fifth switching element, and the twentieth path end receives and receives the reference low voltage; the eleventh switch element comprises a twenty-first path end, a twenty-second path end and an eleventh control end, the twenty-first path end is connected with the fourteenth path end of the seventh switch element, and the eleventh control end and the twenty-second path end receive a second timing signal; the twelfth switching element comprises a twentieth pass end, a twentieth pass end and a twelfth control end, the twentieth pass end receives the reference low voltage, the twelfth control end is connected with the second pass end of the first switching element, and the twentieth pass end is connected with the twenty-first pass end of the eleventh switching element; the thirteenth switching element comprises a twenty-fifth path end, a twenty-sixth path end and a thirteenth control end, wherein the twenty-fifth path end is connected with the tenth path end of the fifth switching element, the twenty-sixth path end receives the reference low voltage, and the thirteenth control end receives the second timing signal; the fourteenth switching element comprises a twenty-seventh path end, a twenty-eighth path end and a fourteenth control end, wherein the twenty-seventh path end receives the reference low voltage, the twenty-eighth path end is connected with the second path end of the first switching element, and the fourteenth control end is connected with the twenty-first path end of the eleventh switching element; the fifteenth switching element comprises a twenty-ninth path end, a thirtieth path end and a fifteenth control end, wherein the twenty-ninth path end receives the reference low voltage, the thirtieth path end is connected with the fourth path end of the second switching element, and the fifteenth control end is connected with the twenty-first path end of the eleventh switching element; the sixteenth switching element comprises a thirty-first path end, a thirty-second path end and a sixteenth control end, wherein the thirty-first path end receives the reference low voltage, the thirty-second path end is connected with the eighth path end of the fourth switching element, and the sixteenth control end is connected with the twenty-first path end of the eleventh switching element;
the first pulse signal is a fourth-stage gate signal output by the gate driving unit with the difference of four stages upwards, the second pulse signal is a fourth-stage transmission signal output by the gate driving unit with the difference of four stages upwards, and the third pulse signal is a fourth-stage gate signal output by the gate driving unit with the difference of four stages downwards except the first gate driving unit with the inverse number, the second gate driving unit with the inverse number and the third gate driving unit with the inverse number.
Preferably, the liquid crystal display includes another gate driver having the same structure and connection as the gate driver, and the another gate driver is disposed at both sides of the display panel opposite to the gate driver. The liquid crystal display with the wide and narrow viewing angles, disclosed by the invention, can be switched to a full high definition FHD (head-up display) resolution picture when being switched from a wide viewing angle display mode to a narrow viewing angle display mode, so that the requirement of a user on high display quality can be met.
In order to make the aforementioned and other objects, features and advantages of the invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a circuit diagram of a liquid crystal display according to a first embodiment.
Fig. 2 is a port schematic diagram of a gate driving unit according to a second embodiment.
Fig. 3 is a schematic structural diagram of a first eight-stage gate driving unit according to a second embodiment.
Fig. 4 is a timing diagram illustrating input signals of the first eight stages of gate driving units in the wide viewing angle display mode according to the second embodiment.
Fig. 5 is a timing diagram illustrating output signals of the first eight stages of gate driving units in the wide viewing angle display mode according to the second embodiment.
Fig. 6 is a diagram illustrating a resolution display in a wide viewing angle display mode according to a second embodiment.
Fig. 7 is a timing diagram illustrating input signals of the first eight stages of gate driving units in the narrow viewing angle display mode according to the second embodiment.
Fig. 8 is a timing diagram illustrating output signals of the first eight stages of gate driving units in the narrow viewing angle display mode according to the second embodiment.
Fig. 9 is a diagram illustrating resolution display in the narrow viewing angle display mode odd numbered frame according to the second embodiment.
Fig. 10 is a diagram illustrating a resolution display in an even frame of the narrow viewing angle display mode according to the second embodiment.
Fig. 11 is a schematic structural diagram of a gate driving unit according to a third embodiment.
Detailed Description
To further illustrate the technical means and effects of the present invention for achieving the intended purpose, the following detailed description is given to specific embodiments, methods, steps, structures, features and effects of the liquid crystal display with wide and narrow viewing angle switching according to the present invention with reference to the accompanying drawings and preferred embodiments.
The foregoing and other aspects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings. While the invention has been described in connection with specific embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention.
First embodiment
Referring to fig. 1, fig. 1 is a circuit connection diagram of a liquid crystal display according to a first embodiment. As shown in fig. 1, the wide and narrow viewing angle switching liquid crystal display of the present embodiment includes a timing controller 100, a gate driver 200, and a source driver 300. The timing controller 100 provides a first set of clock signals and a second set of clock signals, each of which includes n clock signals evenly spaced by a phase difference in sequence, and the phase difference between the corresponding clock signals of the first set of clock signals and the second set of clock signals is 1/2 phase differences in the wide viewing angle display mode and is the same in the narrow viewing angle display mode, where n is an even number greater than 1, one phase difference is T/n, and T is a period of the clock signals. The gate driver 200 provides gate signals to the gate lines of the odd-numbered rows according to the first set of clock signals to turn on the pixel units 401 of the odd-numbered rows on the display panel 400, and provides gate signals to the gate lines of the even-numbered rows according to the second set of clock signals to turn on the pixel units 401 of the even-numbered rows. The source driver 300 provides a corresponding data signal to the data line connected to each pixel unit 401 to charge the turned-on pixel unit 401; the source driver 300 provides corresponding data signals in the wide viewing angle display mode to enable each pixel unit 401 to display a video data point 410 with a first resolution, the source driver 300 provides corresponding data signals in the narrow viewing angle display mode to enable each pixel unit 401 of every four adjacent odd-even columns corresponding to every two rows of gate lines to display a video data point 420 with a second resolution, and the pixel units 401 of odd columns are driven by a first set of gamma voltages, and the pixel units 401 of even columns are driven by a second set of gamma voltages.
In one embodiment, the source driver 300 enables every four adjacent odd-even columns of pixel units 401 corresponding to every two rows of gate lines to receive data signals corresponding to odd-numbered rows of video signals during odd-numbered frames and receive data signals corresponding to even-numbered rows of video signals during even-numbered frames in the narrow viewing angle display mode.
In an embodiment, the gate driver 200 may include a plurality of gate driving units, the gate driving units of the odd rows receiving the first set of clock signals, and the gate driving units of the even rows receiving the second set of clock signals. The gate driver 200 may implement two ways of turning on the pixel unit 401 of the display panel 400 of two modes of the wide viewing angle display mode and the narrow viewing angle display mode through the gate driving unit.
In one embodiment, the liquid crystal display includes another gate driver 200 having the same structure and connection as the gate driver 200, and the another gate driver 200 is disposed at both sides of the display panel 400 opposite to the gate driver 200.
Specifically, in the wide view display mode, the timing controller 100 outputs a first group of clock signals, a second group of clock signals, and the like, where the first group of clock signals and the second group of clock signals each include n clock signals uniformly spaced by one phase difference in sequence, and the phase intervals of the corresponding clock signals of the first group of clock signals and the second group of clock signals are 1/2 phase differences, so that all clock signals of the first group of clock signals and the second group of clock signals are 2n clock signals uniformly spaced by 1/2 phase differences in sequence. The duty cycles of the clock signals of the first and second sets of clock signals may each be 50%. Furthermore, the gate driver 200 provides the gate signals to the gate lines of the odd-numbered rows according to the first set of clock signals to turn on the pixel units 401 of the odd-numbered rows on the display panel 400, and provides the gate signals to the gate lines of the even-numbered rows according to the second set of clock signals to turn on the pixel units 401 of the even-numbered rows. The gate driver 200 may be enabled to sequentially supply the gate signals to the gate lines of each row from top to bottom under the common driving of the first set of clock signals and the second set of clock signals outputted from the timing controller 100, and correspondingly sequentially turn on the pixel units 401 of each row from top to bottom. At this time, the source driver 300 provides the corresponding data signal to make each pixel unit 401 display an image data point 410 of the first resolution, that is, as shown in fig. 1, each pixel unit 401 may include a plurality of sub-pixels, for example, three sub-pixels, which may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively, and receives the corresponding data signals provided by the source driver 300 through corresponding three data lines (S1, S2 …), for example, the first pixel unit 401 of the first row may be the first three sub-pixels of the first row, and receives the data signals S1 provided by the source driver 300 through three data lines, so that each pixel unit 401 displays an image data point 410 of the first resolution.
In the narrow viewing angle display mode, the timing controller 100 outputs a first group of clock signals and a second group of clock signals, where the first group of clock signals and the second group of clock signals each include n clock signals uniformly spaced by a phase difference in sequence, and the phases of the corresponding clock signals of the first group of clock signals and the second group of clock signals are the same, so that all the clock signals of the first group of clock signals and the second group of clock signals are the same clock signals corresponding to each other one by one, that is, the first group of clock signals and the second group of clock signals are the same in timing sequence. The duty cycles of the clock signals of the first and second sets of clock signals may each be 50%. Furthermore, the gate driver 200 provides the gate signals to the gate lines of the odd-numbered rows according to the first set of clock signals to turn on the pixel units 401 of the odd-numbered rows on the display panel 400, and provides the gate signals to the gate lines of the even-numbered rows according to the second set of clock signals to turn on the pixel units 401 of the even-numbered rows. Under the common driving of the first and second sets of clock signals output from the timing controller 100, the driving gate driver 200 may be caused to simultaneously supply gate signals to the gate lines of odd and even two rows from top to bottom at a time, for example, the gate driver 200 is driven to simultaneously supply gate signals to the gate lines of the first and second rows, to simultaneously supply gate signals to the gate lines of the third and fourth rows, then, the gate lines of the fifth and sixth rows are simultaneously supplied with gate signals, and the gate lines of the remaining rows are sequentially supplied with gate signals downward, and correspondingly, the pixel units 401 of odd and even two rows are sequentially and simultaneously turned on from top to bottom, that is, the pixel units 401 of the first row and the second row are turned on at the same time, and then the pixel units 401 of the third row and the fourth row are turned on at the same time, then, the pixel cells 401 of the fifth and sixth rows are simultaneously turned on, and the pixel cells 401 of the remaining rows are sequentially turned down. At this time, the source driver 300 provides corresponding data signals to enable every four adjacent odd-even columns of pixel units 401 corresponding to every two rows of gate lines to display an image data point 420 of the second resolution, that is, as shown in fig. 1, for example, after the pixel units 401 of the first and second rows are simultaneously turned on by the gate driver 200, the pixel units 401 of the first and second columns in the first and second rows display an image data point 420 of the second resolution, the pixel units 401 of the third and fourth columns in the first and second rows display another image data point of the second resolution, and the adjacent four pixel units 401 of the odd-even columns in each two rows sequentially display an image data point 420 of the second resolution, so as to achieve the display effect of switching the resolution. And the source driver 300 drives the pixel units 401 of the odd columns by the first group of gamma voltages and drives the pixel units 401 of the even columns by the second group of gamma voltages to realize the display effect of the narrow viewing angle. Further, the source driver 300 may be configured such that every four adjacent odd-even column pixel cells 401 corresponding to every two rows of gate lines receive data signals corresponding to odd-numbered rows of video in an odd-numbered frame and receive data signals corresponding to even-numbered rows of video in an even-numbered frame. Therefore, the odd and even frames alternately display images, and the problems of image flicker and the like caused by gray scale inversion are solved.
In the wide viewing angle display mode, according to the gate signal output by the gate driver 200, the time for charging the pixels to display images is 1/2 phase differences, i.e., T/(2n), and T is the period of the clock signal. In the narrow viewing angle display mode, according to the gate signal output by the gate driver 200, the time for charging the pixel to the voltage at which the pixel displays the image is a phase difference, i.e., T/n, and T is the period of the clock signal.
In an embodiment, the first resolution may be an ultra high definition UHD, and the second resolution may be a full high definition FHD, that is, when switching from the wide view display mode to the narrow view display mode, the ultra high definition UHD picture may be switched to a full high definition FHD resolution picture.
The liquid crystal display with the wide and narrow viewing angles switching can be switched to a full high definition FHD resolution picture when the wide viewing angle display mode is switched to the narrow viewing angle display mode, so that the requirement of high display quality of a user can be met.
Second embodiment
The second embodiment is substantially the same as the first embodiment, and the first group of clock signals and the second group of clock signals of the timing controller 100 of the liquid crystal display of the second embodiment each include four clock signals evenly spaced by one phase difference in sequence, wherein one phase difference is T/4, and T is the period of the clock signals; the gate driver 200 includes a plurality of gate driving units, the gate driving units of the odd-numbered rows receiving respective signals of the first set of clock signals, and the gate driving units of the even-numbered rows receiving respective signals of the second set of clock signals.
In one embodiment, the 4 clock signals of the first group of clock signals are the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3 and the fourth clock signal CLK4, respectively, the first clock signal CLK1 is one phase difference earlier than the second clock signal CLK2, the second clock signal CLK2 is one phase difference earlier than the third clock signal CLK3, and the third clock signal CLK3 is one phase difference earlier than the fourth clock signal CLK 4; the 4 clock signals of the second group of clock signals are the fifth clock signal CLK5, the sixth clock signal CLK6, the seventh clock signal CLK7 and the eighth clock signal CLK8, respectively, the fifth clock signal CLK5 is one phase difference earlier than the sixth clock signal CLK6, the sixth clock signal CLK6 is one phase difference earlier than the seventh clock signal CLK7, and the seventh clock signal CLK7 is one phase difference earlier than the eighth clock signal CLK 8.
In an embodiment, the duty cycles of the clock signals of the first and second sets of clock signals may each be 50%.
In one embodiment, the timing controller 100 outputs the first trigger signal STV1 to the gate driving units of the first 2 odd-numbered rows, and outputs the second trigger signal STV2 to the gate driving units of the first 2 even-numbered rows.
In one embodiment, the first toggle signal STV1 is one phase difference earlier than the first clock signal CLK1 and the second toggle signal STV2 is one phase difference earlier than the fifth clock signal CLK 5.
Specifically, referring to fig. 2 and 3, fig. 2 is a port schematic diagram of a gate driving unit of a second embodiment. Fig. 3 is a schematic structural diagram of a first eight-stage gate driving unit according to a second embodiment. The timing control signals output the first and second sets of clock signals, and may also output other signals, such as the reference low voltage VGL, the first trigger signal STV1, the second trigger signal STV2, the first timing signal V1, and the second timing signal V2, respectively. The gate driver 200 includes a plurality of gate driving units each inputting a corresponding signal of the timing controller 100 and outputting a gate signal, etc., for example, a gate driving unit shown in fig. 2 inputting a first clock signal CLK1, a second clock signal CLK2, a first timing signal V1, a second timing signal V2, a fourth-order gate signal Gn-4, a fourth-order gate signal Gn +4, a fourth-order transfer signal Zn-4, and a reference low voltage VGL, the gate driving unit outputting a present-order gate signal Gn and a present-order transfer signal Zn. The odd-numbered gate driving units in the gate driver 200 shown in fig. 3 provide gate signals to the gate lines of the odd-numbered rows according to the clock signals in the corresponding first group of clock signals to turn on the pixel units 401 of the odd-numbered rows on the display panel 400, and provide gate signals to the gate lines of the even-numbered rows according to the clock signals in the corresponding second group of clock signals to turn on the pixel units 401 of the even-numbered rows on the display panel 400, and the odd-numbered gate driving units (stage1, stage3, stage5, and stage7) may be driven in cascade with each other, and the even-numbered gate driving units (stage2, stage4, stage6, and stage8) may be driven in cascade with each other, for example, the first-level gate driving unit stage1 may output the present-level gate signal G1 and the present-level transmission signal Z1 to the fifth-level gate driving unit stage5, and may also input the gate signal G5 output by the fifth-level gate driving unit stage 5; the second stage gate driving unit stage2 may output the present stage gate signal G2 and the present stage transfer signal Z2 to the sixth stage gate driving unit stage6, or input the gate signal G6 output by the sixth stage gate driving unit stage 6. The timing controller 100 outputs the first trigger signal STV1 to the gate driving units of the first 2 odd-numbered rows (i.e., the first stage gate driving unit stage1 and the third stage gate driving unit stage3), and outputs the second trigger signal STV2 to the gate driving units of the first 2 even-numbered rows (i.e., the second stage gate driving unit stage2 and the fourth stage gate driving unit stage4), the first trigger signal STV1 is earlier by one phase difference than the first clock signal CLK1, and the second trigger signal STV2 is earlier by one phase difference than the fifth clock signal CLK5 (see fig. 2).
Referring to fig. 4 and 5, fig. 4 is a timing diagram illustrating input signals of the first eight stages of gate driving units in the wide viewing angle display mode according to the second embodiment. Fig. 5 is a timing diagram illustrating output signals of the first eight stages of gate driving units in the wide viewing angle display mode according to the second embodiment. In the wide viewing angle display mode, the timing controller 100 outputs a first set of clock signals, a second set of clock signals, and the like, as shown in fig. 4, each of the first set of clock signals and the second set of clock signals includes 4 clock signals uniformly spaced by a phase difference in sequence, one phase difference is T/4, and T is a period of the clock signals. For example, the 4 clock signals of the first group of clock signals shown in fig. 4 are the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3 and the fourth clock signal CLK4, respectively, the first clock signal CLK1 is earlier than the second clock signal CLK2 by a phase difference, the second clock signal CLK2 is earlier than the third clock signal CLK3 by a phase difference, the third clock signal CLK3 is earlier than the fourth clock signal CLK4 by a phase difference, the 4 clock signals of the second group of clock signals are the fifth clock signal CLK5, the sixth clock signal CLK6, the seventh clock signal CLK7 and the eighth clock signal CLK8, the fifth clock signal CLK5 is earlier than the sixth clock signal CLK6 by a phase difference, the sixth clock signal CLK6 is earlier than the seventh clock signal CLK7 by a phase difference, and the seventh clock signal CLK7 is earlier than the eighth clock signal CLK8 by a phase difference. And the phase interval 1/2 phase differences of the respective clock signals of the first set of clock signals and the second set of clock signals, for example, in fig. 4 the first clock signal CLK1 corresponds to the fifth clock signal CLK5 and the first clock signal CLK1 is 1/2 phase differences earlier than the fifth clock signal CLK5, the second clock signal CLK2 corresponds to the sixth clock signal CLK6 and the second clock signal CLK2 is 1/2 phase differences earlier than the sixth clock signal CLK6, the third clock signal CLK3 corresponds to the seventh clock signal CLK7 and the third clock signal CLK3 is 1/2 phase differences earlier than the seventh clock signal CLK7, the fourth clock signal CLK4 corresponds to the eighth clock signal CLK8 and the fourth clock signal CLK4 is 1/2 phase differences earlier than the eighth clock signal CLK8, then all clock signals of the first set of clock signals and the second set of clock signals are 8 clock signals evenly spaced 1/2 phase differences in sequence. The duty cycles of the clock signals of the first and second sets of clock signals may each be 50%. Furthermore, the gate driver 200 provides the gate signals to the gate lines of the odd-numbered rows according to the first set of clock signals to turn on the pixel units 401 of the odd-numbered rows on the display panel 400, and provides the gate signals to the gate lines of the even-numbered rows according to the second set of clock signals to turn on the pixel units 401 of the even-numbered rows. Under the common driving of the first and second clock signals outputted from the timing controller 100, the gate driver 200 can sequentially supply gate signals to the gate lines of each row from top to bottom (refer to the gate driving signals shown in fig. 5, the gate signal outputted from the first stage gate driving unit is G1, the gate signal outputted from the second stage gate driving unit is G2 …, the gate signal outputted from the eighth stage gate driving unit is G8, and the gate signals are sequentially phase-spaced by T/8), and accordingly, the pixel units 401 of each row are sequentially turned on from top to bottom. At this time, the source driver 300 provides the corresponding data signal to make each pixel unit 401 display an image data point 410 with the first resolution. Fig. 6 is a schematic diagram of resolution display in a wide viewing angle display mode according to a second embodiment, as shown in fig. 6, each pixel unit 401 may include a plurality of sub-pixels, for example, three sub-pixels, which may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and receive corresponding data signals provided by the source driver 300 through corresponding three data lines, so that each pixel unit 401 displays an image data point 410 of a first resolution, and each row of pixel units 401 correspondingly displays data signals of an image of the current row, for example, four rows of pixel units 401 shown in fig. 6, and each row of pixel units 401 correspondingly displays data signals of an image of the current row.
Referring to fig. 7 and 8, fig. 7 is a timing diagram illustrating input signals of the first eight stages of gate driving units in the narrow viewing angle display mode according to the second embodiment. Fig. 8 is a timing diagram illustrating output signals of the first eight stages of gate driving units in the narrow viewing angle display mode according to the second embodiment. In the narrow viewing angle display mode, the timing controller 100 outputs a first set of clock signals, a second set of clock signals, and the like, as shown in fig. 7, each of the first set of clock signals and the second set of clock signals includes 4 clock signals uniformly spaced by a phase difference in sequence, one phase difference is T/4, and T is a period of the clock signals. For example, the 4 clock signals of the first group of clock signals shown in fig. 4 are the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3 and the fourth clock signal CLK4, respectively, the first clock signal CLK1 is earlier than the second clock signal CLK2 by a phase difference, the second clock signal CLK2 is earlier than the third clock signal CLK3 by a phase difference, the third clock signal CLK3 is earlier than the fourth clock signal CLK4 by a phase difference, the 4 clock signals of the second group of clock signals are the fifth clock signal CLK5, the sixth clock signal CLK6, the seventh clock signal CLK7 and the eighth clock signal CLK8, the fifth clock signal CLK5 is earlier than the sixth clock signal CLK6 by a phase difference, the sixth clock signal CLK6 is earlier than the seventh clock signal CLK7 by a phase difference, and the seventh clock signal CLK7 is earlier than the eighth clock signal CLK8 by a phase difference. And the phases of the respective clock signals of the first and second groups of clock signals are the same, all the clock signals of the first and second groups of clock signals are the same clock signals in one-to-one correspondence, i.e., the first and second groups of clock signals are the same in timing, e.g., the first clock signal CLK1 corresponds to and is the same in timing as the fifth clock signal CLK5, the second clock signal CLK2 corresponds to and is the same in timing as the sixth clock signal CLK6, the third clock signal CLK3 corresponds to and is the same in timing as the seventh clock signal CLK7, and the fourth clock signal CLK4 corresponds to and is the same in timing as the eighth clock signal CLK 8. The duty cycles of the clock signals of the first and second sets of clock signals may each be 50%. Furthermore, the gate driver 200 provides the gate signals to the gate lines of the odd-numbered rows according to the first set of clock signals to turn on the pixel units 401 of the odd-numbered rows on the display panel 400, and provides the gate signals to the gate lines of the even-numbered rows according to the second set of clock signals to turn on the pixel units 401 of the even-numbered rows. Under the common driving of the first and second clock signals outputted from the timing controller 100, the gate driver 200 may be driven to simultaneously supply gate signals to the gate lines of odd and even rows from top to bottom (refer to the gate driving signal shown in fig. 8, the gate signal outputted from the first stage gate driving unit is G1, the gate signal outputted from the second stage gate driving unit is G2 …, the gate signal outputted from the eighth stage gate driving unit is G8, the phase of the gate signals of each row is the same, G1 is the same as G3, G3 is the same as G5, and G5 is the same as G7, for example, the gate driver 200 is driven to simultaneously supply the gate signals to the gate lines of the first and second rows, simultaneously supply the gate signals to the gate lines of the third and fourth rows, simultaneously supply the gate signals to the gate lines of the fifth and sixth rows, and sequentially supply the gate signals to the gate lines of the remaining rows, the pixel units 401 in odd and even rows are also sequentially and simultaneously opened from top to bottom, that is, the pixel units 401 in the first and second rows are simultaneously opened, the pixel units 401 in the third and fourth rows are simultaneously opened, the pixel units 401 in the fifth and sixth rows are simultaneously opened, and the pixel units 401 in the remaining rows are sequentially opened downward. At this time, the source driver 300 provides the corresponding data signal to make every four adjacent odd-even columns of pixel units 401 corresponding to every two rows of gate lines display an image data point 420 of the second resolution. For example, after the pixel units 401 in the first and second rows are simultaneously turned on by the gate driver 200, the pixel units 401 in the first and second columns in the first and second rows display one image data point 420 of the second resolution, the pixel units 401 in the third and fourth columns in the first and second rows display another image data point 420 of the second resolution, and the adjacent four pixel units 401 in the odd and even columns in each row sequentially display one image data point 420 of the second resolution, so as to achieve the display effect of switching the resolutions. And the source driver 300 drives the pixel units 401 of the odd columns by the first group of gamma voltages and drives the pixel units 401 of the even columns by the second group of gamma voltages to realize the display effect of the narrow viewing angle. Further, the source driver 300 may be configured such that every four adjacent odd-even column pixel cells 401 corresponding to every two rows of gate lines receive data signals corresponding to odd-numbered rows of video in an odd-numbered frame and receive data signals corresponding to even-numbered rows of video in an even-numbered frame. Fig. 9 is a schematic diagram of resolution display in an odd frame of the narrow viewing angle display mode of the second embodiment, fig. 10 is a schematic diagram of resolution display in an even frame of the narrow viewing angle display mode of the second embodiment, and fig. 9 and fig. 10 can be compared with fig. 6, where fig. 9 schematically shows four rows of pixel units 401, every two odd and even rows of pixel units 401 correspondingly display data signals of an odd-numbered row of image, fig. 10 schematically shows four rows of pixel units 401, and every two odd and even rows of pixel units 401 correspondingly display data signals of an even-numbered row of image. Therefore, the odd and even frames alternately display images, and the problems of image flicker and the like caused by gray scale inversion are solved.
In the wide viewing angle display mode, according to the gate signal output by the gate driver 200, the time for charging the pixels to display images is 1/2 phase differences, i.e., T/8, and T is the period of the clock signal. In the narrow viewing angle display mode, according to the gate signal output by the gate driver 200, the time for charging the pixel to the voltage at which the pixel displays the image is T/4, which is a phase difference, and T is the period of the clock signal.
In an embodiment, the first resolution may be an ultra high definition UHD, and the second resolution may be a full high definition FHD, that is, when switching from the wide view display mode to the narrow view display mode, the ultra high definition UHD picture may be switched to a full high definition FHD resolution picture.
The liquid crystal display with the wide and narrow viewing angles switching can be switched to a full high definition FHD resolution picture when the wide viewing angle display mode is switched to the narrow viewing angle display mode, so that the requirement of high display quality of a user can be met.
Third embodiment
Fig. 11 is a schematic structural diagram of a gate driving unit according to a third embodiment. As shown in fig. 11, a gate driving unit of the gate driver 200 of the lcd of the present embodiment includes first to sixteenth switching elements T1 to T16.
The first switching element T1 includes a first path terminal, a second path terminal, and a first control terminal, where the first path terminal receives the first pulse signal and the first control terminal receives the second pulse signal; the second switching element T2 includes a third path terminal, a fourth path terminal and a second control terminal, the third path terminal receives the first clock signal CLK1, the second control terminal is connected to the second path terminal of the first switching element T1, the fourth path terminal is connected to the second control terminal through the first capacitor C1, and the fourth path terminal outputs the present-stage gate signal Gn; the third switching element T3 includes a fifth path terminal connected to the second path terminal of the first switching element T1, a sixth path terminal receiving the third pulse signal, and a third control terminal receiving the second clock signal CLK 2; the fourth switching element T4 includes a seventh path end, an eighth path end, and a fourth control end, the seventh path end receives the first clock signal CLK1, the fourth control end is connected to the second path end of the first switching element T1, and the eighth path end outputs the present-stage transmission signal Zn; the fifth switch element T5 includes a ninth path terminal, a tenth path terminal and a fifth control terminal, the ninth path terminal and the fifth control terminal receive the first timing signal V1; the sixth switching element T6 includes an eleventh path terminal, a tenth path terminal, and a sixth control terminal, the eleventh path terminal receives the reference low voltage VGL, the sixth control terminal is connected to the second path terminal of the first switching element T1, and the tenth path terminal is connected to the tenth path terminal of the fifth switching element T5; the seventh switching element T7 includes a tenth path terminal, a tenth path terminal and a seventh control terminal, the seventh control terminal receives the first timing signal V1, and the thirteenth path terminal receives the reference low voltage VGL.
The eighth switching element T8 includes a fifteenth path end, a sixteenth path end and an eighth control end, the fifteenth path end is connected to the second path end of the first switching element T1, the sixteenth path end receives the reference low voltage VGL, and the eighth control end is connected to the tenth path end of the fifth switching element T5; the ninth switching element T9 includes a seventeenth path terminal connected to the fourth path terminal of the second switching element T2, an eighteenth path terminal connected to the tenth path terminal of the fifth switching element T5, and a ninth control terminal receiving the reference low voltage VGL; the tenth switching element T10 includes a nineteenth path terminal, a twentieth path terminal, and a tenth control terminal, the nineteenth path terminal is connected to the eighth path terminal of the fourth switching element T4, the tenth control terminal is connected to the tenth path terminal of the fifth switching element T5, and the twentieth path terminal receives the reference low voltage VGL; the eleventh switching element T11 includes a twenty-first path end, a twenty-second path end, and an eleventh control end, the twenty-first path end is connected to the tenth path end of the seventh switching element T7, and the eleventh control end and the twenty-second path end receive the second timing signal V2; the twelfth switching element T12 includes a twentieth pass end, and a twelfth control end, the twentieth pass end receives the reference low voltage VGL, the twelfth control end is connected to the second pass end of the first switching element T1, and the twentieth pass end is connected to the twenty-first pass end of the eleventh switching element T11; the thirteenth switching element T13 includes a twenty-fifth path terminal, a twenty-sixth path terminal and a thirteenth control terminal, the twenty-fifth path terminal is connected to the tenth path terminal of the fifth switching element T5, the twenty-sixth path terminal receives the reference low voltage VGL, and the thirteenth control terminal receives the second timing signal V2; the fourteenth switching element T14 includes a twenty-seventh path end, a twenty-eighth path end, and a fourteenth control end, the twenty-seventh path end receives the reference low voltage VGL, the twenty-eighth path end is connected to the second path end of the first switching element T1, and the fourteenth control end is connected to the twenty-first path end of the eleventh switching element T11; the fifteenth switching element T15 includes a twenty-ninth path terminal receiving the reference low voltage VGL, a thirtieth path terminal connected to the fourth path terminal of the second switching element T2, and a fifteenth control terminal connected to the twenty-first path terminal of the eleventh switching element T11; the sixteenth switching element T16 includes a thirty-first path terminal, a thirty-second path terminal, and a sixteenth control terminal, the thirty-first path terminal receives the reference low voltage VGL, the thirty-second path terminal is connected to the eighth path terminal of the fourth switching element T4, and the sixteenth control terminal is connected to the twenty-first path terminal of the eleventh switching element T11.
The first pulse signal is a four-level upper grid signal Gn-4 output by the grid driving unit with the four levels of upward phase difference, the second pulse signal is a four-level upper transfer signal Zn-4 output by the grid driving unit with the four levels of upward phase difference, and the third pulse signal is a four-level lower grid signal Gn +4 output by the grid driving unit with the four levels of downward phase difference, except the first-to-last grid driving unit, the second-to-last grid driving unit and the third-to-last grid driving unit.
The first timing signal V1 and the second timing signal V2 are both low-frequency signals, and when the first timing signal V1 is high, the second timing signal V2 is low, and when the first timing signal V1 is low, the second timing signal V2 is high.
The gate driving unit of the liquid crystal display of this embodiment can output corresponding gate signals according to the first and second sets of clock signals corresponding to the timing controller 100, so as to drive the pixel unit 401 on the display panel 400 to be correspondingly turned on when the wide viewing angle display mode and the narrow viewing angle display mode are switched.
The liquid crystal display with the wide and narrow viewing angles switching can be switched to a full high definition FHD resolution picture when the wide viewing angle display mode is switched to the narrow viewing angle display mode, so that the requirement of high display quality of a user can be met.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A liquid crystal display for switching between wide and narrow viewing angles, comprising:
a timing controller (100), the timing controller (100) providing a first set of clock signals and a second set of clock signals, the first set of clock signals and the second set of clock signals each including n clock signals evenly spaced by a phase difference in sequence, the phase difference between corresponding clock signals of the first set of clock signals and the second set of clock signals being 1/2 phase differences in a wide viewing angle display mode, and the phase difference being the same in a narrow viewing angle display mode, wherein n is an even number greater than 1, one phase difference is T/n, and T is a period of a clock signal;
a gate driver (200), the gate driver (200) providing gate signals to the gate lines of the odd rows according to the first set of clock signals to turn on the pixel cells (401) of the odd rows on the display panel (400), and providing gate signals to the gate lines of the even rows according to the second set of clock signals to turn on the pixel cells (401) of the even rows;
a source driver (300), the source driver (300) providing a corresponding data signal to the data line connected to each pixel cell (401) to charge the turned-on pixel cell (401); the source driver (300) provides corresponding data signals in the wide viewing angle display mode to enable each pixel unit (401) to display a video data point (410) with a first resolution, the source driver (300) provides corresponding data signals in the narrow viewing angle display mode to enable each pixel unit (401) of every four adjacent odd-even columns corresponding to every two rows of gate lines to display a video data point (420) with a second resolution, the pixel units (401) of the odd columns are driven by a first set of gamma voltages, and the pixel units (401) of the even columns are driven by a second set of gamma voltages.
2. The liquid crystal display device according to claim 1, wherein the source driver (300) in the narrow viewing angle display mode enables every four adjacent odd-even columns of pixel cells (401) corresponding to every two rows of gate lines to receive data signals corresponding to odd-numbered rows of video signals in odd-numbered frames and data signals corresponding to even-numbered rows of video signals in even-numbered frames.
3. The wide and narrow viewing angle switched liquid crystal display of claim 1, wherein the gate driver (200) comprises a plurality of gate driving units, the odd numbered gate driving units receiving the first set of clock signals, and the even numbered gate driving units receiving the second set of clock signals.
4. The wide and narrow viewing angle switched liquid crystal display of claim 3, wherein n is 4.
5. The wide-narrow viewing angle switched liquid crystal display of claim 4, wherein 4 clock signals of the first set of clock signals are a first clock signal (CLK1), a second clock signal (CLK2), a third clock signal (CLK3) and a fourth clock signal (CLK4), respectively, the first clock signal (CLK1) being one phase difference earlier than the second clock signal (CLK2), the second clock signal (CLK2) being one phase difference earlier than the third clock signal (CLK3), the third clock signal (CLK3) being one phase difference earlier than the fourth clock signal (CLK 4);
the 4 clock signals of the second set of clock signals are a fifth clock signal (CLK5), a sixth clock signal (CLK6), a seventh clock signal (CLK7), and an eighth clock signal (CLK8), respectively, the fifth clock signal (CLK5) being one said phase difference earlier than the sixth clock signal (CLK6), the sixth clock signal (CLK6) being one said phase difference earlier than the seventh clock signal (CLK7), the seventh clock signal (CLK7) being one said phase difference earlier than the eighth clock signal (CLK 8).
6. The wide and narrow viewing angle switched liquid crystal display of claim 5, wherein the duty cycles of the clock signals of the first set of clock signals and the second set of clock signals are both 50%.
7. The wide and narrow viewing angle-switched liquid crystal display of claim 6, wherein the timing controller (100) outputs a first trigger signal (STV1) to the first 2 odd-numbered gate driving units and outputs a second trigger signal (STV2) to the first 2 even-numbered gate driving units.
8. The wide and narrow viewing angle switched liquid crystal display of claim 7, wherein the first toggle signal (STV1) is one phase difference earlier than the first clock signal (CLK1), and the second toggle signal (STV2) is one phase difference earlier than the fifth clock signal (CLK 5).
9. The wide and narrow viewing angle switching liquid crystal display as claimed in claim 8, wherein a gate driving unit of the gate driver (200) comprises:
a first switching element (T1) including a first path terminal receiving the first pulse signal, a second path terminal receiving the second pulse signal, and a first control terminal receiving the second pulse signal;
a second switching element (T2) including a third path terminal receiving the first clock signal (CLK1), a fourth path terminal connected to the second path terminal of the first switching element (T1) through a first capacitor (C1), and a second control terminal outputting a local gate signal (Gn);
a third switching element (T3) including a fifth path terminal connected to the second path terminal of the first switching element (T1), a sixth path terminal receiving a third pulse signal, and a third control terminal receiving the second clock signal (CLK 2);
a fourth switching element (T4) including a seventh path terminal receiving the first clock signal (CLK1), an eighth path terminal connected to the second path terminal of the first switching element (T1), and a fourth control terminal outputting the present-stage transfer signal (Zn);
a fifth switching element (T5) including a ninth path terminal, a tenth path terminal, and a fifth control terminal, the ninth path terminal and the fifth control terminal receiving a first timing signal (V1);
a sixth switching element (T6) including an eleventh path terminal receiving a reference low Voltage (VGL), a tenth path terminal connected to the second path terminal of the first switching element (T1), and a sixth control terminal connected to a tenth path terminal of the fifth switching element (T5);
a seventh switching element (T7) including a tenth path terminal, a tenth path terminal and a seventh control terminal, the seventh control terminal receiving the first timing signal (V1), the thirteenth path terminal receiving the reference low Voltage (VGL);
an eighth switching element (T8) including a fifteenth path terminal connected to the second path terminal of the first switching element (T1), a sixteenth path terminal receiving the reference low Voltage (VGL), and an eighth control terminal connected to the tenth path terminal of the fifth switching element (T5);
a ninth switching element (T9) including a seventeenth path terminal connected to the fourth path terminal of the second switching element (T2), an eighteenth path terminal connected to the tenth path terminal of the fifth switching element (T5), and a ninth control terminal receiving the reference low Voltage (VGL);
a tenth switching element (T10) including a nineteenth path terminal connected to the eighth path terminal of the fourth switching element (T4), a twentieth path terminal connected to the tenth path terminal of the fifth switching element (T5), and a tenth control terminal receiving the reference low Voltage (VGL);
an eleventh switching element (T11) including a twenty-first path terminal, a twenty-second path terminal, and an eleventh control terminal, the twenty-first path terminal being connected to the tenth path terminal of the seventh switching element (T7), the eleventh control terminal and the twenty-second path terminal receiving a second timing signal (V2);
a twelfth switching element (T12) including a twentieth pass terminal receiving the reference low Voltage (VGL), a twentieth pass terminal connected to the second pass terminal of the first switching element (T1), and a twelfth control terminal connected to the twenty-first pass terminal of the eleventh switching element (T11);
a thirteenth switching element (T13) including a twenty-fifth path terminal connected to the tenth path terminal of the fifth switching element (T5), a twenty-sixth path terminal receiving the reference low Voltage (VGL), and a thirteenth control terminal receiving the second timing signal (V2);
a fourteenth switching element (T14) including a twenty-seventh path terminal receiving the reference low Voltage (VGL), a twenty-eighth path terminal connected to the second path terminal of the first switching element (T1), and a fourteenth control terminal connected to the twenty-first path terminal of the eleventh switching element (T11);
a fifteenth switching element (T15) including a twenty-ninth path terminal receiving the reference low Voltage (VGL), a thirty-ninth path terminal connected to the fourth path terminal of the second switching element (T2), and a fifteenth control terminal connected to the twenty-first path terminal of the eleventh switching element (T11);
a sixteenth switching element (T16) including a thirty-first path terminal receiving the reference low Voltage (VGL), a thirty-second path terminal connected to the eighth path terminal of the fourth switching element (T4), and a sixteenth control terminal connected to the twenty-first path terminal of the eleventh switching element (T11);
the first pulse signal is a fourth-stage gate signal (Gn-4) output by a gate driving unit with a fourth stage difference upwards, the second pulse signal is a fourth-stage transfer signal (Zn-4) output by a gate driving unit with a fourth stage difference upwards, and the third pulse signal is a fourth-stage gate signal (Gn +4) output by a gate driving unit with a fourth stage difference downwards, except a first-stage gate driving unit, a second-stage gate driving unit and a third-stage gate driving unit with a last number, and the third pulse signal is a fourth-stage gate signal (Gn +4) output by a gate driving unit with a fourth stage difference downwards.
10. The wide and narrow viewing angle switching liquid crystal display of claim 1, wherein the liquid crystal display includes another gate driver having the same structure and connection as the gate driver (200), the another gate driver being disposed at both sides of the display panel (400) opposite to the gate driver (200).
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| CN113593463B (en) * | 2021-07-30 | 2024-05-31 | 福州京东方光电科技有限公司 | Display mode switching system and method and display device |
| CN114242016A (en) * | 2021-12-20 | 2022-03-25 | 惠科股份有限公司 | Scanning driving circuit, array substrate and display terminal |
| CN114333731B (en) * | 2021-12-31 | 2023-04-28 | 惠科股份有限公司 | Scanning driving circuit and array substrate |
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| KR101094304B1 (en) * | 2010-02-23 | 2011-12-19 | 삼성모바일디스플레이주식회사 | Display device and method for image processing thereof |
| CN103700358B (en) * | 2013-12-31 | 2016-06-15 | 合肥京东方光电科技有限公司 | A kind of GIP type liquid crystal indicator |
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| US11187928B2 (en) * | 2017-07-04 | 2021-11-30 | Infovision Optoelectronics (Kunshan) Co., Ltd. | Method for driving liquid crystal display device capable of switching between wide viewing angle and narrow viewing angle |
| CN108196380A (en) * | 2017-12-29 | 2018-06-22 | 昆山龙腾光电有限公司 | The liquid crystal display device and driving method that visual angle can be switched |
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