CN114333731B

CN114333731B - Scanning driving circuit and array substrate

Info

Publication number: CN114333731B
Application number: CN202111676601.0A
Authority: CN
Inventors: 金秉勋; 卢昭阳; 田尚益; 李荣荣
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2023-04-28
Anticipated expiration: 2041-12-31
Also published as: CN114333731A

Abstract

The embodiment of the application discloses a scanning driving circuit, which comprises n scanning driving units and two virtual scanning driving units, wherein the n scanning driving units and the two virtual scanning driving units are sequentially arranged and cascaded, each scanning driving unit is used for outputting scanning driving signals of two preset intervals, and each virtual scanning driving unit is used for outputting hierarchical signals of two preset intervals. The two virtual scanning driving units are respectively connected with the n-1 level scanning driving unit and the n level scanning driving unit, and respectively output two second level transmission signals to the n-1 level scanning driving unit and the n level scanning driving unit so as to drive the scanning driving units to output scanning driving signals. Only the virtual scanning driving units are arranged at the tail ends of the cascaded scanning driving units to control the level transmission output of the scanning driving signals, so that the number of the virtual scanning driving units and occupied space are effectively reduced. The embodiment of the application also discloses an array substrate comprising the scanning driving circuit.

Description

Scanning driving circuit and array substrate

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a scan driving circuit and an array substrate applied in a display panel.

Background

The liquid crystal display has been widely used in various fields due to its advantages such as thin body, power saving, no radiation, etc. Such as: liquid crystal televisions, mobile phones, electronic watches, digital cameras, computer screens, and the like.

The GDL circuit (Gate Driver less technology) is to manufacture a driving circuit of a horizontal scanning line of an original array process of a liquid crystal display panel on a substrate around a display area, so that the driving circuit can replace an external IC (Integrated Circuit, integrated circuit board) to complete driving of the horizontal scanning line. The GDL technology reduces the welding process of the external IC, improves the productivity and reduces the product cost, and the liquid crystal display panel is developed towards the main stream appearance direction of a narrow frame or a frame-free frame.

At present, GDL circuits are respectively disposed on opposite sides of the display panel, and the GDL circuits on opposite sides are used for outputting corresponding scan driving signals in a matching manner. The GDL circuits on each side are connected in a cascade connection. In order to characterize the cascade of GDL circuits in the end-to-end two positions in the GDL circuit, a virtual GDL circuit for cascade driving only, which does not need to output a scan driving signal, needs to be additionally provided in the end-to-end position. However, obviously, the mode of arranging the virtual GDL circuits at the head and the tail easily causes the wiring space of the display panel to be limited, and simultaneously, the design space of the narrow frame of the display panel is limited.

Disclosure of Invention

The present application proposes a scan driving circuit and an array substrate that occupy a small space in view of the above-described deficiencies of the prior art.

The embodiment of the application provides a scanning driving circuit, which comprises n scanning driving units and two virtual scanning driving units, wherein the n scanning driving units and the two virtual scanning driving units are sequentially arranged and cascaded, each scanning driving unit is used for outputting scanning driving signals of two preset intervals, and each virtual scanning driving unit is used for outputting hierarchical signals of two preset intervals. The x-th stage scanning driving unit is cascaded with the x-2 th stage scanning driving unit, and the x-th stage scanning driving unit outputs two first stage transmission signals to the x-2 th stage scanning driving unit, wherein x is more than 2 and less than or equal to n. The two virtual scanning driving units are respectively connected with the n-1 level scanning driving unit and the n level scanning driving unit, and respectively output two second level transmission signals to the n-1 level scanning driving unit and the n level scanning driving unit, wherein the first level transmission signals and the second level transmission signals are used for driving the scanning driving unit to output the scanning driving signals.

In this embodiment, the scan driving circuit only needs to set two virtual scan driving units at the ends of the n scan driving units, where the two virtual scan driving units are respectively connected to the two scan driving units at the ends of the n scan driving units, and output the corresponding second level transmission signal to drive the scan driving units to accurately output the scan driving signals. The number of the virtual scanning driving units is reduced, so that the space occupied by the virtual scanning driving units is correspondingly reduced, and the design space of the narrow frame of the display panel is improved.

Optionally, the n scan driving units and the two virtual scan driving units are divided into 4y groups, each group receives eight clock signals, each scan driving unit and each virtual scan driving unit receives two clock signals, and y is a positive integer.

Because the n scan driving units and the two virtual scan driving units are just divided into 8y groups corresponding to clock signals, each group of GDL circuits can accurately correspond to 8 clock signals, and the compatibility of the scan driving circuits and other functional circuits is effectively improved.

Optionally, each scan driving unit includes two GDL circuits connected to each other, each GDL circuit is configured to output one of the scan driving signals, and the n scan driving units include 2n GDL circuits cascaded to each other, where an xth stage GDL circuit and a 2x—1th stage GDL circuit are included in the xth stage scan driving unit, the 2x stage GDL circuit is cascaded to the 2x—4th stage GDL circuit, the 2x—1th stage GDL circuit is cascaded to the 2x—5th stage GDL circuit, the 2x—1th stage GDL circuit is a first GDL circuit, and the 2x stage GDL circuit is a second GDL circuit. The first GDL circuit is used for receiving the 2x-5 first-stage transmission signals transmitted by the 2x-5 GDL circuit and outputting the 2x-1 first-stage transmission signals and the scanning driving signals according to the 2x-5 first-stage transmission signals. The second GDL circuit is used for receiving the 2x-4 level first level transmission signal transmitted by the 2x-4 level GDL circuit and outputting a 2x level first level transmission signal and a scanning driving signal according to the 2x-4 level first level transmission signal.

In this embodiment, among the 2n GDL circuits cascaded with each other, four GDL circuits are spaced between the GDL circuits cascaded with each other, so that output time periods with the first-stage transmission signal and the scan driving signal are effectively ensured, and meanwhile, output efficiency of the scan driving signal is improved, that is, output frequency of the scan driving signal is effectively improved, and a larger space is provided for improving refresh rate of image display.

Optionally, the first GDL circuit includes a first pull-up control module, a first pull-up module, a first pull-down control module, a second pull-down control module, a first pull-down module, a first node, and a second node. The first pull-up control module, the first pull-up module and the first pull-down control module are electrically connected to the first node. The first pull-up control module is used for pulling up the potential of the first node to a first potential according to the received 2x-5 th-level first-level transmission signal. When the potential of the first node is the first potential, the first pull-up module outputs a 2x-1 stage first stage transmission signal with the first potential, the 2x-1 stage first stage transmission signal is used for controlling a 2x-5 stage GDL circuit in an x-2 stage scanning driving unit to output a 2x-5 stage first stage transmission signal with the second potential and stopping outputting the scanning driving signal, and controlling a 2x+3 stage GDL circuit in an x+2 stage scanning driving unit to output a 2x+3 stage first stage transmission signal with the first potential and outputting the scanning driving signal. The first pull-down control module is used for pulling down the electric potential of the first node to a second electric potential, the second pull-down control module and the first pull-down module are electrically connected to the second node, the second pull-down control module is used for pulling up the electric potential of the second node to the first electric potential, and when the electric potential of the second node is the first electric potential, the first pull-down module outputs a 2x-1 level first-level transmission signal with the second electric potential.

Optionally, the second GDL circuit includes a second pull-up control module, a second pull-up module, a third pull-down control module, a fourth pull-down control module, a second pull-down module, a third node, and a fourth node, where the first pull-down module is electrically connected to the fourth node. The second pull-up control module, the second pull-up module and the third pull-down control module are electrically connected to the third node. The second pull-up control module is used for pulling up the potential of the third node to a first potential according to the received 2x-4 th level first level transmission signal, when the third node is the first potential, the second pull-up module outputs the 2x-4 th level first level transmission signal with the first potential, the 2x-4 th level first level transmission signal is used for controlling a 2x-4 th level first level transmission signal of the second potential to be output by a 2x-4 th level GDL circuit in the x-2 th level scanning driving unit and stopping outputting the scanning driving signal, and controlling a 2x+4 th level GDL circuit in the x+2 th level scanning driving unit to output the 2x+4 th level first level transmission signal of the first potential and outputting the scanning driving signal. The second pull-down control module is used for pulling down the potential of the third node to a second potential. The fourth pull-down control module and the second pull-down module are electrically connected to the fourth node, the fourth pull-down control module is used for pulling up the electric potential of the fourth node to the first electric potential, and when the electric potential of the fourth node is the first electric potential, the second pull-down module outputs a 2 x-level first-level transmission signal with the second electric potential.

In this embodiment, the first GDL circuit effectively ensures stability of the voltages of the first node and the second node by matching the foregoing functional modules, and ensures accurate output of the first-stage transmission signal and the scan driving signal. The second GDL circuit effectively ensures the stability of the voltage of the third node and the fourth node through the matching of the functional modules, and ensures the accurate output of the first-stage transmission signal and the scanning driving signal.

Optionally, the first GDL circuit further includes a first pull-down maintaining module electrically connected to the first node, the second node, and the third node. When the first node is at a first potential, the first pull-down maintaining module pulls down the potential of the second node to a second potential, and the first pull-down module stops outputting the 2x-1 th level first level transmission signal and the scanning driving signal. When the third node is at the first potential, the first pull-down maintaining module controls the second node to stop receiving the power supply voltage, and the first pull-down module stops outputting the 2x-1 level first level transmission signal and the scanning driving signal.

The second GDL circuit further includes a second pull-down maintaining module and a fifth node, wherein the second pull-down maintaining module is electrically connected to the first node, the third node and the fourth node, the third pull-down control module and the second pull-down module are connected to the fifth node, and the fifth node is electrically connected to the second node. When the first node is at the first potential, the second pull-down maintaining module controls the fourth node to stop receiving the power supply voltage, and the second pull-down module stops outputting the 2 x-stage first-level primary transmission signal and the scanning driving signal. When the third node is at the first potential, the second pull-down maintaining module pulls down the potential of the fourth node to the second potential, and the second pull-down module stops outputting the 2 x-stage first-stage transmission signal and the scanning driving signal. When the potential of the second node is the first potential, the potential of the fifth node is the first potential so as to control the second pull-down module to output the 2 x-stage first-stage transmission signal with the second potential and stop outputting the scanning driving signal.

In this embodiment, the first pull-down maintaining module in the first GDL circuit and the second pull-down maintaining module in the second GDL circuit can accurately maintain the output of the first level transmission signal and the scan driving signal stopped in the current scan driving unit by accessing the first level transmission signal provided by the corresponding cascaded GDL circuit, thereby improving the accuracy of the output timing sequence of the scan driving signals of each scan driving unit.

Optionally, when x is 2 < 4, the first pull-down control module includes a first pull-down control transistor, a second pull-down control transistor, and a third pull-down control transistor. The grid electrode of the first pull-down control transistor is electrically connected to the second node, the source electrode of the first pull-down control transistor is electrically connected to the first node, and the drain electrode of the first pull-down control transistor is connected to the first low-voltage power supply end and is connected to a first low-voltage potential. The grid electrode of the second pull-down control transistor is connected with a first primary signal, the source electrode of the second pull-down control transistor is electrically connected with the first node, and the drain electrode of the second pull-down control transistor is connected with a first low-voltage potential. The grid electrode of the third pull-down control transistor is electrically connected with the second node, the source electrode of the third pull-down control transistor is electrically connected with the first node, and the drain electrode of the third pull-down control transistor is connected with a first low-voltage potential.

The third pull-down control module includes a sixth pull-down control transistor, a seventh pull-down control transistor, and an eighth pull-down control transistor. The grid electrode of the sixth pull-down control transistor is electrically connected to the fourth node, the source electrode of the sixth pull-down control transistor is electrically connected to the third node, and the drain electrode of the sixth pull-down control transistor is connected to the first low voltage potential. The grid electrode of the seventh pull-down control transistor is connected with a first primary signal, the source electrode of the seventh pull-down control transistor is electrically connected with the third node, and the drain electrode of the seventh pull-down control transistor is connected with a first low-voltage potential. The gate of the eighth pull-down control transistor is electrically connected to the fifth node, the source of the eighth pull-down control transistor is electrically connected to the third node, and the drain of the eighth pull-down control transistor is connected to the first low voltage potential.

In this embodiment, for any x-stage scan driving units of the n scan driving units, when x is greater than 2 and less than or equal to 4, that is, in the 1 st to 8 th stage GDL circuits, the first pull-down control module and the third pull-down control module respectively include three pull-down control transistors, and the resistance-capacitance loads (RC loading) of the 1 st to 8 th stage GDL circuits are similar, so that the 1 st to 8 th stage GDL circuits have better working stability. Optionally, the first pull-up control module is further configured to access a start signal, and is configured to pull up the potential of the first node to the first potential. When the first node is at the first potential, the first pull-up module outputs a first primary transmission signal with the first potential, and the second pull-up control module is further used for accessing a start signal and pulling up the potential of the third node to the first potential. When the potential of the third node is the first potential, the second pull-up module outputs a first level transmission signal with the first potential.

In this embodiment, the first pull-up control module and the second pull-up control module are directly connected to the start signal, so that the electric potentials of the first node and the third node can be accurately pulled up to the first electric potential, and the first pull-up module and the second pull-up control module can be accurately and rapidly controlled to output the corresponding first-stage transmission signal and the scanning driving signal.

Optionally, when x is more than 2 and less than or equal to 4, the first pull-down control module comprises a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor and a fourth pull-down control transistor. The grid electrode of the first pull-down control transistor is electrically connected to the second node, the source electrode of the first pull-down control transistor is electrically connected to the first node, the drain electrode of the first pull-down control transistor is connected to a first low voltage potential, and the grid electrode of the second pull-down control transistor is connected to a first level transmission signal. The source electrode of the second pull-down control transistor is electrically connected with the first node, and the drain electrode of the second pull-down control transistor is connected with a first low-voltage potential. The grid electrode of the third pull-down control transistor is electrically connected with the second node, the source electrode of the third pull-down control transistor is electrically connected with the first node, and the drain electrode of the third pull-down control transistor is connected with a first low-voltage potential. The grid electrode of the fourth pull-down control transistor is connected with a reset signal, the source electrode of the fourth pull-down control transistor is electrically connected with the first node, the drain electrode of the fourth pull-down control transistor is connected with a first low-voltage potential,

The third pull-down control module includes a fifth pull-down control transistor, a sixth pull-down control transistor, a seventh pull-down control transistor, and an eighth pull-down control transistor. The grid electrode of the fifth pull-down control transistor is connected with a reset signal, the source electrode of the fifth pull-down control transistor is electrically connected with the third node, and the drain electrode of the fifth pull-down control transistor is connected with a first low-voltage potential. The grid electrode of the sixth pull-down control transistor is electrically connected to the fourth node, the source electrode of the sixth pull-down control transistor is electrically connected to the third node, and the drain electrode of the sixth pull-down control transistor is connected to the first low voltage potential. The grid electrode of the seventh pull-down control transistor is connected with a first primary signal, the source electrode of the seventh pull-down control transistor is electrically connected with the third node, and the drain electrode of the seventh pull-down control transistor is connected with a first low-voltage potential. The gate of the eighth pull-down control transistor is electrically connected to the fifth node, the source of the eighth pull-down control transistor is electrically connected to the third node, and the drain of the eighth pull-down control transistor is connected to the first low voltage potential.

In this embodiment, for any x-stage scan driving units in the n scan driving units, when x is greater than 2 and less than or equal to 4, that is, in the 1 st-8 th stage GDL circuit, the first pull-down control module and the third pull-down control module respectively include four pull-down control transistors and are connected with a reset signal, and when the first pull-down module or the second pull-down module is abnormal, each pull-down control transistor in the first pull-down control module and the third pull-down control module can accurately control the stop output of the first level transmission signal and the scan driving signal according to the reset signal. Meanwhile, in the 9 th-2 n-stage GDL circuits, the first pull-down control module and the third pull-down control module also respectively comprise four pull-down control transistors, so that the resistance-capacitance load (RC loading) of each stage GDL circuit is similar, and the electronic elements such as the transistors in each GDL circuit in the 2 n-stage GDL circuits are the same, and the integrity and the working stability are better.

Optionally, the first pull-up control module is further configured to access a start signal, and is configured to pull up the potential of the first node to the first potential. When the first node is at the first potential, the first pull-up module outputs a first primary transmission signal with the first potential, and the second pull-up control module is further used for accessing a start signal and pulling up the potential of the third node to the first potential. When the potential of the third node is the first potential, the second pull-up module outputs a first level transmission signal with the first potential.

Optionally, when x is greater than 4 and less than or equal to n, the first pull-down control module comprises a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor and a fourth pull-down control transistor. The grid electrode of the first pull-down control transistor is electrically connected to the second node, the source electrode of the first pull-down control transistor is electrically connected to the first node, and the drain electrode of the first pull-down control transistor is connected to a first low-voltage potential. The grid electrode of the second pull-down control transistor is connected with a first primary signal, the source electrode of the second pull-down control transistor is electrically connected with the first node, and the drain electrode of the second pull-down control transistor is connected with a first low-voltage potential. The grid electrode of the third pull-down control transistor is electrically connected with the second node, the source electrode of the third pull-down control transistor is electrically connected with the first node, and the drain electrode of the third pull-down control transistor is connected with a first low-voltage potential. The grid electrode of the fourth pull-down control transistor is connected with a starting signal, the source electrode of the fourth pull-down control transistor is electrically connected with the first node, the drain electrode of the fourth pull-down control transistor is connected with a first low-voltage potential,

The third pull-down control module includes a fifth pull-down control transistor, a sixth pull-down control transistor, a seventh pull-down control transistor, and an eighth pull-down control transistor. The grid electrode of the fifth pull-down control transistor is connected with a starting signal, the source electrode of the fifth pull-down control transistor is electrically connected with the third node, and the drain electrode of the fifth pull-down control transistor is connected with a first low-voltage potential. The grid electrode of the sixth pull-down control transistor is electrically connected to the fourth node, the source electrode of the sixth pull-down control transistor is electrically connected to the third node, and the drain electrode of the sixth pull-down control transistor is connected to the first low voltage potential. The grid electrode of the seventh pull-down control transistor is connected with the first level transmission signal, the source electrode of the seventh pull-down control transistor is electrically connected with the third node, and the drain electrode of the seventh pull-down control transistor is connected with the first low voltage potential. The gate of the eighth pull-down control transistor is electrically connected to the fifth node, the source of the eighth pull-down control transistor is electrically connected to the third node, and the drain of the eighth pull-down control transistor is connected to the first low voltage potential.

In this embodiment, for any x-stage scan driving units of the n scan driving units, when x is greater than 4 and less than or equal to n, that is, in the 9 th-2 n-stage GDL circuit, the first pull-down control module and the third pull-down control module respectively include four pull-down control transistors and are connected with a reset signal, and when the first pull-down module or the second pull-down module is abnormal, each pull-down control transistor in the first pull-down control module and the third pull-down control module can accurately control the stop output of the first level transmission signal and the scan driving signal according to the reset signal. Meanwhile, the resistance-capacitance load (RC loading) of each stage of GDL circuit is similar, so that the electronic elements such as transistors in each GDL circuit in the 2n stages of GDL circuits are the same, and the integrity and the working stability are better. Optionally, the first pull-up control module is further configured to access the 2x-5 stage first level signaling, and pull up the potential of the first node to a first potential. When the potential of the first node is the first potential, the first pull-up module outputs a 2x-1 stage first stage transmission signal with the first potential. The second pull-up control module is also used for accessing a 2x-4 level first level transmission signal and is used for pulling up the potential of the third node to the first potential. When the potential of the third node is the first potential, the second pull-up module outputs a 2 x-stage first-stage transmission signal with the first potential.

In this embodiment, four GDL circuits are cascaded to each other and transmit the level transmission signal at intervals, so that the output duration with the first level transmission signal and the scan driving signal is effectively ensured, and meanwhile, the output efficiency of the scan driving signal is improved.

Optionally, each virtual scan driving unit includes two virtual GDL circuits, and four virtual GDL circuits are sequentially arranged. The four virtual GDL circuits are respectively connected with the two GDL circuits in the nth stage scanning driving unit and the two GDL circuits in the n-1 th stage scanning driving unit, and respectively output the second level transmission signals to the two GDL circuits in the nth stage scanning driving unit and the two GDL circuits in the n-1 th stage scanning driving unit so as to drive the two GDL circuits in the nth stage scanning driving unit and the two GDL circuits in the n-1 th stage scanning driving unit to stop outputting the scanning driving signals.

In this embodiment, the two virtual GDL circuits are respectively connected to and output the second-stage transmission signal to the n-1-stage scan driving unit and the n-stage scan driving unit, so as to drive the n-1-stage scan driving unit and the n-stage scan driving unit to accurately output the scan driving signal.

Optionally, the two virtual GDL circuits included in the virtual scan driving unit include a first virtual GDL circuit and a second virtual GDL circuit. The first virtual GDL circuit includes a first virtual pull-up control module, a first virtual pull-up module, a first virtual pull-down control module, a second virtual pull-down control module, a first virtual pull-down module, a first virtual node, and a second virtual node. The first virtual pull-up control module, the first virtual pull-up module and the first virtual pull-down control module are electrically connected to the first virtual node. The first virtual pull-up control module is used for pulling up the potential of the first virtual node to a first potential, when the potential of the first virtual node is the first potential, the first virtual pull-up module outputs the second-stage transmission signal with the first potential, and the second-stage transmission signal is used for controlling one GDL circuit in the nth-stage scanning driving unit and the n-1-stage scanning driving unit to output the first-stage transmission signal with the second potential and stop outputting the scanning driving signal. The first virtual pull-down control module is used for pulling down the potential of the first virtual node to a second potential. The second virtual pull-down control module is electrically connected to the second virtual node, and is used for pulling up the potential of the second virtual node to a first potential, and when the potential of the second virtual node is the first potential, the first virtual pull-down module outputs the second-level transmission signal with the second potential. Optionally, the second virtual GDL circuit includes a second virtual pull-up control module, a second virtual pull-up module, a third virtual pull-down control module, a fourth virtual pull-down control module, a second virtual pull-down module, a third virtual node, and a fourth virtual node. The first virtual pull-down module is electrically connected with the fourth virtual node. The second virtual pull-up control module, the second virtual pull-up module and the third virtual pull-down control module are electrically connected to the third virtual node. The second virtual pull-up control module is used for pulling up the potential of the third virtual node to a first potential, and when the potential of the third virtual node is the first potential, the second virtual pull-up module outputs a second-stage transmission signal with the first potential, and the second-stage transmission signal is used for controlling one GDL circuit in an nth-stage scanning driving unit and an nth-1-stage scanning driving unit to output the first-stage transmission signal with the second potential and stop outputting the scanning driving signal. The second virtual pull-down control module is used for pulling down the potential of the third virtual node to a second potential. The fourth virtual pull-down control module and the second virtual pull-down module are electrically connected to the fourth virtual node, the fourth virtual pull-down control module is used for pulling up the electric potential of the fourth virtual node to a first electric potential, and when the electric potential of the fourth virtual node is the first electric potential, the second virtual pull-down module outputs the second-level transmission signal with a second electric potential.

In this embodiment, the two virtual GDL circuits effectively ensure stability of the voltages of the first virtual node and the second virtual node through cooperation of the foregoing functional modules, and ensure accurate output of the second level transmission signal.

Optionally, the first virtual GDL circuit further includes a first virtual pull-down maintenance module electrically connected to the first virtual node, the second virtual node, and the third virtual node. When the potential of the first virtual node is the first potential, the first virtual pull-down maintaining module pulls down the potential of the second virtual node to the second potential, and the first virtual pull-down module stops outputting the second level transmission signal. When the potential of the third virtual node is the first potential, the first virtual pull-down maintaining module controls the second virtual node to stop receiving the power supply voltage, and the first virtual pull-down module stops outputting the second level transmission signal. The second virtual GDL circuit further includes a second virtual pull-down maintenance module electrically connected to the first virtual node, the third virtual node, and the fourth virtual node. When the potential of the first virtual node is the first potential, the second virtual pull-down maintaining module controls the fourth virtual node to stop receiving the power supply voltage, and the second virtual pull-down module stops outputting a second level transmission signal. When the potential of the third virtual node is the first potential, the second virtual pull-down maintaining module pulls down the fourth virtual node to the second potential, and the second virtual pull-down module stops outputting the second level transmission signal.

In this embodiment, the first virtual pull-down maintaining module in the first virtual GDL circuit and the second virtual pull-down maintaining module in the second virtual GDL circuit can accurately maintain the output of the second-stage signaling stopped in the current virtual scan driving unit by accessing the first-stage signaling provided by the corresponding cascaded GDL circuit, thereby improving the accuracy of the second-stage signaling output timing of each virtual scan driving unit.

Optionally, the application further provides an array substrate including the foregoing scan driving circuit, where the array substrate includes 2n scan lines, a plurality of pixel units arranged in an array, and the foregoing scan driving circuit, where the 2n scan lines are respectively connected to the n scan driving units, and respectively receive 2n scan driving signals from the n scan driving units in sequence, and the plurality of pixel units receive image data and display images under control of the 2n scan driving signals.

Optionally, the application further provides a display terminal comprising the scanning driving circuit.

Compared with the prior art, the array substrate and the scanning driving circuit in the display terminal only need to arrange the virtual scanning driving units at the tail ends of the cascaded scanning driving units to control the cascade output of the scanning driving signals, so that the number of the virtual scanning driving units and occupied space are effectively reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic side view of a display terminal according to an embodiment of the present application;

FIG. 2 is a schematic plan view of an array substrate in the display panel shown in FIG. 1;

FIG. 3 is a schematic diagram illustrating connection of the scan driving circuit shown in FIG. 2 according to an embodiment of the present application;

fig. 4 is a schematic circuit diagram of any one of the scan driving units GDL5 to GDL1080 according to the first embodiment of the present application;

fig. 5 is a circuit configuration diagram of any one of the scan driving units GDL1 to GDL4 shown in fig. 3;

FIG. 6 is a circuit diagram of one of the virtual scan driving units GDL1 and GDL2 shown in FIG. 3;

FIG. 7 is a schematic diagram showing the layout structure of the scan driving units GDL1 to GDL4 shown in FIG. 5;

FIG. 8 is a circuit layout of the scan driving units GDL1 to GDL4 shown in FIG. 5;

Fig. 9 is a schematic diagram showing a layout structure of any four of the scan driving units GDL5 to GDL1080 shown in fig. 4;

fig. 10 is a circuit layout diagram of any four scan driving units among the scan driving units GDL5 to GDL1080 shown in fig. 4;

FIG. 11 is a schematic diagram showing the layout structure of the virtual scan driving units GDL1 and GDL2 shown in FIG. 6;

FIG. 12 is a circuit layout of the virtual scan driving units GDL1 and GDL2 shown in FIG. 6;

FIG. 13 is a timing chart showing a circuit one-frame image display process of any one of the scan driving units GDL1 to GDL 1080;

fig. 14 is a circuit configuration diagram of any one of the scan driving units GDL1 to GDL4 shown in fig. 3 in the second embodiment of the present application.

Reference numerals:

1000-display terminals, 900-display panels, 900 a-image display areas, 900 b-non-display areas, 900 c-array substrates, 900 d-object substrates, 900e display medium layers, P-pixel units, 120-data lines, 130-scanning lines, 101-time sequence control circuits, 102-data driving circuits, 103-scanning driving circuits and G1-G2 n-scanning driving signals;

CK (e) -e clock signal, STV-enable signal, VDD-supply voltage, vss 1-first low voltage potential, vss 2-second low voltage potential, reset-Reset signal;

A 100-scan driving module, a 200-virtual scan driving module, a 100A-first GDL circuit, a 100B-second GDL circuit, a 10-first pull-down control module, a 20-first pull-down module, a 30A-first pull-down control module, a 30B-second pull-down control module, a 40-first pull-down module, a 50-first pull-down maintenance module, a Q (2C-1) (Q (2 i-1)) -first node, a Qb (2C-1) (Qb (2 i-1)) -second node, a 60-second pull-up control module, a 70-second pull-up module, a 80A-third pull-down control module, a 80B-fourth pull-down control module, a 90-second pull-down module, a 55-second pull-down maintenance module, a Q (2C) (Q (2 i)) -third node, a Qb (2C) (Qb (2 i)) -fourth node, a Qb (2c+1) (Qb (2 i)) -fifth node, a C (2 c+1)) -fifth node, a C (2C-1) -C (2 i) -second stage (2 i) -2G (2 i) -signal transmission stage (C-1), a scan driving stage (C) -2 i) -signal transmission stage (C-2 i) -2 (C-1 stage (2 i) -signal transmission stage (1), g (2 i) -2 i-th stage scan driving signals;

200A-a first virtual GDL circuit, 200B-a second virtual GDL circuit, 210-a first virtual pull-up control module, 220-a first virtual pull-up module, 230A-a first virtual pull-down control module, 230B-a second virtual pull-down control module, 240-a first virtual pull-down module, 250-a first virtual pull-down maintenance module, P (2 j-1) -a first virtual node, pb (2 j-1) a second virtual node, 260-a second virtual pull-up control module, 270-a second virtual pull-up module, 280A-a third virtual pull-down control module, 280B-a fourth virtual pull-down control module, 290-a second virtual pull-down module, 255-a second virtual pull-down maintenance module, P (2 j) -a third virtual node, pb (2 j) -a fourth virtual node, pb (2j+1) -a fifth virtual node; ca (1) -Ca (4) -virtual hierarchical signals;

T11-eleventh transistor, T21-twenty-first transistor, T22-twenty-first transistor, T31-thirty-first transistor, T32-thirty-fourth transistor, T33-thirty-third transistor, T34-thirty-fourth transistor, T35-thirty-fifth transistor, T36-thirty-sixth transistor, T37-thirty-seventh transistor, T41-fortieth-first transistor, T42-fortieth transistor, T43-fortieth-third transistor, T44-fortieth-transistor, T51-fifty-first transistor, T52-fifty-fourth transistor, T53-fifty-third transistor, T61-sixty-first transistor, T71-seventy-first transistor, T72-seventy-first transistor, T81-eighty-first transistor, T82-eighty-first transistor, T83-eighty-third transistor, T84-eighty-fourth transistor, T85-eighty-fifth transistor, T86-eighty-sixth transistor, T87-eighty-seventh transistor, T91-ninety-first transistor, T92-ninety-second transistor, T93-ninety-third transistor, T94-ninety-fourth transistor, T95-ninety-fifth transistor, T96-ninety-sixth transistor, T97-ninety-seventh transistor.

Detailed Description

In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The terms "coupled" and "connected," as used herein, are intended to encompass both direct and indirect coupling (coupling), unless otherwise indicated. Directional terms referred to in this application, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., are merely directions referring to the attached drawings, and thus, directional terms are used for better, more clear description and understanding of the present application, rather than indicating or implying that the apparatus or element being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; may be a mechanical connection; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context. It should be noted that the terms "first," "second," and the like in the description and claims of the present application and in the drawings are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprises," "comprising," "includes," "including," "may be" or "including" as used in this application mean the presence of the corresponding function, operation, element, etc. disclosed, but not limited to other one or more additional functions, operations, elements, etc. Furthermore, the terms "comprises" or "comprising" mean that there is a corresponding feature, number, step, operation, element, component, or combination thereof disclosed in the specification, and that there is no intention to exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

Referring to fig. 1, fig. 1 is a schematic side view of a display terminal according to an embodiment of the disclosure. As shown in fig. 1, the display terminal 1000 includes a display panel 900 and other components (not shown) including a power module, a signal processor module, a signal sensing module, and the like.

The display panel 900 includes an image display area 900a and a non-display area 900b. The image display area 900a is used for performing image display, and the non-display area 900b is disposed around the image display area 900a to dispose other auxiliary components or modules. Specifically, the display panel 900 includes an array substrate 900c and an opposite substrate 900d, and a display medium layer 900e sandwiched between the array substrate 900c and the opposite substrate 900 d. In this embodiment, the display medium in the display medium layer is a Liquid Crystal (Liquid Crystal), that is, the display panel 900 in this embodiment is a Liquid Crystal display panel.

Fig. 2 is a schematic plan view of an array substrate in the display panel shown in fig. 1. As shown in fig. 2, the corresponding image display area 900a in the array substrate 900c includes a plurality of m×n Pixel units (pixels) P, m Data lines (Data lines) 120 and n Scan driving lines (Scan lines) 130 arranged in a matrix, where m and n are natural numbers greater than 1.

Corresponding to the non-display area 900b of the display panel 900, the display terminal 1000 further includes a timing control circuit 101, a Data driving circuit (Data Driver) 102, and a Scan driving circuit (Scan Driver) 103 for driving the pixel units to perform image display, which are disposed on the array substrate 900 c.

The data driving circuit 102 is electrically connected to the plurality of data lines 120, and is configured to transmit the image data to be displayed to the plurality of pixel units P in the form of data voltages through the plurality of data lines 120.

The scan driving circuit 103 is electrically connected to the plurality of scan driving lines 130, and is configured to output a scan driving signal G2n through the plurality of scan driving lines 130 to control when the pixel unit P receives the image data. The scan driving circuit 103 sequentially outputs the scan driving signals G1, G2, … G32, …, gn from the plurality of scan driving lines 130 in the position arrangement order from the scan driving lines G1, G2, … G32, …, gn in the scanning period.

The timing control circuit 101 is electrically connected to the data driving circuit 102 and the scan driving circuit 103, and is used for controlling the operation timings of the data driving circuit 102 and the scan driving circuit 103, that is, outputting corresponding timing control signals (clock signals) to the scan driving circuit 103 and the data driving circuit 102, so as to control when to output corresponding scan driving signals Gn.

In this embodiment, the scan driving circuit 103 is disposed in the area corresponding to the array substrate 900c in the form of gate driving (GOA) technology and the process of the array substrate, and preferably, the scan driving circuit 103 may further employ less gate driving technology (GDL) disposed in the area corresponding to the array substrate 900 c.

It can be appreciated that the display terminal 1000 further includes other auxiliary circuits for jointly completing the display of the image, such as an image receiving processing circuit (Graphics Processing Unit, GPU), a power circuit, etc., which will not be described in detail in this embodiment.

Referring to fig. 3, fig. 3 is a schematic diagram illustrating connection of the scan driving circuit shown in fig. 2 in the embodiment of the present application, the scan driving circuit 103 includes a scan driving module 100 and a dummy scan driving module 200, and eight clock signals CK (e) (e=1, 2, …, 8).

In other embodiments of the present application, the number of clock signals received by the scan driving circuit 103 from the timing control circuit 101 is 8, which may respectively represent eight clock signals CK (e) (e=1, 2, …, 8), and may be adjusted according to actual requirements, for example, 4 clock signals, 6 clock signals, 10 clock signals, 12 clock signals, and the number of clock signals is different to correspond to display panels with different resolutions. Further, the scan driving circuit 103 also receives a start signal STV, a Reset signal Reset, a first low voltage potential Vss1, a second low voltage potential Vss2, and a power supply high voltage VDD from the timing control circuit 101.

In this embodiment, n is 1080, and the scan driving module 100 outputs a plurality of corresponding scan driving signals G1 to G2n, which may be denoted as G1 to G2160, corresponding to 2160 scan lines 130 shown in fig. 2. In other embodiments of the present application, the number of scan lines may be set according to the actual resolution, but is not limited thereto.

Specifically, the scan driving module 100 includes a plurality of sequentially cascaded scan driving units GDL1 to GDL1080, and the virtual scan driving module 200 includes two virtual scan driving units GDLa1 to GDLa2. The dummy scan driving units GDLa1 to GDLa2 respectively include a first dummy GDL circuit 200A (fig. 6) and a second dummy GLD circuit 200B (fig. 6).

In the embodiment of the present application, the specific manner in which the scan driving units GDL1 to GDL1080 are cascaded with each other may be that any one scan driving unit is cascaded with the scan driving unit of 1 scan driving unit at intervals, for example, the first stage scan driving unit GDL1 is cascaded with the third stage scan driving unit GDL3, the second stage scan driving unit GDL2 is cascaded with the fourth stage scan driving unit GDL4, and the like, the nth-5 stage scan driving unit GDLn-5 is cascaded with the nth-3 stage scan driving unit GDLn-3, and the nth-4 stage scan driving unit GDLn-4 is cascaded with the nth-2 stage scan driving unit GDLn-2. The n-1 stage scan driving unit GDLn-1 and the n stage scan driving unit GDLn are respectively connected with two virtual scan driving units GDLa1 to GDLa2 in the virtual scan driving module 200, and accurately output corresponding scan driving signals under the driving of the second stage signaling signals output by the two virtual scan driving units GDLa1 to GDLa 2. In the present embodiment, the two dummy scan driving units GDLa1 to GDLa2 in the dummy scan driving module 200 are only used for cascade driving the n-1 st stage scan driving unit GDLn-1 and the n-th stage scan driving unit GDLn without outputting the scan driving signal.

Specifically, the n-1 stage scan driving unit GDLn-1, the n-th stage scan driving unit GDLn, and the virtual scan driving units GDLa1 to GDLa2 are connected in cascade, in which the first stage virtual scan driving unit GDLa1 is connected to the n-1 stage scan driving unit GDLn-1 (scan driving unit GDL 1079), and the second stage virtual scan driving unit GDLa2 is connected to the n-th stage scan driving unit GDLn (scan driving unit GDL 1080).

In this embodiment, the scan driving units GDL1 to GDL1080 are sequentially cascaded, specifically, each scan driving unit outputs a level transmission signal, and the level transmission signal drives the scan driving unit to be cascaded to pull up the node voltage of one of the nodes connected to the scan driving unit, so that the connected scan driving unit accurately outputs the scan driving signal and the level transmission signal.

For example, the gradation signal output from the first stage scan driving unit GDL1 can pull up the node voltage of the third stage scan driving unit GDL3, thereby enabling the scan driving signal and the gradation signal to be output. The gradation signal output from the second stage scan driving unit GDL2 can pull up the node voltage of the second stage scan driving unit GDL4, so that the scan driving signal and the gradation signal are output, and so on.

More specifically, any one of the scan driving units GDL includes a scan driving circuit outputting scan driving signals in two stages, which will be hereinafter simply referred to as a GDL circuit for convenience of description. Each stage of the GDL circuit outputs one scan driving signal correspondingly, so one scan driving unit GDL outputs two scan driving signals. For example, the scan driving unit GDL1 outputs the scan driving signal G1 and the scan driving signal G2, the scan driving unit GDL2 outputs the scan driving signal G3 and the scan driving signals G4, … …, the scan driving unit GDL1079 outputs the scan driving signal G2157 and the scan driving signal G2158, and the scan driving unit GDL1080 outputs the scan driving signal G2159 and the scan driving signal G2160. The virtual scan driving module 200 includes a first stage virtual scan driving unit GDLa1 and a second stage virtual scan driving unit GDLa2.

In this embodiment, since the scan driving units GDL1 to GDLn (scan driving units GDL1 to GDL 1080) are sequentially cascaded with each other, 2n (2060) GDL circuits included in the scan driving units GDL1 to GDL1080 should also be sequentially cascaded with each other. For ease of illustration, the 2n GDL circuits may be defined as a first stage GDL circuit, a second stage GDL circuit, a third stage GDL circuit, a fourth stage GDL circuit, … …, a 2n-1 stage GDL circuit, and a 2n stage GDL circuit, respectively. Correspondingly, the first stage GDL circuit outputs a scan driving signal G1, the second stage outputs scan driving signals G2, … …, and the 2 n-th stage GDL circuit outputs a scan driving signal G2n. In this embodiment, the 2n GDL circuits may be specifically cascaded, where any one GDL circuit is cascaded with a scan driving circuit separated by 4 GDL circuits. In this embodiment, the connection mode may be that, among the n scan driving units, the scan driving units cascaded with each other are separated by one scan driving unit, that is, the x-th scan driving unit is cascaded with the x-2-th scan driving unit, where x is greater than 2 and less than or equal to n. Correspondingly, when the x-th stage scanning driving unit is cascaded with the x-2 th stage scanning driving unit, the x-th stage scanning driving unit outputs two first stage transmission signals to the x-2 th stage scanning driving unit, so that the x-2 th stage scanning driving unit is driven to output scanning driving signals.

In this embodiment, the scan driving circuit 103 only needs to set two virtual scan driving units GDLa1 to GDLa2 at the ends of the n scan driving units GDL1 to GDLn, where the two virtual scan driving units GDLa1 to GDLa2 are respectively connected to the two scan driving units GDLn-1 to GDLn at the ends of the n scan driving units, and output corresponding second level transmission signals to drive the scan driving units GDLn-1 to GDLn to accurately output the scan driving signals. Because the number of the virtual scanning driving units GDLa 1-GDLa 2 is small, the space occupied by the virtual scanning driving units is correspondingly reduced, and the design space of the narrow frame of the display panel is improved.

In the 2 n-stage GDL circuits correspondingly, four GDL circuits are arranged at intervals among the mutually cascaded GDL circuits, namely the 2 x-stage GDL circuit is cascaded with the 2 x-4-stage GDL circuits. More specifically, two GDL circuits in each scan driving unit are defined as a first GDL circuit and a second GDL circuit, respectively. Then, for 2*n mutually cascaded GDL circuits, any one first GDL circuit is used to receive the cascade signal transmitted by the 2x-4 stage GDL circuit, and the second GDL circuit is used to receive the cascade signal transmitted by the 2x-3 stage GDL circuit.

When x=n, that is, the 2n-3 th to 2 n-th stage GDL circuits among the n-1 st and n-1 st stage scan driving units GDLn-1 and GDLn are respectively connected to the four virtual GDL circuits included in the virtual scan driving units GDLa1 to GDLa2, that is, the virtual first virtual GDL circuit 200A and the second virtual GLD circuit 200B included in the virtual scan driving units GDLa1 to GDLa 2. The two virtual scanning driving units GDLa 1-GDLa 2 respectively output two second-stage signal driving to the 2 n-3-stage GDL circuit-2 n-stage GDL circuit, and the 2 n-3-stage GDL circuit-2 n-stage GDL circuit accurately outputs corresponding scanning driving signals under the control of the second-stage signal driving. For example, the first stage GDL circuit is cascaded with the fifth stage GDL circuit, the fourth stage GDL circuit is cascaded with the eighth stage GDL circuit, and so on, and the present embodiment is not described again.

In this embodiment, among the 2n GDL circuits cascaded with each other, four GDL circuits are spaced between the GDL circuits cascaded with each other, so that the output duration with the first-stage transmission signal and the scan driving signal is effectively ensured, and meanwhile, the output efficiency of the scan driving signal is improved, that is, the output frequency of the scan driving signal is effectively improved, and a larger space is provided for improving the refresh rate of image display.

Eight clock signals CK (e) are used to provide scan driving timings for the scan driving units GDL1 to GDLn (the scan driving units GDL1 to GDL 1080) and the two dummy scan driving units GDLa1 to GDLa2 in the scan driving circuit 103, where e=1, 2, … …, 8. In the embodiment of the present application, the clock signal CK (e) is used to supply the clock signals to the multi-stage scan driving unit GDL and the multi-stage virtual scan driving unit GDLa.

Specifically, the n scan driving units and the two virtual scan driving units are commonly divided into 4y groups, that is, the first stage GDL circuit to the 2n stage GDLn and the four virtual GDL circuits are divided into 4 (2 y) groups, where y is a positive integer. Since each group receives eight clock signals, each of the scan driving units and each of the dummy scan driving units receives two clock signals CK, that is, each of the GDL circuits or the dummy GDL circuits in each group receives one clock signal, so that the first-stage GDL circuit to the 2 n-stage GDLn and the four dummy GDL circuits are just divided into 8y groups, each group of GDL circuits can accurately correspond to 8 clock signals, for example, the first-stage GDL circuit to the eighth-stage GDL circuit respectively correspond to clock signals CK (1) to CK (8), the ninth-stage GDL circuit to the sixteenth-stage GDL circuit respectively correspond to clock signals CK (1) to CK (8), and so on, the 2 n-3-stage GDL circuit to the 4 dummy GDL circuits respectively correspond to clock signals CK (1) to CK (8). It can be seen that the first stage GDL circuit starts to directly correspond to the clock signal CK (1), effectively improving the mutual compatibility of the scan driving circuit 103 and the timing control circuit 101.

Referring to fig. 4, fig. 4 is a schematic circuit diagram of any one of the scan driving units GDL5 to GDL1080 shown in fig. 3 according to the first embodiment of the present application. Taking the scan driving unit GDLc as an example, c is greater than 4 and less than n-1 and is a positive integer. The scan driving unit GDLc includes two GDL circuits, which may be defined as a first GDL circuit 100A and a second GDL circuit 100B, respectively, the first GDL circuit 100A of the scan driving unit GDLc outputting the 2C-1 th stage scan driving signal G (2C-1) and outputting the 2C-1 th stage transfer signal C (2C-1), and the second GDL circuit 100B of the scan driving unit GDLc outputting the 2C-th stage scan driving signal G (2C) and outputting the 2C-th stage transfer signal C (2C). In this embodiment, the 2C-1 st level transmission signal C (2C-1) and the 2C-th level transmission signal C (2C) are first level transmission signals.

The first GDL circuit 100A includes a first pull-up control module 10, a first pull-up module 20, a first pull-down control module 30A, a second pull-down control module 30B, a first pull-down module 40, a first pull-down maintenance module 50, a first node Q (2 c-1) and a second node Qb (2 c-1).

The first pull-up control module 10 is electrically connected to the level-pass signal output terminal (C (2C-5)) and the first node Q (2C-1), and is connected to the level-pass signal C (2C-5) of the 2C-5 th level. The first pull-up control module 10 pulls up the potential of the first node Q (2C-1) to a first potential by using the 2C-5 th level transmission signal C (2C-5), wherein the first potential is a high point, and the second potential is a low potential.

In this embodiment, four GDL circuits are cascaded to each other and transmit the level transmission signal at intervals, so that the output duration of the first level transmission signal and the scan driving signal is effectively ensured, and the output efficiency of the scan driving signal is improved.

The first pull-up module 20 is connected to the e-th clock signal CK (e) and electrically connects the first node Q (2C-1), the stage signal output terminal (C (2C-1)) and the scan driving signal output terminal (G (2C-1)). The first pull-up module 20 is configured to output a 2C-1 th level transmission signal C (2C-1) and a 2C-1 th level scan driving signal G (2C-1) according to an e-th clock signal CK (e) under the potential control of the first node Q (2C-1).

The first pull-down control module 30A is connected to the start signal STV, and is electrically connected to the first node Q (2C-1), the second node Qb (2C-1), the first low voltage power supply terminal, and the level signal output terminal (C (2c+3)), and is connected to the first voltage level Vss1 from the first low voltage power supply terminal and the level signal C (2c+3) from the level signal output terminal (C (2c+3)), and the first pull-down control module 30A pulls down the potential of the first node Q (2C-1) to the second potential by using the start signal STV and pulls down the potential of the first node Q (2C-1) by using the level signal C (2c+3).

If the circuit shown in fig. 4 is a schematic circuit diagram of the scan driving units GDL5 to GDL1078, the first pull-down control module 30A of the first GDL circuit 100A is connected to the start signal STV. If the circuit shown in fig. 4 is a schematic circuit structure diagram of the scan driving unit GDL1079, the first pull-down control module 30A of the first GDL circuit 100A accesses the level-pass signal of the first virtual GDL circuit of the virtual scan driving unit GDL 1. If the circuit shown in fig. 4 is a schematic circuit structure diagram of the scan driving unit GDL1080, the first pull-down control module 30A of the first GDL circuit 100A accesses the hierarchical signal of the first virtual GDL circuit of the virtual scan driving unit GDL 2.

The second pull-down control module 30B is connected to the power high voltage VDD, and is electrically connected to the first node Q (2 c-1) and the second node Qb (2 c-1). The second pull-down control module 30B pulls up the potential of the second node Qb (2 c-1) to the first potential using the low level of the first node Q (2 c-1) and the power high voltage VDD.

The first pull-down module 40 is electrically connected to the second node Qb (2C-1), the stage signal output terminal (C (2C-1)), the scan driving signal output terminal (G (2C-1)), the first low voltage power supply terminal (not labeled) and the second low voltage power supply terminal (not labeled), and is connected to the first low voltage power supply terminal from the first low voltage power supply terminal to the first low voltage power level Vss1, and is connected to the second low voltage power supply terminal from the second low voltage power supply terminal to the second low voltage power level Vss2. The first pull-down module 40 outputs the 2C-1 th level transmission signal C (2C-1) by using the first potential of the second node Qb (2C-1), and outputs the 2C-1 th level scanning driving signal G (2C-1) by using the first potential of the second node Qb (2C-1).

The first pull-down maintaining module 50 is electrically connected to the first node Q (2C-1), the second node Qb (2C-1), the level signal output terminal (C (2C-5)) and the first low voltage power terminal, and is connected to the first low voltage power terminal to the first low voltage power supply Vss1 and the level signal output terminal (C (2C-5)) to the level signal C (2C-5). The first pull-down maintaining module 50 maintains the first node Q (2C-1) and the second node Qb (2C-1) levels using the 2C-5 th level transmission signal C (2C-5). The first pull-down maintaining module 50 is configured to pull down the potential of the second node Qb (2C-1) to the second potential when the first node Q (2 n-1) is at the first potential, and the first pull-down module 40 stops outputting the 2C-1 st level transmission signal C (2C-1) and the 2C-1 st level transmission signal C (2C-1) scanning driving signal G (2C-1).

In this embodiment, the 2C-5 th and 2c+3 th level transmission signals C (2C-5) and C (2c+3) are first level transmission signals. The first virtual GDL circuit's signaling signal is a second signaling signal.

The first GDL circuit 100A effectively ensures the stability of the voltages of the first node Q (2 c-1) and the second node Qb (2 c-1) through the cooperation of the foregoing functional modules, and ensures the accurate output of the first-stage transmission signal and the scan driving signal. Specifically, the first pull-up control module 10 includes an eleventh transistor T11. The gate and source of the eleventh transistor T11 are electrically connected to the level-pass signal output terminal (C (2C-5)) and are connected to the level-pass signal C (2C-5) of level 2C-5, and the drain is electrically connected to the first node Q (2C-1).

The first pull-up module 20 includes a twenty-first transistor T21 and a twenty-second transistor T22. The source of the twenty-first transistor T21 is connected to the e-th clock signal CK (e), the gate is electrically connected to the first node Q (2C-1), and the drain is electrically connected to the level signaling output terminal (C (2C-1)). The source electrode of the twenty-second transistor T22 is connected to the e-th clock signal CK (e), the grid electrode is electrically connected to the first node Q (2C-1), and the drain electrode is electrically connected to the level signaling output end (C (2C-1)).

The first pull-down control module 30A includes a thirty-first transistor T31, a thirty-second transistor T32, a thirty-third transistor T33, and a thirty-fourth transistor T34. The thirty-first transistor T31 has a gate connected to the start signal STV, a source electrically connected to the first node Q (2 c-1), a drain electrically connected to the first low voltage power supply terminal, and a first low voltage potential Vss1 connected from the first low voltage power supply terminal. The thirty-second transistor T32 has a gate electrically connected to the second node Qb (2 c-1), a source electrically connected to the first node Q (2 c-1), a drain electrically connected to the first low voltage power supply terminal, and a first low voltage potential Vss1 connected from the first low voltage power supply terminal. The thirty-third transistor T33 has a gate electrically connected to the level-signaling output terminal (C (2c+3)) and an access to the 2c+3-level-signaling C (2c+3)), a source electrically connected to the first node Q (2C-1), a drain electrically connected to the first low-voltage power supply terminal, and an access to the first low-voltage power supply Vss1 from the first low-voltage power supply terminal. The gate of the thirty-fourth transistor T34 is electrically connected to the second node Qb (2 c-1), the source is electrically connected to the first node Q (2 c-1), the drain is electrically connected to the first low voltage power supply terminal, and the first low voltage power supply terminal is connected to the first low voltage power supply Vss1. For ease of understanding and explanation, the thirty-first transistor T32 may be defined as a first pull-down control transistor, the thirty-third transistor T33 may be defined as a second pull-down control transistor, the thirty-fourth transistor T34 may be defined as a third pull-down control transistor, and the thirty-first transistor T31 may be defined as a fourth pull-down control transistor.

If the circuit shown in fig. 4 is a circuit connection configuration diagram of the scan driving units GDL5 to GDL1078, the gate of the thirty-third transistor T33 of the first GDL circuit 100A is connected to the start signal STV. If the circuit shown in fig. 4 is a circuit connection structure diagram of the scan driving unit GDL1079, a gate of the thirty-third transistor T33 of the first GDL circuit 100A is electrically connected to the virtual stage signal output terminal, and is connected to the stage signal of the first virtual GDL circuit of the virtual scan driving unit GDL 1. If the circuit shown in fig. 4 is a circuit connection structure diagram of the scan driving unit GDL1080, a gate of the thirty-third transistor T33 of the first GDL circuit 100A is electrically connected to the virtual stage signal output terminal, and is connected to the stage signal of the first virtual GDL circuit of the virtual scan driving unit GDL 2.

The second pull-down control module 30B includes a thirty-fifth transistor T35, a thirty-sixth transistor T36, and a thirty-seventh transistor T37. The source and gate of the thirty-fifth transistor T35 are electrically connected to the power supply voltage VDD, and the drain is electrically connected to the gate of the thirty-sixth transistor T36 and the source of the thirty-seventh transistor T37. The thirty-sixth transistor T36 has a source electrically connected to the power supply voltage VDD and a drain electrically connected to the second node Qb (2 c-1). The thirty-seventh transistor T37 has a gate electrically connected to the first node Q (2 c-1), a drain electrically connected to the first low voltage power supply terminal, and a first low voltage potential Vss1 connected from the first low voltage power supply terminal.

The first pull-down module 40 includes a forty-first transistor T41, a forty-second transistor T42, a forty-third transistor T43, and a forty-fourth transistor T44. The gate of the forty-first transistor T41 is electrically connected to the second node Qb (2C-1), the source is electrically connected to the level signaling output terminal (C (2C-1)), and the drain is electrically connected to the first low voltage power supply terminal, and is connected to the first low voltage potential Vss1 from the first low voltage power supply terminal. The gate of the forty-second transistor T42 is electrically connected to the second node Qb (2 c-1), the source is electrically connected to the scan driving signal output terminal (G (2 c-1)), and the drain is electrically connected to the second low voltage power terminal, and the second low voltage power terminal is connected to the second low voltage power level Vss2. The forty-third transistor T43 has a gate electrically connected to the fourth node Qb (2 c), a source electrically connected to the scan driving signal output terminal (G (2 c-1)), and a drain electrically connected to the second low voltage power terminal, and is connected to the second low voltage potential Vss2 from the second low voltage power terminal. The gate of the forty-fourth transistor T44 is electrically connected to the fourth node Qb (2C), the source is electrically connected to the level signaling output terminal (C (2C-1)), and the drain is electrically connected to the second low voltage power terminal, and the second low voltage potential Vss2 is connected from the second low voltage power terminal.

The first pull-down maintaining module 50 includes a fifty-first transistor T51, a fifty-second transistor T52, and a thirteenth transistor T53. The fifty-first transistor T51 has a gate electrically connected to the first node Q (2 c-1), a source electrically connected to the second node Qb (2 c-1), a drain electrically connected to the first low voltage power terminal, and a first low voltage potential Vss1 connected from the first low voltage power terminal. The fifty-th transistor T52 has a gate electrically connected to the stage signal output terminal (C (2C-5)) and an access to the stage signal C (2C-5) of the 2C-5 stage, a drain electrically connected to the first low voltage power supply terminal, a source electrically connected to the second node Qb (2C-1), and an access to the first low voltage power supply Vss1 from the first low voltage power supply terminal. The fifty-third transistor T53 has a gate electrically connected to the third node Q (2 c), a source electrically connected to the drain of the thirty-fifth transistor T35, and a drain electrically connected to the first low voltage power supply terminal and connected to the first low voltage potential Vss1 from the first low voltage power supply terminal.

The second GDL circuit 100B includes a second pull-up control module 60, a second pull-up module 70, a third pull-down control module 80A, a fourth pull-down control module 80B, a second pull-down module 90, a second pull-down maintenance module 55, a third node Q (2 c), a fourth node Qb (2 c), and a fifth node Qb (2c+1).

The second pull-up control module 60 is electrically connected to the stage signal output terminal (C (2C-4)) and the third node Q (2C), and is connected to the stage signal C (2C-4) of the 2C-4 th stage from the stage signal output terminal (C (2C-4)). The second pull-up control module 60 pulls up the potential of the third node Q (2C) to a first potential by using the 2C-4 th level transmission signal C (2C-4), wherein the first potential is a high point, and the second potential is a low potential.

The second pull-up module 70 is connected to the (e+1) th clock signal CK (e+1), and is electrically connected to the third node Q (2C), the stage signal output terminal (C (2C)) and the scan driving signal output terminal (G (2C)). The second pull-up module 70 is configured to output a 2C-th level transmission signal C (2C) and a 2C-th level scan driving signal G (2C) through the first potential of the third node Q (2C) under the control of the e+1th clock signal CK (e+1).

The third pull-down control module 80A is connected to the start signal STV, and is electrically connected to the third node Q (2C), the fourth node Qb (2C), the first low voltage power supply terminal, and the level signaling signal output terminal (C (2c+4)), and is connected to the first low voltage power supply terminal to the first low voltage power Vss1 and the level signaling signal output terminal (C (2c+4)) to the 2c+4 level signaling signal C (2c+4), and the third pull-down control module 80A pulls down the potential of the third node Q (2C) to the second potential by using the start signal STV and by using the 2c+4 level signaling signal C (2c+4).

The third pull-down control module 80A and the second pull-down module 90 are connected to the fifth node Qb (2c+1), and the fifth node Qb (2c+1) is electrically connected to the second node Qb (2 c-1), and when the second node Qb (2 c-1) is at the first potential, the potential of the fifth node Qb (2c+1) is also at the first potential, so as to control the second pull-down module 90 to output the 2 x-stage first-level signal with the second potential and stop outputting the scan driving signal.

If the circuit shown in fig. 4 is a circuit connection configuration diagram of the scan driving units GDL5 to GDL1078, the third pull-down control module 80A of the second GDL circuit 100B is connected to the start signal STV. If the circuit shown in fig. 4 is a circuit connection structure diagram of the scan driving unit GDL1079, the third pull-down control module 80A of the second GDL circuit 100B is electrically connected to the virtual stage signal output terminal and is connected to the stage signal of the second virtual GDL circuit of the virtual scan driving unit GDL 1. If the circuit shown in fig. 4 is a circuit connection structure diagram of the scan driving unit GDL1080, the third pull-down control module 80A of the second GDL circuit 100B is electrically connected to the virtual stage signal output terminal and is connected to the stage signal of the second virtual GDL circuit of the virtual scan driving unit GDL 2.

The fourth pull-down control module 80B is connected to the power high voltage VDD, and is electrically connected to the third node Q (2 c) and the fourth node Qb (2 c). The fourth pull-down control module 80B pulls up the potential of the fourth node Qb (2 c) to the first potential using the low level of the third node Q (2 c) and the power high voltage VDD.

The second pull-down module 90 is electrically connected to the fourth node Qb (2C), the stage signal output terminal (C (2C)), the scan driving signal output terminal (G (2C)), the first low voltage power supply terminal and the second low voltage power supply terminal, and is connected to the first low voltage power supply terminal for accessing the first low voltage power level Vss1 and the second low voltage power supply terminal for accessing the second low voltage power level Vss2. The second pull-down module 90 outputs the 2C-th level hierarchical signal C (2C) using the first potential of the fourth node Qb (2C), and outputs the 2C-th level scan driving signal G (2C) using the first potential of the fourth node Qb (2C).

The second pull-down maintaining module 55 is electrically connected to the third node Q (2C), the fourth node Qb (2C), the level signal output terminal (C (2C-5)) and the first low voltage power supply terminal, and is connected to the first low voltage power supply terminal for accessing the first low voltage power Vss1 and the level signal output terminal (C (2C-5)) for accessing the level signal C (2C-5). The third node Q (2C) and fourth node Qb (2C) levels are maintained with the 2C-5 th level of the hierarchical signal C (2C-5). The second pull-down maintaining module 55 is configured to pull down the potential of the fourth node Qb (2 c) to the second potential when the third node Q (2 c) is at the first potential.

In this embodiment, the 2C-4 th and 2c+4 th level transmission signals C (2C-4) and C (2c+4) are first level transmission signals. The second virtual GDL circuit's signaling signal is a second signaling signal.

The second GDL circuit 100B effectively ensures the stability of the voltages of the third node Q (2 c) and the fourth node Qb (2 c) through the cooperation of the foregoing functional modules, and ensures accurate output of the first-stage transmission signal and the scan driving signal.

In an exemplary embodiment, when the first node Q (2 c-1) is at a first potential, the first pull-down maintaining module 50 pulls down the potential of the second node Qb (2 c-1) to a second potential, the first pull-down module 40 stops outputting the first pumping signal and the scan driving signal, and when the third node Q (2 c) is at the first potential, the first pull-down maintaining module 50 controls the second node Qb (2 c-1) to stop receiving the power supply voltage, and the first pull-down module 40 stops outputting the first pumping signal and the scan driving signal. When the first node Q (2 c-1) is at the first potential, the second pull-down maintaining module 55 controls the fourth node Qb (2 c) to stop receiving the power voltage, the second pull-down module 90 stops outputting the first-level transmission signal and the scan driving signal, and when the third node Q (2 c) is at the first potential, the second pull-down maintaining module 55 pulls down the potential of the fourth node Qb (2 c) to the second potential, and the second pull-down module 90 stops outputting the first-level transmission signal and the scan driving signal.

In this embodiment, the first pull-down maintaining module 50 in the first GDL circuit 100A and the second pull-down maintaining module 55 in the second GDL circuit 100B can accurately maintain the output of the first-stage transmission signal and the scan driving signal stopped in the current scan driving unit by accessing the first-stage transmission signal provided by the corresponding cascaded GDL circuit, thereby improving the accuracy of the output timing of the scan driving signal of each scan driving unit.

The second pull-up control module 60 includes a sixty-one transistor T61. The gate and source of the sixty-first transistor T61 are electrically connected to the stage signaling output terminal (C (2C-4)) and connected to the stage signaling C (2C-4) of the 2C-4 th stage, and the drain is electrically connected to the third node Q (2C).

The second pull-up module 70 includes a seventy-first transistor T71 and a seventy-second transistor T72. The source of the seventy-first transistor T71 is connected to the (e+1) th clock signal CK (e+1), the gate is electrically connected to the third node Q (2C), and the drain is electrically connected to the stage signal output terminal (C (2C)). The source electrode of the seventy-second transistor T72 is connected to the (e+1) th clock signal CK (e+1), the gate electrode is electrically connected to the third node Q (2C), and the drain electrode is electrically connected to the stage signal output end (C (2C)).

The third pull-down control module 80A includes an eighty-one transistor T81, an eighth twelve transistor T82, an eighty-three transistor T83, and an eighty-four transistor T84. The eighth transistor T81 has a gate connected to the start signal STV, a source electrically connected to the third node Q (2 c), a drain electrically connected to the first low voltage power supply terminal, and a first low voltage potential Vss1 connected from the first low voltage power supply terminal. The eighth transistor T82 has a gate electrically connected to the fourth node Qb (2 c), a source electrically connected to the third node Q (2 c), and a drain electrically connected to the first low voltage power supply terminal, and is connected to the first low voltage potential Vss1 from the first low voltage power supply terminal. The eighth transistor T83 has a gate electrically connected to the level signal output terminal (C (2c+4)) and an access to the 2c+4 level signal C (2c+4), a source electrically connected to the third node Q (2C), a drain electrically connected to the first low voltage power supply terminal, and an access to the first low voltage power supply Vss1 from the first low voltage power supply terminal. The eighth transistor T84 has a gate electrically connected to the fifth node Qb (2c+1), a source electrically connected to the third node Q (2 c), a drain electrically connected to the first low voltage power supply terminal, and a first low voltage potential Vss1 connected from the first low voltage power supply terminal.

In this embodiment, the first pull-down control module 30A and the third pull-down control module 80A in the 9 th-2 n stage GDL circuit respectively include four pull-down control transistors and are connected to a Reset signal Reset, and when the first pull-down module 20 or the second pull-down module 70 is abnormal, each pull-down control transistor in the first pull-down control module 30A and the third pull-down control module 80A can accurately control the stop output of the first stage transmission signal and the scan driving signal according to the Reset signal Reset. Meanwhile, the resistance-capacitance load (RC loading) of each stage of GDL circuit is similar, so that the electronic elements such as transistors in each GDL circuit in the 2n stages of GDL circuits are the same, and the integrity and the working stability are better.

For ease of understanding and explanation, the eighty-one transistor may be defined as a fifth pull-down control transistor, the eighth twelve transistor may be defined as a sixth pull-down control transistor, the eighty-three transistor may be defined as a seventh pull-down control transistor, and the eighty-four transistor may be defined as an eighth pull-down control transistor.

If the circuit shown in fig. 4 is a circuit connection configuration diagram of the scan driving units GDL5 to GDL1078, the gate of the eighteenth transistor T81 of the second GDL circuit 100B is connected to the start signal STV. If the circuit shown in fig. 4 is a circuit connection structure diagram of the scan driving unit GDL1079, a gate of the eighteenth transistor T81 of the second GDL circuit 100B is electrically connected to the virtual stage signal output terminal, and is connected to the stage signal of the second virtual GDL circuit of the virtual scan driving unit GDL 1. If the circuit shown in fig. 4 is a circuit connection structure diagram of the scan driving unit GDL1080, a gate of the eighteenth transistor T81 of the second GDL circuit 100B is electrically connected to the virtual stage signal output terminal, and is connected to the stage signal of the second virtual GDL circuit of the virtual scan driving unit GDL 2.

The fourth pull-down control module 80B includes an eighty-five transistor T85, an eighty-six transistor T86, and an eighty-seven transistor T87. The source and gate of the eighty-fifth transistor T85 are connected to the power supply voltage VDD, and the drain is electrically connected to the gate of the eighty-sixth transistor T86 and the source of the eighty-seventh transistor T87. The eighth transistor T86 has a source connected to the power voltage VDD, and a drain electrically connected to the fourth node Qb (2 c). The eighth seventh transistor T87 has a gate electrically connected to the third node Q (2 c), a drain electrically connected to the first low voltage power supply terminal, and a first low voltage potential Vss1 connected from the first low voltage power supply terminal.

The second pull-down module 90 includes a ninety-one transistor T91, a ninety-two transistor T92, a ninety-three transistor T93, and a ninety-four transistor T94. The ninety-first transistor T91 has a gate electrically connected to the fourth node Qb (2C), a source electrically connected to the level signaling output terminal (C (2C)), and a drain electrically connected to the first low voltage power terminal, and is connected to the first low voltage potential Vss1 from the first low voltage power terminal. The gate of the ninety transistor T92 is electrically connected to the fourth node Qb (2 c), the source outputs the 2 c-stage scan driving signal G (2 c), and the drain is connected to the second voltage Vss2. The ninety three transistor T93 has a gate electrically connected to the fifth node Qb (2c+1), a source electrically connected to the scan driving signal output terminal (G (2 c)), and a drain electrically connected to the second low voltage power terminal, and is connected to the second low voltage potential Vss2 from the second low voltage power terminal. The ninety-fourth transistor T94 has a gate electrically connected to the fifth node Qb (2c+1), a source electrically connected to the stage signal output terminal (C (2C)), and a drain electrically connected to the second low voltage power terminal, and is connected to the second low voltage potential Vss2 from the second low voltage power terminal.

The second pull-down maintenance module 55 includes a ninety-fifth transistor T95, a ninety-sixth transistor T96, and a ninety-seventh transistor T97. The ninety-fifth transistor T95 has a gate electrically connected to the third node Q (2 c), a source electrically connected to the fourth node Qb (2 c), and a drain electrically connected to the first low voltage power supply terminal, and is connected to the first low voltage potential Vss1 from the first low voltage power supply terminal. The ninety-sixth transistor T96 has a gate electrically connected to the stage signal output terminal (C (2C-5)) and an access to the stage signal C (2C-5) of the 2C-5 stage, a drain electrically connected to the first low voltage power supply terminal, and an access to the first low voltage potential Vss1 from the first low voltage power supply terminal, and a source electrically connected to the fourth node Qb (2C). The ninety-seventh transistor T97 has a gate electrically connected to the first node Q (2 c-1), a source electrically connected to the drain of the eighty-fifth transistor T85, and a drain electrically connected to the first low voltage power supply terminal, and is connected to the first low voltage potential Vss1 from the first low voltage power supply terminal.

Referring to fig. 5, fig. 5 is a circuit configuration diagram of any one of the scan driving units GDL1 to GDL4 shown in fig. 3. Taking the scan driving unit GDLi as an example, i=1, 2,3,4. The first GDL circuit 100A of the scan driving unit GDLi is different from the first GDL circuit 100A of the scan driving unit GDLc in that: the thirty-first transistor T31 and the non-access start signal STV are not designed in the first pull-down control module 30A of the first GDL circuit 100A of the scan driving unit GDLi. The second GDL circuit 100B of the scan driving unit GDLi is different from the second GDL circuit 100B of the scan driving unit GDLc in that: the eighty-one transistor T81 and the non-access start signal STV are not designed in the second pull-down control module 80A of the second GDL circuit 100B of the scan driving unit GDLi. In this embodiment, i.e. in the 1 st to 8 th stage GDL circuits, the first pull-down control module 30A and the third pull-down control module 80A respectively include three pull-down control transistors, and the resistance-capacitance loads (RC loading) of the 1 st to 8 th stage GDL circuits are similar, so that the 1 st to 8 th stage GDL circuits have better working stability.

Specifically, in the embodiment of the present application, the first pull-up control module 10 in the scan driving units GDL1 to GDL4 is connected to the start signal STV, and is configured to pull up the potential of the first node Q (2 i-1) to the first potential, and when the first node Q (2 i-1) is at the first potential, the first pull-up module 20 outputs a hierarchical signal having the first potential. That is, the gate and source of the eleventh transistor T11 in the scan driving units GDL1 to GDL4 are connected to the start signal STV. The first pull-down maintaining module 50 in the scan driving units GDL1 and GDL2 is connected to the start signal STV, the scan driving units GDL3 and GDL4 are electrically connected to the level transmission signal output terminal (C (2 i-5)) and connected to the level transmission signal C (2 i-5) of the level 2i-5, that is, the gates of the fifty-th transistor T52 in the scan driving units GDL1 and GDL2 are connected to the start signal STV, the gates of the fifty-th transistor T52 in the scan driving units GDL3 and GDL4 are electrically connected to the level transmission signal output terminal (C (2 i-5)) and connected to the level transmission signal C (2 i-5) of the level 2 i-5.

In this embodiment, the 2i-1 st level transmission signal C (2 i-1) and the 2 i-th level transmission signal C (2 i) are first level transmission signals.

The second pull-up control module 60 in the scan driving units GDL1 to GDL4 is connected to a start signal STV for pulling up the potential of the third node Q (2 i) to the first potential, and when the potential of the third node Q (2 i) is the first potential, the second pull-up module 70 outputs a gradation signal having the first potential. That is, the gate and source of the sixty-one transistor T61 in the scan driving units GDL1 to GDL4 are connected to the start signal STV. The second pull-down maintenance module 55 in the scan driving units GDL1 and GDL2 is connected to the start signal STV, the scan driving units GDL3 and GDL4 are connected to the second pull-down maintenance module 55 level signaling output terminal (C (2 i-5)), and connected to the 2i-5 level signaling signal C (2 i-5), that is, the gate of the ninety-six transistor T96 in the scan driving units GDL1 and GDL2 is connected to the start signal STV, the gate of the ninety-six transistor T96 in the scan driving units GDL3 and GDL4 is connected to the level signaling signal output terminal (C (2 i-5)), and the 2i-5 level signaling signal C (2 i-5).

The first pull-up control module 10 and the second pull-up control module 60 directly access the start signal, so that the electric potential of the first node Q (2 i-1) and the third node Q (2 i) can be accurately pulled up to the first electric potential, and the first pull-up control module 20 and the second pull-up control module 70 can be accurately and rapidly controlled to output the corresponding first level transmission signal and the scanning driving signal.

Referring to fig. 6, fig. 6 is a circuit diagram of any one of the virtual scan driving units GDL1 and GDL2 shown in fig. 3.

Each virtual scanning driving unit comprises two virtual GDL circuits, four virtual GDL circuits are sequentially arranged, the four virtual GDL circuits are respectively connected with the two GDL circuits in the nth stage scanning driving unit and the two GDL circuits in the n-1 th stage scanning driving unit, and respectively output the second-stage transmission signals to the two GDL circuits in the nth stage scanning driving unit and the two GDL circuits in the n-1 th stage scanning driving unit so as to drive the two GDL circuits in the nth stage scanning driving unit and the two GDL circuits in the n-1 th stage scanning driving unit to stop outputting the scanning driving signals.

The dummy scan driving units GDL1 to GDL2 also include a first dummy GDL circuit 200A and a second dummy GLD circuit 200B, respectively.

The first virtual GDL circuit 200A includes a first virtual pull-up control module 210, a first virtual pull-up module 220, a first virtual pull-down control module 230A, a second virtual pull-down control module 230B, a first virtual pull-down module 240, a first virtual pull-down maintenance module 250, a first virtual node P (2 j-1), and a second virtual node Pb (2 j-1).

The first virtual pull-up control module 210, the first virtual pull-up module 220, and the first virtual pull-down control module 230A are electrically connected to the first virtual node P (2 j-1).

The first virtual pull-up control module 210 is configured to pull up the potential of the first virtual node P (2 j-1) to a first potential, and when the potential of the first virtual node P (2 j-1) is the first potential, the first virtual pull-up module 220 outputs the second level transmission signal having the first potential, where the second level transmission signal is used to control one of the nth and nth-1 level scan driving units, and the GDL circuit outputs the first level transmission signal having the second potential and stops outputting the scan driving signal.

The first virtual pull-down control module 230A is configured to pull down the potential of the first virtual node P (2 j-1) to a second potential.

The second virtual pull-down control module 230B and the first virtual pull-down module 240 are electrically connected to the second virtual node Pb (2 j-1), and the second virtual pull-down control module 230B is configured to pull up the potential of the second virtual node Pb (2 j-1) to a first potential, and when the potential of the second virtual node Pb (2 j-1) is the first potential, the first virtual pull-down module 240 outputs the second level transmission signal having the second potential.

The second virtual GDL circuit 200B includes a second virtual pull-up control module 260, a second virtual pull-up module 270, a third virtual pull-down control module 280A, a fourth virtual pull-down control module 280B, a second virtual pull-down module 290, a second virtual pull-down maintenance module 255, a third virtual node P (2 j), a fourth virtual node Pb (2 j), and a fifth virtual node Pb (2j+1), and the first virtual pull-down module 240 is electrically connected to the fourth virtual node Pb (2 j).

The second virtual pull-up control module 260, the second virtual pull-up module 270, and the third virtual pull-down control module 280A are electrically connected to the third virtual node P (2 j).

The second virtual pull-up control module 260 is configured to pull up the potential of the third virtual node P (2 j) to a first potential, and when the potential of the third virtual node P (2 j) is the first potential, the second virtual pull-up module 270 outputs a second level transmission signal having the first potential, where the second level transmission signal is used to control one of the GDL circuit in the nth level scan driving unit and the n-1 th level scan driving unit to output the first level transmission signal having the second potential and stop outputting the scan driving signal.

The second virtual pull-down control module 290 is configured to pull down the potential of the third virtual node P (2 j) to a second potential.

The fourth virtual pull-down control module 280B and the second virtual pull-down module 290 are electrically connected to the fourth virtual node Pb (2 j), and the fourth virtual pull-down control module 280B is configured to pull up the potential of the fourth virtual node Pb (2 j) to the first potential, and when the potential of the fourth virtual node Pb (2 j) is the first potential, the second virtual pull-down module 290 outputs the second level transmission signal having the second potential.

The first virtual pull-down maintaining module 250 is electrically connected to the first virtual node P (2 j-1), the second virtual node Pb (2 j-1) and the third virtual node P (2 j), when the potential of the first virtual node P (2 j-1) is a first potential, the first virtual pull-down maintaining module 250 pulls down the potential of the second virtual node Pb (2 j-1) to a second potential, the first virtual pull-down module 240 stops outputting the second level transmission signal, and when the potential of the third virtual node P (2 j) is a first potential, the first virtual pull-down maintaining module 250 controls the second virtual node Pb (2 j-1) to stop receiving the power voltage, and the first virtual pull-down module 240 stops outputting the second level transmission signal.

The second virtual pull-down maintaining module 290 is electrically connected to the first virtual node P (2 j-1), the third virtual node P (2 j) and the fourth virtual node Pb (2 j), when the potential of the first virtual node P (2 j-1) is the first potential, the second virtual pull-down maintaining module 255 controls the fourth virtual node Pb (2 j) to stop receiving the power voltage, the second virtual pull-down module 290 stops outputting the second level transmission signal, and when the potential of the third virtual node P (2 j) is the first potential, the second virtual pull-down maintaining module 255 pulls down the fourth virtual node Pb (2 j) to the second potential, and the second virtual pull-down module 290 stops outputting the second level transmission signal.

The third virtual pull-down control module 280A and the second virtual pull-down module 290 are connected to the fifth virtual node Pb (2j+1), and the fifth virtual node Pb (2j+1) is electrically connected to the second virtual node Pb (2 j-1), and when the second virtual node Pb (2 j-1) is at the first potential, the potential of the fifth virtual node Pb (2j+1) is also at the first potential, so as to control the second virtual pull-down module 290 to output the second level transmission signal with the second potential.

In this embodiment, the two virtual GDL circuits effectively ensure the stability of the voltages of the first virtual node P (2 j-1) and the second virtual node Pb (2 j-1) by matching the foregoing functional modules, and ensure the accurate output of the second level transmission signal.

In this embodiment, the first virtual pull-down maintaining module 250 in the first virtual GDL circuit 200A and the second virtual pull-down maintaining module 255 in the second virtual GDL circuit 200B can accurately maintain the output of the stopped second-stage signaling in the current virtual scan driving unit by accessing the first-stage signaling provided by the corresponding cascaded GDL circuit, thereby improving the accuracy of the second-stage signaling output timing of each virtual scan driving unit.

Specifically, the first dummy GDL circuit 200A of the dummy scan driving unit GDL1 outputs the first dummy pass signal Ca (1) and the first dummy scan driving signal Ga (1), the second dummy GDL circuit 200B of the dummy scan driving unit GDL1 outputs the first dummy pass signal Ca (2) and the first dummy scan driving signal Ga (2), the first dummy GDL circuit 200A of the dummy scan driving unit GDL2 outputs the third dummy pass signal Ca (3) and the third dummy scan driving signal Ga (3), and the second dummy GDL circuit 200A of the dummy scan driving unit GDL2 outputs the fourth dummy pass signal Ca (1) and the fourth dummy scan driving signal Ga (1).

In this embodiment, the first virtual signaling Ca (1) to the fourth virtual signaling Ca (4) are the second signaling.

The first virtual GDL circuit 200A has the same structure as the first GDL circuit 100A, and the second virtual GDL circuit 200B has the same structure as the second GDL circuit 100B. That is, the circuit structure of the first virtual pull-up control module 210 is the same as that of the first pull-up control module 10, the circuit structure of the first virtual pull-up module 220 is the same as that of the first pull-up module 20, the circuit structure of the first virtual pull-down control module 230A is the same as that of the first pull-down control module 30A, the circuit structure of the second virtual pull-down control module 230B is the same as that of the second pull-down control module 30B, the circuit structure of the first virtual pull-down module 240 is the same as that of the first pull-down module 40, and the circuit structure of the first virtual pull-down maintaining module 250 is the same as that of the first pull-down maintaining module 50.

The second virtual pull-up control module 260 has the same circuit structure as the second pull-up control module 60, the second virtual pull-up module 270 has the same circuit structure as the second pull-up module 70, the third virtual pull-down control module 280A has the same circuit structure as the third pull-down control module 80A, the fourth virtual pull-down control module 280B has the same circuit structure as the fourth pull-down control module 80B, the second virtual pull-down module 290 has the same circuit structure as the second pull-down module 90, and the second virtual pull-down maintenance module 255 has the same circuit structure as the second pull-down maintenance module 55.

Since the first GDL circuit 100A and the second GDL circuit 100B have been described in detail above, they are not described in detail herein.

The virtual scan driving unit GDL is different from the scan driving unit GDL in that: the first pull-down control block 230A of the first dummy GDL circuit 200A of the dummy scan driving units GDL1 to GDL2 is not connected with the gradation signal, and is connected with the Reset signal Reset. The first virtual pull-down control module 280A of the virtual scan driving units GDL1 to GDL2 is not connected with the hierarchical signal, and is connected with the Reset signal Reset.

Specifically, in the embodiment of the present application, the gate of the thirty-first transistor T31 of the first virtual GDL circuit 200A of the virtual scan driving units GDL1 to GDL2 is connected to the Reset signal Reset, and the gate of the thirty-third transistor T33 is connected to the start signal STV. The gate of the eighteenth transistor T81 of the second dummy GDL circuit 200B of the dummy scan driving units GDL1 to GDL2 is connected to the Reset signal Reset, and the gate of the eighteenth transistor T83 is connected to the start signal STV.

The gate of the eleventh transistor T11 of the first virtual GDL circuit 200A of the virtual scan driving unit GDL1 is electrically connected to the stage signal output terminal (C (2157)), and is connected to the stage signal C (2157)), the gate of the sixty-first transistor T61 of the second virtual GDL circuit 200B of the virtual scan driving unit GDL1 is electrically connected to the stage signal output terminal (C (2158)), and is connected to the stage signal C (2158)), the gate of the eleventh transistor T11 of the first virtual GDL circuit 200A of the virtual scan driving unit GDL2 is electrically connected to the stage signal output terminal (C (2159)), and is connected to the stage signal C (2159), and the gate of the second virtual GDL circuit 200B of the virtual scan driving unit GDL2 is electrically connected to the stage signal output terminal (C (2160)), and is connected to the stage signal C (2160).

The gate of the fifty-th transistor T52 of the first virtual GDL circuit 200A of the virtual scan driving unit GDL1 is electrically connected to the level signal output terminal (C (2157)), and is connected to the 2157 th level signal C (2157), the gate of the nineteenth transistor T96 of the second virtual GDL circuit 200B of the virtual scan driving unit GDL1 is electrically connected to the level signal output terminal (C (2157)), and is connected to the 2157 th level signal C (2157), the gate of the fifty-th transistor T52 of the first virtual GDL circuit 200A of the virtual scan driving unit GDL2 is electrically connected to the level signal output terminal (C (2159)), and is connected to the 2159 th level signal C (2159), and the gate of the nineteenth transistor T96 of the second virtual GDL circuit 200B of the virtual scan driving unit GDL2 is electrically connected to the level signal output terminal (C (2157)), and is connected to the 2159 th level signal C (9).

Referring to fig. 7 and 8 together, fig. 7 is a schematic layout diagram of the scan driving units GDL1 to GDL4 shown in fig. 5, and fig. 8 is a circuit layout diagram of the scan driving units GDL1 to GDL4 shown in fig. 5.

As shown in fig. 7 and 8, the first GDL circuit 100A and the second GDL circuit 100B of the scan driving unit GDL1 to the first GDL circuit 100A and the second GDL circuit 100B of the scan driving unit GDL4 respectively correspond to the access clock signals CK (1) to CK (8), so that the first GDL circuit 100A of the scan driving unit GDL1 directly corresponds to the first clock signal CK (1), and the matching degree with the timing control circuit 101 is better.

The first and

second GDL circuits

100A and 100B of the scan driving unit GDL1 to the first and

second GDL circuits

100A and 100B of the scan driving unit GDL4 are each connected to the first and second voltage potentials Vss1 and Vss2. Two parts of the first GDL circuit 100A and the second GDL circuit 100B of the scan driving unit GDL1 and the first GDL circuit 100A and the second GDL circuit 100B of the scan driving unit GDL2 are connected to the start signal STV, and only one part of the first GDL circuit 100A and the second GDL circuit 100B of the scan driving unit GDL3 and the first GDL circuit 100A and the second GDL circuit 100B of the scan driving unit GDL4 is connected to the start signal STV, because the circuits of the scan driving unit GDL3 and the GDL4 are pulled down by the gradation signals of the scan driving unit GDL1 and the GDL 2.

Referring to fig. 9 and 10 together, fig. 9 is a schematic diagram of a layout structure of any four scan driving units of the scan driving units GDL5 to GDL1080 shown in fig. 4, and fig. 10 is a circuit layout diagram of any four scan driving units of the scan driving units GDL5 to GDL1080 shown in fig. 4.

As shown in fig. 9 and 10, the 8k+1-th stage GDL circuit to the 8k+8-th stage GDL circuit are respectively connected to the clock signals CK (1) to CK (8), for example, the 8k+1-th stage GDL circuit is connected to the first clock signal CK (1), and the 8k+5-th stage GDL circuit is connected to the fifth clock signal CK (5).

The 8k+1th stage GDL circuit to 8k+8th stage GDL are connected to the first voltage level Vss1, the second voltage level Vss2 and the start signal STV. The 8k+1-th stage GDL circuit outputs the 8k+1-th stage transfer signal C (8k+1) and the 8k+1-th stage scan drive signal G (8k+1), the 8k+2-th stage GDL circuit outputs the 8k+2-th stage transfer signal C (8k+2) and the 8k+2-th stage scan drive signal G (8k+2), … …, and the 8k+8-th stage GDL circuit outputs the 8k+8-th stage transfer signal C (8k+1) and the 8k+8-th stage scan drive signal G (8k+1).

Referring to fig. 11 and 12 together, fig. 11 is a schematic layout diagram of the virtual scan driving units GDL1 and GDL2 shown in fig. 6, and fig. 12 is a circuit layout diagram of the virtual scan driving units GDL1 and GDL2 shown in fig. 6.

As shown in fig. 11 and 12, the first to fourth stage virtual GDL circuits respectively correspond to the access clock signals CK (1) to CK (4), and each of the first to fourth stage virtual GDL circuits accesses the first low voltage potential Vss1, the second low voltage potential Vss2, the start signal STV, and the Reset signal Reset. The first stage virtual GDL circuit outputs a first virtual hierarchical signal Ca (1) and a first virtual stage scan drive signal Ga (1), … …, and the fourth stage virtual GDL circuit outputs a fourth virtual hierarchical signal Ca (4) and a fourth virtual stage scan drive signal Ga (4).

Referring to fig. 13, fig. 13 is a timing chart showing a circuit one-frame image display process of any one of the scan driving units GDL1 to GDL 1080. As shown in FIG. 13, C (2 n-5) is the level-pass signal C (2 n-5) of the 2n-5 th stage GDL circuit, C (2 n-4) is the level-pass signal C (2 n-4) of the 2n-4 th stage GDL circuit, and STV is the start signal. Q (2 n-1) is the first node Q (2 n-1) of the first GDL circuit of the scan driving unit GDLn, and Q (2 n) is the third node Q (2 n) of the second GDL circuit of the scan driving unit GDLn. G (2 n-1) is a 2n-1 th stage scan driving signal G (2 n-1) outputted from the first GDL circuit of the scan driving unit GDLn, and G (2 n) is a 2 n-th stage scan driving signal G (2 n) outputted from the second GDL circuit of the scan driving unit GDLn.

In the scan driving unit GDL1, the potential of the first node Q (1) is pulled up by the start signal STV, the first stage scan driving signal G (1) is output under the control of the clock signal CK (e), and the potential of the third node Q (2) is pulled up by the start signal STV, the first stage scan driving signal G (2) is output under the control of the clock signal CK (e).

In the scan driving unit GDL2, the potential of the first node Q (3) is pulled up by the start signal STV, the third stage scan driving signal G (3) is output under the control of the clock signal CK (e), the potential of the third node Q (4) is pulled up by the start signal STV, and the fourth stage scan driving signal G (4) is output under the control of the clock signal CK (e).

In any one of the scan driving units GDL3 to GDL1080, the potential of the first node Q (2 n-1) is pulled up by the 2n-5 th-stage hierarchical signal C (2 n-5), and the 2n-1 th-stage scan driving signal G (2 n-1) is outputted under the control of the clock signal CK (e). The potential of the third node Q (2 n) is pulled up by the 2n-4 th-stage transfer signal C (2 n-4), and the 2 n-th-stage scan driving signal G (2 n) is outputted under the control of the clock signal CK (e+1).

Specifically, in the present embodiment, in the scan driving units GDL1 to GDL2, when the start signal STV is at a high potential, the eleventh transistor T11 is turned on, the first node rises to a high potential, the twenty transistor T22 is turned on, and the scan driving signal is output under the control of the clock signal CK (e). When the start signal STV is at a high potential, the sixty-first transistor T61 is turned on, the third node rises to a high potential, the seventy-second transistor T72 is turned on, and the scan driving signal is outputted under the control of the clock signal CK (e). In the scan driving units GDL3 to GDL1080, when the 2n-5 th stage transmission signal C (2 n-5) is at a high potential, the eleventh transistor T11 is turned on, the first node Q (2 n-1) rises to a high potential, the twenty-second transistor T22 is turned on, and the 2n-1 th stage scan driving signal G (2 n-1) is outputted under the control of the clock signal CK (e). When the 2n-4 th level transmission signal C (2 n-4) is at a high potential, the sixty-first transistor T61 is turned on, the third node Q (2 n) rises to be at a high potential, the seventy-second transistor T72 is turned on, and the 2n-1 st level scanning driving signal G (2 n-1) is output under the control of the clock signal CK (e+1).

In summary, in the embodiment of the present application, the scan driving circuit 103 includes the scan driving module 100 and the virtual scan driving module 200, and the start signal STV is connected to the first pull-down control module 30A and the second pull-down control module 80A in the scan driving units GDL1 to GDL8 in the scan driving module 100, so that the scan driving circuit 103 can normally drive.

Further, in the 1 st to 8 th stage GDL circuits, that is, the first pull-down control module 30A of the 2i-1 st stage GDL circuit, the thirty-first transistor T31 is not provided, and the second pull-down control module 80A of the 2 i-th stage GDL circuit, the eighty-first transistor T81 is not provided, wherein i=1, 2,3,4. The number of transistors of each stage of the scanning driving unit GDL is ensured to be consistent, and the stability of a circuit structure can be effectively improved.

Referring to fig. 14, fig. 14 is a circuit configuration diagram of any one of the scan driving units GDL1 to GDL4 shown in fig. 3 according to the second embodiment of the present application. The difference between the embodiment of the present application and the first embodiment is that the scan driving units GDL1 to GDL4 shown in fig. 5 are: the first pull-down control module 30A of the scan driving units GDL1 to GDL4 of the second embodiment is provided with a thirty-first transistor T31 and is connected to a Reset signal Reset, and the second pull-down control module 80A of the scan driving units GDL1 to GDL4 of the second embodiment is provided with an eighty-first transistor T81 and is connected to a Reset signal Reset.

Specifically, in the embodiment of the application, the gate of the thirty-first transistor T31 of the scan driving units GDL1 to GDL4 of the second embodiment is connected to the Reset signal Reset, the source is electrically connected to the first node Q (2 i-1), the drain is electrically connected to the first low voltage power supply terminal, and the first low voltage power supply Vss1 is connected from the first low voltage power supply terminal. The eighth transistor T81 of the scan driving units GDL1 to GDL4 of the second embodiment has a gate connected to the Reset signal Reset, a source electrically connected to the third node Q (2 i), a drain electrically connected to the first low voltage power supply terminal, and a first low voltage potential Vss1 connected from the first low voltage power supply terminal.

Further, the GDL circuits or the dummy GDL circuits in each group respectively receive one clock signal, and meanwhile, the GDL circuit at the first stage can receive the first clock signal CK (1), that is, the first stage GDL circuit directly corresponds to the first clock CK (1), so that the matching degree between the scan driving circuit 103 and the timing control circuit 101 and other functional circuits adopting clock signals is better.

In this embodiment, in the 1 st to 8 th stage GDL circuits, the first pull-down control module 30A and the third pull-down control module 80A respectively include four pull-down control transistors and are connected to a Reset signal Reset, and when the first pull-down module 20 or the second pull-down module 70 is abnormal, each pull-down control transistor in the first pull-down control module 30A and the third pull-down control module 80A can accurately control the stop output of the first stage transmission signal and the scan driving signal according to the Reset signal Reset. Meanwhile, in the 9 th-2 n-stage GDL circuits, the first pull-down control module 30A and the third pull-down control module 80A also respectively include four pull-down control transistors, so that the resistance-capacitance load (RC loading) of each stage of GDL circuit is similar, and thus, the electronic elements such as the transistors in each GDL circuit in the 2 n-stage GDL circuits are the same, and the integrity and the working stability are better.

In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

It is to be understood that the application of the present application is not limited to the examples described above, but that modifications and variations can be made by a person skilled in the art from the above description, all of which modifications and variations are intended to fall within the scope of the claims appended hereto. Those skilled in the art will recognize that the methods of accomplishing all or part of the above embodiments and equivalents thereof may be employed and still fall within the scope of the present application.

Claims

1. A scan driving circuit comprises n scan driving units and two virtual scan driving units which are sequentially arranged and cascaded, wherein each scan driving unit is used for outputting two scan driving signals with preset intervals, each virtual scan driving unit is used for outputting two cascade signals with preset intervals,

The x-th stage scanning driving unit is cascaded with the x-2 th stage scanning driving unit, and the x-th stage scanning driving unit outputs two first stage transmission signals to the x-2 th stage scanning driving unit, wherein x is more than 2 and less than or equal to n;

the two virtual scanning driving units are respectively connected with the n-1 level scanning driving unit and the n level scanning driving unit, and respectively output two second level transmission signals to the n-1 level scanning driving unit and the n level scanning driving unit, wherein the first level transmission signals and the second level transmission signals are used for driving the scanning driving unit to output the scanning driving signals;

each scanning driving unit comprises a first GDL circuit and a second GDL circuit which are mutually connected, wherein the first GDL circuit and the second GDL circuit are used for outputting the scanning driving signals, the first GDL circuit comprises a first pull-up control module, a first pull-up module, a first pull-down control module, a second pull-down control module, a first pull-down maintenance module, a first node and a second node, and the second GDL circuit comprises a second pull-up control module, a second pull-up module, a third pull-down control module, a fourth pull-down control module, a second pull-down module, a third node and a fourth node; wherein,

The first pull-up control module is electrically connected with the first pull-up module and is used for pulling up the potential of the first node to a first potential according to the received 2x-5 th-level first-level transmission signal, and when the potential of the first node is the first potential, the first pull-up module outputs the 2x-1 th-level first-level transmission signal with the first potential; the first pull-down module is electrically connected with the fourth node, and the second pull-up control module, the second pull-up module and the third pull-down control module are electrically connected with the third node;

the first pull-down control module is electrically connected to the first node and the second node respectively, and is used for pulling down the potential of the first node to a second potential, and the first pull-up module stops outputting the 2x-1 level first level transmission signal with the first potential;

the second pull-down control module and the first pull-down module are electrically connected to the second node, the second pull-down control module is used for pulling up the electric potential of the second node to a first electric potential, and when the electric potential of the second node is the first electric potential, the first pull-down module outputs the 2x-1 level first level transmission signal with the second electric potential;

The first pull-down maintaining module is electrically connected to the first node, the second node and the third node, when the first node is at a first potential, the first pull-down maintaining module pulls down the potential of the second node to a second potential, and the first pull-down module stops outputting the 2x-1 level first level transmission signal with the second potential;

when the third node is at the first potential, the first pull-down maintaining module controls the second node to stop receiving the power supply voltage, the first pull-down module stops outputting the 2x-1 th level first level transmission signal and the scanning driving signal, the second pull-up module outputs the 2x level first level transmission signal with the first potential, the 2x level first level transmission signal is used for controlling a 2x-4 th level first level transmission signal of the second potential to be output by a 2x-4 th level GDL circuit in an x-2 th level scanning driving unit and stopping outputting the scanning driving signal, and controlling a 2x+4 th level first level transmission signal of the first potential to be output by a 2x+4 th level GDL circuit in an x+2 th level scanning driving unit and outputting the scanning driving signal;

the 2x-1 th stage first stage transmission signal is used for controlling a 2x-5 th stage GDL circuit in an x-2 th stage scanning driving unit to output a 2x-5 th stage first stage transmission signal of a second potential and stopping outputting the scanning driving signal, and controlling a 2x+3 th stage GDL circuit in an x+2 th stage scanning driving unit to output a 2x+3 th stage first stage transmission signal of the first potential and outputting the scanning driving signal;

The second pull-up control module is used for pulling up the potential of the third node to a first potential according to the received 2x-4 level first-level transmission signal, the third pull-down control module is used for pulling down the potential of the third node to a second potential,

the fourth pull-down control module and the second pull-down module are electrically connected to the fourth node, the fourth pull-down control module is used for pulling up the electric potential of the fourth node to a first electric potential, and when the electric potential of the fourth node is the first electric potential, the second pull-down module outputs the 2 x-stage first-level transmission signal with a second electric potential.

2. The scan driving circuit according to claim 1, wherein,

the n scan driving units and the two virtual scan driving units are divided into 4y groups, each group receives eight clock signals, each scan driving unit and each virtual scan driving unit receives two clock signals, and y is a positive integer.

3. The scan driving circuit according to any one of claims 1 to 2, wherein,

the n scan driving units comprise 2n mutually cascaded GDL circuits, wherein the x-th stage scan driving unit comprises a 2 x-th stage GDL circuit and a 2 x-1-th stage GDL circuit, the 2 x-th stage GDL circuit is cascaded with the 2 x-4-th stage GDL circuit, the 2 x-1-th stage GDL circuit is cascaded with the 2 x-5-th stage GDL circuit, the 2 x-1-th stage GDL circuit is the first GDL circuit, the 2 x-th stage GDL circuit is the second GDL circuit,

The first GDL circuit is used for receiving the 2x-5 level first level transmission signal transmitted by the 2x-5 level GDL circuit and outputting the 2x-1 level first level transmission signal and the scanning driving signal according to the 2x-5 level first level transmission signal;

the second GDL circuit is used for receiving the 2x-4 level first level transmission signal transmitted by the 2x-4 level GDL circuit and outputting the 2x level first level transmission signal and the scanning driving signal according to the 2x-4 level first level transmission signal.

4. The scan driving circuit according to claim 3, wherein,

when x is more than 4 and less than or equal to n,

the first pull-down control module is used for receiving a start signal to pull down the potential of the first node to the second potential, and the first pull-down control module is used for receiving a 2x+3rd first level transmission signal to pull down the potential of the first node to the second potential.

5. The scan driving circuit according to claim 4, wherein,

the second GDL circuit further includes a second pull-down maintaining module and a fifth node, the second pull-down maintaining module is electrically connected to the first node, the third node and the fourth node, the third pull-down control module and the second pull-down module are connected to the fifth node, and the fifth node is electrically connected to the second node,

When the first node is at a first potential, the second pull-down maintaining module controls the fourth node to stop receiving the power supply voltage, the second pull-down module stops outputting a 2 x-stage first-stage transmission signal and a scanning driving signal, and when the third node is at the first potential, the second pull-down maintaining module pulls down the potential of the fourth node to a second potential, and the second pull-down module stops outputting the 2 x-stage first-stage transmission signal and the scanning driving signal;

when the potential of the second node is the first potential, the potential of the fifth node is the first potential so as to control the second pull-down module to output the 2 x-stage first-stage transmission signal with the second potential and stop outputting the scanning driving signal.

6. The scan driving circuit according to claim 5, wherein,

when x is more than 2 and less than or equal to 4,

the first pull-down control module comprises a first pull-down control transistor, a second pull-down control transistor and a third pull-down control transistor, wherein the grid electrode of the first pull-down control transistor is electrically connected with the second node, the source electrode of the first pull-down control transistor is electrically connected with the first node, the drain electrode of the first pull-down control transistor is connected with a first low voltage power supply end and is accessed to a first low voltage potential, the grid electrode of the second pull-down control transistor is accessed to a first level transmission signal, the source electrode of the second pull-down control transistor is electrically connected with the first node, the drain electrode of the second pull-down control transistor is accessed to a first low voltage potential, the grid electrode of the third pull-down control transistor is electrically connected with the second node, the source electrode of the third pull-down control transistor is electrically connected with the first node, the drain electrode of the third pull-down control transistor is accessed to the first low voltage potential,

The third pull-down control module comprises a sixth pull-down control transistor, a seventh pull-down control transistor and an eighth pull-down control transistor, wherein a grid electrode of the sixth pull-down control transistor is electrically connected to the fourth node, a source electrode of the sixth pull-down control transistor is electrically connected to the third node, a drain electrode of the sixth pull-down control transistor is connected to a first low voltage potential, a grid electrode of the seventh pull-down control transistor is connected to a first-stage transmission signal, a source electrode of the seventh pull-down control transistor is electrically connected to the third node, a drain electrode of the seventh pull-down control transistor is connected to a first low voltage potential, a grid electrode of the eighth pull-down control transistor is electrically connected to the fifth node, a source electrode of the eighth pull-down control transistor is electrically connected to the third node, and a drain electrode of the eighth pull-down control transistor is connected to the first low voltage potential.

7. The scan driving circuit according to claim 6, wherein,

the first pull-up control module is further used for accessing a start signal, pulling up the electric potential of the first node to a first electric potential, when the first node is the first electric potential, the first pull-up module outputs a first-stage transmission signal with the first electric potential, and the second pull-up control module is further used for accessing a start signal, pulling up the electric potential of the third node to the first electric potential, and when the electric potential of the third node is the first electric potential, the second pull-up module outputs the first-stage transmission signal with the first electric potential.

8. The scan driving circuit according to claim 5, wherein,

when x is more than 2 and less than or equal to 4,

the first pull-down control module comprises a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor and a fourth pull-down control transistor, wherein the grid electrode of the first pull-down control transistor is electrically connected with the second node, the source electrode of the first pull-down control transistor is electrically connected with the first node, the drain electrode of the first pull-down control transistor is connected with a first low voltage potential, the grid electrode of the second pull-down control transistor is connected with a first primary signal, the source electrode of the second pull-down control transistor is electrically connected with the first node, the drain electrode of the second pull-down control transistor is connected with a first low voltage potential, the grid electrode of the third pull-down control transistor is electrically connected with the second node, the source electrode of the third pull-down control transistor is electrically connected with the first node, the drain electrode of the third pull-down control transistor is connected with a first low voltage potential, the grid electrode of the fourth pull-down control transistor is connected with a reset signal, the source electrode of the fourth pull-down control transistor is electrically connected with the first node, the drain electrode of the fourth pull-down control transistor is connected with the first low voltage potential,

The third pull-down control module comprises a fifth pull-down control transistor, a sixth pull-down control transistor, a seventh pull-down control transistor and an eighth pull-down control transistor, wherein a grid electrode of the fifth pull-down control transistor is connected with a reset signal, a source electrode of the fifth pull-down control transistor is electrically connected with the third node, a drain electrode of the fifth pull-down control transistor is connected with a first low voltage potential, a grid electrode of the sixth pull-down control transistor is electrically connected with the fourth node, a source electrode of the sixth pull-down control transistor is electrically connected with the third node, a drain electrode of the sixth pull-down control transistor is connected with a first low voltage potential, a grid electrode of the seventh pull-down control transistor is connected with a first-stage transmission signal, a source electrode of the seventh pull-down control transistor is electrically connected with the third node, a drain electrode of the seventh pull-down control transistor is connected with the first low voltage potential, a grid electrode of the eighth pull-down control transistor is electrically connected with the fifth node, a source electrode of the eighth pull-down control transistor is electrically connected with the third node, and a drain electrode of the eighth pull-down control transistor is electrically connected with the first low voltage potential.

9. The scan driving circuit according to claim 8, wherein,

10. The scan driving circuit according to claim 5, wherein,

when x is more than 4 and less than or equal to n,

the first pull-down control module comprises a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor and a fourth pull-down control transistor, wherein the grid electrode of the first pull-down control transistor is electrically connected with the second node, the source electrode of the first pull-down control transistor is electrically connected with the first node, the drain electrode of the first pull-down control transistor is connected with a first low voltage potential, the grid electrode of the second pull-down control transistor is connected with a first primary signal, the source electrode of the second pull-down control transistor is electrically connected with the first node, the drain electrode of the second pull-down control transistor is connected with a first low voltage potential, the grid electrode of the third pull-down control transistor is electrically connected with the second node, the source electrode of the third pull-down control transistor is electrically connected with the first node, the drain electrode of the fourth pull-down control transistor is connected with a first low voltage potential, the source electrode of the fourth pull-down control transistor is connected with a first low voltage potential,

The third pull-down control module comprises a fifth pull-down control transistor, a sixth pull-down control transistor, a seventh pull-down control transistor and an eighth pull-down control transistor, wherein a grid electrode of the fifth pull-down control transistor is connected with a starting signal, a source electrode of the fifth pull-down control transistor is electrically connected with the third node, a drain electrode of the fifth pull-down control transistor is connected with a first low voltage potential, a grid electrode of the sixth pull-down control transistor is electrically connected with the fourth node, a source electrode of the sixth pull-down control transistor is electrically connected with the third node, a drain electrode of the sixth pull-down control transistor is connected with a first low voltage potential, a grid electrode of the seventh pull-down control transistor is connected with the first level transmission signal, a drain electrode of the seventh pull-down control transistor is electrically connected with the third node, a grid electrode of the eighth pull-down control transistor is electrically connected with the fifth node, a grid electrode of the eighth pull-down control transistor is electrically connected with the third node, and a drain electrode of the eighth pull-down control transistor is electrically connected with the first low voltage potential.

11. The scan driving circuit according to claim 10, wherein,

The first pull-up control module is also used for accessing the 2x-5 th level first level transmission signal, for pulling up the potential of the first node to a first potential, when the potential of the first node is the first potential, the first pull-up module outputs the 2x-1 th level first level transmission signal with the first potential,

the second pull-up control module is further used for accessing a 2x-4 th-stage first-stage transmission signal and is used for pulling up the potential of the third node to the first potential, and when the potential of the third node is the first potential, the second pull-up control module outputs the 2 x-stage first-stage transmission signal with the first potential.

12. The scan driving circuit according to claim 4, wherein,

13. The scan driving circuit according to claim 12, wherein,

the virtual scan driving unit includes two virtual GDL circuits including a first virtual GDL circuit and a second virtual GDL circuit,

the first virtual GDL circuit includes a first virtual pull-up control module, a first virtual pull-up module, a first virtual pull-down control module, a second virtual pull-down control module, a first virtual pull-down module, a first virtual node, and a second virtual node,

the first virtual pull-up control module, the first virtual pull-up module and the first virtual pull-down control module are electrically connected to the first virtual node,

the first virtual pull-up control module is used for pulling up the potential of the first virtual node to a first potential, when the potential of the first virtual node is the first potential, the first virtual pull-up module outputs the second-stage transmission signal with the first potential, the second-stage transmission signal is used for controlling one GDL circuit in the nth-stage scanning driving unit and the n-1-stage scanning driving unit to output the first-stage transmission signal with the second potential and stop outputting the scanning driving signal,

the first virtual pull-down control module is used for pulling down the potential of the first virtual node to a second potential,

The second virtual pull-down control module is electrically connected to the second virtual node, and is used for pulling up the potential of the second virtual node to a first potential, and when the potential of the second virtual node is the first potential, the first virtual pull-down module outputs the second-level transmission signal with the second potential.

14. The scan driving circuit according to claim 13, wherein,

the second virtual GDL circuit comprises a second virtual pull-up control module, a second virtual pull-up module, a third virtual pull-down control module, a fourth virtual pull-down control module, a second virtual pull-down module, a third virtual node and a fourth virtual node, wherein the first virtual pull-down module is electrically connected with the fourth virtual node,

the second virtual pull-up control module, the second virtual pull-up module and the third virtual pull-down control module are electrically connected to the third virtual node,

the second virtual pull-up control module is used for pulling up the potential of the third virtual node to a first potential, when the potential of the third virtual node is the first potential, the second virtual pull-up module outputs a second-stage transmission signal with the first potential, the second-stage transmission signal is used for controlling one GDL circuit in an nth-stage scanning driving unit and an n-1-stage scanning driving unit to output the first-stage transmission signal with the second potential and stop outputting the scanning driving signal,

The second virtual pull-down control module is used for pulling down the potential of the third virtual node to a second potential,

the fourth virtual pull-down control module and the second virtual pull-down module are electrically connected to the fourth virtual node, the fourth virtual pull-down control module is used for pulling up the electric potential of the fourth virtual node to a first electric potential, and when the electric potential of the fourth virtual node is the first electric potential, the second virtual pull-down module outputs the second-level transmission signal with a second electric potential.

15. The scan driving circuit according to claim 14, wherein,

the first virtual GDL circuit further comprises a first virtual pull-down maintaining module, the first virtual pull-down maintaining module is electrically connected to the first virtual node, the second virtual node and the third virtual node, when the potential of the first virtual node is a first potential, the first virtual pull-down maintaining module pulls down the potential of the second virtual node to a second potential, the first virtual pull-down maintaining module stops outputting the second-level transmission signal, and when the potential of the third virtual node is a first potential, the first virtual pull-down maintaining module controls the second virtual node to stop receiving the power supply voltage, and the first virtual pull-down module stops outputting the second-level transmission signal; the second virtual GDL circuit further includes a second virtual pull-down maintaining module, the second virtual pull-down maintaining module is electrically connected to the first virtual node, the third virtual node and the fourth virtual node, when the potential of the first virtual node is a first potential, the second virtual pull-down maintaining module controls the fourth virtual node to stop receiving the power supply voltage, the second virtual pull-down module stops outputting the second level transmission signal, and when the potential of the third virtual node is a first potential, the second virtual pull-down maintaining module pulls down the fourth virtual node to a second potential, and the second virtual pull-down module stops outputting the second level transmission signal.

16. An array substrate, characterized in that the array substrate comprises 2n scan lines, a plurality of pixel units arranged in an array, and the scan driving circuit according to any one of claims 1 to 15, the 2n scan lines are respectively connected to the n scan driving units, and respectively receive 2n scan driving signals from the n scan driving units in sequence, and the plurality of pixel units receive image data and display images under the control of the 2n scan driving signals.