KR101568249B1 - Shift register - Google Patents

Abstract

The present invention relates to a shift register capable of changing the output order of stages, and more particularly, to a shift register in which a plurality of stages for sequentially outputting a scan pulse and a top dummy for setting or resetting a first stage, An upper dummy stage for outputting scan pulses; And a lower dummy stage for outputting a lower dummy scan pulse for setting or resetting a last stage positioned at the lowest one of the stages; Each stage includes a scan direction controller for selectively outputting a forward voltage and an inverse voltage having potentials opposite to each other in accordance with a scan pulse from the front stage and a scan pulse from the rear stage; A node controller for controlling signal states of first and second set nodes and first and second reset nodes according to an output signal from the scan direction controller; And an output for sequentially supplying one scan pulse to the succeeding stage in accordance with the voltages of the first and second set nodes and the first and second reset nodes and supplying another scan pulse to the preceding stage, And the like.

A shift register, a dummy stage, a node control section,

Description

SHIFT REGISTER {SHIFT REGISTER}

The present invention relates to a shift register, and more particularly to a shift register capable of changing the output order of stages.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged in an intersecting manner, and a pixel region is located in an area defined by vertically intersecting the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed on the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) as a switching element. The thin film transistor is turned on by a scan pulse applied to a gate terminal via the gate line so that a data signal of the data line is charged to the pixel voltage.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, And a power supply unit for supplying various driving voltages used in the plasma display apparatus.

The gate driver sequentially supplies scan pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. Here, the gate driver includes a shift register for sequentially outputting the scan pulses as described above.

Conventional shift registers include a plurality of stages that sequentially output scan pulses. The stages output scan pulses in the order of the stages located in one direction, that is, the most upper stage to the lowermost stage. That is, the conventional shift register outputs the scan pulse in only one direction. Accordingly, the conventional shift register shows many problems to be used in various models of liquid crystal display devices.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a shift register capable of controlling the output order of scan pulses.

According to an aspect of the present invention, there is provided a shift register including a plurality of stages for sequentially outputting scan pulses, an upper dummy scan circuit for setting or resetting a first stage located at the uppermost stage of the stages, An upper dummy stage for outputting pulses; And a lower dummy stage for outputting a lower dummy scan pulse for setting or resetting a last stage positioned at the lowest one of the stages; Each stage includes a scan direction controller for selectively outputting a forward voltage and an inverse voltage having potentials opposite to each other in accordance with a scan pulse from the front stage and a scan pulse from the rear stage; A node controller for controlling signal states of first and second set nodes and first and second reset nodes according to an output signal from the scan direction controller; And an output for sequentially supplying one scan pulse to the succeeding stage in accordance with the voltages of the first and second set nodes and the first and second reset nodes and supplying another scan pulse to the preceding stage, And the like.

The shift register according to the present invention has the following effects.

The shift register of the present invention can change the output order of the stages through the scan direction control unit. Accordingly, the shift register according to the present invention can be applied to display devices of various models.

Further, in the present invention, since the third forward switching element and the third reverse switching element complement each other's operation in the forward operation and the reverse operation, the forward driving and the reverse driving can be effectively performed without the additional switching element . Therefore, the internal area of the shift register can be reduced.

2 is a timing chart of various signals supplied to the shift register of FIG. 1 during forward driving, and FIG. 3 is a timing chart of shift signals of the shift register of FIG. 1 during reverse driving. Is a timing chart of various signals supplied to the registers.

The shift register according to the first embodiment of the present invention includes n stages and two dummy stages ST0 and STn + 1 as shown in Fig. Here, each of the stages ST1 to STn outputs two scan pulses during one frame period.

Each of the stages ST1 to STn drives the gate line connected thereto by using the scan pulse and controls the operation of the stage located at the rear stage from itself and the stage located at the preceding stage from the stage itself.

The scan pulses Vout0 to Vout2n + 1 are sequentially output to the entire stages ST0 to STn + 1 including the upper dummy stage ST0 and the lower stage dummy stage STn + 1.

At this time, the overall stages ST0 to STn + 1 are driven in the forward direction or in the reverse direction according to the signal states of the forward voltage V_F and the reverse voltage V_R.

In the forward driving, the stages ST0 to STn + 1 sequentially output scan pulses in the order of the upper dummy stage ST0 to the lower dummy stage STn + 1.

That is, the upper dummy stage ST0 outputs the upper dummy scan pulse Vout0, the first stage ST1 sequentially outputs the first and second scan pulses Vout1 and Vout2, The third stage ST2 sequentially outputs the third and fourth scan pulses Vout3 and Vout4 and then the third stage ST3 sequentially outputs the fifth and sixth scan pulses Vout5 and Vout6. And then the ninth stage STn sequentially outputs the second n-3 and the second n scan pulses Vout2n-3 and Vout2n and finally the lower stage dummy stage STn + 1 outputs the lower stage dummy scan pulse Vout2n +1).

On the other hand, during the backward driving, the stages ST0 to STn + 1 output scan pulses in order from the bottom dummy stage STn + 1 to the top dummy stage ST0.

That is, the lower dummy stage STn + 1 outputs the lower dummy scan pulse Vout2n + 1, and the n-th stage STn then outputs the second and n-1th scan pulses Vout2n and Vout2n-1 And the n-2th stage STn-1 sequentially outputs the 2n-2 th and (2n-3) th scan pulses Vout2n-2 and Vout2n-3, The first stage ST1 sequentially outputs the second and first scan pulses Vout1 and finally the upper stage dummy stage ST0 outputs the second and first scan pulses Vout1, And outputs a dummy scan pulse Vout0.

The scan pulses Vout1 to Vout2n output from the stages ST1 to STn except for the upper and lower dummy stages ST0 and STn + 1 are sequentially supplied to the gate lines of the liquid crystal panel (not shown) , The gate lines are sequentially scanned.

 Such a shift register can be incorporated in the liquid crystal panel. That is, the liquid crystal panel has a display portion for displaying an image and a non-display portion surrounding the display portion, and the shift register is embedded in the non-display portion.

As shown in FIGS. 2 and 3, the stages ST1 to STn included in the shift register constructed as described above are provided with first to fourth clock pulses CLK1 to CLK4 having a sequential phase difference with each other and circulating The first and second AC voltages Vac1 and Vac2, the forward voltage V_F, and the reverse voltage V_R, which are supplied with the clock pulse, the charging voltage, and the first and second AC voltages Vac1 and Vac2.

On the other hand, the upper and lower dummy stages ST0 and STn + 1 are connected to one of the first to fourth clock pulses CLK1 to CLK4 having a sequential phase difference with each other and a start pulse Vst, A charging voltage, a discharging voltage, a forward voltage V_F, and an inverse voltage V_R.

Wherein the charging voltage and the discharging voltage are both DC voltages, the charging voltage is positive, and the discharging voltage is negative. On the other hand, the discharge voltage may be a ground voltage.

The first and second AC voltages Vac1 and Vac2 are signals for controlling the charging and discharging of the reset nodes among the nodes of the stages ST1 to STn and the first AC voltage Vac1 and the second AC voltage Vac1, The voltage Vac2 is all an alternating voltage. The first AC voltage (Vac1) is inverted by 180 degrees with respect to the second AC voltage (Vac2). The voltage value of the first and second AC voltages Vac1 and Vac2 in the high state may be the same as the voltage value of the charging voltage and the low state of the first and second AC voltages Vac1 and Vac2 May be the same as the voltage value of the discharge voltage. The first and second AC voltages (Vac1, Vac2) are inverted in their p-frame periods. Here, p is a natural number.

The first to fourth clock pulses CLK1 to CLK4 are signals used to generate scan pulses of the stages ST1 to STn and each stage ST1 to STn outputs the first to fourth clock pulses CLK1 To CLK4, and outputs two scan pulses. For example, the odd-numbered stages of the stages output two scan pulses using the first and second clock pulses CLK1 and CLK2, and the odd-numbered stages of the stages output the third and fourth clock pulses (CLK3, CLK4) are used to output two scan pulses.

Although four clock pulses having different phase differences are used in the present invention, the number of clock pulses may be two or more.

The first to fourth clock pulses CLK1 to CLK4 are output with a phase difference from each other. The second clock pulse CLK2 is delayed in phase with the first clock pulse CLK1 and the third clock pulse CLK3 is delayed in phase with the second clock pulse CLK2, The fourth clock pulse CLK4 is delayed in phase with the third clock pulse CLK3 and the first clock pulse CLK1 is delayed in phase with respect to the fourth clock pulse CLK4.

The first to fourth clock pulses CLK1 to CLK4 are sequentially output, and are output while being circulated. That is, the signals are sequentially output from the first clock pulse CLK1 to the fourth clock pulse CLK4, and sequentially output from the first clock pulse CLK1 to the fourth clock pulse CLK4. Accordingly, the first clock pulse CLK1 is output in a period between the fourth clock pulse CLK4 and the second clock pulse CLK2.

Each of the clock pulses CLK1 to CLK4 is output several times during one frame period, but the start pulse Vst is output only once during one frame period. In other words, each of the clock pulses CLK1 to CLK4 exhibits a plurality of active states (high state) periodically for one frame period, but the start pulse Vst shows only one active state for one frame period. The start pulse Vst is output first from any of the clock pulses CLK1 to CLK4 in one frame period.

During forward driving, as shown in FIG. 2, the clock pulses CLK1 to CLK4 are output from the first clock pulse CLK1 to the fourth clock pulse CLK4. 3, the clock pulses CLK1 to CLK4 are sequentially output from the fourth clock pulse CLK4 to the first clock pulse CLK1.

In the present invention, the first through fourth clock pulses CLK1 through CLK4 overlapping the pulse width sections as shown in FIGS. 2 and 3 may be used.

That is, as shown in FIG. 2, the first half period of the pulse width section of the i-th clock pulse (i is a natural number of 2 or more) overlaps with the second half period of the pulse width section of the (i- And the second half of the pulse width of the i-th clock pulse overlaps with the first half of the pulse width of the (i + 1) -th clock pulse.

In addition, as shown in FIG. 3, the first half period of the pulse width section of the i-th clock pulse overlaps with the second half period of the pulse width section of the (i + 1) -th clock pulse, the second half of the pulse width of the i clock pulse overlaps with the second half of the pulse width of the (i + 1) th clock pulse.

For example, if the first to fourth clock pulses CLK1 to CLK4 each have a pulse width section corresponding to two horizontal periods (2H), as shown in FIGS. 2 and 3, The clock pulses overlap each other by a period corresponding to one horizontal period.

The length of the overlapping pulse width is not limited to the length corresponding to the 1/2 section and can be adjusted to any extent.

When the overlapped clock pulses CLK1 to CLK4 are used, the pulse widths of the scan pulses output from the stages ST1 to STn overlap each other, as shown in Figs.

During forward driving, as shown in FIG. 2, a first dummy clock pulse DCLK1 is output between the output period of the start pulse Vst and the output period of the first clock pulse CLK1. The first dummy clock pulse DCLK1 is a signal used as a scan pulse of the upper dummy stage ST0, and the first dummy clock pulse DCLK1 is output only once in one frame period. The first dummy clock pulse DCLK1 is output as a fourth clock pulse CLK4 through a clock transmission line transmitting the fourth clock pulse CLK4.

2, a second dummy clock pulse DCLK2 is generated between the output end period of the fourth clock pulse CLK4 and the output period of the start pulse Vst of the next frame period . In other words, this second dummy clock pulse DCLK2 is output just before the blanking period of one frame. This second dummy clock pulse DCLK2 is used as a scan pulse of the lower dummy stage STn + 1, and this second dummy clock pulse DCLK2 is outputted only once in one frame period. The second dummy clock pulse DCLK2 is output as a first clock pulse CLK1 through a clock transmission line for transmitting the first clock pulse CLK1.

3, when the output order of the start pulse Vst and the output period of the fourth clock pulse CLK4 are changed as the output order of the first to fourth clock pulses CLK1 to CLK4 is changed, The second dummy clock pulse DCLK2 is output. This second dummy clock pulse DCLK2 is used as a scan pulse of the lower dummy stage STn + 1, and this second dummy clock pulse DCLK2 is outputted only once in one frame period. The second dummy clock pulse DCLK2 is output as the first clock pulse CLK1 through the clock transmission line that transmits the first clock pulse CLK1 as described above.

3, when the output order of the first to fourth clock pulses CLK1 to CLK4 is changed, the output end time of the first clock pulse CLK1 and the start end time of the next frame period A first dummy clock pulse DCLK1 is output between the output periods of the pulse Vst. In other words, this first dummy clock pulse DCLK1 is output just before the blanking period of one frame. This first dummy clock pulse DCLK1 is used as a scan pulse of the lower dummy stage STn + 1, and this second dummy clock pulse DCLK2 is outputted only once in one frame period. The first dummy clock pulse DCLK1 is output as a fourth clock pulse CLK4 through a clock transmission line that transmits the fourth clock pulse CLK4, as described above.

The upper and lower dummy stages ST0 and STn + 1 shown in FIG. 1 and the stages ST1 to STn operate in response to various signals having the above-described characteristics.

In order for each stage ST1 to STn to output a scan pulse, the enable operation of each stage ST1 to STn must be preceded. The fact that the stage is enabled means that the stage is set in a state in which it can output, that is, a state in which a clock pulse supplied thereto can be outputted as a scan pulse.

During forward driving, each of the stages ST1 to STn is supplied with the scan pulse output from the first one of the two scan pulses from the stage located at the previous stage. For example, the j < th > stage is enabled in response to the scan pulse output earlier than the two scan pulses from the j-1 < th > stage.

However, in the forward driving, the first stage ST1 located at the uppermost position is enabled in response to the upper dummy scan pulse Vout0 from the upper dummy stage ST0. The upper dummy stage ST0 is enabled by receiving a start pulse Vst from the start transmission line.

On the other hand, at the time of the reverse driving, each stage ST1 to STn is supplied with the scan pulse outputted first from the two scan pulses from the stage located at the next stage from the stage itself. For example, the j < th > stage is enabled in response to the scan pulse output earlier than the two scan pulses from the (j + 1) th stage.

However, in the reverse driving, the n-th stage STn positioned at the lowermost is enabled in response to the lower dummy scan pulse Vout2n + 1 from the lower dummy stage STn + 1. The lower dummy stage STn + 1 is enabled by receiving a start pulse Vst from the start transmission line.

On the other hand, each of the stages ST1 to STn is disabled after the scan pulse is output. The stage is disabled because the stage can not output a clock pulse supplied thereto, State is reset.

During forward driving, each stage ST1 to STn is supplied with a scan pulse output from the next two scan pulses from the stage located at the subsequent stage from itself, and is disabled. For example, the j < th > stage is disabled in response to a scan pulse output later in the two scan pulses from the (j + 1) th stage.

In the forward driving, the n-th stage STn positioned at the lowermost position is disabled in response to the lower dummy scan pulse Vout2n + 1 from the lower dummy stage STn + 1. Then, the lower dummy stage STn + 1 is disabled by receiving the start pulse Vst from the start transmission line.

On the other hand, at the time of the reverse driving, each stage ST1 to STn is supplied with a scan pulse output from one of the two scan pulses from the stage located at the previous stage from the stage itself, and is disabled. For example, the j-th stage is disabled in response to a scan pulse output later in the two scan pulses from the j-1 stage.

However, in the reverse driving, the first stage ST1 located at the uppermost position is disabled in response to the upper dummy scan pulse Vout0 from the upper dummy stage ST0. The upper dummy stage STn0 is disabled by receiving the start pulse Vst from the start transmission line.

The structure of each stage ST1 to STn including the upper and lower dummy stages ST0 and STn + 1 in the shift register constructed as described above will be described in more detail as follows.

FIG. 4 is a diagram showing the configuration of the upper dummy stage ST0 provided in FIG.

The upper dummy stage ST0 has a node control unit NC, an output unit OP and a scan direction control unit SDC, as shown in Fig.

The node control unit NC includes first to third switching elements Tr1 to Tr3.

The first switching element Tr1 is controlled on / off in accordance with the signal state of the reset node QB and is connected between the set node and the discharge power supply line for transmitting the discharge voltage VSS. To this end, the gate terminal of the first switching device Tr1 is connected to the reset node, the drain terminal is connected to the set node Q, and the source terminal is connected to the discharge power supply line.

The second switching element Tr2 is turned on / off according to the charging voltage VDD from the charging power supply line, and is connected between the charging power supply line and the reset node QB. To this end, the gate terminal and the drain terminal of the second switching device Tr2 are connected to the charging power supply line, and the source terminal is connected to the reset node QB.

The third switching element Tr3 is controlled on / off in accordance with the signal state of the set node Q, and is connected between the reset node and the discharge power supply line. To this end, the gate terminal of the third switching device Tr3 is connected to the set node Q, the drain terminal is connected to the reset node QB, and the source terminal is connected to the discharge power supply line.

The output section OP includes a pull-up switching device Trpu and a pull-down switching device Trpd.

The pull-up switching device Trpu is turned on / off according to the signal state of the set node Q and is connected between any one of the clock transmission lines transmitting the clock pulses CLK1 to CLK4 and the output terminal 333 Respectively. To this end, the gate terminal of the pull-up switching element Trpu is connected to the set node Q, the drain terminal is connected to any one of the clock transmission lines, and the source terminal is connected to the output terminal 333. [ Here, the drain terminal of the pull-up switching device Trpu is connected to the fourth clock transmission line for transmitting the fourth clock pulse CLK4.

The scan direction controller SDC includes a forward switching element Tr_F and a reverse switching element Tr_R.

The forward switching element Tr_F is connected between the set power supply line and the set node Q, which are controlled on / off by a start pulse Vst from a start transmission line and transmit a forward voltage V_F. To this end, the gate terminal of the forward switching device Tr_F is connected to the start transmission line, the drain terminal is connected to the forward power supply line, and the source terminal is connected to the set node Q.

The switching element Tr_R is turned on / off according to the first scan pulse Vout1 from the first stage ST1 and is connected between the set node Q and the reverse power line for transmitting the reverse voltage V_R Respectively. To this end, the gate terminal of the reverse switching element Tr_R is connected to one of the two output terminals of the first stage ST1, the drain terminal is connected to the set node Q, and the source terminal is connected in the reverse direction And is connected to a power supply line.

Fig. 5 is a diagram showing a configuration of the lower stage dummy stage STn + 1 provided in Fig. 1. Fig.

The lower dummy stage STn + 1 has a node control unit NC, an output unit OP and a scan direction control unit SDC, as shown in Fig.

The node control unit NC includes first to third switching elements Tr1 to Tr3.

The first switching element Tr1 is controlled on / off in accordance with the signal state of the reset node QB and is connected between the set node Q and the discharge power supply line for transmitting the discharge voltage VSS. To this end, the gate terminal of the first switching device Tr1 is connected to the reset node QB, the drain terminal is connected to the set node Q, and the source terminal is connected to the discharge power supply line do.

The second switching element Tr2 is turned on / off according to the charging voltage VDD from the charging power supply line, and is connected between the charging power supply line and the reset node QB. To this end, the gate terminal and the drain terminal of the second switching device Tr2 are connected to the charging power supply line, and the source terminal is connected to the reset node QB.

The third switching element Tr3 is turned on / off according to the signal state of the set node Q, and is connected between the reset node QB and the discharge power supply line. To this end, the gate terminal of the third switching device Tr3 is connected to the set node Q, the drain terminal is connected to the reset node QB, and the source terminal is connected to the discharge power supply line.

The output section OP includes a pull-up switching device Trpu and a pull-down switching device Trpd.

The pull-up switching device Trpu is controlled on / off according to the signal state of the set node Q and is connected between the output terminal and any one of the clock transmission lines for transmitting the clock pulses CLK1 to CLK4. To this end, the gate terminal of the pull-up switching element Trpu is connected to the set node Q, the drain terminal is connected to any one of the clock transmission lines, and the source terminal is connected to the output terminal 333. [ Here, the drain terminal of the pull-up switching device Trpu is connected to the first clock transmission line for transmitting the first clock pulse CLK1.

The scan direction controller SDC includes a forward switching element Tr_F and a reverse switching element Tr_R.

The forward switching device Tr_F is controlled on / off according to one of two scan pulses from the n-th stage STn. The forward switching device Tr_F includes a forward power line for transmitting a forward voltage V_F, Respectively. To this end, the gate terminal of the forward switching device Tr_F is connected to one of the two output terminals of the n-th stage STn, the drain terminal is connected to the forward power line, (Q).

The reverse switching element Tr_R is controlled on / off according to a start pulse Vst from the start transmission line and is connected between the set node Q and a reverse power supply line for transmitting a reverse voltage V_R. To this end, the gate terminal of the reverse switching element Tr_R is connected to the start transmission line, the drain terminal is connected to the set node Q, and the source terminal is connected to the reverse power supply line.

Fig. 6 is a diagram showing the configuration of any stage provided in Fig. 1. Fig.

Each stage ST1 to STn has a node control unit, a scan direction control unit (SDC), and an output unit OP as shown in Fig.

The node control unit controls the signal states of the first set node Q1, the second set node Q2, the first reset node QB1, and the second reset node QB2.

The node control section of the k-th stage includes the first to fifteenth switching elements Tr1 to Tr15.

The first switching device Tr1 provided in the k-th stage is controlled on / off according to the signal state of the first reset node QB1 and is connected between the first set node Q1 and the discharge power supply line . To this end, the gate terminal of the first switching device Tr1 provided in the k-th stage is connected to the first reset node QB1, the drain terminal is connected to the first set node Q1, The source terminal is connected to the discharge power line.

The second switching element Tr2 provided in the k-th stage is controlled on / off in accordance with the signal state of the second reset node QB2, and the connection between the first set node Q1 and the discharge power supply line do. To this end, the gate terminal of the second switching element Tr2 provided in the k-th stage is connected to the second reset node QB2, the drain terminal is connected to the first set node Q1, Terminal is connected to the discharge power supply line.

The third switching device Tr3 provided in the k-th stage is turned on / off according to the signal state of the first set node Q1, and is connected between the first reset node QB1 and the discharge power supply line. To this end, the gate terminal of the third switching device Tr3 provided in the k-th stage is connected to the first set node Q1, the drain terminal is connected to the first reset node QB1, And the source terminal is connected to the discharge power supply line.

The fourth switching device Tr4 provided in the k-th stage is turned on / off according to the first AC voltage Vac1 from the first AC power supply line, and the first AC power supply line and the first common node CN1 . To this end, the gate terminal and the drain terminal of the fourth switching device Tr4 provided in the k-th stage are connected to the first AC power supply line, and the source terminal is connected to the first common node CN1.

The fifth switching device Tr5 provided in the k-th stage is controlled on / off in accordance with the signal state of the first common node CN1, and between the first AC power supply line and the first reset node QB1 Respectively. To this end, the gate terminal of the fifth switching device Tr5 provided in the k-th stage is connected to the first common node CN1, the drain terminal is connected to the first AC power supply line, And is connected to the first reset node QB1.

The sixth switching element Tr6 provided in the k-th stage is turned on / off according to the signal state of the first set node Q1 and is connected between the first common node CN1 and the discharge power supply line. To this end, the gate terminal of the sixth switching device Tr6 provided in the k-th stage is connected to the first set node Q1, the drain terminal is connected to the first common node CN1, The terminals are connected to a discharge power line.

The seventh switching device Tr7 provided in the k-th stage is turned on / off according to the signal state of the second set node Q2 and is connected between the first common node CN1 and the discharge power supply line. To this end, the gate terminal of the seventh switching device Tr7 provided in the k-th stage is connected to the second set node Q2, the drain terminal is connected to the first common node CN1, Terminal is connected to the discharge power supply line.

The eighth switching device Tr8 provided in the k-th stage is turned on / off according to the output from the scan direction controller SDC, and is connected between the second reset node QB2 and the discharge power supply line. To this end, the gate terminal of the eighth switching device Tr8 provided in the k-th stage is connected to the output terminal of the scan direction controller SDC, and the drain terminal thereof is connected to the second reset node QB2 , And a source terminal is connected to the discharge power supply line.

The ninth switching element Tr9 provided in the k-th stage is controlled on / off in accordance with the signal state of the first reset node QB1 and is connected between the second set node Q2 and the discharge power supply line . To this end, the gate terminal of the ninth switching device Tr9 provided in the k-th stage is connected to the first reset node QB1, the drain terminal is connected to the second set node Q2, And the source terminal is connected to the discharge power line.

The tenth switching device Tr10 provided in the k-th stage is controlled on / off in accordance with the signal state of the second reset node QB2, and the connection between the second set node Q2 and the discharge power supply line do. To this end, the gate terminal of the tenth switching element TrlO provided in the k < th > stage is connected to the second reset node QB2, the drain terminal is connected to the second set node Q2, Terminal is connected to the discharge power supply line.

The eleventh switching device Tr11 provided in the k-th stage is turned on / off according to the signal state of the second set node Q2, and is connected between the second reset node QB2 and the discharge power supply line. To this end, the gate terminal of the eleventh switching device Tr11 provided in the k-th stage is connected to the second set node Q2, the drain terminal is connected to the second reset node QB2, And the source terminal is connected to the discharge power supply line.

The twelfth switching element Tr12 provided in the k-th stage is turned on / off according to the second AC voltage Vac2 from the second AC power supply line, and the second AC power supply line and the second common node CN2 . To this end, the gate terminal and the drain terminal of the twelfth switching device Tr12 provided in the k-th stage are connected to the second AC power supply line, and the source terminal is connected to the second common node CN2.

The thirteenth switching device Tr13 provided in the k-th stage is turned on / off according to the signal state of the second common node CN2, and between the second AC power supply line and the second reset node QB2 Respectively. To this end, the gate terminal of the thirteenth switching element Tr13 provided in the k-th stage is connected to the second common node CN2, the drain terminal is connected to the second AC power supply line, Is connected to the second reset node QB2.

The fourteenth switching device Tr14 provided in the k-th stage is turned on / off according to the signal state of the second set node Q2, and is connected between the second common node CN2 and the discharge power supply line. To this end, the gate terminal of the fourteenth switching device Tr14 provided in the k-th stage is connected to the second set node Q2, the drain terminal is connected to the second common node CN2, The terminals are connected to a discharge power line.

The fifteenth switching device Tr15 provided in the k-th stage is turned on / off according to the signal state of the first set node Q1 and is connected between the second common node CN2 and the discharge power supply line. To this end, a gate terminal of the fifteenth switching device Tr15 provided in the k-th stage is connected to the first set node Q1, a drain terminal is connected to the second common node CN2, Terminal is connected to the discharge power supply line.

The scan direction controller SDC includes first to third forward switching elements Tr_F1 to Tr_F3, first to third reverse switching elements Tr_R1 to Tr_R3, and a control switching element Tr_C.

The first forward switching device Tr_F1 provided in the k-th stage is turned on / off according to the scan pulse (front-end output) output first among the scan pulses from the (k-1) And is connected between set nodes Q1. To this end, the gate terminal of the first forward switching device Tr_F1 provided in the k-th stage is connected to the first output terminal 111a of the k-th stage, and the drain terminal is connected to the forward power line , And a source terminal is connected to the first set node (Q1).

However, the gate terminal of the first forward switching element Tr_F1 provided in the first stage ST1 is connected to the output terminal of the upper dummy stage ST0.

The first reverse switching element Tr_R1 provided in the k-th stage is turned on / off according to a scan pulse (post-stage output) output later in the scan pulses from the (k + 1) ) And the reverse power line. To this end, the gate terminal of the first reverse-direction switching element Tr_R1 provided in the k-th stage is connected to the second output terminal 111b of the (k + 1) -th stage and the drain terminal is connected to the first set node Q1. And the source terminal is connected to the reverse power line.

The second forward switching device Tr_F2 provided in the k-th stage is turned on / off according to the scan pulse output from the scan pulse from the (k-1) th stage, and the second power supply line and the second set node Q2 . To this end, the gate terminal of the second forward switching device Tr_F2 provided in the k-th stage is connected to the first output terminal 111a of the (k-1) -th stage, the drain terminal is connected to the forward power line, And the source terminal is connected to the second set node Q2.

However, the gate terminal of the second forward switching element Tr_F2 provided in the first stage ST1 is connected to the output terminal of the upper dummy stage ST0.

The second switching element Tr_R2 provided in the k-th stage is turned on / off according to a scan pulse output from among the scan pulses from the (k + 1) -th stage, and the second set node Q2 and the inverse power Line. To this end, the gate terminal of the first reverse-direction switching element Tr_R1 provided in the k-th stage is connected to the second output terminal 111b of the (k + 1) -th stage and the drain terminal is connected to the second set node Q2. And the source terminal is connected to the reverse power line.

The third forward switching device Tr_F3 provided in the k-th stage is turned on / off by the scan pulse output first among the two scan pulses from the (k-1) th stage, and the third common node CN3 And are connected between the forward power lines. To this end, the gate terminal of the third forward switching device Tr_F3 is connected to the first output terminal 111a of the (k-1) -th stage, the drain terminal is connected to the third common node CN3, Terminal is connected to the forward power supply line.

The third reverse-direction switching element Tr_R3 provided in the k-th stage is turned on / off by a scan pulse output later than two scan pulses from the (k + 1) th stage, (CN3). To this end, the gate terminal of the third reverse switching device Tr_R3 is connected to the second output terminal 111b of the (k + 1) th stage, the drain terminal is connected to the reverse power supply line, And is connected to the node CN3.

The control switching element Tr_C provided in the k-th stage is controlled according to the signal state of the third common node CN3 and is connected between the first reset node QB1 and the discharge power supply line. To this end, the gate terminal of the control switching element Tr_C provided in the k-th stage is connected to the third common node CN3, the drain terminal is connected to the first reset node QB1, Terminal is connected to the discharge power supply line.

On the other hand, the gate terminal of the eighth switching device Tr8 provided in the k-th stage is connected to the third common node CN3.

The output part OP includes first and second pull-up switching elements Trpu1 and Trpu2, and first to fourth pull-down switching elements Trpd1 to Trpd4.

The first pull-up switching device Trpu1 is controlled on / off according to the signal state of the first set node Q1 and is connected to any one of the clock transmission lines for transmitting the clock pulses CLK1 to CLK4, Terminals 111a. To this end, the gate terminal of the first pull-up switching device Trpu1 is connected to the first set node Q1, the drain terminal is connected to any one of the clock transmission lines, and the source terminal is connected to the first output terminal 111a.

The second pull-up switching device Trpu2 is turned on / off according to the signal state of the second set node Q2 and is connected to any one of the clock transmission lines for transmitting the clock pulses CLK1 to CLK4, Terminals 111b. To this end, the gate terminal of the second pull-up switching device Trpu2 is connected to the second set node Q2, the drain terminal is connected to any one of the clock transmission lines, and the source terminal is connected to the second output terminal 111b.

At this time, the terminals of the first pull-up switching device Trpu1 and the second pull-up switching device Trpu2 are connected to different clock transmission lines.

The first pull-down switching element Trpd1 is turned on / off according to the signal state of the first reset node QB1, and is connected between the first output terminal 111a and the discharge power supply line. To this end, the gate terminal of the first pull-down switching device Trpd1 is connected to the first reset node QB1, the drain terminal is connected to the first output terminal 111a, Respectively.

The second pull-down switching element Trpd2 is turned on / off according to the signal state of the second reset node QB2 and is connected between the first output terminal 111a and the discharge power supply line. To this end, the gate terminal of the first pull-down switching device Trpd1 is connected to the second reset node QB2, the drain terminal is connected to the first output terminal 111a, Respectively.

The third pull-down switching device Trpd3 is on / off controlled in accordance with the signal state of the first reset node QB1, and is connected between the second output terminal 111b and the discharge power supply line. To this end, the gate terminal of the third pull-down switching device Trpd3 is connected to the first reset node QB1, the drain terminal is connected to the second output terminal 111b, Respectively.

The fourth pull-down switching device Trpd4 is turned on / off according to the signal state of the second reset node QB2, and is connected between the second output terminal 111b and the discharge power supply line. To this end, the gate terminal of the first pull-down switching device Trpd1 is connected to the second reset node QB2, the drain terminal is connected to the second output terminal 111b, Respectively.

The operation of the shift register constructed as described above will be described below.

The operation of the shift register according to the forward driving will be described with reference to FIGS. 2, 4, 5, and 6. FIG.

2, the clock pulses CLK1 to CLK4 are output in the order of the first clock pulse CLK1 to the fourth clock pulse CLK4, the forward voltage V_F is in the high state , And the reverse voltage V_R is low.

First, the operation of the first initial period Ts in the first frame period will be described as follows.

During the first frame period, the first AC voltage (Vac1) shows positive polarity and the second AC voltage (Vac2) shows negative polarity.

During the first initial period (Ts), as shown in FIG. 2, only the start pulse (Vst) output from the timing controller remains high and the remaining clock pulses remain low.

The start pulse Vst output from the timing controller is supplied to the upper dummy stage ST0 and the lower stage dummy stage STn + 1.

That is, as shown in FIG. 4, the start pulse Vst is supplied to the gate terminal of the forward switching device Tr_F provided in the upper dummy stage ST0. Accordingly, the forward switching element Tr_F is turned on, and the forward voltage V_F of the high state is supplied to the set node through the turned-on forward switching element Tr_F. Then, the set node Q is charged, and the pull-up switching device Trpu and the third switching device Tr3, which are connected to the charged set node Q through the gate terminal, are turned on.

The discharge voltage VSS is supplied to the reset node through the turned-on third switching element Tr3. On the other hand, since the second switching device Tr2 is always turned on by the charging voltage VDD, which is a DC voltage of a high state, the charging voltage VDD is supplied to the second switching device Tr2 via the second switching device Tr2. And is supplied to the reset node QB. Therefore, the high level charging voltage VDD output through the second switching element Tr2 and the low-level discharging voltage (VDD) output through the third switching element Tr3 are output to the reset node QB VSS) are supplied together. At this time, since the size of the third switching device Tr3 is set to be larger than the size of the second switching device Tr2, the reset node is set to the low-state discharging mode through the third switching device Tr3 And is discharged by the voltage VSS. Accordingly, the pull-down switching device Trpd and the first switching device Tr1 connected to the discharged reset node QB through the gate terminal are turned off.

On the other hand, since there is no output from the first stage ST1 in the first initial period Ts, the reverse switching element Tr_R provided in the upper dummy stage ST0 is in the turn-off state.

Thus, the upper dummy stage ST0 is set in the first initial period Ts. On the other hand, the lower stage dummy stage STn + 1 which receives the start pulse Vst in the first initial period Ts is reset. This will be described in more detail as follows.

That is, as shown in FIG. 5, the start pulse Vst is supplied to the gate terminal of the reverse switching element Tr_R provided in the lower dummy stage STn + 1. Accordingly, the reverse switching element Tr_R is turned on, and the reverse voltage V_R in the low state is supplied to the set node Q through the turned-on reverse switching element Tr_R. Then, the set node Q is discharged, and the pull-up switching element and the third switching element Tr3 connected to the discharged set node Q through the gate terminal are turned off.

Since the second switching device Tr2 is always in a turn-on state by the charging voltage VDD which is a DC voltage of a high state, the charging voltage VDD is supplied to the second switching device Tr2 through the second switching device Tr2, And is supplied to the node QB. Then, the reset node QB is charged, and the pull-down switching device Trpd and the first switching device Tr1 connected to the charged reset node QB through the gate terminal are turned on .

The turned-on first switching device Tr1 supplies the discharge voltage VSS to the set node Q so that the set node Q stays in a more stable discharge state. The turned-on first switching device Tr1 outputs the discharge voltage VSS and supplies it to the n-th stage STn.

Thus, the lower dummy stage STn + 1 is reset in the first initial period Ts.

Next, the operation during the second initial period T0 will be described as follows.

In the second initial period T0, only the first dummy clock pulse DCLK1 indicates the high state, and the remaining start pulse Vst and all the clock pulses remain in the low state.

The forward switching element Tr_F of the upper dummy stage ST0 changes to the turn-off state because the start pulse Vst has changed to the low state in the second initial period T0, The set node Q of the dummy stage ST0 is kept in the floating state. Therefore, the charging voltage VDD supplied to the set node Q of the upper dummy stage ST0 in the first initial period Ts is maintained in the set node Q in the second initial period T0 do.

The set node Q of the upper dummy stage ST0 is continuously held in the charged state by the charging voltage VDD applied during the first initial period Ts so that the pull-up of the upper dummy stage ST0 The switching element Trpu and the third switching element Tr3 maintain the turn-on state. At this time, as the first dummy clock pulse DCLK1 is applied to the drain terminal of the turn-on pull-up switching device Trpu, the first dummy clock pulse DCLK1 is supplied to the set node in the floating state, The voltage VDD is amplified by bootstrapping.

Therefore, the first dummy clock pulse DCLK1 applied to each drain terminal of the pull-up switching device Trpu of the upper dummy stage ST0 is stably outputted through the source terminal (output terminal). The first dummy clock pulse DCLK1 output through the pull-up switching element is the upper dummy scan pulse Vout0. The upper dummy scan pulse Vout0 is supplied to the first stage ST1 to enable the first stage ST1.

That is, the upper dummy scan pulse Vout0 output from the upper dummy stage ST0 is supplied to the first forward switching element Tr_F1, the third forward switching element Tr_F3, and the second forward switching element Tr_F2 provided in the first stage ST1, And is supplied to each gate terminal of the switching element Tr_F2.

Then, the first forward switching device Tr_F1, the third forward switching device Tr_F3 and the second forward switching device Tr_F2 are turned on and the first forward switching device Tr_F1 is turned on A high forward voltage V_F is applied to the first set node Q1. Accordingly, the first pull-up switching device Trpu1, the third switching device Tr3, and the third switching device Tr3, which are charged with the first set node Q1 and connected to the charged first set node Q1 through the gate terminal, The sixth switching element Tr6 and the fifteenth switching element Tr15 are turned on.

Here, the discharge voltage VSS is supplied to the first reset node QB1 through the turned-on third switching element Tr3 so that the first reset node QB1 is discharged. Accordingly, the first pull-down switching device Trpd1, the first switching device Tr1, the third pulldown switching device Trpd3, and the ninth switching device Tr9 (Tr9), which are connected to the first reset node QB1 through the gate terminal, Is turned off.

On the other hand, since the first AC voltage (Vac1) is maintained in the high state during the first frame period, the fourth switching device Tr4 receiving the first AC voltage (Vac1) is turned on during the first frame period State. The first AC voltage Vac1 is supplied to the first common node CN1 of the first stage ST1 through the turned-on fourth switching device Tr4. At this time, the discharge voltage VSS output through the sixth switching device Tr6 turned on is also supplied to the first common node CN1. That is, the first common node CN1 is supplied with a first AC voltage Vac1 in a high state and a discharge voltage VSS in a low state together.

Since the size of the sixth switching element Tr6 for supplying the discharge voltage VSS is set to be larger than the size of the fourth switching element Tr4 for supplying the first AC voltage Vac1, 1 common node CN1 is maintained at the discharge voltage VSS. On the other hand, as will be described later, the discharging voltage VSS output by the seventh switching device Tr7 turned on is further supplied to the first common node CN1. Accordingly, the first common node CN1 is discharged, and the fifth switching element Tr5 connected to the discharged first common node CN1 via the gate terminal is turned off.

On the other hand, a high forward voltage V_F is applied to the second set node Q2 through the turned-on second forward switching element Tr_F2 in the second initial period T0. Thus, the second pull-up switching device Trpu2, the eleventh switching device Tr11, and the second switching device Tr11, which are charged with the second set node Q2 and connected to the charged second set node Q2 through the gate terminal, 14 switching element Tr14 and seventh switching element Tr7 are turned on.

Here, the discharge voltage VSS is supplied to the second reset node QB2 through the turn-on eleventh switching device Tr11 so that the second reset node QB2 is discharged. Accordingly, the fourth pull-down switching device Trpd4, the tenth switching device Tr10, the second pulldown switching device Trpd2, and the second switching device Tr2 (Tr2), which are connected to the second reset node QB2 through the gate terminal, Is turned off.

Meanwhile, since the second AC voltage (Vac2) is maintained in the low state during the first frame period, the twelfth switching element (Tr12) receiving the second AC voltage (Vac2) is turned off during the first frame period State.

The discharging voltage VSS output by the fifteenth switching element Tr15 turned on is supplied to the second common node CN2. Therefore, the second common node CN2 is discharged, and the thirteenth switching device Tr13 connected to the discharged second common node CN2 via the gate terminal is turned off.

On the other hand, a forward voltage V_F in a high state is applied to the third common node CN3 through the turned-on third forward switching device Tr_F3 in the second initial period T0. Thus, the third common node CN3 is charged, and the control switching element Tr_C and the eighth switching element Tr8 connected to the charged third common node CN3 through the gate terminal are turned on do.

The turned-on control switching element Tr_C maintains the first reset node QB1 in a stable discharge state by supplying a discharge voltage VSS to the first reset node QB1, - The turned-on eighth switching element Tr8 maintains the second reset node QB2 in a more stable discharge state by supplying the discharging voltage VSS to the second reset node QB2.

In this manner, during the second initial period, the first and second set nodes Q1 and Q2 of the first stage ST1 are charged and the first and second reset nodes QB1 and QB2 are discharged, 1 stage ST1 is enabled.

The operation during the first period T1 will now be described.

In this first period T1, as shown in Fig. 2, only the first clock pulse CLK1 indicates a high state and the remaining clock pulses including the start pulse Vst are held in a low state.

As the first set node Q1 of the first stage ST1 is kept in the charged state by the charging voltage VDD applied during the first initial period Ts, The first pull-up switching device Trpu1 of the first switch SW1 maintains the turn-on state. At this time, as the first clock pulse CLK1 is applied to the drain terminal of the turn-on first pull-up switching device Trpu1, the first set node Q1 in the floating state of the first stage ST1 The charged charge voltage (VDD) is amplified by bootstrapping.

Therefore, the first clock pulse CLK1 applied to the drain terminal of the first pull-up switching device Trpu1 of the first stage ST1 is stably outputted through the source terminal (first output terminal 111a). Here, the first clock pulse CLK1 outputted through the first pull-up switching device Trpu1 is the first scan pulse Vout1. The first scan pulse Vout1 is supplied to the first gate line, the second stage ST2, and the upper dummy stage ST0. Thus, the first gate line is driven in this first period T1, the second stage ST2 is enabled, and the upper dummy stage ST0 is disabled.

The enable operation of the second stage ST2 in the first period T1 is the same as the enable operation of the first stage ST1 in the first initial period Ts described above.

The first scan pulse Vout1 output from the first stage ST1 in the first period T1 is supplied to the upper dummy stage ST0 to disable the upper dummy stage ST0. This disable operation will be described in more detail as follows.

That is, the first scan pulse Vout1 is supplied to the gate terminal of the reverse switching element Tr_R provided in the upper dummy stage ST0. Then, the reverse switching element Tr_R is turned on and the reverse voltage V_R of the low state is supplied to the set node Q of the upper dummy stage ST0 through the turned-on reverse switching element Tr_R . Accordingly, the set node Q is discharged, and the pull-up switching device Trpu and the third switching device Tr3, which are connected to the discharged set node Q through the gate terminal, are turned off.

The third switching element Tr3 of the upper dummy stage ST0 is turned off so that the reset node QB of the upper dummy stage ST0 is in the high state outputted through the second switching element Tr2 The charging voltage VDD is supplied. Thereby, the pull-down switching element Trpd of the upper dummy stage ST0, which is charged with the reset node QB and connected to the charged reset node QB through the gate terminal thereof, (Tr1) is turned on.

The turn-on pull-down switching device Trpu outputs the discharge voltage VSS and supplies it to the first stage ST1.

The first switching device Tr1 of the upper dummy stage ST10 is supplied with the discharging voltage VSS to the set node Q of the upper dummy stage ST0 so as to stably discharge the set node .

Next, the operation during the second period T2 will be described as follows.

In this second period T2, only the first and second clock pulses CLK1 and CLK2 are in the high state, and the remaining clock pulses including the start pulse Vst are kept in the low state.

The first pull-up switching device Trpu1 provided in the first stage ST1 by the first clock pulse CLK1 outputs the full type first scan pulse Vout1. In the second period T2, the second stage ST2 is enabled by the first scan pulse Vout1.

Also, the second pull-up switching device Trpu2 provided in the first stage ST1 starts to output the second scan pulse Vout2 by the second clock pulse CLK2.

That is, as the second set node Q2 of the first stage ST1 is kept in the charged state by the charging voltage VDD that was applied during the first initial period Ts, the first stage ST1 ) Of the second pull-up switching device Trpu2 maintains the turn-on state. At this time, as the second clock pulse CLK2 is applied to the drain terminal of the turn-on second pull-up switching device Trpu2, the second set node Q2 in the floating state of the first stage ST1 The charged charge voltage (VDD) is amplified by bootstrapping.

Therefore, the second clock pulse CLK2 applied to the drain terminal of the second pull-up switching device Trpu2 of the first stage ST1 is stably outputted through the source terminal (the second output terminal 111b). Here, the second clock pulse CLK2 outputted through the second pull-up switching device Trpu2 is the second scan pulse Vout2. The second scan pulse Vout2 is supplied to the second gate line to drive the second gate line.

Next, the operation during the third period T3 will be described as follows.

In this third period T3, only the second and third clock pulses CLK3 are in the high state and the remaining clock pulses including the start pulse Vst are kept in the low state.

The second pull-up switching device Trpu2 provided in the first stage ST1 by the second clock pulse CLK2 outputs the second scan pulse Vout2 of the complete type to the second gate line. Then, the first pull-up switching device Trpu1 provided in the second stage ST2 starts to output the third scan pulse Vout3 by the third clock pulse CLK3.

In the third period T3, the third scan pulse Vout3 from the second stage ST2 is supplied to the third gate line to start driving the third gate line, and in the third stage ST3, And the third stage ST3 is enabled.

Next, the operation during the fourth period T4 will be described as follows.

In this fourth period T4, only the third and fourth clock pulses CLK3 and CLK4 are in the high state, and the remaining clock pulses including the start pulse Vst are kept in the low state.

The first pull-up switching device Trpu1 provided in the second stage ST2 by the third clock pulse CLK3 outputs the third scan pulse Vout3 of the complete form, 4 stage ST4. In addition, the second pull-up switching device Trpu2 provided in the second stage ST2 outputs the fourth scan pulse Vout4 by the fourth clock pulse CLK4. This fourth scan pulse Vout4 is supplied to the fourth gate line to start driving the fourth gate line, and is also supplied to the first stage ST1 to disable the first stage ST1.

The disabling operation of the first stage ST1 will be described in detail as follows.

That is, the fourth scan pulse Vout4 is applied to each gate of the first reverse switching element Tr_R1, the second reverse switching element Tr_R2, and the third reverse switching element Tr_R3 of the first stage ST1, Terminal. Then, the first reverse switching element Tr_R1, the second reverse switching element Tr_R2, and the third reverse switching element Tr_R3 are turned on.

A reverse voltage V_R in a low state is supplied to the first set node Q1 of the first stage ST1 through the turned-on first reverse switching element Tr_R1. Therefore, the first set node Q1 is discharged, and the first pull-up switching device Trpu1, the third switching device Tr3, the sixth switching device Tr3, the sixth pull- The switching element Tr6 and the fifteenth switching element Tr15 are turned off.

Also, a reverse voltage V_R in a low state is supplied to the second set node Q2 of the first stage ST1 through the turned-on second reverse switching device Tr_R2. Therefore, the second set node Q2 is discharged, and the second pull-up switching device Trpu2, the eleventh switching device Tr11, the seventeenth switching device Tr11, and the twelfth switching device Tr11, which are connected to the discharged second set node Q2 through the gate terminal, The switching element Tr14 and the seventh switching element Tr7 are turned off.

Also, a reverse voltage V_R in a low state is supplied to the third common node CN3 of the first stage ST1 through the turned-on third reverse switching device Tr_R3. Therefore, the third common node CN3 is discharged, and the control switching element Tr_C and the eighth switching element Tr8 connected to the discharged third common node CN3 through the gate terminal are turned off .

The fourth switching element Tr4 is connected to the first common node CN1 of the first stage ST1 as the sixth and seventh switching elements Tr6 and Tr7 of the first stage ST1 are turned off, And the first AC voltage (Vac1) output through the first switch SW2 is supplied. Thus, the first common node CN1 is charged, and the fifth switching element Tr5 connected to the charged first common node CN1 via the gate terminal is turned on.

The first AC voltage Vac1 is supplied to the first reset node QB1 of the first stage ST1 through the turn-on fifth switching element Tr5. Then, the first pull-down switching device Trpd1 of the first stage ST1 which is charged with the first reset node QB1 and connected to the charged first reset node QB1 through the gate terminal thereof, 3 pulldown switching element Trpd3, the first switching element Tr1 and the ninth switching element Tr9 are turned on.

The discharge voltage VSS is supplied to the first set node Q1 of the first stage ST1 through the turned-on first switching device Tr1 so that the discharge state of the first set node Q1 Is maintained more stably. The discharge voltage VSS is supplied to the second set node Q2 of the first stage ST1 through the turn-on ninth switching element Tr9 so that the discharge of the second set node Q2 The state is further stably maintained.

As described above, during the fourth period T4, the first and second set nodes Q1 and Q2 of the first stage ST1 are discharged, the first reset node QB1 is charged, The first stage ST1 is disabled by discharging the set node QB2.

As the first pull-down switching device Trpd1 and the third pulldown switching device Trpd3 of the first stage ST1 are turned on during the fourth period T4, the first pull-down switching device Trpd1 Supplies the discharge voltage VSS to the first gate line, the second stage ST2 and the upper dummy stage ST0 through the first output terminal 111a and the third pull-down switching element Trpd3 Outputs a discharge voltage VSS through the second output terminal 111b and supplies it to the second gate line.

Hereinafter, the fifth to lower dummy stages STn + 1 are sequentially driven by the operation as described above.

On the other hand, in the second frame period, the first alternating-current voltage Vac1 is kept negative and the second alternating-current voltage Vac2 is kept in the positive polarity. Therefore, during the disabled period, The set node QB1 is discharged and the second reset node QB2 is charged. Accordingly, during the second frame period, the second and fourth pulldown switching elements Trpd4 of the stages ST1 to STn operate.

Next, the operation of the shift register according to the forward driving will be described with reference to FIGS. 3, 4, 5, and 6. FIG.

3, the clock pulses are output in the order of the fourth clock pulse CLK4 to the first clock pulse CLK1, the forward voltage V_F is in the low state, the reverse voltage V_R is in the low state, Is in a high state.

First, the operation of the first initial period Ts in the first frame period will be described as follows.

During the first frame period, the first AC voltage (Vac1) shows positive polarity and the second AC voltage (Vac2) shows negative polarity.

During the first initial period (Ts), as shown in FIG. 3, only the start pulse (Vst) output from the timing controller is kept in the high state and the remaining clock pulses are held in the low state.

The start pulse Vst output from the timing controller is supplied to the upper dummy stage ST0 and the lower stage dummy stage STn + 1.

That is, as shown in FIG. 4, the start pulse Vst is supplied to the gate terminal of the forward switching device Tr_F provided in the lower dummy stage STn + 1. Accordingly, the reverse switching element Tr_R is turned on, and a high reverse voltage V_R is supplied to the set node Q through the turned-on reverse switching element Tr_R. Then, the set node Q is charged, and the pull-up switching device Trpu and the third switching device Tr3, which are connected to the charged set node Q through the gate terminal, are turned on.

The discharge voltage VSS is supplied to the reset node QB through the third switching element Tr3 turned on. On the other hand, since the second switching device Tr2 is always turned on by the charging voltage VDD, which is a DC voltage of a high state, the charging voltage VDD is supplied to the second switching device Tr2 via the second switching device Tr2. And is supplied to the reset node QB. Therefore, the high level charging voltage VDD output through the second switching element Tr2 and the low-level discharging voltage (VDD) output through the third switching element Tr3 are output to the reset node QB VSS) are supplied together. At this time, since the size of the third switching device Tr3 is set to be larger than the size of the second switching device Tr2, the reset node QB is set to the low state supplied through the third switching device Tr3 The discharge voltage VSS of the plasma display panel is set to the discharge state. Accordingly, the pull-down switching device Trpd and the first switching device Tr1 connected to the discharged reset node QB through the gate terminal are turned off.

On the other hand, since there is no output from the n-th stage STn in the first initial period Ts, the forward switching element Tr_F provided in the upper dummy stage ST0 is in the turn-off state.

Thus, the lower dummy stage STn + 1 is set in the first initial period Ts. On the other hand, the upper dummy stage ST0 receiving the start pulse Vst in the first initial period Ts is reset. This will be described in more detail as follows.

That is, as shown in FIG. 4, the start pulse Vst is supplied to the gate terminal of the forward switching device Tr_F provided in the upper dummy stage ST0. Accordingly, the forward switching device Tr_F is turned on, and a low forward voltage V_F is supplied to the set node Q through the turned-on forward switching device Tr_F. Then, the set node Q is discharged, and the pull-up switching device Trpu and the third switching device Tr3 connected to the discharged set node Q through the gate terminal are turned off.

Since the second switching device Tr2 is always in a turn-on state by the charging voltage VDD which is a DC voltage of a high state, the charging voltage VDD is supplied to the second switching device Tr2 through the second switching device Tr2, And is supplied to the node QB. Then, the reset node QB is charged, and the pull-down switching device Trpd and the first switching device Tr1 connected to the charged reset node QB through the gate terminal are turned on .

The turned-on first switching device Tr1 supplies the discharge voltage VSS to the set node Q so that the set node Q stays in a more stable discharge state. The turned-on first switching device Tr1 outputs the discharge voltage VSS to the first stage ST1.

Thus, the upper dummy stage ST0 is reset in the first initial period Ts.

Next, the operation during the second initial period T0 will be described as follows.

In the second initial period T0, only the second dummy clock pulse DCLK2 indicates the high state, and the remaining start pulse Vst and all the clock pulses remain in the low state.

Since the start pulse Vst has changed to the low state in the second initial period T0, the reverse switching element Tr_R of the lower dummy stage STn + 1 changes to the turn-off state, The set node Q of the lower dummy stage STn + 1 is kept in a floating state. Therefore, the charging voltage VDD supplied to the set node Q of the lower dummy stage STn + 1 in the first initial period Ts is supplied to the set node Q in the second initial period T0 .

As the set node Q of the lower dummy stage STn + 1 is continuously held in the charged state by the charging voltage VDD applied during the first initial period Ts, the upper dummy stage ST0, The pull-up switching device Trpu and the third switching device Tr3 maintain their turn-on states. At this time, as the second dummy clock pulse DCLK2 is applied to the drain terminal of the turn-on pull-up switching device Trpu, the set node Q in the floating state provided in the lower dummy stage STn + Is charged by the bootstrapping.

Therefore, the first dummy clock pulse DCLK1 applied to the drain terminal of the pull-up switching element Trpu of the lower dummy stage STn + 1 is stably outputted through the source terminal (output terminal). The second dummy clock pulse DCLK2 output through the pull-up switching element Trpu is the lower dummy scan pulse Vout2n + 1. The lower dummy scan pulse Vout2n + 1 is supplied to the n-th stage STn to enable the n-th stage STn.

That is, the lower dummy scan pulse Vout2n + 1 output from the lower dummy stage STn + 1 is applied to the first reverse-direction switching element Tr_R1, the third reverse-direction switching element Tr_R3, And the second reverse-direction switching element Tr_R2.

Then, the first reverse switching element Tr_R1, the third reverse switching element Tr_R3 and the second reverse switching element Tr_R2 are turned on and the first reverse switching element Tr_R1 is turned on A high state reverse voltage V_R is applied to the first set node Q1. Accordingly, the first pull-up switching device Trpu1, the third switching device Tr3, and the third switching device Tr3, which are charged with the first set node Q1 and connected to the charged first set node Q1 through the gate terminal, The sixth switching element Tr6 and the fifteenth switching element Tr15 are turned on.

Here, the discharge voltage VSS is supplied to the first reset node QB1 through the turned-on third switching element Tr3 so that the first reset node QB1 is discharged. Accordingly, the first pull-down switching device Trpd1, the first switching device Tr1, the third pulldown switching device Trpd3, and the ninth switching device Tr9 (Tr9), which are connected to the first reset node QB1 through the gate terminal, Is turned off.

On the other hand, since the first AC voltage (Vac1) is maintained in the high state during the first frame period, the fourth switching device Tr4 receiving the first AC voltage (Vac1) is turned on during the first frame period State. The first AC voltage Vac1 is supplied to the first common node CN1 of the first stage ST1 through the turned-on fourth switching device Tr4. At this time, the discharge voltage VSS output through the sixth switching device Tr6 turned on is also supplied to the first common node CN1. That is, the first common node CN1 is supplied with a first AC voltage Vac1 in a high state and a discharge voltage VSS in a low state together.

Since the size of the sixth switching element Tr6 for supplying the discharge voltage VSS is set to be larger than the size of the fourth switching element Tr4 for supplying the first AC voltage Vac1, 1 common node CN1 is maintained at the discharge voltage VSS. On the other hand, as will be described later, the discharging voltage VSS output by the seventh switching device Tr7 turned on is further supplied to the first common node CN1. Accordingly, the first common node CN1 is discharged, and the fifth switching element Tr5 connected to the discharged first common node CN1 via the gate terminal is turned off.

On the other hand, a reverse voltage V_R of a high state is applied to the second set node Q2 through the turned-on second reverse switching element Tr_R2 in the second initial period T0. Thus, the second pull-up switching device Trpu2, the eleventh switching device Tr11, and the second switching device Tr11, which are charged with the second set node Q2 and connected to the charged second set node Q2 through the gate terminal, 14 switching element Tr14 and seventh switching element Tr7 are turned on.

Here, the discharge voltage VSS is supplied to the second reset node QB2 through the turn-on eleventh switching device Tr11 so that the second reset node QB2 is discharged. Accordingly, the fourth pull-down switching device Trpd4, the tenth switching device Tr10, the second pulldown switching device Trpd2, and the second switching device Tr2 (Tr2), which are connected to the second reset node QB2 through the gate terminal, Is turned off.

Meanwhile, since the second AC voltage (Vac2) is maintained in the low state during the first frame period, the twelfth switching element (Tr12) receiving the second AC voltage (Vac2) is turned off during the first frame period State.

The discharging voltage VSS output by the fifteenth switching element Tr15 turned on is supplied to the second common node CN2. Accordingly, the second common node CN2 is discharged, and the thirteenth switching element Tr13 connected to the discharged second common node CN2 via the gate terminal is turned off.

On the other hand, a reverse voltage V_R of a high state is applied to the third common node CN3 through the turned-on third reverse switching element Tr_R3 in the second initial period T0. Thus, the third common node CN3 is charged, and the control switching element Tr_C and the eighth switching element Tr8 connected to the charged third common node CN3 through the gate terminal are turned on do.

The turned-on control switching element Tr_C maintains the first reset node QB1 in a stable discharge state by supplying a discharge voltage VSS to the first reset node QB1, - The turned-on eighth switching element Tr8 maintains the second reset node QB2 in a more stable discharge state by supplying the discharging voltage VSS to the second reset node QB2.

Thus, during the second initial period T0, the first and second set nodes Q1 and Q2 of the first stage ST1 are charged and the first and second reset nodes QB1 and QB2 are discharged So that the first stage ST1 is enabled.

The operation during the first period T1 will now be described.

In this first period T1, as shown in Fig. 3, only the fourth clock pulse CLK4 indicates a high state, and the remaining clock pulses including the start pulse Vst remain in a low state.

As the second set node Q2 of the first stage ST1 is kept in the charged state by the charging voltage VDD applied during the first initial period Ts, The second pull-up switching device Trpu2 of the second transistor Q2 maintains the turn-on state. At this time, as the fourth clock pulse CLK4 is applied to the drain terminal of the turn-on second pull-up switching device Trpu2, the second set node Q2 in the floating state of the first stage ST1 The charged charge voltage (VDD) is amplified by bootstrapping.

Therefore, the fourth clock pulse CLK4 applied to the drain terminal of the second pull-up switching device Trpu2 of the first stage ST1 is stably outputted through the source terminal (the second output terminal 111b). Here, the fourth clock pulse CLK4 output through the second pull-up switching device Trpu2 is an m-th scan pulse. The mth scan pulse is supplied to the m-th gate line, the (n-1) th stage STn-1, and the lower dummy stage STn + 1. Thus, the n-th gate line is driven in the first period T1, the n-1st stage STn-1 is enabled, and the lower stage dummy stage STn + 1 is disabled.

The enable operation of the n-1-th stage STn-1 in this first period T1 is the same as the enable operation of the first stage ST1 in the first initial period Ts described above.

On the other hand, the mth scan pulse output from the nth stage STn in the first period T1 is supplied to the lower stage dummy stage STn + 1 to disable the lower stage dummy stage STn + 1. This disable operation will be described in more detail as follows.

That is, the mth scan pulse is supplied to the gate terminal of the forward switching device Tr_F provided in the lower dummy stage STn + 1. Then, the forward switching device Tr_F is turned on, and the forward voltage V_F in the low state is supplied to the set node of the bottom dummy stage STn + 1 via the turned- do. Accordingly, the set node Q is discharged, and the pull-up switching device Trpu and the third switching device Tr3, to which the gate terminal is connected to the discharged set node Q, are turned off.

As the third switching device Tr3 of the lower dummy stage STn + 1 is turned off, the reset node QB of the lower dummy stage STn + 1 is connected to the second switching device Tr2 via the second switching device Tr2 And the high-level charge voltage VDD to be outputted is supplied. Thus, the pull-down switching element of the lower dummy stage STn + 1, to which the reset node QB is charged and the gate terminal is connected to the charged reset node QB, and the first switching element Tr1 Is turned on.

The turn-on pull-down switching device Trpd outputs a source of the discharge voltage VSS and supplies it to the n-th stage STn.

The first switching device Tr1 of the lower dummy stage STn + 1 is supplied with the discharging voltage VSS to the set node Q of the lower dummy stage STn + 1, ) In a more stable discharge state.

Next, the operation during the second period T2 will be described as follows.

In this second period T2, only the fourth and third clock pulses CLK3 and CLK4 are in the high state, and the remaining clock pulses including the start pulse Vst are kept in the low state.

The second pull-up switching device Trpu2 provided in the n-th stage STn by the fourth clock pulse CLK4 outputs the complete m-th scan pulse. In the second period T2, the (n-1) th stage STn-1 is enabled by the mth scan pulse.

Also, the first pull-up switching device Trpu1 provided in the n-th stage STn starts outputting the (m-1) th scan pulse by the third clock pulse CLK3.

That is, as the first set node Q1 of the n-th stage STn is kept in the charged state by the charging voltage VDD applied during the first initial period Ts, the first set ST1 The first pull-up switching device Trpu1 of the first switch SW1 maintains the turn-on state. At this time, as the third clock pulse CLK3 is applied to the drain terminal of the turned-on first pull-up switching device Trpu1, the first set node Q1 in the floating state of the first stage ST1 The charged charge voltage (VDD) is amplified by bootstrapping.

Accordingly, the third clock pulse CLK3 applied to the drain terminal of the first pull-up switching device Trpu1 of the n-th stage STn is stably outputted through the source terminal (the first output terminal 111a). Here, the third clock pulse CLK3 output through the first pull-up switching device Trpu1 is the (m-1) th scan pulse. The (m-1) th scan pulse is supplied to the (m-1) th gate line to drive the (m-1) th gate line.

Next, the operation during the third period T3 will be described as follows.

In this third period T3, only the third and second clock pulses CLK2 are in the high state and the remaining clock pulses including the start pulse Vst are kept in the low state.

The first pull-up switching device Trpu1 provided in the n-th stage STn by the third clock pulse CLK3 outputs the (m-1) th scan pulse of the complete type to the (m-1) th gate line. Then, the second pull-up switching device Trpu2 provided in the (n-1) th stage STn-1 starts to output the (m-2) th scan pulse by the second clock pulse CLK2.

During the third period T3, the (m-2) th scan pulse from the (n-1) th stage STn-1 is supplied to the (m-2) th gate line to start driving the And is also supplied to the (n-2) th stage to enable the (n-2) th stage.

Next, the operation during the fourth period T4 will be described as follows.

In this fourth period T4, only the second and first clock pulses CLK2 and CLK1 are in the high state, and the remaining clock pulses including the start pulse Vst are kept in the low state.

The second pull-up switching device Trpu2 provided in the (n-1) th stage STn-1 by the second clock pulse CLK2 outputs the complete m-2th scan pulse, 2 gate line and the (n-3) th stage. Also, the first pull-up switching device Trpu1 provided in the (n-1) th stage STn-1 outputs the (m-3) th scan pulse by the first clock pulse CLK1. The (m-3) th scan pulse is supplied to the (m-3) -th gate line to start driving the (m-3) -th gate line and is also supplied to the n-th stage STn, .

The disabling operation of the n-th stage STn will be described in detail as follows.

That is, the m-3th scan pulse is applied to each gate terminal of the first forward switching element Tr_F1, the second forward switching element Tr_F2, and the third forward switching element Tr_F3 of the n-th stage STn, . Then, the first forward switching element Tr_F1, the second forward switching element Tr_F2 and the third forward switching element Tr_F3 are turned on.

The forward voltage V_F in the low state is supplied to the first set node Q1 of the n-th stage STn through the turn-on first forward switching device Tr_F1. Therefore, the first set node Q1 is discharged, and the first pull-up switching device Trpu1, the third switching device Tr3, the sixth switching device Tr3, the sixth pull- The switching element Tr6 and the fifteenth switching element Tr15 are turned off.

Also, a forward voltage V_F in a low state is supplied to the second set node Q2 of the first stage ST1 through the turned-on second forward switching device Tr_F2. Therefore, the second set node Q2 is discharged, and the second pull-up switching device Trpu2, the eleventh switching device Tr11, the seventeenth switching device Tr11, and the twelfth switching device Tr11, which are connected to the discharged second set node Q2 through the gate terminal, The switching element Tr14 and the seventh switching element Tr7 are turned off.

Also, a forward voltage V_F in a low state is supplied to the third common node CN3 of the n-th stage STn through the turned-on third forward switching device Tr_F3. Therefore, the third common node CN3 is discharged, and the control switching element Tr_C and the eighth switching element Tr8 connected to the discharged third common node CN3 through the gate terminal are turned off do.

The fourth switching element Tr4 is connected to the first common node CN1 of the n-th stage STn as the sixth and seventh switching elements Tr6 and Tr7 of the n-th stage STn are turned off, And the first AC voltage (Vac1) output through the first switch SW2 is supplied. Thus, the first common node CN1 is charged, and the fifth switching element Tr5 connected to the charged first common node CN1 via the gate terminal is turned on.

The first alternating-current voltage Vac1 is supplied to the first reset node QB1 of the n-th stage STn via the turn-on fifth switching element Tr5. Then, the first pull-down switching device Trpd1 of the n-th stage STn connected to the first reset node QB1 through the gate terminal is charged and the first reset node QB1 is charged, 3 pulldown switching element Trpd3, the first switching element Tr1 and the ninth switching element Tr9 are turned on.

The discharging voltage VSS is supplied to the first set node Q1 of the n-th stage STn through the turned-on first switching device Tr1 so that the discharging state of the first set node Q1 Is maintained more stably. Also, the discharge voltage VSS is supplied to the second set node Q2 of the n-th stage STn via the turn-on ninth switching element Tr9, so that the discharge of the second set node Q2 The state is further stably maintained.

In this way, during the fourth period T4, the first and second set nodes Q2 of the n-th stage STn are discharged, the first reset node QB1 is charged, and the second reset node The n-th stage STn is disabled by discharging the n-th stage QB2.

As the first pull-down switching device Trpd1 and the third pulldown switching device Trpd3 of the n-th stage STn are turned on during the fourth period T4, the first pull-down switching device Trpd1 ) Supplies the discharge voltage VSS to the m-1 gate line through the first output terminal 111a and the third pull-down switching element Trpd3 through the second output terminal 111b And outputs the exclusive voltage VSS to the n-th gate line, the (n-1) th stage STn-1, and the lower dummy stage STn + 1.

Hereinafter, the fifth to lower dummy stages STn + 1 are sequentially driven by the operation as described above.

On the other hand, in the second frame period, the first alternating-current voltage Vac1 is kept negative and the second alternating-current voltage Vac2 is kept in the positive polarity. Therefore, during the disabled period, The set node QB1 is discharged and the second reset node QB2 is charged. Accordingly, during the second frame period, the second and fourth pulldown switching elements Trpd4 of the stages ST1 to STn operate.

As described above, in the present invention, the direction of scan pulse output of the stages can be controlled through the scan direction controller (SDC).

On the other hand, the upper and lower dummy stages ST0 and STn + 1 may have a circuit configuration provided in the above-described first to n-th stages ST1 to STn.

The shift register according to the present invention may be provided in the following liquid crystal display device.

7 is a view illustrating a shift register according to a second embodiment of the present invention.

The shift register according to the second embodiment of the present invention includes n stages ST1 to STn and two dummy stages ST0 and STn + 1 as shown in Fig. Here, each of the stages ST1 to STn outputs two scan pulses during one frame period.

Each of the stages ST1 to STn drives the gate line connected thereto by using the scan pulse and controls the operation of the stage located at the rear stage from itself and the stage located at the preceding stage from the stage itself.

The shift register according to the second embodiment receives a signal as shown in FIG. 2 at the time of forward driving and receives a signal as shown in FIG. 3 at the time of reverse driving. The upper dummy stage ST0 and the lower stage dummy stage STn + 1 provided in the shift register according to the second embodiment are similar to the upper dummy stage ST0 of the shift register according to the first embodiment described above, Is the same as the stage STn + 1.

The shift register according to the second embodiment shows a difference in the way of exchanging signals between the shift register and the stages of the first embodiment described above, and the rest of the configuration is the same as that of the shift register of the first embodiment.

The difference is as follows.

First, the enable operation will be described as follows.

In the forward driving, each stage ST1 to STn is supplied with two scan pulses from the stage located at the previous stage from the stage itself. In other words, each of the stages ST1 to STn has two sub stages therein. Among these two sub stages, the sub stage which outputs the scan pulse firstly outputs the first scan pulse And is supplied with a pulse. On the other hand, among the two sub-stages, a sub-stage that outputs a scan pulse is enabled by receiving a scan pulse output later than two scan pulses from the previous stage. Specifically, one of the two sub-stages provided at the j-th stage is a sub-stage for outputting a scan pulse. The sub-stage is supplied with a scan pulse, which is output first among two scan pulses from the j-1 stage, The other sub stage that outputs a scan pulse of the two sub stages provided in the j-th stage is supplied with a scan pulse output later than two scan pulses from the (j-1) th stage.

For example, one sub stage that outputs the fifth scan pulse among the two sub stages provided in the third stage ST3 is enabled by the third scan pulse Vout3 from the second stage ST2. And the other sub stage for outputting the sixth scan pulse Vout6 among the two sub stages included in the third stage ST3 is the fourth scan pulse Vout4 from the second stage ST2, Lt; / RTI >

 However, in the forward driving, the first stage ST1 located at the uppermost position is enabled in response to the upper dummy scan pulse Vout0 from the upper dummy stage ST0. The upper dummy stage ST0 is supplied with a start pulse Vst from the start transmission line and is enabled.

On the other hand, in the backward driving, each of the stages ST1 to STn is supplied with two scan pulses from the stage located at the rear end thereof. That is, each of the stages ST1 to STn has two sub-stages therein. Among the two sub-stages, the sub-stage that outputs the scan pulse firstly outputs the scan pulse And is enabled. On the other hand, among the two sub-stages, a sub-stage that outputs a scan pulse later is supplied with a scan pulse output later than the two scan pulses from the subsequent stage. Specifically, one of the two sub-stages provided in the j-th stage is a sub-stage for outputting a scan pulse, which is supplied with a scan pulse output first among two scan pulses from the (j + 1) The other sub stage that outputs a scan pulse of the two sub stages provided in the j-th stage is supplied with a scan pulse output later than the two scan pulses from the (j + 1) th stage.

For example, one sub stage for outputting the fifth scan pulse Vout5 among the two sub stages provided in the third stage ST3 is connected to the seventh scan pulse Vout7 from the fourth stage ST4 , And the remaining one sub stage for outputting the sixth scan pulse (Vout6) of the two sub stages provided in the third stage (ST3) is enabled by the eighth scan pulse (Vout8).

However, in the reverse driving, the n-th stage STn positioned at the lowermost is enabled in response to the lower dummy scan pulse Vout2n + 1 from the lower dummy stage STn + 1. The lower dummy stage STn + 1 is enabled by receiving a start pulse Vst from the start transmission line.

Next, the disabling operation will be described as follows.

In the forward driving, each stage ST1 to STn is supplied with two scan pulses from the stage located at the rear end thereof, and is disabled. That is, each of the stages ST1 to STn has two sub-stages therein. Among the two sub-stages, the sub-stage that outputs the scan pulse firstly outputs the scan pulse And is disabled. On the other hand, a sub-stage that outputs a scan pulse of the two sub-stages later is disabled by receiving a scan pulse output later than the two scan pulses from the subsequent stage. Specifically, one sub stage that outputs a scan pulse among two sub stages provided in the j < th > stage is disabled by receiving a scan pulse output first among two scan pulses from a (j + 1) The other sub stage that outputs a scan pulse of the two sub stages included in the j-th stage is disabled by receiving a scan pulse output later of two scan pulses from the (j + 1) th stage.

For example, one sub stage for outputting the fifth scan pulse Vout5 among the two sub stages provided in the third stage ST3 is connected to the seventh scan pulse Vout7 from the fourth stage ST4 And the remaining one sub stage for outputting the sixth scan pulse Vout6 among the two sub stages provided in the third stage ST3 is disabled by the eighth scan pulse from the fourth stage ST4, (Vout8).

In the forward driving, the n-th stage STn positioned at the lowermost position is disabled in response to the lower dummy scan pulse Vout2n + 1 from the lower dummy stage STn + 1. Then, the lower dummy stage STn + 1 is disabled by receiving the start pulse Vst from the start transmission line.

On the other hand, in the backward driving, each of the stages ST1 to STn is supplied with two scan pulses from the stage located at the previous stage thereof and is disabled. That is, each stage has two sub stages in the sub stage. The sub stage, which outputs the first scan pulse among the two sub stages, receives the first scan pulse among the two scan pulses from the previous stage, do. On the other hand, among the two sub-stages, a sub-stage that outputs a scan pulse is enabled by receiving a scan pulse output later than two scan pulses from the previous stage. Specifically, one of the two sub-stages provided in the j-th stage is a sub-stage that outputs a scan pulse in the first stage. The sub-stage is disabled by receiving a scan pulse that is output first among two scan pulses from the j-1 stage, The other sub stage that outputs a scan pulse of the two sub stages provided in the j-th stage is disabled by receiving a scan pulse output later than the two scan pulses from the j-1 stage.

For example, one sub-stage that outputs the fifth scan pulse Vout5 among the two sub-stages provided in the third stage ST3 may be connected to the third scan pulse Vout3 from the second stage ST2 And the remaining one sub stage that outputs the sixth scan pulse Vout6 among the two sub stages of the third stage ST3 is enabled by the fourth scan pulse V2 from the second stage ST2, (Vout4).

However, in the reverse driving, the first stage ST1 located at the uppermost position is disabled in response to the upper dummy scan pulse Vout0 from the upper dummy stage ST0. The upper dummy stage STn0 is disabled by receiving the start pulse Vst from the start transmission line.

Fig. 8 is a diagram showing the configuration of any stage provided in Fig. 7. Fig.

The structure shown in Fig. 8 is almost the same as the structure shown in Fig. 6, and there is a difference in the scan pulse supplied to each gate terminal of the second forward switching element, the first reverse switching element, and the third reverse switching element .

That is, according to the structure shown in FIG. 8, the second forward switching element Tr_F2 provided in the k-th stage is turned on / off according to a scan pulse (rear output) output later in the scan pulses from the (k- Off, and is connected between the forward power supply line and the second set node Q2. To this end, the gate terminal of the second forward switching device Tr_F2 provided in the k-th stage is connected to the second output terminal 111b of the (k-1) -th stage, and the drain terminal is connected to the forward power line , And a source terminal is connected to the second set node (Q2).

The first reverse switching element Tr_R1 provided in the k-th stage is turned on / off according to the scan pulse (front-end output) output first among the scan pulses from the (k + 1) ) And the reverse power line. To this end, the gate terminal of the first reverse switching device Tr_R1 provided in the k-th stage is connected to the first output terminal 111a of the (k + 1) -th stage and the drain terminal is connected to the first set node Q1. And the source terminal is connected to the reverse power line.

The third reverse-direction switching device Tr_R3 provided in the k-th stage is turned on / off by the scan pulse output first among the two scan pulses from the (k + 1) th stage, (CN3). To this end, the gate terminal of the third reverse switching element Tr_R3 is connected to the first output terminal 111a of the (k + 1) -th stage, the drain terminal is connected to the reverse power supply line, And is connected to the node CN3.

9 is a view illustrating a liquid crystal display device having a backlight of a fluorescent lamp driving type and a liquid crystal display device having a backlight of a light emitting diode driving type.

That is, the above-described shift register SR is mounted on the non-display portion of the liquid crystal panel 701. This liquid crystal panel 701 is a liquid crystal display device having a backlight of a fluorescent lamp driving type and a backlight of a light emitting diode driving type In order to apply it to both liquid crystal display devices, the liquid crystal panel 701 needs to be rotated 180 degrees.

9 (a), when the liquid crystal panel 701 is mounted on a liquid crystal display device having a backlight of a fluorescent lamp driving type, the first gate line GL1 is connected to the liquid crystal panel 701 and the last gate line GL2n is located at the lowermost side of the liquid crystal panel 701. [

However, when such a liquid crystal panel 701 is mounted on a liquid crystal display device having a backlight of the LED driving type, there is a case where the liquid crystal panel 701 is rotated 180 degrees due to a systematic difference between the two devices do. In this case, the first gate line GL1 is located at the lowermost side of the liquid crystal panel 701, and the last gate line GL2n is located at the uppermost side of the liquid crystal panel 701. [

In order to normally display an image on the screen of the liquid crystal panel 701, it is preferable that the first gate line GL1 of the liquid crystal panel 701, The gate line located on the uppermost side of the screen of the display unit 701 must be driven first.

Specifically, in order to drive the gate lines of the liquid crystal panel 701 as shown in FIG. 9A, the first gate line GL1 located on the uppermost side of the liquid crystal panel 701 must be driven, In order to drive the gate lines of the liquid crystal panel 701 as shown in FIG. 9 (b), the last gate line GL2n positioned on the uppermost side of the liquid crystal panel 701 must be driven.

By using the first or second shift register (SR) according to the present invention, it is possible to satisfy both the driving sequence in the two devices.

For example, in the liquid crystal display device shown in FIG. 9A, the first gate line GL1 located on the uppermost side of the liquid crystal panel 701 is operated by operating the shift register SR in the forward driving mode, .

On the other hand, in the liquid crystal display device as shown in FIG. 9B, by operating the shift register SR in the reverse driving mode, the last gate line GL2n positioned at the lowermost side of the liquid crystal panel 701 Can be driven.

On the other hand, the drawing number D-IC which has not been described represents a data driver IC (Integrated Circuit) for driving the data lines of the liquid crystal panel, the drawing number T represents a TCP (Tape Carrier Package) on which the data driver IC is mounted, And a data printed circuit board on which the controller TC is mounted. The plurality of TCPs (T) connect between the data printed circuit board (PCB) and the liquid crystal panel 701.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

1 is a view showing a shift register according to a first embodiment of the present invention;

Fig. 2 is a timing chart of various signals supplied to the shift register of Fig. 1 during forward driving

Fig. 3 is a timing chart of various signals supplied to the shift register of Fig. 1 during reverse driving

4 is a view showing a configuration of an upper dummy stage provided in Fig. 1

5 is a view showing the configuration of the lower stage dummy stage provided in Fig. 1

6 is a view showing the configuration of any stage provided in Fig. 1

7 is a view illustrating a shift register according to a second embodiment of the present invention.

8 is a view showing the configuration of any stage provided in Fig. 7

9 is a view showing a liquid crystal display device having a backlight of a fluorescent lamp driving type and a liquid crystal display device having a backlight of a light emitting diode driving type

Description of the Related Art

ST1 to Sn: stages Vout1 to Vout2n: scan pulse

ST0: Upper dummy stage STn + 1: Lower dummy stage

Vout0: Upper dummy scan pulse Vout2n + 1: Lower dummy scan pulse

Claims (8)

A plurality of stages sequentially outputting scan pulses, An upper dummy stage for outputting an upper dummy scan pulse for setting or resetting the first stage located at the uppermost one of the stages; And And a lower stage dummy stage for outputting a lower stage dummy scan pulse for setting or resetting the last stage positioned at the lowest one of the stages; In each stage, A scan direction controller for selectively outputting a forward voltage and an inverse voltage having potentials opposite to each other in accordance with a scan pulse from the front stage and a scan pulse from the rear stage; A node controller for controlling signal states of first and second set nodes and first and second reset nodes according to an output signal from the scan direction controller; And And an output unit for sequentially supplying one scan pulse to the subsequent stage in accordance with the voltages of the first and second set nodes and the first and second reset nodes and supplying another scan pulse to the previous stage In addition, The node controller included in the k < th > A first switching element connected between the first set node and a discharge power supply line for transmitting a discharge voltage, the on / off being controlled according to a signal state of the first reset node; A second switching element connected between the first set node and the discharging power supply line, the second switching element being on / off controlled according to a signal state of the second reset node; A third switching element connected between the first reset node and the discharging power supply line, the third switching element being on / off controlled according to a signal state of the first set node; A fourth switching device connected between the first AC power supply line and the first common node, the fourth switching device being on / off controlled according to a first AC voltage from the first AC power supply line; A fifth switching device connected between the first AC power supply line and the first reset node, the on / off being controlled according to a signal state of the first common node; A sixth switching device connected between the first common node and the discharge power supply line, the on / off being controlled according to a signal state of the first set node; And a seventh switching element connected between the first common node and the discharge power supply line, the on / off being controlled according to a signal state of the second set node. An eighth switching device connected between the second reset node and the discharge power supply line, the on / off being controlled in accordance with an output from the scan direction control unit; A ninth switching element connected between the second set node and the discharge power supply line, the on / off being controlled according to a signal state of the first reset node; A tenth switching element connected between the second set node and the discharge power supply line, the on / off being controlled according to a signal state of the second reset node; An eleventh switching element connected between the second reset node and the discharging power supply line, the on / off being controlled according to the signal state of the second set node; A twelfth switching element connected between the second AC power supply line and the second common node, the on / off being controlled in accordance with a second AC voltage from the second AC power supply line; A thirteenth switching element controlled on / off in accordance with a signal state of the second common node, and connected between the second AC power supply line and the second reset node; A fourth switch connected between the second common node and the discharge power supply line, the fourth switch being on / off controlled according to a signal state of the second set node; And And a fifteenth switching element connected between the second common node and the discharge power supply line, the on / off being controlled according to a signal state of the first set node, The scan direction control unit provided in the k < th > A first forward switching element connected between a forward power line for transmitting the forward voltage and the first set node, the on / off being controlled in accordance with a scan pulse output from the (k-1) th stage; The on / off control is controlled in accordance with the scan pulse output from the (k + 1) -th stage in the scan pulse either earlier or earlier than the scan pulse from the (k + 1) th stage. ; A second forward switching element connected between the forward power line and the second set node, the on / off being controlled in accordance with a scan pulse output first or later among the scan pulses from the (k-1) th stage; A second reverse switching element connected between the second set node and the reverse power supply line, the on / off being controlled in accordance with a scan pulse output from a scan pulse from a (k + 1) th stage; A third forward switching element connected between the third common node and the forward power supply line, the third forward switching element being on / off controlled by the first scan pulse among the two scan pulses from the (k-1) th stage; A third reverse switching element connected between the reverse power supply line and the third common node, the third reverse switching element being on / off controlled by a scan pulse output earlier or later than two scan pulses from the (k + 1) th stage; And And a control switching element controlled in accordance with a signal state of the third common node and connected between the first reset node and a discharge power supply line, The output section provided in the k < th > A first pull-up switching element connected between any one of the clock transmission lines transmitting clock pulses and a first output terminal, the first pull-up switching element being on / off controlled according to a signal state of the first set node; A second pull-up switching element connected between any one of the clock transmission lines transmitting clock pulses and a second output terminal, the second pull-up switching element being controlled on / off according to a signal state of the second set node; A first pull-down switching element connected between the first output terminal and a discharge power supply line, the first pull-down switching element being on / off controlled according to a signal state of the first reset node; A second pull-down switching element connected between the first output terminal and a discharge power supply line, the second pull-down switching element being on / off controlled according to a signal state of the second reset node; A third pull-down switching element connected between a second output terminal and a discharge power supply line, the third pull-down switching element being on / off controlled according to a signal state of the first reset node; And And a fourth pull-down switching element connected between the second output terminal and a discharge power source line, the fourth pull-down switching element being controlled on / off according to a signal state of the second reset node. delete delete delete delete The method according to claim 1, Wherein the upper dummy stage comprises: A first scan direction controller for selectively outputting a forward voltage and a reverse voltage having opposite potentials according to a start pulse from the outside; A first node controller for controlling a signal state of the set and reset nodes of the upper dummy stage according to an output signal from the first scan direction controller; And a first output unit for outputting an upper dummy scan pulse according to a voltage of the set and reset nodes of the upper dummy stage and supplying the upper dummy scan pulse to the first stage; And, The lower stage dummy stage, A second scan direction controller for selectively outputting a forward voltage and a reverse voltage having opposite potentials according to a start pulse from the outside; A second node controller for controlling a signal state of the set and reset nodes of the lower dummy stage according to an output signal from the second scan direction controller; And a second output unit for outputting a lower dummy scan pulse according to the set voltage of the lower dummy stage and the reset node and supplying the lower dummy scan pulse to the last stage. The method according to claim 6, Wherein the stages sequentially receive two scan pulses received from any one of a plurality of clock pulses having a phase difference supplied from a plurality of clock transmission lines; Wherein the upper dummy stage receives a first dummy clock pulse included in one of the clock pulses and outputs an upper dummy scan pulse; Wherein the lower dummy stage receives a second dummy clock pulse included in any one of the clock pulses and outputs a lower dummy scan pulse. delete

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