JP5078533B2 - Gate line drive circuit - Google Patents

Gate line drive circuit Download PDF

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JP5078533B2
JP5078533B2 JP2007264198A JP2007264198A JP5078533B2 JP 5078533 B2 JP5078533 B2 JP 5078533B2 JP 2007264198 A JP2007264198 A JP 2007264198A JP 2007264198 A JP2007264198 A JP 2007264198A JP 5078533 B2 JP5078533 B2 JP 5078533B2
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洋一 飛田
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三菱電機株式会社
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  The present invention relates to a shift register circuit composed of only field effect transistors of the same conductivity type used in, for example, a scanning line driving circuit of an image display device, and in particular, both of which can reverse the direction in which a signal is shifted. The present invention relates to a direction shift register.

  In an image display device such as a liquid crystal display device (hereinafter “display device”), a gate line (scanning line) is provided for each pixel row (pixel line) of a display panel in which a plurality of pixels are arranged in a matrix, and a display signal is displayed. The display image is updated by sequentially selecting and driving the gate lines in the period of one horizontal period. As such a gate line driving circuit (scanning line driving circuit) for sequentially selecting and driving pixel lines, that is, gate lines, a shift register that performs a shift operation that makes a round in one frame period of a display signal can be used. .

  The shift register used in the gate line driver circuit is preferably composed of only field effect transistors of the same conductivity type in order to reduce the number of steps in the manufacturing process of the display device. For this reason, various shift registers composed only of N-type or P-type field effect transistors and display devices equipped with the shift registers have been proposed. As the field effect transistor, a MOS (Metal Oxide Semiconductor) transistor, a thin film transistor (TFT), or the like is used.

  The gate line driving circuit includes a shift register (multi-stage shift register) including a plurality of stages. That is, the gate line driving circuit is configured by cascading a plurality of shift register circuits provided for each pixel line, that is, for each gate line. In this specification, each shift register circuit constituting each stage of a multistage shift register is referred to as a “unit shift register”.

  In a matrix type liquid crystal display device in which liquid crystal pixels are arranged in a matrix, there is often a demand for changing the display pattern, such as inverting the display image vertically and horizontally, or changing the display order during display. .

  For example, display inversion is desired when a liquid crystal display device is applied to a projector for OHP (Overhead Projector) and a transmission screen is used. This is because when a transmissive screen is used, an image is projected from the back side of the screen as viewed from the viewer, and the image on the screen is inverted compared to the case of projecting from the front side of the screen. In addition, changing the display order has a dramatic effect on the display of bar graphs, histograms, etc. by causing the display image to gradually appear from the top to the bottom or vice versa. Desired if you want to get.

  One method for changing the display pattern of such a display device is to switch the signal shift direction (scanning direction) in the gate line driving circuit. Therefore, a shift register capable of switching the signal shift direction has been proposed (for example, Patent Documents 1 to 3 below). Hereinafter, a shift register capable of switching the signal shift direction may be referred to as a “bidirectional shift register”, and each stage thereof may be referred to as a “bidirectional unit shift register”.

  FIG. 13 of Patent Document 1 discloses an n-stage bidirectional shift register composed of only N-channel field effect transistors. In this bidirectional shift register, the first control signal (D1) is supplied to the first stage unit shift register (RS (1)) as the signal for controlling the start and end of the signal shift operation, and the nth stage. The second control signal (D2) is input to each unit shift register (RS (n)).

  When performing “forward scanning” in which the signal is shifted in the direction from the first stage to the n-th stage, the first control signal (D1) starts the operation of the first stage, which is the first stage of forward scanning. It becomes a start signal (start pulse), and the second control signal (D2) becomes an end signal (end pulse) for stopping the operation of the nth stage, which is the final stage of forward scanning. In addition, when performing “reverse scanning” in which the signal is shifted in the direction from the n-th stage to the first stage, the second control signal (D2) performs the operation of the n-th stage, which is the first stage of the backward scanning. The start signal is a start signal, and the first control signal (D1) is an end signal that stops the operation of the first stage, which is the final stage of the backward scanning.

  Thus, the first and second control signals (D1, D2) in FIG. 13 of Patent Document 1 are two types of signals that are activated at different timings. These first and second control signals are supplied from a drive control circuit provided outside the gate line drive circuit. The number of signals supplied from the drive control circuit is as much as possible from the viewpoint of cost reduction of the display device. Less is preferred.

  On the other hand, FIG. 16 of Patent Document 2 discloses a bidirectional shift register that can be operated using only one type of control signal, that is, a start signal. The bidirectional shift register of FIG. 16 is configured by cascading the bidirectional unit shift registers of FIG.

  The unit shift register includes a first transistor (M1) (output pull-up transistor) that supplies a clock signal (CKV) to an output terminal of an output signal (GOUT [N]), and a reference voltage (VSS) to the output terminal. And a second transistor (M2) (output pull-down transistor) for supplying and discharging the output terminal. Here, a node (gate node) to which the gate of the first transistor (M1) is connected is defined as a “first node”, and a gate node of the second transistor (M2) is defined as a “second node”.

  The first transistor (M1) is driven by the following third and fourth transistors (M3, M5). The third transistor (M3) supplies a predetermined first voltage signal (Vbuf) to the first node based on the output signal (GOUT [N−1]) of the previous stage. The fourth transistor (M5) supplies a predetermined second voltage signal (Vdis) to the first node based on the output signal (GOUT [N + 1]) of the next stage. The first and second voltage signals (Vbuf, Vdis) are complementary signals in which one voltage level (hereinafter simply referred to as “level”) is H (High) level and the other is L (Low) level. It is.

  On the other hand, the second transistor (M2) is driven by inverters (M6, M7) having the first node as an input terminal. That is, the gate node (second node) of the second transistor is connected to the output terminal of the inverter (M6, M7).

  In a period (selection period) in which the unit shift register outputs an output signal, the third and fourth transistors set the first node to the H level and turn on the first transistor. When the first node becomes H level, the inverter sets the second node to L level, so that the second transistor is turned off. In this state, when a clock signal is input to the unit shift register, the clock signal is transmitted to the output terminal through the first transistor, and as a result, an output signal is output.

  On the other hand, during a period when the unit shift register does not output an output signal (non-selection period), the third and fourth transistors set the first node to the L level and turn off the first transistor. Meanwhile, since the inverter sets the second node to the H level, the second transistor is turned on, and the output terminal (output signal) is held at the L level. Note that, in FIG. 17 of Patent Document 2, the fifth transistor (M4) whose gate is connected to the second node and supplies the reference voltage (VSS) to the first node ensures that the first node is at the L level during the non-selection period. It works to prevent malfunctions.

  For example, when the first voltage signal (Vbuf) is at the H level and the second voltage signal (Vdis) is at the L level, each unit shift register has the first node at the H level when the output signal of its previous stage is activated. When the level and the second node become L level, the first transistor is turned on and the second transistor is turned off. Therefore, when a clock signal is input next, it is transmitted to the output terminal, and an output signal is output from the shift register circuit. That is, when the first voltage signal is at the H level and the second voltage signal is at the L level, each unit shift register shifts the output signal of its previous stage in terms of time and uses it as its own output signal as the next stage. It works to output to. As a result, the multistage bidirectional shift register (FIG. 16 of the cited document 3) performs forward scanning.

  On the other hand, when the first voltage signal (Vbuf) is at the L level and the second voltage signal (Vdis) is at the H level, in each unit shift register, the first output signal is activated when the next output signal is activated. When the node becomes H level and the second node becomes L level, the first transistor is turned on and the second transistor is turned off. Therefore, when a clock signal is input next, it is transmitted to the output terminal and an output signal is output. That is, when the first voltage signal is at the L level and the second voltage signal is at the H level, each unit shift register shifts the output signal of its next stage temporally and uses it as its own output signal as the previous stage. It works to output to. As a result, the multistage bidirectional shift register performs reverse scanning.

  As described above, the conventional bidirectional unit shift register (FIG. 17 of Patent Document 2) supplies the first and second transistors supplied to the gate of the first transistor (M1) through the third and fourth transistors (M3 and M5). The signal shift direction is switched by switching the level of the voltage signal (Vbuf, Vdis).

  As described above, the bidirectional shift register of FIG. 16 of Patent Document 2 can be operated using only one type of control signal (start signal). In order to make this possible, a first dummy stage (0) is provided further before the first stage (SRC1), and a second dummy stage (1) is provided further after the last stage (SRC4). Yes. The output signal of the first dummy stage (0) can be used as an end signal during backward scanning, and the output signal of the second dummy stage (1) can be used as an end signal during forward scanning.

  The start signal (STV) or the output signal of the first dummy stage (end signal at the time of backward scanning) is selectively inputted to the gate of the third transistor of the first stage (SRC1) according to the scanning direction. As shown, two selection transistors (M8, M9) controlled by the first and second voltage signals (Vbuf, Vdis) are provided (see FIG. 19). Similarly, either the start signal (STV) or the output signal of the second dummy stage (end signal at the time of forward scanning) is selected according to the scanning direction for the gate of the fourth transistor in the last stage (SRC4). Two selection transistors (M10, M11) controlled by first and second voltage signals (Vbuf, Vdis) are provided so as to be inputted (see FIG. 20).

JP 2001-350438 A JP 2004-157508 A Japanese National Patent Publication No. 11-502355

  A display device in which a shift register of a gate line driving circuit is composed of an amorphous silicon TFT (a-Si TFT) is easy to increase in area and has high productivity. For example, a notebook PC screen or a large screen display device. Widely adopted. However, on the other hand, when the gate electrode is continuously positively biased, the a-Si TFT has a tendency that the threshold voltage shifts in the positive direction and the driving ability (ability to flow current) becomes small.

  In each unit shift register of FIG. 17 of Patent Document 2, the second node is fixed at the H level during the non-selection period. That is, in each unit shift register, the operation of positively biasing the second transistor (M2) (output pull-down transistor) and the fifth transistor (M4) is positively DC-biased for about one frame period (about 16 ms). To be done. Therefore, their driving ability gradually decreases.

  If the driving capability of the second transistor is reduced, when the charge is unnecessarily supplied to the output terminal due to noise or the like, the charge cannot be discharged and the gate line is erroneously activated. Occurs. Further, when the driving capability of the fifth transistor is reduced, the level of the first node in the inactive period is likely to rise, so that the first transistor is easily turned on, which also causes the gate line to be erroneously activated. .

  Further, it has been found that this threshold voltage shift problem occurs not only in an a-Si TFT but also in an organic TFT.

  As described above, since the bidirectional shift register of FIG. 16 of Patent Document 2 is operated only by the start signal, the gates of the third transistors of the first stage unit shift register (SRC1) are respectively connected to the first transistor. Two selection transistors (M8, M9) controlled by the first and second voltage signals (Vbuf, Vdis) are connected. Similarly, two selection transistors (M10, M11) controlled by the first and second voltage signals (Vbuf, Vdis) are connected to the gate of the fourth transistor of the last unit shift register (SRC4). .

  The selection transistor provided in the first stage unit shift register drives the third transistor, and the selection transistor provided in the last stage unit shift register drives the fourth transistor. The first and second voltage signals (Vbuf, Vdis) are DC signals that are maintained at a constant level unless the scanning direction is switched. Therefore, a threshold voltage shift also occurs in the above-described four selection transistors (M8 to M10) controlled thereby.

  Since the selection transistor operates as a source follower, when a threshold voltage shift occurs, the level of the signal supplied to the gates of the third transistor at the first stage and the fourth transistor at the last stage decreases by the shift amount. The driving ability of the is reduced. As a result, the gate (first node) of the first transistor (M1) at the first stage or the last stage is not sufficiently charged, and the driving capability of the first transistor is lowered. As a result, the charge capacity of the gate line is reduced in the first-stage or last-stage unit shift register. In addition, there is a concern that the signal shift operation may not be performed normally.

  The threshold voltage shift of the transistor causes a problem also in the circuit of the dummy stage (dummy stages 0 and 1) of FIG. For example, in the first dummy stage (FIG. 18), the gate of the first transistor (M1) is charged when the output signal of the first stage is input, and is discharged when the start signal is input. Therefore, at the time of forward scanning, an operation in which the gate of the first transistor of the first dummy stage is positively biased in a direct current is continuously performed for about one frame period (about 16 ms), and its driving capability gradually decreases.

  Then, when switching to the backward scanning after that, the first dummy stage supplies a signal having sufficient charging capability (end signal at the time of backward scanning) to the gate of the third transistor of the first stage. I can't. As a result, the gate (first node) of the first transistor in the first stage cannot be sufficiently discharged, and an error signal is output from the first stage without turning off the first transistor. Since the same problem occurs in the second dummy stage (FIG. 21) during backward scanning, an error signal is output from the last stage when switching from backward scanning to forward scanning. .

  The present invention has been made to solve the above-described problems. In a bidirectional shift register that can be operated using only one type of start signal, it is possible to shift the threshold voltage of transistors constituting the shift register. The purpose is to suppress the occurrence of malfunctions.

A gate line driving circuit according to the present invention includes a multi-stage shift register capable of driving a gate line of a display panel and changing a signal shift direction, and a dummy stage provided at a stage before the foremost stage of the multi-stage shift register. A gate line driving circuit comprising: a first dummy stage that is a shift register; and a second dummy stage that is a dummy shift register provided at the next stage after the last stage of the multi-stage shift register. The dummy stage outputs a first dummy signal according to the output signal of the foremost stage regardless of the signal shift direction, and the second dummy stage outputs the output signal of the last stage regardless of the signal shift direction. The second dummy signal is output in response to the first dummy signal, and the first dummy signal is an end signal that terminates the operation of the forefront stage during reverse scanning in which the signal is shifted from the last stage toward the forefront stage. Is used as the second dummy signal, said at forward scan shifting the signal to from the forefront to the last stage, the final stage is used as an end signal to terminate operation of said first and second Each dummy signal is output at the same frequency as each output signal of each stage of the multi-stage shift register regardless of the signal shift direction .

  The first and second dummy stages operate so as to output a signal in the same manner as each stage of the multistage shift register that drives the gate line regardless of the signal shift direction. Therefore, in the transistors constituting the first and second dummy stages, the same threshold voltage shift as that of the transistors constituting the multistage shift register can be caused. This solves the problem that the first and second dummy signals are likely to malfunction.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, in order to avoid duplication and redundant description, elements having the same or corresponding functions are denoted by the same reference symbols in the respective drawings.

<Embodiment 1>
FIG. 1 is a schematic block diagram showing a configuration of a display device according to Embodiment 1 of the present invention, and shows an overall configuration of a liquid crystal display device 10 as a representative example of the display device.

  The liquid crystal display device 10 includes a liquid crystal array unit 20, a gate line driving circuit (scanning line driving circuit) 30, and a source driver 40. As will be apparent from the following description, the bidirectional shift register according to the embodiment of the present invention is mounted on the gate line driving circuit 30.

The liquid crystal array unit 20 includes a plurality of pixels 25 arranged in a matrix. Each of the pixel rows (hereinafter also referred to as “pixel lines”) is provided with a gate line GL 1 , GL 2 ,... (Generically referred to as “gate line GL”). Are also provided with data lines DL 1 , DL 2 ,... (Generic name “data line DL”). FIG. 1 representatively shows the pixels 25 in the first and second columns of the first row, and the corresponding gate lines GL 1 and data lines DL 1 and DL 2 .

  Each pixel 25 includes a pixel switch element 26 provided between the corresponding data line DL and the pixel node Np, a capacitor 27 and a liquid crystal display element 28 connected in parallel between the pixel node Np and the common electrode node NC. have. The orientation of the liquid crystal in the liquid crystal display element 28 changes according to the voltage difference between the pixel node Np and the common electrode node NC, and the display brightness of the liquid crystal display element 28 changes in response to this. Thereby, the luminance of each pixel can be controlled by the display voltage transmitted to the pixel node Np via the data line DL and the pixel switch element 26. That is, by applying an intermediate voltage difference between the voltage difference corresponding to the maximum luminance and the voltage difference corresponding to the minimum luminance between the pixel node Np and the common electrode node NC, the intermediate luminance is reduced. Can be obtained. Therefore, gradation brightness can be obtained by setting the display voltage stepwise.

  The gate line driving circuit 30 sequentially selects and drives the gate lines GL based on a predetermined scanning cycle. In the present embodiment, the gate line driving circuit 30 is composed of a bidirectional shift register, and the direction of the order of activating the gate line GL can be switched. The gate electrodes of the pixel switch elements 26 are connected to the corresponding gate lines GL. While a specific gate line GL is selected, the pixel switch element 26 is in a conductive state in each pixel connected thereto, and the pixel node Np is connected to the corresponding data line DL. The display voltage transmitted to the pixel node Np is held by the capacitor 27. In general, the pixel switch element 26 includes a TFT formed on the same insulator substrate (glass substrate, resin substrate, etc.) as the liquid crystal display element 28.

The source driver 40 is for outputting a display voltage, which is set stepwise by a display signal SIG that is an N-bit digital signal, to the data line DL. Here, as an example, the display signal SIG is a 6-bit signal and is composed of display signal bits DB0 to DB5. Based on the 6-bit display signal SIG, 2 6 = 64 gradation display is possible in each pixel. Furthermore, if one color display unit is formed by three pixels of R (Red), G (Green), and B (Blue), approximately 260,000 colors can be displayed.

  As shown in FIG. 1, the source driver 40 includes a shift register 50, data latch circuits 52 and 54, a gradation voltage generation circuit 60, a decode circuit 70, and an analog amplifier 80.

  In the display signal SIG, display signal bits DB0 to DB5 corresponding to the display brightness of each pixel 25 are serially generated. That is, the display signal bits DB0 to DB5 at each timing indicate the display luminance in any one pixel 25 in the liquid crystal array unit 20.

  The shift register 50 instructs the data latch circuit 52 to take in the display signal bits DB0 to DB5 at a timing synchronized with the cycle at which the setting of the display signal SIG is switched. The data latch circuit 52 sequentially takes in the serially generated display signal SIG and holds the display signal SIG for one pixel line.

  The latch signal LT input to the data latch circuit 54 is activated at the timing when the display signal SIG for one pixel line is taken into the data latch circuit 52. In response thereto, the data latch circuit 54 takes in the display signal SIG for one pixel line held in the data latch circuit 52 at that time.

  The gradation voltage generation circuit 60 is composed of 63 voltage dividing resistors connected in series between the high voltage VDH and the low voltage VDL, and generates 64 gradation voltages V1 to V64, respectively.

The decode circuit 70 decodes the display signal SIG held in the data latch circuit 54 and outputs it to each decode output node Nd 1 , Nd 2 ,... (Generic name “decode output node Nd”) based on the decode result. The voltage is selected from the gradation voltages V1 to V64 and output.

As a result, at the decode output node Nd, a display voltage (one of the gradation voltages V1 to V64) corresponding to the display signal SIG for one pixel line held in the data latch circuit 54 is simultaneously (in parallel). ) Is output. In FIG. 1, the decode output nodes Nd 1 and Nd 2 corresponding to the data lines DL 1 and DL 2 in the first column and the second column are representatively shown.

The analog amplifier 80 outputs analog voltages corresponding to the display voltages output from the decode circuit 70 to the decode output nodes Nd 1 , Nd 2 ,... To the data lines DL 1 , DL 2 ,.

Based on a predetermined scanning cycle, the source driver 40 outputs a display voltage corresponding to a series of display signals SIG to the data line DL for each pixel line, and the gate line driving circuit 30 performs gate operation in synchronization with the scanning cycle. By driving the lines GL 1 , GL 2 ,... In this order or in the reverse order, an image based on the display signal SIG or an inverted image thereof is displayed on the liquid crystal array unit 20.

  1 shows a configuration example of the liquid crystal display device 10 in which the gate line driving circuit 30 and the source driver 40 are integrally formed with the liquid crystal array unit 20, but the gate line driving circuit 30 and the liquid crystal array unit 20 are shown. And the source driver 40 can be provided as an external circuit of the liquid crystal array unit 20, or the gate line driving circuit 30 and the source driver 40 can be provided as an external circuit of the liquid crystal array unit 20. .

FIG. 2 is a diagram illustrating a configuration of the gate line driving circuit 30. The gate line driving circuit 30 can be operated using one type of start signal, and is constituted by a plurality of stages of bidirectional shift registers. That is, the gate line driving circuit 30 includes n bidirectional unit shift registers SR 1 , SR 2 , SR 3 , SR 4 ,..., SR n connected in cascade (cascade connection) (hereinafter referred to as cascade connection). Shift registers SR 1 , SR 2 ,..., SR n are collectively referred to as “unit shift register SR”).

  One unit shift register SR is provided for each pixel line, that is, one gate line GL, and each gate line GL is connected to the output terminal OUT of the corresponding unit shift register SR. That is, a signal (output signal) output to the output terminal OUT of the unit shift register SR becomes a vertical (horizontal) scanning pulse for activating the gate line GL.

In the gate line drive circuit 30, so that their n unit shift register SR 1 to SR n drives the gate lines. More front of the unit shift register SR 1 of the first stage, the dummy stage SRD1 is connected a shift register of the dummy, In a more next stage unit shift register SR n of the last stage, a dummy shift register A certain dummy stage SRD2 is connected. Hereinafter, the unit shift registers SR 1 to SR n for driving the gate lines excluding the dummy stages SRD1 and SRD2 may be collectively referred to as “gate line driving stages”.

  As shown in FIG. 2, each of the unit shift registers SR of the gate line driving stage includes a first input terminal IN1, a second input terminal IN2, an output terminal OUT, a first clock terminal CK1, a second clock terminal CK2, and a first voltage signal. A terminal T1 and a second voltage signal terminal T2 are provided.

However, the unit shift registers SR 1 and SR n which are the foremost stage and the last stage of the gate line driving stage further include a reset terminal RST. The dummy stages SRD1 and SRD2 each have an input terminal IN, an output terminal OUT, a first clock terminal CK1, a second clock terminal CK2, and a reset terminal RST. The reset terminals RST provided in the unit shift registers SR 1 and SR n and the dummy stages SRD 1 and SRD 2 are control terminals for setting each of them to a “reset state” described later.

  The clock generator 31 supplies two-phase clock signals CLK and / CLK having different phases to the gate line driving stage and the dummy stages SRD1 and SRD2. These clock signals CLK and / CLK are complementary to each other, and are controlled so as to be alternately activated at timings synchronized with the scanning period of the display device (the activation periods do not overlap each other).

The clock signals CLK and / CLK output from the clock generator 31 are supplied to the first and second clock terminals CK1 and CK2 of each unit shift register SR and dummy stages SRD1 and SRD2 of the gate line driving stage. In the odd-numbered unit shift registers SR 1 , SR 3 ,..., SR n-1 and the dummy stage SRD2, the clock signal CLK is input to the first clock terminal CK1, and the clock signal / CLK is input to the second clock terminal CK2. . In the even-numbered unit shift registers SR 2 , SR 4 ,..., SR n and the dummy stage SRD1, the clock signal / CLK is input to the first clock terminal CK1 and the clock signal CLK is input to the second clock terminal CK2. .

The voltage signal generator 33 generates a first voltage signal Vn and a second voltage signal Vr that determine the shift direction (scanning direction) of the signal in the bidirectional shift register. The voltage signal generator 33 sets the first voltage signal Vn to the H level when shifting the signal in the direction from the front stage to the rear stage (forward direction), that is, in the order of the unit shift registers SR 1 , SR 2 , SR 3 ,. Activation), the second voltage signal Vr is set to L level. On the contrary, when the signal is shifted in the order from the rear stage to the front stage (reverse direction), that is, the unit shift registers SR n , SR n-1 , SR n-2 ,..., The second voltage signal Vr is set to the H level ( Activation), the first voltage signal Vn is set to L level. That is, the first and second voltage signals Vn and Vr are complementary to each other. The first voltage signal Vn is input to the first voltage signal terminal T1 of each unit shift register SR, and the second voltage signal Vr is input to the second voltage signal terminal T2 of each unit shift register SR.

The start signal generator 32 generates first and second control signals STn and STr. One of the first and second control signals STn and STr is a start signal according to the scanning direction, and the other is a signal fixed at the L level. The first control signal STn is input to the first input terminal IN1 of the unit shift register SR 1 is a foremost stage gate line drive stage, the second control signal STr, the unit shift register is the last stage of the gate line driving stage is input to the second input terminal IN2 of the SR n. During forward scanning, the first control signal STn serves as a start signal, and the second control signal STr is fixed at the L level. During reverse scanning, the second control signal STr serves as a start signal, and the first control signal STn is fixed at the L level.

  Since the signal fixed to the L level can be supplied from a low-potential side power supply (supply source of the potential VSS described later), the start signal generator 32 has one type each for forward scanning and backward scanning. Only the start signal is generated. That is, the operation of the bidirectional shift register does not require an end signal for ending the signal shift operation. The reason is that the output signal D2 of the dummy stage SRD2 (hereinafter referred to as “dummy signal D2”) functions as an end signal during forward scanning, and the output signal D1 of the dummy stage SRD1 (hereinafter referred to as “dummy signal D1”) during backward scanning. This is because it functions as an end signal.

  Clock signals CLK, / CLK, first and second control signals STn, STr, and first and second voltage signals Vn, Vr generated by the clock generator 31, the start signal generator 32, and the voltage signal generator 33 are respectively These programs can be exchanged according to the scanning direction by changing the connection of the program or wiring. The exchange by changing the connection of the wiring is effective when the scanning direction is fixed before the display device is manufactured. The replacement by the program is effective when the shift direction is fixed after the display device is manufactured, or when the scanning direction can be changed while the display device is in use.

  As shown in FIG. 2, the output terminal OUT of each unit shift register SR is connected to the first input terminal IN1 at the next stage of the unit shift register SR and the second input terminal IN2 at the front stage of the unit shift register SR. In other words, the first input terminal IN1 of each unit shift register SR is connected to its own preceding output terminal OUT, and the second input terminal IN2 is connected to its own succeeding output terminal OUT. As a result, the unit shift registers SR are cascaded in both directions.

However, in the unit shift register SR 1, the output terminal OUT is connected to the input terminal IN of the first input terminal IN1 and the dummy stage SRD1 unit shift register SR 2, the first control as described above to the first input terminal IN1 The signal STn is input, and the reset terminal RST is connected to the output terminal OUT of the dummy stage SRD1. Similarly to the second clock terminal CK2, the clock signal CLK is input to the reset terminal RST of the dummy stage SRD1.

On the other hand, in the unit shift register SR n , the output terminal OUT is connected to the first input terminal IN2 of the unit shift register SR n−1 and the input terminal IN of the dummy stage SRD2, and the first input terminal IN1 is connected to the first input terminal IN1 as described above. 2 The control signal STr is input, and the reset terminal RST is connected to the output terminal OUT of the dummy stage SRD2. Similarly to the second clock terminal CK2, the clock signal / CLK is input to the reset terminal RST of the dummy stage SRD2.

  In the present embodiment, the transistors constituting the gate line driving stage and the dummy stages SRD1 and SRD2 are all field effect transistors of the same conductivity type, and here are all N-type a-Si TFTs. The N-type TFT is activated (on) when the gate is at the H level and deactivated (off) at the L level. However, the unit shift register and the dummy shift register can be configured by P-type transistors. In the case of a P-type transistor, when the gate becomes L level, it becomes active (ON), and when it becomes H level, it becomes inactive (OFF). Further, the application of the present invention is not limited to the a-Si TFT, but can be applied to a unit shift register SR constituted by, for example, an organic TFT.

3 to 5 are diagrams showing specific circuit configurations of the gate line driving circuit 30 according to the present embodiment. FIG. 3 shows the first two stages (unit shift registers SR 1 and SR 2 ) of the dummy stage SRD1 and the gate line driving stage. FIG. 4 shows the ( k− 1 ) -th to ( k + 1 ) -th stages (unit shift registers SR k−1 , SR k , SR k + 1 ) as intermediate stages of the gate line driving stage. FIG. 5 shows the last two stages (unit shift registers SR n−1 , SR n ) of the gate line driving stage and the dummy stage SRD2.

The first and last stages (unit shift registers SR 1 and SR n ), the intermediate stage (unit shift registers SR 2 to SR n-1 ), and the dummy stages SRD 1 and SRD 2 of the gate line driving stage are slightly different from each other. The configuration is different. However, in FIGS. 3 to 5, elements that function in the same manner are denoted by the same reference numerals.

First, the configuration of the unit shift register SR in the intermediate stage (second stage to (n-1) th stage) of the gate line driving stage will be described. Since all the intermediate unit shift registers SR have the same configuration, the unit shift register SR k shown in FIG. 4 will be typically described here.

As shown in FIG. 4, the unit shift register SR k includes the first and second input terminals IN1 and IN2, the output terminal OUT, the first and second clock terminals CK1 and CK2, and the first and second voltages already shown in FIG. In addition to the signal terminals T1 and T2, the first power supply terminal S1 to which the low potential side power supply potential VSS is supplied is provided. In the following description, the low-potential-side power supply potential VSS is a circuit reference potential (= 0V). However, in actual use, the reference potential is set with reference to the voltage of data written to the pixel. For example, the high potential side power supply potential (VDD) is set to 17V, the low potential side power supply potential (VSS) is set to -12V, and the like. .

As shown in FIG. 4, the output stage of the unit shift register SR k includes a transistor Q1 connected between the output terminal OUT and the first clock terminal CK1, and between the output terminal OUT and the first power supply terminal S1. The transistors Q2 and Q7 are connected. That is, the transistor Q1 supplies a clock signal input to the first clock terminal CK1 to the output terminal OUT, and the transistors Q2 and Q7 each have the potential of the first power supply terminal S1 (low potential side power supply potential VSS). Is supplied to the output terminal OUT to discharge the output terminal OUT. Here, a node connected to the gate (control electrode) of the transistor Q1 is defined as “node N1”, and a node connected to the gate of the transistor Q2 is defined as “node N2”.

  A capacitive element C1 is provided between the gate and source of the transistor Q1, that is, between the node N1 and the output terminal OUT. The capacitive element C1 is for enhancing the boosting effect of the node N1 accompanying the increase in the level of the output terminal OUT.

  A transistor Q3 whose gate is connected to the first input terminal IN1 is connected between the node N1 and the first voltage signal terminal T1 to which the first voltage signal Vn is input, and the node N1 and the second voltage signal Vr are A transistor Q4 whose gate is connected to the second input terminal IN2 is connected between the input second voltage signal terminal T2. That is, the transistor Q3 supplies the first voltage signal Vn to the node N1 based on a signal (first input signal) input to the first input terminal IN1. The transistor Q4 supplies the second voltage signal Vr to the node N1 based on a signal (second input signal) input to the second input terminal IN2.

The unit shift register SR k includes two inverters each having the node N1 as an input terminal. One is an inverter composed of a transistor Q6 and a capacitive element C2 (hereinafter “first inverter”), and the other is an inverter composed of a transistor Q9 and a capacitive element C3 (hereinafter “second inverter”).

  In the first inverter, the transistor Q6 is connected between the node N2 and the first power supply terminal S1, and its gate is connected to the node N1. The capacitive element C2 is connected between the node N2 and the first clock terminal CK1. That is, the first inverter is a capacitive load type inverter using the capacitive element C2 as a load element, and has the node N1 as an input end and the node N2 as an output end. However, the first inverter is different from a normal inverter in that a clock signal input to the first clock terminal CK1 is supplied as a power source. That is, the first inverter performs an alternating operation activated by the clock signal input to the first clock terminal CK1. Therefore, the capacitive element C2 is a load element of the first inverter and also functions as a coupling capacitance between the output terminal (node N2) and the first clock terminal CK1.

  On the other hand, in the second inverter, the transistor Q9 is connected between a node (defined as “node N3”) serving as an output terminal of the second inverter and the first power supply terminal S1, and its gate is connected to the node N1. Connect to. The capacitive element C3 is connected between the node N3 and the second clock terminal CK2. That is, the second inverter is a capacitive load type inverter having the capacitive element C3 as a load element, and has the node N1 as an input end and the node N3 as an output end. However, the second inverter is different from a normal inverter in that a clock signal input to the second clock terminal CK2 is supplied as a power source. That is, the second inverter performs an alternating operation activated by the clock signal input to the second clock terminal CK2. Therefore, the capacitive element C3 is a load element of the second inverter and also functions as a coupling capacitance between the output terminal (node N3) and the second clock terminal CK2.

  The output terminal of the first inverter is connected to the gate of the transistor Q5 connected between the node N1 and the first power supply terminal S1. Similarly, the output terminal of the second inverter is connected to the gate of the transistor Q8 connected between the node N1 and the first power supply terminal S1. That is, these transistors Q5 and Q8 are transistors that discharge the node N1, respectively, controlled based on the level of the node N1 inverted by the first and second inverters.

The output of the first inverter is the gate node of the output is a pull-down transistor transistor Q2 to the output terminal OUT of the unit shift register SR k discharge (pull-down) (node N2). That is, the transistor Q2 is also controlled based on the level obtained by inverting the level of the node N1 by the first inverter. Therefore, the first inverter also functions as a “pull-down drive circuit” (corresponding to the inverter composed of the transistors M6 and M7 in FIG. 17 of Patent Document 2) for driving the output pull-down transistor (transistor Q2). On the other hand, the gate of the transistor Q7, which is another output pull-down transistor connected in parallel to the transistor Q2, is connected to the second clock terminal CK2.

Next, the configuration of the unit shift registers SR 1 and SR n which are the foremost stage and the last stage of the gate line driving stage will be described with reference to FIGS. As can be seen from FIGS. 3 and 5, the unit shift registers SR 1 and SR n both have the same circuit configuration, which is similar to the intermediate unit shift register SR k described above. That is, the unit shift registers SR 1 and SR n are connected to the intermediate unit shift register SR k between the node N1 and the first power supply terminal S1, and the gate of the transistor Q10 is connected to the reset terminal RST. Is further provided.

Next, the configuration of the dummy stages SRD1 and SRD2 will be described. As can be seen from FIGS. 3 and 5, the dummy stage SRD1, SRD2 is both have the same circuit configuration, they are also similar to the unit shift register SR k of the intermediate stage. That is, the dummy stage SRD1, SRD2, compared circuitry of the unit shift register SR k of the intermediate stage, a second inverter (capacitive element C3 and the transistor Q9) and the transistor Q8 is omitted, and, instead of the transistors Q3, Q4 follows Transistors Q3D and Q4D.

  The transistors Q3D and Q4D are both connected between the node N1 and the input terminal IN. Among them, the gate of the transistor Q3D is connected to the input terminal IN (that is, the transistor Q3D is diode-connected so that the input terminal IN side is an anode and the node N1 side is a cathode). Thus, the transistor Q3D functions to charge the node N1 in accordance with a signal input to the input terminal IN. On the other hand, the gate of the transistor Q4D is connected to the reset terminal RST. Therefore, the transistor Q4D functions to discharge the node N1 in accordance with the clock signal CLK when the input terminal IN is at L level.

  An operation of the gate line driving circuit 30 according to the first embodiment will be described. In the following, for the sake of simplicity, it is assumed that the clock signals CLK and / CLK, the first and second control signals STn and STr, and the first and second voltage signals Vn and Vr are equal to each other in H level and L level. The H level potential is the high potential side power supply potential VDD, and the L level potential is the low potential side power supply potential VSS. The potential VSS is 0V. Furthermore, it is assumed that the threshold voltages of the transistors constituting the unit shift register SR and the dummy stages SRD1 and SRD2 are all equal, and the value is Vth.

  In the following, for convenience of explanation, an example is shown in which a certain interval is provided between the active period of the clock signal CLK (the period when it is at the H level) and the active period of the clock signal / CLK. Good. That is, a two-phase clock may be used in which the clock signal / CLK falls simultaneously with the rise of the clock signal CLK and the clock signal / CLK rises simultaneously with the fall of the clock signal CLK.

First, the operation at the time of forward scanning of the k-th unit shift register SR k which is an intermediate stage of the gate line driving stage will be described with reference to FIG. During forward scanning, the first voltage signal Vn supplied from the voltage signal generator 33 is at the H level (VDD), and the second voltage signal Vr is at the L level (VSS).

Here, the first clock terminal CK1 of the unit shift register SR k is inputted clock signal CLK as shown in FIG. 4, it is assumed that the clock signal / CLK is input to the second clock terminal CK2 (FIG. 2 Equivalent to the odd number of stages). Also, the output signal of the i-th unit shift register SR i is represented as G i .

As an initial state, a state node N1 of the unit shift register SR k is L level has not been charged (the node N1 is referred to the state of the L level and "reset state") is assumed. Since the transistors Q6 and Q9 are off when the node N1 is at the L level, the nodes N2 and N3 are in the floating state, but both are assumed to be at the L level in the initial state. At this time, the clock signals CLK and / CLK are both at the L level.

Then, it is assumed that the output signal G k-1 is output from the previous unit shift register SR k-1 and input to the first input terminal IN1 of the unit shift register SR 1 at the rising timing of the clock signal / CLK.

Then, in the unit shift register SR k , the transistor Q3 is turned on, and the node N1 is charged and becomes H level (VDD−Vth) (a state where the node N1 is at the H level is referred to as a “set state”). Accordingly, the transistor Q1 is turned on. At this time, since the clock signal CLK is at the L level, the output terminal OUT becomes the L level of low impedance when the transistor Q1 is turned on. Further, since the clock signal / CLK is at the H level, the transistor Q7 is turned on, and this also serves to bring the output terminal OUT to the L level with a low impedance.

  At this time, the first inverter composed of the capacitive element C2 and the transistor Q6 is not supplied with power (clock signal CLK) and is in an inactive state. However, since the transistor Q6 is turned on when the node N1 becomes H level, the node N2, which is the output terminal, becomes L level with low impedance. Therefore, the transistors Q2 and Q5 are kept off.

  On the other hand, the power supply (clock signal / CLK) is supplied to the second inverter composed of the capacitive element C3 and the transistor Q9, so that the second inverter is activated. Since the node N1 that is the input terminal is at the H level, the transistor Q9 is turned on, and the node N3 that is the output terminal is at the L level with low impedance. Therefore, the transistor Q8 is kept off.

After that, when the clock signal / CLK and the output signal G k-1 of the previous stage become L level, the transistor Q3 is turned off, but the node N1 is maintained at H level (VDD−Vth) in a floating state. The transistor Q7 is also turned off, but the transistor Q1 is kept on, so that the output terminal OUT is kept at a low impedance L level. At this time, since the first and second inverters are inactivated, the nodes N2 and N3, which are their output terminals, both maintain the L level, and the transistors Q5 and Q8 maintain OFF.

Next, when the clock signal CLK rises, the first inverter is activated. However, since the node N1 is at the H level, the transistor Q6 is kept on, and the node N2 is maintained at the L level with low impedance. That is, at this time, the transistor Q1 is on and the transistors Q2 and Q7 are off. Therefore, the level of the output terminal OUT (output signal G k ) rises to the H level with the rise of the clock signal CLK. When the level of the output terminal OUT rises, the level of the node N1 is boosted due to the coupling between the gate-channel capacitance of the transistor Q1 and the capacitive element C1.

By boosting the level of the node N1, the driving capability of the transistor Q1 is kept large even while the output signal Gk is being output. Since the transistor Q1 performs a non-saturation operation, the level of the output signal G k reaches up to the same VDD to H level of the clock signal CLK. As a result, the gate line GL k is selected. Hereinafter, a period during which the unit shift register SR i outputs the output signal G i, "selection period" of the unit shift register SR i or the gate line GL i, the others referred to as "non-selection period".

Then, when the clock signal CLK becomes L level, the output signal G k also becomes L level (VSS) following it, and the selection period of the gate line GL k ends. Also with the fall of the output signal G k, the level of the node N1 returns to VDD-Vth.

Next, when the clock signal / CLK rises, the output signal G k + 1 of the next unit shift register SR k + 1 becomes H level at this timing. Then the transistor Q4 of the unit shift register SR k is turned on, to discharge the node N1 to the L level of low impedance. That is, the unit shift register SR k returns to the reset state. Thereby, the transistor Q1 is turned off, but the transistor Q7 is turned on almost at the same time, so that the output terminal OUT is maintained at the L level of low impedance.

  At this time, since the first inverter is inactive, the node N2 does not change from the L level even when the node N1 becomes the L level. Therefore, the transistors Q2 and Q5 are kept off. On the other hand, since the second inverter is in the active state, when the node N1 that is the input terminal becomes L level and the transistor Q9 is turned off, the node N3 that is the output terminal becomes H level. Therefore, the transistor Q8 is turned on.

When the clock signal / CLK and the next stage output signal G k + 1 become L level, the transistors Q4 and Q7 are turned off. Since the second inverter is also deactivated, the node N3 becomes L level and the transistor Q8 is also turned off.

  However, immediately after that, when the clock signal CLK becomes H level, the first inverter is activated, the node N2 which is the output terminal thereof becomes H level, and the transistors Q2 and Q5 are turned on, so that the output terminal OUT and the node N1 Both are set to L level with low impedance.

  Thereafter, when the clock signal CLK becomes L level, the first inverter is deactivated and the transistors Q2 and Q5 are turned off. However, immediately after that, when the clock signal / CLK becomes H level, the transistor Q7 is turned on. Since the second inverter is activated and the transistor Q8 is turned on, both the output terminal OUT and the node N1 are at the L level with low impedance.

Thereafter, until the output signal G k−1 of the previous stage is input to the first input terminal IN1 again (that is, until the selection period of the unit shift register SR k in the next frame), the transistor Q2 is active during the active period of the clock signal CLK. , Q5 are turned on, and the transistors Q7, Q8 are turned on alternately during the active period of the clock signal / CLK. That is, during the non-selection period, both the output terminal OUT and the node N1 are maintained at the L level with low impedance.

The operation of the unit shift register SR k during the above-described forward scanning will be described together. When the previous stage output signal G k−1 is input to the first input terminal IN1, the transistor Q3 is turned on and the node N1 becomes H level. That is, the unit shift register SR k is set. Then, node N2 that is the output terminal of the first inverter (capacitance element C2 and transistor Q6) and node N3 that is the output terminal of the second inverter (capacitance element C3 and transistor Q9) are both fixed to the L level. As a result, transistors Q2, Q5 and Q8 are turned off. Therefore, when the clock signal CLK of the first clock terminal CK1 next becomes H level, the output signal Gk is output from the output terminal OUT (the second clock terminal CK2 has a phase different from that of the first clock terminal CK1). Since the clock signal / CLK is input, the transistor Q7 is off at this time).

When the next-stage output signal G k + 1 is input to the second input terminal IN2, the node N1 becomes L level. That is, the unit shift register SR k is reset. In this state, node N2 is at H level while the first inverter is activated by clock signal CLK, and node N3 is at H level while the second inverter is activated by clock signal / CLK. That is, nodes N2 and N3 alternately become H level in synchronization with clock signals CLK and / CLK. Therefore, the output terminal OUT and the node N1 in the non-selected period are discharged (pulled down) by the transistor Q5 during the active period of the clock signal CLK, and discharged by the transistor Q8 during the active period of the clock signal / CLK. Accordingly, the node N1 during most of the non-selection period is at the L level with low impedance.

On the other hand, the transistor Q2 that pulls down the output terminal OUT is driven by a first inverter that is activated by the clock signal CLK. The clock signal / CLK is input to the gate of the transistor Q7. Therefore, in the non-selection period, the output terminal OUT is alternately discharged by the transistors Q2 and Q7, and the output terminal OUT becomes L level with low impedance for most of the period. Accordingly, the output signal G k is not activated during that time.

Thus a plurality of unit shift registers SR operating cascaded as shown in FIG. 2, when constituting the gate line driving circuit 30, first as a start signal inputted to the first input terminal IN1 of the unit shift register SR 1 The output signals G 1 , G 2 ,... Are sequentially output at the timing synchronized with the clock signals CLK, / CLK as shown in the timing chart of FIG. Thereby, the gate line driving circuit 30 can drive the gate lines GL1, GL2, GL3... In this order in a predetermined scanning cycle.

As described above, in the unit shift register SR k of the present embodiment, the gates of the transistors Q2 and Q7 that discharge the output terminal OUT during the non-selection period are alternately set to the H level in synchronization with the clock signals CLK and / CLK. The That is, it is not DC biased. Thus the shift of their threshold voltages is suppressed, decrease in the driving capability has been suppressed, it is possible to prevent the generation of the output signal G k as a false signal more reliably.

  In the non-selection period, the gates of the transistors Q5 and Q8 are alternately set to the H level in synchronization with the clock signals CLK and / CLK. In other words, since the gates of the transistors Q5 and Q8 are not DC-biased, the threshold voltage shift, that is, the reduction in driving capability is suppressed.

  The transistors Q5 and Q8 function to maintain the node N1 in the non-selection period at the L level with low impedance. For example, when the node N1 is in a high impedance state, the level of the node N1 becomes unnecessary due to the coupling through the overlap capacitance between the drain and gate of the transistor Q1 when the clock signal CLK input to the first clock terminal CK1 rises. To rise. When the transistor Q1 is turned on by the increase, an output signal Gk as an erroneous signal is output. In the present embodiment, since the reduction in driving capability of the transistors Q5 and Q8 is suppressed, the generation of this erroneous signal can be prevented more reliably.

Next, the operation of the unit shift register SR k during reverse scanning will be described. When the gate line driving circuit 30 performs reverse scanning, the voltage signal generator 33 sets the first voltage signal Vn to L level (VSS) and the second voltage signal Vr to H level (VDD). That During a reverse scan, as opposed to when the forward shift, the transistor Q3 of the unit shift register SR k functions as a transistor for discharging (pulling down) the node N1, the transistor Q4 is charged (pulled up) the node N1 Functions as a transistor. Although such functional transistors Q3, Q4 is change places, the unit shift register SR k performs substantially the same operation as the forward scan.

That is, in the unit shift register SR k at the time of reverse scanning, when the next stage output signal G k + 1 is input to the second input terminal IN 2 , the transistor Q4 is turned on and the node N1 becomes H level. That is, the unit shift register SR k is set. Then, as in the forward scan, both the node N2 that is the output terminal of the first inverter (capacitance element C2 and transistor Q6) and the node N3 that is the output terminal of the second inverter (capacitance element C3 and transistor Q9) are both Fixed to L level. As a result, transistors Q2, Q5 and Q8 are turned off. Therefore, when the clock signal CLK of the first clock terminal CK1 next becomes H level, the output signal Gk is output from the output terminal OUT (the second clock terminal CK2 has a phase different from that of the first clock terminal CK1). Since the clock signal / CLK is input, the transistor Q7 is off at this time).

When the previous stage output signal G k-1 is input to the first input terminal IN1, the node N1 becomes L level. That is, the unit shift register SR k is reset. In this state, as in the forward scan, while the first inverter is activated by the clock signal CLK, the node N2 is at the H level, and while the second inverter is activated by the clock signal / CLK, Node N3 goes high. That is, nodes N2 and N3 alternately become H level in synchronization with clock signals CLK and / CLK. Therefore, the output terminal OUT and the node N1 in the non-selected period are discharged (pulled down) by the transistor Q5 during the active period of the clock signal CLK, and discharged by the transistor Q8 during the active period of the clock signal / CLK. Accordingly, the node N1 during most of the non-selection period is at the L level with low impedance.

Therefore, the gate line drive circuit 30 during the reverse scan, and the second control pulse STr as a start signal inputted to the second input terminal IN2 of the unit shift register SR n a trigger, a timing diagram shown in FIG. 7 As described above, the output signals G n , G n−1 , G n−2 ,... Are output in order at the timing synchronized with the clock signals CLK and / CLK. As a result, the gate line driving circuit 30 can drive the gate lines GL n , GL n−1 , GL n−2 ,... In this order, that is, in the order opposite to the forward shift.

The above-described light of the operation of the unit shift register SR k of intermediate stages and, in the forward scanning, the operation at the first stage and the last stage unit of the shift register SR 1, SR n and dummy stage SRD1, SRD2.

When the dummy signal D1 is at the L level, the transistor Q10 of the unit shift register SR 1 is turned off, the unit shift register SR 1 therebetween operates similarly to unit shift register SR k of the intermediate stage. Thus as shown in FIG. 6, with the rise of the clock signal / CLK, when the first control signal STn as the start signal is input to the input terminal IN of the unit shift register SR 1, then the timing of the clock signal CLK becomes H level Thus, the output signal G 1 is output from the unit shift register SR 1 . The output signal G 1 is input to the first input terminal IN 1 of the unit shift register SR 2 and also input to the input terminal IN of the dummy stage SRD 1.

At the rising edge of the clock signal CLK, the the output signal G 1 to the input terminal IN of the dummy stage SRD1 is input, the transistor Q3D are turned on. The gate of the transistor Q4D is the clock signal CLK via the reset terminal RST is input, at this time the transistor Q4D the output signal G 1 of the same-phase source is input is not turned on. Therefore, the node N1 is charged to the H level (VDD−Vth) by the transistor Q3D, and the transistor Q1 is turned on. That is, the dummy stage SRD1 is set. At this time, the first inverter (capacitance element C2 and transistor Q6) of the dummy stage SRD1 is inactive, but since the transistor Q6 is turned on when the node N1 becomes H level, the node N2 has low impedance and L level. become. Therefore, the transistor Q2 is turned off.

When the clock signal CLK and the output signal G 1 is at the L level, the transistor Q3D, Q 4 D is turned off. Since the first inverter (capacitance element C2 and transistor Q6) is inactive and the node N2 is at L level, the transistor Q5 is also off. Therefore, the node N1 of the dummy stage SRD1 is maintained at the H level in a floating state.

Next, when the clock signal / CLK becomes H level, the dummy signal D1 is output from the dummy stage SRD1. Dummy signal D1 is input to the reset terminal RST of the unit shift register SR 1, the transistor Q10 of the unit shift register SR 1 is turned on. As a result, the node N1 of the unit shift register SR 1 becomes L level, the unit shift register SR 1 is returned to the reset state. As a result, the output signal G 1 is maintained at the L level until the selection period of the unit shift register SR 1 in the next frame.

In dummy stage SRD1 after outputting dummy signal D1, the first inverter turns on transistors Q2 and Q5 at the activation timing of clock signal / CLK. The transistors Q7 and Q4D are turned on at the activation timing of the clock signal CLK. That period until the output signal G 1 to the frame period of the next becomes H level, the node N1 of the dummy stage SRD1 is maintained are discharged alternately by the transistor Q 4 D, Q5 to L level, also the output terminal OUT, the transistor Q2, They are alternately discharged by Q7 and maintained at the L level. Therefore, the dummy signal D1 is not output during that time.

Incidentally, at the same timing as the dummy signal D1 is input to the reset terminal RST of the unit shift register SR 1, the second input terminal IN2 of the unit shift register SR 1, the output signal G 2 of the unit shift register SR 2 is Entered. Therefore, the node N1 of the unit shift register SR 1 is discharged by the transistor Q4. Therefore, theoretically Needless to dummy stage SRD1 during forward scan outputs a dummy signal D1, it is possible to the unit shift register SR 1 in reset state. The reason why such an operation is performed in this embodiment will be described later.

Thereafter, after the output signal G 1 is output from the unit shift register SR 1 , the unit shift registers SR 2 , SR 3 ,..., At timing synchronized with the clock signals CLK, / CLK, as shown in FIG. Output signals G 2 , G 3 ,..., G n are sequentially output from SR n .

When the dummy signal D2 is at the L level, the transistor Q10 of the unit shift register SR n is off, the unit shift register SR n therebetween, operates similarly to the unit shift register SR k of the intermediate stage. Therefore, as shown in FIG. 6, when the output signal G n-1 is input to the input terminal IN of the unit shift register SR n with the rise of the clock signal CLK, the unit becomes the next timing when the clock signal / CLK becomes H level. An output signal G n is output from the shift register SR n . The output signal G n is input to the second input terminal IN2 of the unit shift register SR n−1 and also input to the input terminal IN of the dummy stage SRD2.

When the output signal G n is input to the input terminal IN of the dummy stage SRD2, in the dummy stage SRD2, the transistor Q3D is turned on and the node N1 is charged. The clock signal / CLK supplied to the reset terminal RST is input to the gate of the transistor Q4D of the dummy stage SRD2, while the output signal Gn having the same phase as the clock signal / CLK is input to the source of the transistor Q4D. Therefore, at this time, the transistor Q4D is not turned on. Accordingly, the node N1 of the dummy stage SRD2 is charged to the H level (VDD−Vth) by the transistor Q3D. That is, the dummy stage SRD2 is set and the transistor Q1 is turned on.

When the clock signal / CLK and the output signal G n become L level, the transistors Q3D and Q4D of the dummy stage SRD2 are turned off. Since the first inverter (capacitance element C2 and transistor Q6) is inactive, transistor Q5 is also off. Therefore, the node N1 of the dummy stage SRD2 is maintained at the H level in a floating state.

Next, when the clock signal CLK becomes H level, the dummy signal D2 is output from the dummy stage SRD2. Dummy signal D2 is inputted to the reset terminal RST of the unit shift register SR n, transistor Q10 of the unit shift register SR n is turned on. As a result, the node N1 of the unit shift register SR n becomes L level, the unit shift register SR n returns to the reset state.

In the dummy stage SRD2 after outputting the dummy signal D2, the first inverter turns on the transistors Q2 and Q5 at the activation timing of the clock signal CLK. Transistors Q7 and Q4D are turned on at the activation timing of clock signal / CLK. That is, during the period until the output signal G n becomes H level in the next frame period, the node N1 of the dummy stage SRD1 is alternately discharged by the transistors Q4D and Q5 and maintained at the L level. They are alternately discharged by Q7 and maintained at the L level. Therefore, the dummy signal D2 is not output during that time.

As described above, the unit shift register SR n includes the reset terminal RST and the transistor Q10 for setting it to the reset state, and the dummy signal D2 output from the dummy stage SRD2 is input thereto. It can function as an end signal during forward scanning. As a result, the gate line driving circuit 30 can operate only with the start signal.

  In the dummy stages SRD1 and SRD2 during which the dummy signals D1 and D2 are not output, the gates of the transistors Q4D and Q5 that discharge the node N1 and the gates of the transistors Q2 and Q7 that discharge the output terminal OUT are clock signals. Biased alternately in synchronization with CLK and / CLK. That is, since it is not continuously biased, those threshold voltage shifts, that is, a decrease in driving capability can be suppressed. Therefore, the node N1 and the output terminal OUT can be more reliably maintained at the L level with low impedance, and generation of the dummy signal D2 as an erroneous signal can be prevented.

Note that when the gate line driving circuit 30 performs reverse scanning, the first voltage signal Vn becomes L level (VSS), the second voltage signal Vr becomes H level (VDD), and the second control pulse. STr as a start signal is input to the second input terminal IN2 of the unit shift register SR n. As a result, the signal shift in the gate destination drive stage is reversed, but basically the dummy stages SRD1 and SRD2 themselves perform the same operation regardless of the scanning direction.

That is, in the reverse scanning, the dummy stage SRD1 outputs a dummy signal D1 at the next timing of the output signal G 1 is outputted, the dummy stage SRD2 is the next timing of the output signal G n is outputted A dummy signal D2 is output. Dummy signal D1 at the time of backward scanning functions as an end signal of the transistor Q10 of the unit shift register SR 1 of the final stage of the reverse scan is turned on to the unit shift register SR 1 reset state.

As described above, in the present embodiment, the unit shift registers SR 1 and SR n are provided with the reset terminal RST for setting each of them, and the dummy signals D1 and D2 are input respectively. Therefore at the time of forward scan, the dummy signal D2 to the unit shift register SR n can function as an end signal to the reset state and at the time of reverse scan end signal to the unit shift register SR 1 in reset state Can function as. As a result, the gate line driving circuit 30 can operate with only one type of start signal during forward scanning and backward scanning.

Note that the reverse scan, at the same timing as the dummy signal D2 is input to the reset terminal RST of the unit shift register SR n, the first input terminal IN2 of the unit shift register SR n is unit shift register SR n-1 Output signal G n-1 is input. Therefore, the node N1 of the unit shift register SR n is discharged by the transistor Q3. Therefore, theoretically Needless to dummy stage SRD2 during reverse scan outputs a dummy signal D2, the unit shift register SR 1 can be in the reset state.

  As described above, this is the same for the dummy signal D1 during forward scanning. That is, the dummy signal D1 at the time of forward scanning and the dummy signal D2 at the time of backward scanning are not necessarily required for the operation of the gate destination drive stage. However, in this embodiment, they are output intentionally. The reason for this will be described below.

  For example, when the dummy signal S1 is not output from the dummy stage SRD1 during forward scanning, the output terminal OUT, which is the source of the transistor Q1 of the dummy stage SRD1, is always fixed to the L level by the transistors Q2 and Q7. become. The gate (node N1) of the transistor Q1 is always fixed at the L level by the transistor Q5. Therefore, the gate of the transistor Q1 of the dummy stage SRD1 is not biased to the H level, and no threshold voltage shift occurs in the transistor Q1.

  On the other hand, the transistor Q5 of the dummy stage SRD1 is repeatedly turned on and off according to the clock signal / CLK in order to maintain the node N1 at the L level. That is, the gate of the transistor Q5 is positively biased in an alternating manner by the clock signal / CLK. Since the gate of the transistor Q5 is not DC-biased, the threshold voltage shift is suppressed as described above, but a certain amount of shift occurs. As a result, the driving ability of the transistor Q5, that is, the ability to discharge (pull down) the node N1 is slightly reduced.

  In the dummy stage SRD1, the discharge of the node N1 by the transistor Q5 is caused by the coupling through the overlap capacitance between the drain and gate of the transistor Q1 at the rise of the clock signal / CLK input to the first clock terminal CK1. This is to prevent the level from rising unnecessarily. Therefore, when the discharge capability of node N1 in transistor Q5 decreases, the level increase of node N1 accompanying the rise of clock signal / CLK cannot be suppressed, and transistor Q1 is turned on to generate dummy signal D1 as an erroneous signal. become.

Sonaruto, Samatageraru in the unit shift register SR 1, the charge of the node N1 in response to the first control signal STn as the start signal by the transistor Q10D is turned on by the dummy signal D1 as false signal. In addition, when switching to the backward scanning is performed after that, in the unit shift register SR 1 , the charging of the node N1 according to the output signal G 2 is turned on by the transistor Q10D being turned on by the dummy signal D1 as an erroneous signal. Be disturbed. As a result, there arises a problem that the unit shift register SR 1 malfunctions.

This problem, even if the dummy signal D2 from the dummy stage SRD2 during reverse scan is prevented from being outputted, similarly occur in the dummy stage SRD2, malfunction of the unit shift register SR n is likely to occur in that case.

  On the other hand, in each stage of the gate line driving stage, the gate (node N1) of the transistor Q1 is periodically biased to the H level by charging via the transistor Q3 or Q4 and boosting when the output signal G is output. Therefore, a certain shift occurs in the threshold voltage. Although the shift of the threshold voltage in the transistor Q1 seems to cause a problem, the transistor Q1 is hardly turned on. Therefore, the malfunction due to the slight decrease in the discharge capability of the transistor Q5 as described above. There is an advantage of acting so as to be prevented.

  In each stage of the gate line driving stage, assuming that the threshold voltage shift occurs in both transistors Q1 and Q5, their dimensions (gate width, that is, channel width) are set so that the above malfunction does not occur. Is determined. This is because the overlap capacitance of the transistor Q1 is proportional to its gate width. The capacitance value of the boost capacitor C1 is also related to the phenomenon of the level increase of the node N1 due to the overlap capacitance between the drain and gate of the transistor Q1. This is because the capacitive element C1 functions as a stabilizing capacitor for the level of the node N1 when the level of the node N1 rises, and as the capacitance value increases, the level rise of the node N1 is suppressed.

  As described above, in each stage of the gate line driving stage, a threshold voltage shift occurs in both the transistors Q1 and Q5 in order to take measures against a rise in the level of the node N1 due to the overlap capacitance between the drain and gate of Q1. In consideration of the above, the gate width W (Q1) of the transistor Q1, the gate width W (Q5) of the transistor Q5, and the capacitance value C1 of the capacitive element C1 are set to have a certain relationship.

  Therefore, the dummy stage SRD1 during forward scanning and the dummy stage SRD2 during backward scanning do not output the dummy signals D1 and D2, respectively, so that the threshold voltage shift of the transistor Q1 in the dummy stages SRD1 and SRD2 is shifted. If it does not occur, the setting of the values of W (Q1), W (Q5), and C1 in each stage of the gate line driving stage cannot be applied to the dummy stages SRD1 and SRD2 as they are. That is, it is necessary to individually set the values of W (Q1), W (Q5), and C1 in the gate line driving stage and the dummy stages SRD1 and SRD2.

  In the present embodiment, dummy signals D1 and D2 are output once in one frame period to dummy stage SRD1 during forward scanning and dummy stage SRD2 during backward scanning as well as each stage of the gate line driving stage. As a result, in the dummy stages SRD1 and SRD2, the threshold voltage of the transistor Q1 is shifted as in the gate line driving stage.

  Similarly to the output signal G of the gate line driving stage, the dummy signals D1 and D2 have the same pulse width as one pulse width of the clock signals CLK and / CLK. That is, the dummy signals D1 and D2 and each of the output signals G of the gate line driving stage are output at the same frequency, and the active time (time to be H level, that is, pulse width), that is, duty ratio (active) within one frame period. The ratio of time to frame period length) is equal. Therefore, the shift amount of the threshold voltage of the transistor Q1 is substantially the same between the dummy stages SRD1 and SRD2 and the gate line driving stage.

By doing so, the values of W (Q1), W (Q5), and C1 can be made uniform in the gate line driving stage and the dummy stages SRD1, SRD2. That is, the value of the ratio of W (Q5) to W (Q1) and the value of the ratio of C1 to W (Q1) between each of the dummy stages SRD1 and SRD2 and each stage of the gate line driving stage, respectively. The following equations (1) and (2) can be made equal to each other. In the equations (1) and (2), [•] DM represents a value in the dummy stages SRD1 and SRD2, and [•] GD represents a value in the gate line driving stage.

[W (Q5) / W (Q1)] DM = [W (Q5) / W (Q1)] GD Formula (1)

[C1 / W (Q1)] DM = [Cl / W (Q1)] GD Formula (2)

  As described above, in the gate line driving circuit 30 according to the present embodiment, the dummy signal D2 output from the dummy stage SRD2 functions as an end signal during forward scanning, and therefore it is not necessary to input an end signal from the outside. . Therefore, during forward scanning, the start signal generator 32 causes the first control signal STn to function as a start signal, and fixes the second control signal STr to L level (see FIG. 6). Further, since the dummy signal D1 output from the dummy stage SRD1 functions as an end signal during backward scanning, it is not necessary to input an end signal from the outside. Therefore, at the time of backward scanning, the start signal generator 32 causes the second control signal STr to function as a start signal and fixes the first control signal STn to the L level (FIG. 7).

  Since the signal fixed to the L level can be supplied from the low potential side power supply potential VSS, the start signal generator 32 only has to generate one type of start signal at the time of forward scanning and backward scanning. It will be good. In this way, the number of signals for driving the gate line driving circuit 30 is reduced, which can contribute to cost reduction.

  Further, in each of the dummy stages SRD1, SRD2 and the gate line driving stage, in order to prevent an erroneous signal from being output, the discharge of the output terminal OUT and the gate of the transistor Q1 (node N1) during each non-selection period. Is done. The output terminal OUT is discharged when the transistors Q2 and Q7 are alternately turned on in synchronization with the clock signals CLK and / CLK. The discharge of the node N1 is alternately turned on in synchronization with the clock signals CLK and / CLK at the gate line driving stage, and the transistors Q5 and Q8 are alternately turned on at the dummy stages SRD1 and SRD2, respectively. Is done.

  That is, the gates of the transistors Q2, Q5, Q4D, Q7, and Q8 are not continuously biased, and the threshold voltage shift is suppressed. As a result, a decrease in driving capability (discharge capability) of the transistors Q2, Q5, Q4D, Q7, and Q8 can be suppressed, and malfunction of the gate line driving circuit 30 can be prevented.

  In the present embodiment, the clock signals CLK and / CLK, the first and second control signals STn and STr, and the first and second voltage signals Vn and Vr have the same potential at the H level and the L level, respectively. However, this is not necessarily the case, and any value within a range that can sufficiently drive each transistor of the gate line driving circuit 30 may be used.

<Embodiment 2>
FIGS. 8A and 8B are circuit diagrams showing configurations of the dummy stages SRD1 and SRD2 according to the second embodiment of the present invention. The dummy stages SRD1 and SRD2 in FIGS. 8A and 8B are connected to the circuit of the dummy stage SRD1 shown in FIG. 3 and the dummy stage SRD2 shown in FIG. 5 with respect to the node N1 and the first power supply terminal S1, respectively. A transistor Q10D connected between them is further provided.

  The gate of the transistor Q10D is connected to a reset terminal RST1 provided separately from the reset terminal RST. Hereinafter, in the second embodiment and the third embodiment described later, the reset terminals RST of the dummy stages SRD1 and SRD2 are referred to as “first reset terminals” and the reset terminals RST1 are referred to as “second reset terminals”. The first control signal STn is input to the second reset terminal RST1 of the dummy stage SRD1, and the second control signal STr is input to the second reset terminal RST1 of the dummy stage SRD2.

  Accordingly, the transistor Q10D of the dummy stage SRD1 is turned on in response to the start signal (first control signal STn) during forward scanning, and discharges the node N1 of the dummy stage SRD1. Further, the transistor Q10D of the dummy stage SRD2 is turned on in response to the start signal (second control signal STr) at the time of backward scanning, and discharges the node N1 of the dummy stage SRD2.

For example, in the unit shift register SR 1 of the forward scanning, when the start signal to the input terminal IN (first control signal STn) is the node N1 is inputted is charged, the dummy signal D1 is the reset terminal of the false signal RST Is input to the node N1, the node N1 is discharged by the transistor Q10. In this case, the unit shift register SR 1 cannot be set and cannot operate normally. In the unit shift register SR n at the time of backward scanning, the same problem occurs when the dummy signal D2 as an erroneous signal is generated when the start signal (second control signal STr) is input.

In this embodiment, during forward scanning, the timing of the start signal to the unit shift register SR 1 (first control signal STn) is input, the transistor Q1 of the dummy stage SRD1 is surely turned off. Therefore, the dummy signal D1 as an erroneous signal is prevented from being output at that time. Also in the reverse scanning, the timing of the start signal to the unit shift register SR n (second control signal STr) is input, the dummy signal D2 as an error signal is output is prevented. Therefore, the above problem does not occur.

  However, in this embodiment, it should be noted that the area occupied by the circuits of the dummy stages SRD1, SRD2 is increased by the amount of the signal wiring of the transistor Q10D and the first and second control signals STn, STr.

  Note that the transistor Q10D of the dummy stage SRD2 at the time of forward scanning is always turned off (the second control signal STr at the time of forward scanning is fixed to L level), which affects the operation of the dummy stage SRD2. do not do. Similarly, the transistor Q10D of the dummy stage SRD1 at the time of backward scanning is always off (the first control signal STn at the time of backward scanning is fixed at L level). It does not affect.

<Embodiment 3>
FIGS. 9A and 9B are circuit diagrams showing configurations of dummy stages SRD1 and SRD2 according to Embodiment 3 of the present invention. The dummy stages SRD1 and SRD2 shown in FIGS. 9A and 9B are connected to the circuits of the dummy stages SRD1 and SRD2 shown in FIGS. 8A and 8B, respectively, with respect to the node N1 and the first power supply terminal S1. A transistor Q11D connected between them is further provided. The gate of the transistor Q11D is connected to a third reset terminal RST2 provided separately from the first reset terminal RST and the second reset terminal RST1. The third reset terminal RST2 dummy stage SRD1 is connected to the output terminal OUT of the unit shift register SR 2, third reset terminal RST2 dummy stage SRD2 is connected to the output terminal OUT of the unit shift register SR n-1 .

  The drain of the transistor Q3D of the dummy stage SRD1 is connected to the second voltage signal terminal T2 to which the second voltage signal Vr is supplied. That is, the transistor Q3D of the dummy stage SRD1 is connected between the node N1 and the second voltage signal terminal T2, and the gate is connected to the input terminal IN. On the other hand, the drain of the transistor Q3D of the dummy stage SRD2 is connected to the first voltage signal terminal T1 to which the first voltage signal Vn is supplied. That is, the transistor Q3D of the dummy stage SRD2 is connected between the node N1 and the first voltage signal terminal T1, and the gate is connected to the input terminal IN.

For example during the forward scan, the node N1 of the dummy stage SRD1 is discharged by the transistor Q10D in response to the start signal (first control signal STn), followed by being discharged by the transistor Q3D in accordance with the output signal G 1 (Forward the second voltage signal Vr are the time of scanning is L level), it is discharged by the transistor Q11D further accordance with the output signal G 2. Therefore, the dummy stage SRD1 is not set. Therefore, as shown in FIG. 10, the dummy signal D1 is not output from the dummy stage SRD1 during forward scanning.

Note that the node N1 of the dummy stage SRD2 during forward scanning is discharged by the transistor Q11D in response to the output signal G n−1 , but when the output signal G n is subsequently input, the transistor Q3D is turned on and charged. (Because it is during forward scanning, the first voltage signal Vn is at H level). Therefore, the set state is established at the input timing of the output signal Gn , and the dummy signal D2 as the end signal can be output.

In reverse scanning, the node N1 of the dummy stage SRD2 is discharged by the transistor Q10D according to the start signal (second control signal STr), and then discharged by the transistor Q3D according to the output signal Gn (reverse direction). The first voltage signal Vn is at L level during scanning), and further, the transistor Q11D discharges according to the output signal G n−1 . Therefore, the dummy stage SRD2 is not set. Accordingly, as shown in FIG. 11, the dummy signal D2 is not output from the dummy stage SRD2 during reverse scanning.

Node N1 of the dummy stage SRD1 during reverse scan also is discharged by the transistor Q11D in accordance with the output signal G 2, when followed by the output signal G 1 is inputted is charging transistor Q3D is turned on ( Since it is during backward scanning, the second voltage signal Vr is at H level). Therefore becomes the set state at the input timing of the output signals G 1, it outputs the dummy signal D1 as an end signal.

As described in the first embodiment, the dummy signal D1 during forward scanning and the dummy signal D2 during backward scanning are not necessarily required for the operation of the unit shift registers SR 1 and SR n , so that they are output. Even if not, there is no effect on the operation of the gate line driving stage. The operation of transistor Q10D is as described in the second embodiment.

Here, the operation of the transistor Q11D will be described. As described in the first embodiment, for example, when the dummy stage SRD1 does not output the dummy signal D1 during forward scanning, the threshold voltage of the transistor Q5 shifts in the dummy stage SRD1, but the threshold value of the transistor Q1 The voltage does not shift. Therefore, dummy signal D1 as an erroneous signal is likely to be output from dummy stage SRD1 at the activation timing of clock signal / CLK. Sonaruto, when switching to the subsequent backward scanning, charging is prevented at the node N1 in response to the output signal G 2 in the unit shift register SR 1, the unit shift register SR 1 is malfunctioning.

Transistor Q11D of dummy stages SRD1 is provided in order to prevent malfunction of the unit shift register SR 1 during the reverse scan. In other words, at the timing when the output signal G 2 is output, prevents the level of the node N1 of the dummy stage SRD1 rises, it is the dummy signal D1 as false signal is prevented from being output.

Similarly, transistor Q11D of dummy stages SRD2 is provided in order to prevent malfunction of the unit shift register SR n during forward scan. That is, the level of the node N1 in the dummy stage SRD2 is prevented from rising at the timing when the output signal G n-1 during forward scanning is output, and the dummy signal D2 as an erroneous signal is prevented from being output. Yes.

  As described above, in the dummy stages SRD1 and SRD2 of the present embodiment, the gate (node N1) of the transistor Q1 is almost always at a low impedance L level, so that the transistor Q1 can be reliably kept off. . Therefore, generation of dummy signals D1 and D2 as erroneous signals can be prevented without causing a threshold voltage shift of transistor Q1 as in the first embodiment.

  However, it should be noted that the area occupied by the circuits of the dummy stages SRD1 and SRD2 is increased by the amount of the wiring region of the transistor Q11D and the first and second voltage signals Vn and Vr as compared with the first and second embodiments. .

<Embodiment 4>
FIGS. 12A and 12B are circuit diagrams showing configurations of dummy stages SRD1 and SRD2 according to the fourth embodiment of the present invention. The dummy stages SRD1 and SRD2 in FIGS. 12A and 12B have transistors Q10D and Q11D, respectively, with respect to the circuits of the dummy stages SRD1 and SRD2 in the third embodiment shown in FIGS. 9A and 9B. Excluded. Accordingly, the area occupied by the circuits of the dummy stages SRD1 and SRD2 can be made smaller than that in the third embodiment.

  In the dummy stages SRD1 and SRD2 of the present embodiment, as in the third embodiment, the dummy stage SRD1 is not set during forward scanning, so the dummy signal D1 is not output, and the dummy stage SRD2 is set during backward scanning. Since the state is not reached, the dummy signal D2 is not output.

  Therefore, the threshold voltage shift of the transistor Q1 in the dummy stages SRD1 and SRD2 does not occur. However, since dummy stages SRD1 and SRD2 of this embodiment do not have transistors Q10D and Q11D, if threshold voltage shift does not occur in transistor Q1, discharge of node N1 due to threshold voltage shift of transistor Q5. There is a concern that dummy signals D1 and D2 as erroneous signals are likely to be generated due to a decrease in capability.

  As described in the first embodiment, in each stage of the gate line driving stage, the gate widths (W (Q1), W (Q5)) and capacitances of the transistors Q1 and Q5 are prevented so that they do not generate an error signal. The capacitance value (C1) of the element C1 is set to have a predetermined relationship.

Therefore, in the present embodiment, the values are set so that the dummy stages SRD1 and SRD2 are less likely to generate an error signal than the gate line driving stage. That is, in the dummy stages SRD1 and SRD2, the ratio between the drain-gate overlap capacitance of the transistor Q1 (proportional to the gate width of the transistor Q1) and the driving capability of the transistor Q5 (proportional to the gate width of the transistor Q5). Is set sufficiently larger than that of the gate line driving stage. That is, the relationship of the following formula (3) is satisfied. Here, [•] DM represents a value in the dummy stages SRD1, SRD2, and [•] GD represents a value in the gate line driving stage.

[W (Q5) / W (Q1)] DM > [W (Q5) / W (Q1)] GD Formula (3)

  If each parameter is set so that the relationship of Expression (3) is satisfied, the discharge capability of the transistor Q5 in the dummy stages SRD1 and SRD2 becomes relatively high. Therefore, even if the threshold voltage shift does not occur in the transistor Q1 of the dummy stages SRD1 and SRD2, it is possible to suppress the level of the node N1 from rising unnecessarily. As a result, generation of dummy signals D1 and D2 as erroneous signals can be prevented.

  Alternatively, in the dummy stages SRD1 and SRD2, the ratio between the gate width of the transistor Q1 and the capacitance value (C1) of the capacitor C1 may be sufficiently larger than that of the gate line driving stage. That is, the relationship of the following formula (4) is satisfied. This also makes the dummy stages SRD1 and SRD2 less likely to generate an error signal than the gate line driving stage.

[C1 / W (Q1)] DM > [C1 / W (Q1)] GD Formula (4)

  Even if each parameter is set so that the relationship of Expression (4) is satisfied, the level increase of the node N1 of the dummy stages SRD1 and SRD2 can be suppressed, and the same effect as described above can be obtained.

<Embodiment 5>
FIG. 13 is a diagram showing a configuration of the gate line driving circuit 30 according to the fifth embodiment. 14 to 16 are diagrams showing specific circuit configurations of the gate line driving circuit 30. FIG. FIG. 14 shows the dummy stage SRD1 and the foremost stage (unit shift register SR 1 ) of the gate line driving stage, FIG. 15 shows the intermediate stage (unit shift register SR k ) of the gate line driving stage, and FIG. 16 shows the gate line driving. A final stage (unit shift register SR n ) and a dummy stage SRD2 are shown.

  As can be seen from FIGS. 14 to 16, each of the dummy stages SRD1, SRD2 and the gate line driving stage of the present embodiment has two transistors (output pull-down transistors) that discharge the output terminal OUT (transistors Q2A, Q2B) have. There are also two transistors (transistors Q5A and Q5B) for discharging the node N1.

  The frame signal generator 34 shown in FIG. 13 generates first and second frame signals VFR and / VFR for switching and operating these transistors Q2A, Q2B, Q5A, and Q5B. Each of the dummy stages SRD1 and SRD2 and the gate line driving stage has a first frame signal terminal TA to which the first frame signal VFR is input and a second frame signal terminal TB to which the second frame signal / VFR is input. doing.

The first frame signal VFR and the second frame signal / VFR are complementary signals. The first and second frame signals VFR, / VFR are preferably controlled so that the level is switched (alternated) during the blanking period between frames of the display image. The level is controlled to switch. The period may not be every frame, but may be an integer multiple thereof (for example, every 2 frames, every 3 frames, etc.). Since the gate line driving circuit 30 operates so as to repeatedly activate the gate lines GL 1 to GL n every frame period, the frame period of the video signal becomes the operation period.

With reference to FIG. 15, the configuration of the bidirectional unit shift register SR k which is an intermediate stage of the gate line driving stage will be described. The output stage of the unit shift register SR k includes a transistor Q1 connected between the output terminal OUT and the first clock terminal CK1, and transistors Q2A and Q2B both connected between the output terminal OUT and the first power supply terminal S1. It is comprised by. The transistor Q1 supplies a clock signal input to the first clock terminal CK1 to the output terminal OUT. Each of the transistors Q2A and Q2B discharges the output terminal OUT by supplying the potential of the first power supply terminal S1 to the output terminal OUT.

  Here, as shown in FIG. 15, a node connected to the gate of the transistor Q1 is defined as a node N1, a node connected to the gate of the transistor Q2A is defined as a node N2A, and a node connected to the gate of the transistor Q2B is defined as a node N2B.

  A capacitive element C1 is provided between the gate and source of the transistor Q1, that is, between the node N1 and the output terminal OUT. A transistor Q3 having a gate connected to the first input terminal IN1 is connected between the node N1 and the first voltage signal terminal T1, and a gate is connected between the node N1 and the first voltage signal terminal T1. A transistor Q4 connected to the second input terminal IN2 is connected. Further, between the node N1 and the first power supply terminal S1, a transistor Q5A having a gate connected to the node N2A and a transistor Q5B having a gate connected to the node N2B are connected.

  The transistor Q13A is connected between the first frame signal terminal TA and the node N2A, and the transistor Q13B is connected between the second frame signal terminal TB and the node N2B. Transistor Q13A has its gate connected to the drain (node N2B) of transistor Q13B, and transistor Q13B has its gate connected to the drain (node N2A) of transistor Q13A. That is, the transistor Q13A and the transistor Q13B have one main electrode (drain in this case) connected to the gates of each other so as to form a so-called flip-flop circuit.

  The transistor Q12A is diode-connected, and is connected between the node N2A and the first frame signal terminal TA. The transistor Q6A is connected between the node N2A and the first power supply terminal S1, and has a gate connected to the node N1. These transistors Q6A and Q12A constitute a ratio type inverter having the node N1 as an input terminal and the node N2A as an output terminal. That is, the transistor Q6A is set to have a sufficiently lower on-resistance than the transistor Q12A, and the L-level output potential of the inverter is a value determined by the ratio of the on-resistances. However, unlike the normal inverter, the inverter is supplied with the first frame signal VFR as its power source.

  The transistor Q12B is diode-connected, and is connected between the node N2B and the second frame signal terminal TB. The transistor Q6B is connected between the node N2B and the first power supply terminal S1, and has a gate connected to the node N1. These transistors Q6B and Q12B constitute a ratio type second inverter having the node N1 as an input terminal and the node N2B as an output terminal, but unlike a normal inverter, the second frame signal / VFR is supplied as its power supply. Has been.

  In the present embodiment, an inverter composed of transistors Q6A and Q12A is referred to as a “first inverter”, and an inverter composed of transistors Q6B and Q12B is referred to as a “second inverter”.

  The first inverter has a node N1 as an input end and a node N2A to which the gates of the transistors Q2A and Q5A are connected as an output end. Therefore, the transistors Q2A and Q5A are controlled based on the level obtained by inverting the level of the node N1 by the first inverter. The second inverter has the node N1 as an input end and the node N2B to which the gates of the transistors Q2B and Q5B are connected as an output end. Therefore, the transistors Q2B and Q5B are controlled based on the level obtained by inverting the level of the node N1 by the second inverter.

Next, the configuration of the unit shift registers SR 1 and SR n which are the foremost stage and the last stage of the gate line driving stage will be described. As can be seen from FIGS. 14 and 16, the unit shift registers SR 1 and SR n both have the same circuit configuration, which is similar to the intermediate unit shift register SR k described above. That is, the unit shift registers SR 1 and SR n are connected to the intermediate unit shift register SR k between the node N1 and the first power supply terminal S1, and the gate of the transistor Q10 is connected to the reset terminal RST. Is further provided.

The configuration of the dummy stages SRD1 and SRD2 will be described. As can be seen from FIGS. 14 and 16, dummy stage SRD1, SRD2 is both have the same circuit configuration, they are also similar to the unit shift register SR k of the intermediate stage. That is, the dummy stage SRD1, SRD2, compared circuitry of the unit shift register SR k of the intermediate stage, transistors Q3, instead of Q4 following transistor Q3D, those comprising Q 4 D.

  The transistors Q3D and Q4D are both connected between the node N1 and the input terminal IN. Among them, the gate of the transistor Q3D is connected to the input terminal IN (that is, the transistor Q3D is diode-connected so that the input terminal IN side is an anode and the node N1 side is a cathode). Thus, the transistor Q3D functions to charge the node N1 in accordance with a signal input to the input terminal IN. On the other hand, the gate of the transistor Q4 is connected to the reset terminal RST. Therefore, the transistor Q4D functions to discharge the node N1 in accordance with the clock signal CLK when the input terminal IN is at L level.

  An operation of the gate line driving circuit 30 according to the present embodiment will be described. Here, for simplicity, the clock signals CLK and / CLK, the first and second control signals STn and STr, the first and second voltage signals Vn and Vr, the first and second frame signals VFR and / VFR at the H level and The L level potentials are equal to each other, the H level potential is the high potential side power supply potential VDD, and the L level potential is the low potential side power supply potential VSS. The potential VSS is 0V. The levels of the first and second frame signals VFR and / VFR are switched to a blanking period for each frame. Further, it is assumed that the threshold voltages of the transistors constituting each unit shift register SR and dummy stages SRD1 and SRD2 are all equal, and the value is Vth.

First, the operation at the time of forward scanning of the k-th unit shift register SR k which is an intermediate stage of the gate line driving stage will be described with reference to FIG. During forward scanning, the first voltage signal Vn generated by the voltage signal generator 33 is at the H level (VDD), and the second voltage signal Vr is at the L level (VSS). Further, it is assumed that the clock signal CLK is input to the first clock terminal CK1 of the unit shift register SR k as shown in FIG. 15, and the clock signal / CLK is input to the second clock terminal CK2 (the odd number in FIG. 13). Equivalent to the step).

Assume that the first frame signal VFR is switched to the H level and the second frame signal / VFR is switched to the L level during the blanking period. Then, in the unit shift register SR k , the potential of the drain and gate (first frame signal terminal TA) of the transistor Q12A changes from VSS to VDD, and the transistor Q12A is turned on. That is, power is supplied to the first inverter composed of the transistors Q6A and Q12A, and the first inverter is activated. At this time, since the transistor Q5B is on and the node N1 is at the L level, the transistor Q6A is not turned on and the level of the node N2A rises.

  On the other hand, the potential of the drain and gate (second frame signal terminal TB) of the transistor Q12B changes from VDD to VSS. That is, no power is supplied to the second inverter composed of the transistors Q6B and Q12B. Since the transistor Q12B functions as a diode having the second frame signal terminal TB side as an anode and the node N2B side as a cathode, the charge at the node N2B is not discharged through the transistor Q6. However, as described above, the level of the node N2A is increased, and the source of the transistor Q13B (second frame signal terminal TB) is at the L level (VSS), so that the transistor Q13B is turned on and the node N2B becomes L Level (VSS). Accordingly, transistor Q13A is turned off, and node N2A is at the H level (VDD-Vth).

Thus, during the period in which the first frame signal VFR is at the H level and the second frame signal / VFR is at the L level, the second inverter is not activated, and the node N2B that is the output terminal is fixed at the L level. Therefore, the transistors Q2B and Q5B in the meantime are not biased and are in a resting state. That is, during this period, in this unit shift register SR k , a circuit equivalent to the bidirectional unit shift register shown in FIG. 17 of Patent Document 2 is constituted by the combination of transistors Q1, Q2A, Q3, Q4, Q5A, Q6A, and Q12A. The same operation is possible.

That is, when the output signal G k-1 in the previous stage becomes H level, it is input to the first input terminal IN1, and the transistor Q3 is turned on. At this time, the transistor Q5A is also turned on, but the on-resistance of the transistor Q3 is set sufficiently lower than the on-resistance of the transistor Q5A, the node N1 is at the H level (VDD-Vth), and the transistor Q1 is turned on. That is, the unit shift register SR k is set.

When node N1 becomes H level, node N2A becomes L level by the operation of the first inverter formed of transistors Q6A and Q12A. Accordingly, the transistors Q2A and Q5A are turned off. Thereafter, when the output signal G k-1 at the previous stage returns to the L level, the transistor Q3 is turned off, but the node N1 is in a floating state, so that the H level of the node N1 is maintained.

Since the transistor Q1 is on and the transistors Q2A and Q2B are off, the next time when the clock signal CLK becomes H level, the H level is transmitted to the output terminal OUT and the output signal Gk becomes H level. At this time, the level of the node N1 is boosted by a specific voltage due to coupling through the gate-channel capacitance of the capacitive element C1 and the transistor Q1. Accordingly, the source-gate voltage of the transistor Q1 is kept high, and the transistor Q1 is maintained at a low impedance.

Thereafter, when the clock signal CLK becomes L level and the clock signal / CLK becomes H level, the output signal G k + 1 of the shift register at the next stage becomes H level. Whereby the transistor Q4 of the unit shift register SR k is turned on, the node N1 becomes the L level. That is, the unit shift register SR k is reset. Accordingly, transistor Q6A is turned off and node N2A returns to the H level (VDD-Vth). Thereafter, this state is maintained until the levels of the first and second frame signals VFR, / VFR are inverted in the next blanking period.

  Then, when the first frame signal VFR becomes L level and the second frame signal / VFR becomes H level in the blanking period, the second inverter composed of the transistors Q6B and Q12B is activated and the node is inverted. N2B becomes H level. Accordingly, since the transistor Q13A is turned on and the first inverter is inactive, the node N2A becomes L level (VSS).

That is, during the period in which the first frame signal VFR is at the L level and the second frame signal / VFR is at the H level, the gates of the transistors Q2A and Q5A are not biased, and the transistors Q2A and Q5A are in a dormant state. The first inverter also does not operate because no power is supplied. Therefore, in the unit shift register SR k , a circuit equivalent to the bidirectional unit shift register shown in FIG. 17 of Patent Document 2 is configured by the combination of the transistors Q1, Q2B, Q3, Q4, Q5B, Q6B, and Q12B. Thus, the signal shift operation is performed.

On the other hand, when the gate line driving circuit 30 performs reverse scanning, the voltage signal generator 33 sets the first voltage signal Vn to L level (VSS) and the second voltage signal Vr to H level (VDD). . That is, when the reverse scan, as opposed to when the forward shift, the transistor Q3 of the unit shift register SR k functions as a transistor for discharging (pulling down) node N1, the transistor Q4 charges the node N1 (pull Function as a transistor to up).

Accordingly, during reverse scanning, the unit shift register SR k maintains the reset state while the next stage output signal G k + 1 is not input to the second input terminal IN2. In the reset state, since the transistor Q1 is off and one of the transistors Q2A and Q2B is on, the output terminal OUT (output signal G k ) is maintained at a low impedance L level (VSS). When the output signal G k + 1 is input to the second input terminal IN2, the unit shift register SR k is switched to the set state. Since the transistor Q1 is on and the transistors Q2A and Q2B are off in the set state, the output terminal OUT is at the H level and the output signal Gk is output while the clock signal CLK is at the H level. Thereafter, when the output signal G k−1 of the previous stage is input to the first input terminal IN1, the original reset state is restored.

As described above, the unit shift register SR k of FIG. 15 can perform the same operation as the conventional bidirectional unit shift register (FIG. 17 of Patent Document 2). Each time the first and second frame signals VFR and / VFR are inverted, the pair of the transistors Q2A and Q5A and the pair of the transistors Q2B and Q5B are alternately in a resting state, so that their gates are continuously biased. Is prevented. Therefore, it is possible to suppress the threshold voltage shift of the transistors Q2A and Q2B that discharge (pull down) the output terminal OUT and the transistors Q5A and Q5B that discharge the node N1 during the non-selection period. As a result, it is possible to prevent the output signal G k as an erroneous signal from being output from the unit shift register SR k .

The above-described light of the operation of the unit shift register SR k of intermediate stages and, in the forward scanning, the operation at the first stage and the last stage unit of the shift register SR 1, SR n and dummy stage SRD1, SRD2. The operation of the gate line driving circuit 30 of this embodiment is represented by the same timing chart as FIG. Here, it is assumed that the first frame signal VFR is at the H level and the second frame signal / VFR is at the L level.

When the dummy signal D1 is at the L level, the transistor Q10 of the unit shift register SR 1 is turned off, the unit shift register SR 1 during which operates similarly to unit shift register SR k of the intermediate stage. Therefore, as shown in FIG. 6, when the first control signal STn as the start signal is input to the input terminal IN of the unit shift register SR 1 with the rising edge of the clock signal / CLK, the next time the clock signal CLK becomes H level. The unit shift register SR 1 outputs an output signal G 1 . The output signal G 1 is input to the first input terminal IN 1 of the unit shift register SR 2 and also input to the input terminal IN of the dummy stage SRD 1.

In the dummy stage SRD1, when the output signal G 1 is inputted, the transistor Q3D are turned on. The gate of the transistor Q4, the clock signal CLK via the reset terminal RST is input, at this time the transistor Q4 is not turned on since the output signal G 1 of the same-phase source is input. Therefore, the node N1 is charged to the H level (VDD−Vth) by the transistor Q3D, and the transistor Q1 is turned on. That is, the dummy stage SRD1 is set.

When the clock signal CLK and the output signal G 1 is at the L level, the input terminal IN of the dummy stage SRD1 becomes L level. However, since the transistors Q3D and Q4D are turned off and the node N1 is at the H level, the node N2A that is the output terminal of the first inverter (transistors Q6A and Q12A) is at the L level, and the transistor Q5A is also off. . Since the second inverter (transistors Q6B and Q12B) is inactive, the node N2B, which is the output terminal, is at L level, and the transistor Q5B is also off. Therefore, the node N1 of the dummy stage SRD1 is maintained at the H level in a floating state.

At this time, the transistor Q1 of the dummy stage SRD1 is on, and the transistors Q2A and Q2B are off. Therefore, when the clock signal / CLK becomes H level next time, the dummy signal D1 is output from the dummy stage SRD1. Dummy signal D1 is input to the reset terminal RST of the unit shift register SR 1, the transistor Q10 of the unit shift register SR 1 is turned on. As a result, the node N1 of the unit shift register SR 1 becomes L level, the unit shift register SR 1 is returned to the reset state. As a result, the output signal G 1 is maintained at the L level until the selection period of the unit shift register SR 1 in the next frame.

  In the dummy stage SRD1 after the dummy signal D1 is output, the transistor Q4D is turned on and the node N1 is set to the L level when the clock signal CLK input to the reset terminal RST rises. When the node N1 becomes L level, the node N2A that is the output terminal of the first inverter becomes H level and the transistor Q5A is turned on, so that the node N1 is maintained at L level with low impedance.

Even if the levels of the first and second frame signals VFR, / VFR are switched during the next blanking period, the second inverter is activated and the node N2B is set to the H level, so that the transistor Q5B is turned on. The node N1 is maintained at the L level. Thus the period until the next frame period to the output signal G 1 is at the H level, the dummy signal D1 is not outputted.

Note the time of forward shift in the present embodiment, at the same timing as the dummy signal D1 is input to the reset terminal RST of the unit shift register SR 1, the second input terminal IN2 of the unit shift register SR 1, the output of signal G 2 is input. Therefore, the node N1 of the unit shift register SR 1 is discharged by the transistor Q4. Therefore, dummy stage SRD1 during forward scan without even outputs a dummy signal D1, becomes the unit shift register SR 1 in reset state in theory. The reason why such an operation is performed in the present embodiment is as described in the first embodiment. That is, a threshold voltage shift is caused in the transistor Q1 of the dummy stage SRD1, thereby suppressing the generation of an error signal.

After the output signal G 1 is output from the unit shift register SR 1 , the unit shift registers SR 2 , SR 3 ,..., SR n are synchronized with the clock signals CLK, / CLK as shown in FIG. , Output signals G 2 , G 3 ,..., G n are output in order.

When the dummy signal D2 is at the L level, the transistor Q10 of the unit shift register SR n is turned off, the unit shift register SR n is between operates similarly to unit shift register SR k of the intermediate stage. Therefore, as shown in FIG. 6, when the output signal G n-1 is input to the input terminal IN of the unit shift register SR n as the clock signal CLK rises, the unit shift is performed at the next timing when the clock signal / CLK becomes H level. register SR n outputs an output signal G n. The output signal G n is input to the second input terminal IN2 of the unit shift register SR n−1 and also input to the input terminal IN of the dummy stage SRD2.

Then, in the dummy stage SRD2, the transistor Q3D is turned on and the node N1 is charged. The clock signal / CLK supplied to the reset terminal RST is input to the gate of the transistor Q4D of the dummy stage SRD2, while the output signal Gn having the same phase as the clock signal / CLK is input to the source of the transistor Q4D. Therefore, at this time, the transistor Q4D is not turned on. Accordingly, the node N1 of the dummy stage SRD2 is charged to the H level (VDD−Vth) by the transistor Q3D. That is, the dummy stage SRD2 is set and the transistor Q1 is turned on.

When the clock signal / CLK and the output signal G n become L level, the input terminal IN of the dummy stage SRD2 becomes L level. However, since the transistors Q3D and Q4D are turned off and the node N1 is at the H level, the node N2A that is the output terminal of the first inverter (transistors Q6A and Q12A) is at the L level, and the transistor Q5A is also off. . Since the second inverter (transistors Q6B and Q12B) is inactive, the node N2B, which is the output terminal, is at L level, and the transistor Q5B is also off. Therefore, the node N1 of the dummy stage SRD2 is maintained at the H level in a floating state.

At this time, the transistor Q1 of the dummy stage SRD2 is on and the transistors Q2A and Q2B are off. Therefore, when the clock signal CLK becomes H level next time, the dummy signal D2 is output from the dummy stage SRD2. Dummy signal D2 is inputted to the reset terminal RST of the unit shift register SR n, transistor Q10 of the unit shift register SR n is turned on. As a result, the node N1 of the unit shift register SR n becomes L level, the unit shift register SR n returns to the reset state.

In the dummy stage SRD2 after outputting the dummy signal D2, the transistor Q4D is turned on at the rising edge of the clock signal CLK input to the reset terminal RST, and the node N1 is set to L level. When the node N1 becomes L level, the node N2A that is the output terminal of the first inverter becomes H level and the transistor Q5A is turned on, so that the node N1 is maintained at L level. Even if the levels of the first and second frame signals VFR, / VFR are switched during the next blanking period, the second inverter is activated and the node N2B is set to the H level, so that the transistor Q5B is turned on and the node N1 is maintained at the L level. Therefore, the dummy signal D2 is not output during the period until the output signal G n becomes H level in the next frame period.

  In the above description, the case where the first frame signal VFR is at the H level and the second frame signal / VFR is at the L level has been described. However, even if those levels are switched, only the transistors contributing to the operation are replaced. Basically, the same operation as described above is performed.

When the gate line driving circuit 30 performs reverse scanning, the first voltage signal Vn becomes L level (VSS) and the second voltage signal Vr becomes H level (VDD). The second control pulse STr as a start signal is input to the second input terminal IN2 of the final stage is a unit shift register SR n gate first driver stage. As a result, the signal shift in the gate destination drive stage is in the reverse direction, but the operations of the dummy stages SRD1, SRD2 are the same as in the forward scan.

That is, in the reverse scanning, the dummy stage SRD1 outputs a dummy signal D1 at the next timing of the output signal G 1 is outputted, the dummy stage SRD2 is the next timing of the output signal G n is outputted A dummy signal D2 is output. Thus, the dummy signal D1 acts as an end signal to the unit shift register SR 1 of the final stage of the reverse scan in the reset state.

  In the gate line driving circuit 30 according to the present embodiment, the switching cycle (corresponding to the frame period) between the transistors Q2A, Q5A and the transistors A2B, Q5B is implemented in each of the dummy stages SRD1, SRD2 and the gate line driving stage. The switching cycle of the transistors Q2 and Q5 and the transistors Q7 and Q8 (corresponding to the cycle of the clock signals CLK and / CLK) in the first embodiment is several ten times longer. Therefore, power consumption can be reduced as compared with the first embodiment. However, it is necessary to provide the gate line driving circuit 30 with the frame signal generator 34 for generating the first and second frame signals VFR and / VFR that are alternated with each other in the frame period and are complementary to each other.

  In this embodiment, the clock signals CLK and / CLK, the first and second control signals STn and STr, the first and second voltage signals Vn and Vr, and the first and second frame signals VFR and / VFR are at the H level. It is assumed that the potentials at the L level and the L level are equal to each other, but it is not always necessary to be so long as each transistor of the gate line driving circuit 30 can be sufficiently driven.

  In this embodiment, an example in which one gate is connected to the other drain in the transistor Q13A and the transistor Q13B configuring the flip-flop circuit is shown, but one gate is connected to the other source. You may do it. That is, as shown in FIG. 17, the gate of the transistor Q13A is connected to the source of the transistor Q13B (second frame signal terminal TB), and the gate of the transistor Q13B is connected to the source of the transistor Q13A (first frame signal terminal TA). May be. Even if comprised in this way, the operation | movement similar to the above can be performed.

  Embodiments 2 to 4 described above are also applicable to dummy stages SRD1 and SRD2 of the present embodiment. FIGS. 18A and 18B are examples in which the second embodiment is applied. In this case, a transistor Q10D connected between the node N1 and the first power supply terminal S1 is further provided for the circuits of the dummy stage SRD1 shown in FIG. 14 and the dummy stage SRD2 shown in FIG.

  The gate of the transistor Q10D is connected (second reset terminal) to a reset terminal RST1 provided separately from the reset terminal RST (first reset terminal). The first control signal STn is input to the second reset terminal RST1 of the dummy stage SRD1, and the second control signal STr is input to the second reset terminal RST1 of the dummy stage SRD2. With this configuration, the same effect as in the second embodiment can be obtained.

FIGS. 19A and 19B are examples in which the third embodiment is applied. In this case, the dummy stages SRD1 and SRD2 further include a transistor Q11D connected between the node N1 and the first power supply terminal S1 with respect to the circuits of the dummy stages SRD1 and SRD2 shown in FIGS. Provided. The gate of the transistor Q11D is connected to a third reset terminal RST2 provided separately from the first reset terminal RST and the second reset terminal RST1. The third reset terminal RST2 dummy stage SRD1 is connected to the output terminal OUT of the unit shift register SR 2, third reset terminal RST2 dummy stage SRD2 is connected to the output terminal OUT of the unit shift register SR n-1 .

  The drain of the transistor Q3D in the dummy stage SRD1 is connected to the second voltage signal terminal T2 to which the second voltage signal Vr is supplied, and the drain of the transistor Q3D in the dummy stage SRD2 is supplied with the first voltage signal Vn. One voltage signal terminal T1 is connected. Also with this configuration, the same effect as in the third embodiment can be obtained.

  FIGS. 20A and 20B are examples in which the fourth embodiment is applied. In this case, the dummy stages SRD1 and SRD2 are obtained by removing the transistors Q10D and Q11D from the circuits of the dummy stages SRD1 and SRD2 shown in FIGS.

  Also in this case, it is desirable to satisfy the condition of the above formula (3) or formula (4). However, in this embodiment, instead of the transistor Q5 of the first embodiment, the transistors Q5A and Q5B operate one by one. Therefore, the value of W (Q5) in the equation (3) is the transistor Q5A and Q5B. The gate width of transistors Q5A and Q5B is usually the same.

<Embodiment 6>
In the fifth embodiment, in each of the dummy stages SRD1, SRD2 and the gate line driving stage, the transistors Q2A, Q5A and the transistors Q2B, Q5B are alternately driven using two inverters. In the embodiment, an example in which the same operation is performed using one inverter is shown.

21 to 23 are diagrams illustrating specific circuit configurations of the gate line driving circuit 30. FIG. 21 shows the dummy stage SRD1 and the foremost stage (unit shift register SR 1 ) of the gate line driving stage, FIG. 22 shows the intermediate stage (unit shift register SR k ) of the gate line driving stage, and FIG. 23 shows the gate line driving. A final stage (unit shift register SR n ) and a dummy stage SRD2 are shown. In this embodiment, the overall configuration of the gate line driving circuit 30 (connection relationship between the dummy stages SRD1, SRD2 and the gate line driving stage) is the same as that in FIG.

With reference to FIG. 22, the configuration of bidirectional unit shift register SR k that is an intermediate stage of gate line driving circuit 30 will be described. In unit shift register SR k of the present embodiment, a pull-down drive circuit for driving transistors Q2A and Q2B includes an inverter composed of transistors Q6 and Q12, an output terminal (defined as “node N4”) of the inverter, and a node The transistor Q14A is connected between the node N2A and the transistor Q14B is connected between the node N4 and the node N2B. The gate of the transistor Q14A is connected to the first frame signal terminal TA to which the first frame signal VFR is input, and the gate of the transistor Q14B is connected to the second frame signal terminal TB to which the second frame signal / VFR is input. In the inverter, the transistor Q12 is connected between the node N4 and the second power supply terminal S2 to which the high power supply potential VDD1 is supplied, the second power supply terminal S2 side being the anode and the node N4 side being the cathode. It is diode-connected. The transistor Q6 is connected between the node N4 and the first power supply terminal S1, and its gate is connected to the node N1, which is the input terminal of the inverter. Note that the potential VDD1 may be the same as the above-described potential VDD (H level of each signal).

  According to this configuration, the transistor Q14A is on and the transistor Q14B is off while the first frame signal VFR is at the H level and the second frame signal / VFR is at the L level. Electrically connected to N2A. In other words, during that period, the transistors Q2A and Q5A are driven, and the transistors Q2B and Q5B are in a dormant state. Conversely, during the period when the first frame signal VFR is L level and the second frame signal / VFR is H level, the transistor Q14A is off and the transistor Q14B is on, so that the node N4 is electrically connected to the node N2B. . In other words, during that period, the transistors Q2B and Q5B are driven, and the transistors Q2A and Q5A are in a dormant state.

  Thus, transistors Q14A and Q14B alternately connect the output terminal (node N4) of the inverter formed of transistors Q6 and Q12 to nodes N2A and N2B based on first and second frame signals VFR and / VFR. Functions as a switching circuit to be connected.

Next, the configuration of the unit shift registers SR 1 and SR n which are the foremost stage and the last stage of the gate line driving stage will be described. As can be seen from FIGS. 21 and 23, the unit shift registers SR 1 and SR n both have the same circuit configuration, which is similar to the intermediate unit shift register SR k described above. That is, the unit shift registers SR 1 and SR n are connected to the intermediate unit shift register SR k between the node N1 and the first power supply terminal S1, and the gate of the transistor Q10 is connected to the reset terminal RST. Is further provided.

The configuration of the dummy stages SRD1 and SRD2 will be described. As can be seen from FIGS. 21 and 23, dummy stage SRD1, SRD2 is both have the same circuit configuration, they are also similar to the unit shift register SR k of the intermediate stage. That is, the dummy stage SRD1, SRD2, compared circuitry of the unit shift register SR k of the intermediate stage, transistors Q3, instead of Q4 following transistor Q3D, those comprising Q 4 D.

  The transistors Q3D and Q4D are both connected between the node N1 and the input terminal IN. Among them, the gate of the transistor Q3D is connected to the input terminal IN (that is, the transistor Q3D is diode-connected so that the input terminal IN side is an anode and the node N1 side is a cathode). Thus, the transistor Q3D functions to charge the node N1 in accordance with a signal input to the input terminal IN. On the other hand, the gate of the transistor Q4 is connected to the reset terminal RST. Therefore, the transistor Q4D functions to discharge the node N1 in accordance with the clock signal CLK when the input terminal IN is at L level.

  In the fifth embodiment, in each of the dummy stages SRD1, SRD2 and the gate line driving stage, the transistors Q2A, Q5A and the transistors Q2B, Q5B are alternately driven, the first inverter that drives the transistors Q2A, Q5A, and the transistor This is done by alternately operating the second inverter that drives Q2B and Q5B. In contrast, in the present embodiment, the connection destination of the output terminal of a single inverter (transistors Q6, Q12) is alternately switched between the gate of the transistor Q2A (node N1) and the gate of the transistor Q2B (node N2). Is going by. Except for this point, the operation of the gate line drive circuit 30 of this embodiment (the operation of each of the dummy stages SRD1 and SRD2 and the gate line drive stage) is the same as that of the fifth embodiment, and the details here are as follows. The detailed explanation is omitted.

  Also in the present embodiment, every time the first and second frame signals VFR, / VFR are inverted, the pair of transistors Q2A, Q5A and the pair of transistors Q2B, Q5B are alternately in a resting state. Is prevented from being DC biased. Therefore, similarly to the fifth embodiment, the threshold voltage shift of the transistors Q2A, Q2B, Q5A, Q5B can be prevented, and the generation of an erroneous signal can be prevented.

  Further, in this embodiment, since transistors Q2A and Q2B are driven using one inverter, there is an advantage that power consumption can be made smaller than in the fifth embodiment. Further, as compared with the fifth embodiment, the number of transistors whose gates are connected to node N1 is small, and the gate capacitance of the transistors connected to node N1 is small. Therefore, the parasitic capacitance of the node N1 is reduced, the boosting effect of the node N1 by the clock signal input to the first clock terminal CK1 is increased, and there is an advantage that the driving capability of the transistor Q1 is improved. Further, since fewer transistors are used than in the fifth embodiment, there is an advantage that the area occupied by the circuit is reduced.

  21 to 23 show examples in which one of the gates of the transistors Q13A and Q13B constituting the flip-flop circuit is connected to the other drain, FIG. 17 shown in Embodiment Mode 5 and FIG. Similarly, one gate may be connected to the other source.

  The second to fourth embodiments can also be applied to the dummy stages SRD1 and SRD2 of the present embodiment. FIGS. 24A and 24B are examples in which the second embodiment is applied. In this case, a transistor Q10D connected between the node N1 and the first power supply terminal S1 is further provided for the circuit of the dummy stage SRD1 shown in FIG. 21 and the dummy stage SRD2 shown in FIG.

  The gate of the transistor Q10D is connected (second reset terminal) to a reset terminal RST1 provided separately from the reset terminal RST (first reset terminal). The first control signal STn is input to the second reset terminal RST1 of the dummy stage SRD1, and the second control signal STr is input to the second reset terminal RST1 of the dummy stage SRD2. With this configuration, the same effect as in the second embodiment can be obtained.

FIGS. 25A and 25B are examples in which the third embodiment is applied. In this case, the dummy stages SRD1 and SRD2 further include a transistor Q11D connected between the node N1 and the first power supply terminal S1 with respect to the circuits of the dummy stages SRD1 and SRD2 shown in FIGS. Provided. The gate of the transistor Q11D is connected to a third reset terminal RST2 provided separately from the first reset terminal RST and the second reset terminal RST1. The third reset terminal RST2 dummy stage SRD1 is connected to the output terminal OUT of the unit shift register SR 2, third reset terminal RST2 dummy stage SRD2 is connected to the output terminal OUT of the unit shift register SR n-1 .

  The drain of the transistor Q3D in the dummy stage SRD1 is connected to the second voltage signal terminal T2 to which the second voltage signal Vr is supplied, and the drain of the transistor Q3D in the dummy stage SRD2 is supplied with the first voltage signal Vn. One voltage signal terminal T1 is connected. Also with this configuration, the same effect as in the third embodiment can be obtained.

  FIGS. 26A and 26B are examples in which the fourth embodiment is applied. In this case, the dummy stages SRD1 and SRD2 are obtained by removing the transistors Q10D and Q11D from the circuits of the dummy stages SRD1 and SRD2 shown in FIGS.

  Also in this case, it is desirable to satisfy the condition of the above formula (3) or formula (4). However, in this embodiment, instead of the transistor Q5 of the first embodiment, the transistors Q5A and Q5B operate one by one. Therefore, the value of W (Q5) in the equation (3) is the transistor Q5A and Q5B. The gate width of transistors Q5A and Q5B is usually the same.

<Embodiment 7>
In the present embodiment, a modification of dummy stages SRD1 and SRD2 is shown. Hereinafter, modifications of the connection destination of the drain of the transistor Q3D will be described. In the third and fourth embodiments, the drain of the transistor Q3D of the dummy stage SRD1 is connected to the second voltage signal terminal T2, and the drain of the transistor Q3D of the dummy stage SRD2 is Since it is necessary to connect to the first voltage signal terminal T1, respectively, the following modification is not applied.

  Except for the third and fourth embodiments, the transistor Q3D is used exclusively for charging the node N1, so that the drain of the transistor Q3D is supplied with the high potential side power supply potential VDD2 as shown in FIG. You may connect to 3 power supply terminals S3. The potential VDD2 may be the same as the above-described potential VDD (H level of each signal), or may be the same as the potential VDD1 (the power supply potential of the inverter) when applied to the sixth embodiment.

  As shown in FIG. 27B, a diode-connected transistor Q15n is connected between the drain of the transistor Q3D and the first voltage signal terminal T1, and between the drain of the transistor Q3D and the second voltage signal terminal T2. A diode-connected transistor Q15r may be connected to the transistor. Since the first and second voltage signals Vn and Vr are complementary to each other, an H level potential is always supplied to the drain of the transistor Q3D by one of the first and second voltage signals Vn and Vr. This is almost equivalent to the case of supplying a constant potential as in a).

  In the fourth and fifth embodiments, as shown in FIG. 27C, a diode-connected transistor Q15A is connected between the drain of the transistor Q3D and the first frame signal terminal TA, and the drain of the transistor Q3D A diode-connected transistor Q15B may be connected between the second frame signal terminal TB. Since the first and second frame signals VFR and / VFR are complementary to each other, the drain of the transistor Q3D is always supplied with an H level potential by one of the first and second frame signals VFR and / VFR. This is almost equivalent to the case where a constant potential is supplied as shown in FIG.

According to the present embodiment, it is possible to reduce the load capacitance applied to the output terminals OUT of the dummy stages SRD1 and SRD2 and the gate line driving stage. Further, the load capacity applied to the output terminal OUT is made uniform between the foremost stage and the last stage (unit shift registers SR 1 and SR n ) and the intermediate stage (unit shift registers SR 2 to SR n-1 ) of the gate line driving stage. can do.

It is a schematic block diagram which shows the structure of the display apparatus which concerns on embodiment of this invention. FIG. 3 is a block diagram illustrating a configuration example of a gate line driving circuit using the bidirectional unit shift register according to the first embodiment. FIG. 3 is a diagram illustrating a circuit configuration of a unit shift register and a dummy stage according to the first embodiment. 3 is a diagram illustrating a circuit configuration of a unit shift register according to the first embodiment. FIG. FIG. 3 is a diagram illustrating a circuit configuration of a unit shift register and a dummy stage according to the first embodiment. FIG. 6 is a timing chart showing an operation during forward scanning of the gate line driving circuit according to the first embodiment. FIG. 6 is a timing chart showing an operation during reverse scanning of the gate line driving circuit according to the first embodiment. FIG. 6 is a diagram illustrating a circuit configuration of a dummy stage according to a second embodiment. FIG. 6 is a diagram illustrating a circuit configuration of a dummy stage according to a third embodiment. FIG. 10 is a timing chart showing an operation during forward scanning of the gate line driving circuit according to the third embodiment. FIG. 10 is a timing diagram illustrating an operation during backward scanning of the gate line driving circuit according to the third embodiment. FIG. 10 is a diagram illustrating a circuit configuration of a dummy stage according to a fourth embodiment. FIG. 10 is a block diagram illustrating a configuration example of a gate line driving circuit using a bidirectional unit shift register according to a fifth embodiment. FIG. 10 is a diagram illustrating a circuit configuration of a unit shift register and a dummy stage according to a fifth embodiment. FIG. 10 is a diagram illustrating a circuit configuration of a unit shift register according to a fifth embodiment. FIG. 10 is a diagram illustrating a circuit configuration of a unit shift register and a dummy stage according to a fifth embodiment. FIG. 10 is a diagram for explaining a modification of the unit shift register according to the fifth embodiment. FIG. 16 is a diagram showing a modification of the dummy stage according to the fifth embodiment. FIG. 16 is a diagram showing a modification of the dummy stage according to the fifth embodiment. FIG. 16 is a diagram showing a modification of the dummy stage according to the fifth embodiment. FIG. 10 is a diagram illustrating a circuit configuration of a unit shift register and a dummy stage according to a sixth embodiment. FIG. 10 is a diagram illustrating a circuit configuration of a unit shift register according to a sixth embodiment. FIG. 10 is a diagram illustrating a circuit configuration of a unit shift register and a dummy stage according to a sixth embodiment. FIG. 23 is a diagram showing a modification of the dummy stage according to the sixth embodiment. FIG. 23 is a diagram showing a modification of the dummy stage according to the sixth embodiment. FIG. 23 is a diagram showing a modification of the dummy stage according to the sixth embodiment. FIG. 38 is a diagram for explaining a modification of the dummy stage according to the seventh embodiment.

Explanation of symbols

  30 gate line drive circuit, 31 clock generator, 32 start signal generator, 33 voltage signal generator, SR unit shift register, SRD1, SRD2 dummy stage, IN1 first input terminal, IN2 second input terminal, OUT output terminal, GL gate line, S1, S2, S3 power supply terminal, CK1, CK2 clock terminal, C1-C3 capacitive element, Q1-Q15 transistor, RST, RST1, RST2 reset terminal, T1 first voltage signal terminal, T2 second voltage signal terminal , TA first frame signal terminal, TB second frame signal terminal.

Claims (10)

  1. A multi-stage shift register that can drive the gate line of the display panel and change the signal shift direction;
    A first dummy stage, which is a dummy shift register provided at a further preceding stage of the multi-stage shift register;
    A gate line driving circuit including a second dummy stage, which is a dummy shift register provided in the next stage after the last stage of the multi-stage shift register,
    The first dummy stage is
    Regardless of the signal shift direction, the first dummy signal is output in accordance with the output signal at the front stage,
    The second dummy stage is
    Regardless of the signal shift direction, the second dummy signal is output in accordance with the output signal of the last stage,
    The first dummy signal is
    Used as an end signal for ending the operation of the forefront stage during backward scanning for shifting the signal from the last stage toward the forefront stage,
    The second dummy signal is
    At the time of forward scanning that shifts the signal from the foremost stage toward the last stage, it is used as an end signal for ending the operation of the last stage ,
    Each of the first and second dummy signals is:
    The gate line driving circuit , wherein the output frequency is the same as each output signal of each stage of the multi-stage shift register regardless of the signal shift direction .
  2. The gate line driving circuit according to claim 1,
    Each of the first and second dummy signals is:
    Regardless of the shift direction of the signal, pulse width, the gate line driving circuit, characterized in that it is the same as the output signal of each of the respective stages of said multistage shift register.
  3. A gate line driving circuit according to claim 1 or 2, wherein
    Each of the first and second dummy stages is
    A first input terminal, a first output terminal, a first clock terminal and a first reset terminal;
    A first transistor for supplying a first clock signal input to the first clock terminal to the first output terminal;
    A second transistor for discharging the first output terminal;
    A third transistor having a control electrode connected to the first input terminal and charging a first node to which the control electrode of the first transistor is connected;
    A fourth transistor having a control electrode connected to the first reset terminal and discharging the first node;
    The first stage output signal is input to the first input terminal of the first dummy stage,
    The gate line driving circuit, wherein the output signal of the last stage is inputted to the first input terminal of the second dummy stage.
  4. A gate line driving circuit according to claim 3,
    In each of the first and second dummy stages,
    The fourth transistor is connected between the first node and the first input terminal,
    A gate line driving circuit, wherein a second clock signal having a phase different from that of the first clock signal is input to the first reset terminal.
  5. A gate line driving circuit according to claim 3 or 4, wherein
    Each of the first and second dummy stages includes two of the second transistors,
    In the first dummy stage,
    During the period when the first dummy signal is not output, the two second transistors are alternately turned on in a predetermined cycle,
    In the second dummy stage,
    The gate line driving circuit, wherein the two second transistors are alternately turned on in a predetermined cycle during a period in which the second dummy signal is not output.
  6. The gate line driving circuit according to claim 5,
    The gate line driving circuit, wherein the predetermined period corresponds to a period of the first clock signal.
  7. The gate line driving circuit according to claim 5,
    The gate line driving circuit according to claim 1, wherein the predetermined period corresponds to an operation period of the gate line driving circuit or an integral multiple thereof.
  8. A gate line driving circuit according to any one of claims 3 to 7,
    Each stage of the multistage shift register is
    A second and third input terminal, a second output terminal and a second clock terminal;
    First and second voltage signal terminals to which first and second voltage signals complementary to each other are respectively input;
    A fifth transistor for supplying a third clock signal input to the second clock terminal to the second output terminal;
    A sixth transistor for discharging the second output terminal;
    A seventh transistor having a control electrode connected to the second input terminal and supplying the first voltage signal to a second node connected to the control electrode of the fifth transistor;
    An eighth transistor having a control electrode connected to the third input terminal and supplying the second voltage signal to the second node;
    The foremost stage and the last stage of the multistage shift register are further
    A second reset terminal;
    A gate line driving circuit, comprising: a control transistor connected to the second reset terminal; and a ninth transistor for discharging the second node.
  9. The gate line driving circuit according to claim 8, wherein
    The first voltage signal is a signal that is activated while the forward scanning is performed,
    The second voltage signal is a signal that is activated while the backward scanning is performed,
    In each of the intermediate stages excluding the front and last stages of the multistage shift register,
    The second input terminal is connected to the second output terminal of the previous stage;
    The third input terminal is connected to the second output terminal of its next stage,
    In the first stage,
    A start signal for starting the operation of the forefront stage is input to the second input terminal during the forward scanning,
    The third input terminal is connected to the second output terminal of the next stage;
    The second reset terminal is connected to the first output terminal of the first dummy stage;
    In the last stage,
    The second input terminal is connected to the second output terminal of the previous stage;
    A start signal for starting the operation of the last stage is input to the third input terminal during the backward scanning,
    The gate line driving circuit, wherein the second reset terminal is connected to the first output terminal of the second dummy stage.
  10. A gate line driving circuit according to any one of claims 3 to 9,
    Each of the first and second dummy stages includes:
    A third reset terminal;
    A tenth transistor having a control electrode connected to the third reset terminal and discharging the first node;
    In the third reset terminal of the first dummy stage,
    A start signal for starting the operation of the foremost stage at the time of forward scanning is input,
    In the third reset terminal of the second dummy stage,
    A gate line driving circuit, wherein a start signal for starting the operation of the last stage is input during backward scanning.
JP2007264198A 2007-10-10 2007-10-10 Gate line drive circuit Active JP5078533B2 (en)

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