KR102437178B1 - Gate driver - Google Patents

Abstract

The present invention relates to a gate driving circuit that can be repaired using a carry signal output from a carry signal output part of another stage even when a defect occurs in a carry signal output part of an arbitrary stage, which is connected dependently, and each carry signal A plurality of stages comprising an output unit and a scan signal output unit for outputting a carry signal and a scan signal, wherein the carry signal output from an odd-numbered (or even-numbered) stage sets two subsequent stages, and two preceding stages is configured to reset.

Description

gate driver circuit {Gate driver}

The present invention relates to a gate driving circuit of a display device, and more particularly, to a gate driving circuit capable of repairing a defect in a carry output unit.

As the information society develops and various portable electronic devices such as mobile communication terminals and notebook computers develop, the demand for a flat panel display device that can be applied thereto is gradually increasing.

As such a flat panel display, a liquid crystal display (LCD) using liquid crystal and an OLED display using an organic light emitting diode (OLED) are used.

Such display devices include a display panel having a plurality of gate lines and a plurality of data lines to display an image, and a driving circuit for driving the display panel.

The driving circuit includes a gate driving circuit driving the plurality of gate lines, a data driving circuit driving the plurality of data lines, and timing for supplying image data and various control signals to the gate driving circuit and the data driving circuit. controller, etc.

The display panel is defined as an active area (AA) providing an image to a user and a non-active area (NA) surrounding the display area (AA).

In addition, a gate driving circuit and a data driving circuit are provided outside the non-display area or the display panel to provide scan pulses and data signals for driving each pixel of the plurality of gate lines and the plurality of data lines of the display panel. provided

The gate driving circuit may include at least one gate driving IC, but the display panel is not displayed in the process of forming the plurality of signal lines (gate lines and data lines) and sub-pixels of the display panel. It may be simultaneously formed on the area NA. As a result, the gate driving circuit is included in the display panel. This is called a Gate-In-Panel (hereinafter also referred to as “GIP”).

The gate driving circuit as described above is configured to include a plurality of stages equal to or greater than the number of gate lines in order to sequentially supply scan pulses to each gate line.

That is, when the number of gate lines is n, n or more stages are provided.

1 is a block diagram of a conventional gate driving circuit, FIG. 2 is a configuration block diagram of a conventional n-th stage, FIG. 3 is a circuit diagram of the output unit 20 of FIG. 2, and FIG. 4 is Waveform diagrams of the conventional (n-3)-th to (n+3)-th stage carry signals C(n-3) to C(n+3) and the first node Q.

As shown in FIG. 1 , the conventional gate driving circuit includes a plurality of stages ((n-3)th stage to (n+3)th stage) connected cascadingly, and one stage is and an output unit that sequentially generates a scan signal SCOUT and a carry signal C according to the applied clock signals SCCLKs and CRCLKs.

Specifically, a plurality of clock signals SCCLKs and CRCLKs, a gate high voltage VGH, a plurality of gate low voltages VGLs, and a gate start pulse VST are applied to the gate driving circuit from the timing controller.

The plurality of clock signals SCCLKs and CRCLKs include a clock signal SCCLKs for outputting a scan pulse and a clock signal CRCLKs for outputting a carry pulse.

The scan signal SCOUT output from each stage is for sequentially driving the corresponding gate line, and the carry signal C output from each stage resets the previous stage or drives the next stage. It is a signal to set.

Accordingly, the nth stage ((n)th stage) is performed by the carry signal C(n-3) output from the previous stage ((n-3)th stage) or the start signal VST output from the timing controller. It is set and reset by the carry signal C(n+3) output from the subsequent stage ((n+3)th stage) or the reset signal RST output from the timing controller to reset the carry signal C(n+3) ) and a scan signal SCOUT(n).

As shown in FIG. 2, each stage is set by the carry signal C output from the previous stage, and reset by the carry signal C output from the subsequent stage to the first and second nodes ( a node controller 10 for controlling the voltages of Q and Qb, and one of the plurality of scan pulse output clock signals SCCLKs and one of the plurality of carry pulse output clock signals CRCLKs An output unit receiving a clock signal for outputting a carry pulse and outputting the scan signal SCOUT(n) and the carry signal C(n) according to voltage levels of the first and second nodes Q and Qb (20) is included.

As shown in FIG. 3 , the output unit 20 includes a carry signal output unit 21 and a scan signal output unit 22 .

The carry signal output unit 21 includes a carry pulse output clock signal terminal CRCLK(n) to which one carry pulse output clock signal among a plurality of carry clock signals CRCLKs is applied, and a first gate low voltage terminal VGL1 ) and a first pull-up transistor (Tpc) and a first pull-down transistor (Tdc) connected in series between.

The first pull-up transistor Tpc is turned on/off according to the voltage level of the first node Q, and the first pull-down transistor Tdc is turned on/off according to the voltage level of the second node Qb. to output the carry signal C(n).

The scan signal output unit 22 includes a scan pulse output clock signal terminal SCCLK(n) to which one of a plurality of scan pulse output clock signals SCCLKs is applied, and a second gate low voltage terminal. A second pull-up transistor Tp1 and a second pull-down transistor Td1 connected in series between VGL2, and a first for boosting connected between the gate electrode and the source electrode of the second pull-up transistor Tp1 Consists of a capacitor (C1).

The second pull-up transistor Tp1 is turned on/off according to the voltage level of the first node Q, and the second pull-down transistor Td1 is turned on/off according to the voltage level of the second node Qb. to output the scan signal SCOUT(n).

Here, the first pull-up transistor Tpc and the second pull-up transistor Tp1 of the carry signal output unit 21 and the scan signal output unit 22 have the weakest structure to failure.

Accordingly, the voltage waveform of the first node Q of the (n)-th and (n+1)-th stages is as shown in FIG. 4 .

That is, as described above, the (n)th stage ((n)th stage) is set by the carry signal C(n-3) output from the third previous stage ((n-3)th stage) and , since it is reset by the carry signal C(n+3) output from the third subsequent stage ((n+3)th stage), the first node Q of the (n)th stage is the carry signal C (n-3)) is synchronized with the gate high voltage VGH, and synchronized with the carry signal C(n+3), the gate low voltage VGL is entered. Then, it is boost-trapped by the clock signal CRCLK(n) for the carry pulse output applied to the (n)th stage, and is in a high voltage (2VGH) state higher than the gate high voltage (VGH). .

In the state in which the first node Q is bootstrapped as described above, the clock signal CRCLK(n) for outputting the carry pulse is output as the carry signal C(n).

Similarly, the first node Q of the (n+1)-th stage is synchronized with the carry signal C(n-2) to become a gate high voltage VGH, and the carry signal C(n+4) )) in synchronization with the gate low voltage VGL. Then, the high voltage higher than the gate high voltage VGH by being boost-trapped by the clock signal CRCLK(n+1) for outputting the carry pulse applied to the (n+1)th stage ((n+1)th stage) (2VGH) state.

In the state in which the first node Q is bootstrapped as described above, the clock signal CRCLK(n+1) for outputting the carry pulse is output as the carry signal C(n+1).

In this way, the conventional gate driving circuit is configured such that a plurality of stages are dependently connected, each stage is set by a carry signal output from a previous stage, and reset by a carry signal output from a subsequent stage, so that the carry When a defect occurs in the first pull-up transistor Tpc of the signal output unit, it is impossible to transmit a signal for setting and resetting each stage, so that the display panel is not driven.

The present invention provides a gate driving circuit that can be repaired using the carry signal output from the carry signal output part of another stage even if a defect occurs in the carry signal output part of any stage to solve the problems as in the prior art. but it has a purpose.

A gate driving circuit according to the present invention for achieving the above object includes a plurality of stages connected dependently, each having a carry signal output unit and a scan signal output unit to output a carry signal and a scan signal, and The carry signal output from the th (or even-numbered) stage sets the two rear stages and resets the two previous stages.

Here, it is characterized in that the carry signal output from the even-numbered (or odd-numbered) stage is not used to set or reset another stage.

An output terminal of the carry signal output unit of the even-numbered (or odd-numbered) stage overlaps an output terminal of the carry signal output unit of the odd-numbered (or even-numbered) stage.

When the carry signal is not output from the carry signal output unit of the odd (or even) stage, the output terminal of the carry signal output unit of the even (or odd) stage and the odd-numbered ( or even number) the output terminal of the carry signal output unit of the stage is electrically connected to repair.

The carry signal output from the carry signal output unit of the (n)-th stage sets the (n+2)-th stage and the (n+3)-th stage, and the (n-4)-th stage and the (n-3)-th stage It is characterized by resetting the.

The carry signal output unit and the scan signal output unit of each stage are driven by a clock signal of the same phase having the same phase.

The scan signal output unit of each stage is driven by a clock signal for outputting a k-phase scan pulse that is sequentially shifted by overlapping 1/2H period, and the carry signal output unit of each stage is shifted so as not to overlap with each other, a k/2-phase carry pulse It is characterized in that it is driven by a clock signal for output.

The same clock signal among the clock signals for outputting the k/2-phase carry pulse is applied to two adjacent stages.

The gate driving circuit according to the present invention having the above characteristics has the following effects.

That is, the carry signal output from the odd-numbered (or even-numbered) stage sets the two subsequent stages, resets the two previous stages, and the carry signal output from the even-numbered (or odd) stage sets the latter stage. or reset the previous stage, and the output terminal of the carry signal output unit of the even-numbered (or odd-numbered) stage is configured to overlap the output terminal of the carry signal output unit of the odd-numbered (or even-numbered) stage. Accordingly, when the carry signal is not output in the odd (or even) stage, the output terminal of the carry signal output unit of the even (or odd) stage and the odd (or even) in the overlapping region Since the output terminal of the carry signal output unit of the stage can be electrically connected, repair can be easily performed.

1 is a block diagram of a conventional gate driving circuit;
2 is a block diagram of a conventional n-th stage;
3 is a circuit diagram of the output unit 20 of FIG. 2 .
4 is a waveform diagram of the conventional (n-3)-th to (n+3)-th stage carry signals C(n-3) to C(n+3) and the first node Q;
5 is a schematic diagram illustrating a flat panel display device according to the present invention;
6 is a block diagram of a gate driving circuit according to an embodiment of the present invention;
7 is a block diagram of a gate driving circuit for explaining a repair method according to an embodiment of the present invention;
8 shows clock signals SCCLK1 to SCCLK6, scan signals SCOUT(n-3) to SCOUT(n+4), and a Q node Q(n) for a scan pulse output of a gate driving circuit according to an embodiment of the present invention. Output waveform diagram of ~Q(n+1))
9 shows clock signals CRCLK1 to CRCLK6 for outputting carry pulses, carry signals C(n-3) to C(n+4), and a Q node Q( Output waveform diagram of n) to Q(n+1))
10 shows clock signals CRCLK1 to CRCLK3 for outputting carry pulses, carry signals C(n-3) to C(n+4), and a Q node Q( Output waveform diagram of n) to Q(n+1))

A gate driving circuit and a flat panel display having the same according to the present invention having the above characteristics will be described in more detail with reference to the accompanying drawings.

5 is a schematic diagram illustrating a flat panel display device according to the present invention.

As shown in FIG. 5 , a flat panel display according to the present invention includes a display panel 1 , a gate driving circuit 2 , a data driving circuit 3 , and a timing controller 4 .

In the display panel 1 , a plurality of gate lines GL and a plurality of data lines DL are disposed, and a plurality of gate lines GL and a plurality of data lines DL are disposed in an intersection region of the display panel 1 . A plurality of sub-pixels P are arranged in a matrix form. The plurality of sub-pixels P display an image according to an image signal (data voltage) supplied from the plurality of data lines DL in response to a scan pulse G supplied from the gate lines GL. indicate

When the display panel 1 is a display panel (liquid crystal display panel) of a liquid crystal display, the liquid crystal display panel includes a thin film transistor array substrate on which a thin film transistor array is formed on a glass substrate, and a color filter array on the glass substrate. and a color filter array substrate on which is formed, and a liquid crystal layer filled between the thin film transistor array substrate and the color filter array substrate.

The thin film transistor array substrate includes a plurality of gate lines GL extending in a first direction and a plurality of data lines DL extending in a second direction perpendicular to the first direction, and each gate line and one sub-pixel area Pixel (P) is defined by each data line. One thin film transistor and a pixel electrode are formed in one sub-pixel area P.

The liquid crystal display panel configured as described above applies a voltage to an electric field generating electrode (a pixel electrode and a common electrode) to generate an electric field in the liquid crystal layer, and adjusts an arrangement state of liquid crystal molecules of the liquid crystal layer by the electric field to increase the amount of incident light. Display an image by controlling the polarization.

In addition, when the display panel 1 is an OLED display panel of an OLED display device, in the OLED display panel, a plurality of gate lines and a plurality of data lines intersect to define a sub-pixel, and each sub-pixel is an anode and an OLED including a cathode and an organic light emitting layer between the anode and the cathode, and a pixel circuit independently driving the OLED.

The pixel circuit may be configured in various ways, but includes at least one switching TFT, a capacitor, and a driving TFT.

The at least one switching TFT charges the capacitor with a data voltage in response to a scan pulse. The driving TFT controls the amount of light emitted by the OLED by controlling the amount of current supplied to the OLED according to the data voltage charged in the capacitor.

The display panel 1 is defined as an active area AA that provides an image to a user and a non-active area NA that is a peripheral area of the display area AA.

The gate driving circuit 2 is a gate in panel (GIP) type gate driver and is disposed in a non-display area of the display panel 1 .

The gate driving circuit 2 sequentially supplies a scan signal (a gate driving signal, SCOUT) to each of the gate lines GL according to a plurality of gate control signals GCS provided from the timing controller 4 . It consists of shift registers.

The plurality of gate control signals GCS include a plurality of clock signals CLK1 - 6 having different phases, a gate start signal VST for instructing the start of driving of the gate driving circuit 2 , and a reset signal RST ), a gate high voltage VGH, and gate low voltages VGL1 and VGL2, and the like.

The data driving circuit 3 converts digital image data RGB input from the timing controller 4 into an analog data voltage using a reference gamma voltage, and converts the converted analog data voltage to the plurality of data lines ( DL). The data driving circuit 3 is controlled according to a plurality of data control signals DCS provided from the timing controller 4 .

The timing controller 4 aligns image data RGB input from the outside according to the size and resolution of the display panel 1 and supplies it to the data driving circuit 3 . In addition, the timing controller 4 may include synchronization signals SYNC input from the outside, for example, a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync. is used to generate a plurality of gate control signals GCS and a plurality of data control signals DCS and respectively supply them to the gate driving circuit 2 and the data driving circuit 3 .

The gate driving circuit 2 includes a plurality of stages to sequentially supply a scan signal (a gate driving signal, SCOUT(n)) to each of the plurality of gate lines GL.

Each stage of the gate driving circuit 2 according to the present invention outputs a scan signal to each gate line in the same manner as in the conventional gate driving circuit, but outputs a carry signal differently from the conventional gate driving circuit.

That is, the carry signal output from the odd-numbered (or even-numbered) stage sets the two subsequent stages, resets the two previous stages, and the carry signal output from the even-numbered (or odd) stage sets the latter stage. or reset the previous stage.

6 is a block diagram of a gate driving circuit according to the present invention.

As shown in FIG. 6 , the gate driving circuit according to the present invention includes a plurality of cascadingly connected stages ((n-3)th stage to (n+3)th stage). One stage includes an output unit that sequentially generates a scan signal SCOUT and a carry signal C according to clock signals SCCLKs and CRCLKs applied from the timing controller.

Specifically, a plurality of clock signals SCCLKs and CRCLKs, a gate high voltage VGH, a plurality of gate low voltages VGLs, and a gate start pulse VST are applied to the gate driving circuit from the timing controller.

The plurality of clock signals SCCLKs and CRCLKs include a clock signal SCCLKs for outputting a scan pulse and a clock signal CRCLKs for outputting a carry pulse.

Each of the stages ((n-3)th stage to (n+3)th stage) outputs scan signals SCOUT(n-3) to SCOUT(n+3) for driving a corresponding gate line.

However, each of the stages ((n-3)th stage to (n+3)th stage) has a carry signal C(n−) for resetting the previous stage or setting the rear stage. 3) to C(n+3) are output, but all stages ((n-3)th stage to (n+3)th stage) reset the previous stage, or do not set

Carry signal output from odd (or even) stage (…, (n-3)th stage, (n-1)th stage, (n+1)th stage, (n+3)th stage, …) (…, (C(n-3), C(n-1), C(n+1), C(n+3), …) resets the previous stage, or resets the next stage. It is not used to set, that is, the odd (or even) stage (..., (n-3)th stage, (n-1)th stage, (n+1)th stage, ( The carry signal output stage (..., C(n-3), C(n-1), C(n+1), C(n+3), ...) of the n+3)th stage, ...) is the previous stage and It is not connected to the downstream stage.

Carry signal output stage of the odd-numbered (or even-numbered) stage (..., (n-3)th stage, (n-1)th stage, (n+1)th stage, (n+3)th stage, ...) (..., C(n-3), C(n-1), C(n+1), C(n+3), ...) are superimposed on the carry signal output terminals of the previous stage and the rear stage.

On the other hand, the carry signal (..., (C(n-) 2), C(n), C(n+2), ...) resets the two previous stages and sets the two rear stages, that is, the even (or odd) th) the carry signal output stage (…, C(n-2), C(n), C) of the stage (…, (n-2)th stage, (n)th stage, (n+2)th stage,…) (n+2), ...) is connected to two front-end stages and two rear-end stages.

That is, the carry signal C(n-2) of the (n-2)th stage ((n-2)th stage) is the (n)th stage ((n)th stage) and the (n+1)th stage ((n+1)th stage) is set, and (n-6)th stage ((n-6)th stage) and (n-5)th stage ((n-5)th stage) are reset .

The carry signal C(n) of the (n)-th stage ((n)th stage) is the (n+2)-th stage ((n+2)th stage) and the (n+3)-th stage ((n+) 3)th stage) is set, and the (n-4)th stage ((n-4)th stage) and (n-3)th stage ((n-3)th stage) are reset.

The carry signal C(n+2) of the (n+2)th stage ((n+2)th stage) is the (n+4)th stage ((n+4)th stage) and (n+5) Set the th stage ((n+5)th stage), and restart the (n-2)th stage ((n-2)th stage) and (n-1)th stage ((n-1)th stage) set it

The carry signal C(n+4) of the (n+4)th stage ((n+4)th stage) is the (n+6)th stage ((n+6)th stage) and (n+7) The (n+7)th stage is set, and the (n)th stage ((n)th stage) and (n+1)th stage ((n-1)th stage) are reset.

In the gate driving circuit according to the present invention, the configuration of each stage is as shown in FIGS. 2 and 3 described in the prior art.

That is, each stage is set by the carry signal C output from the previous stage and reset by the carry signal C output from the subsequent stage, so that the first and second nodes as shown in FIG. 2 . The node controller 10 for controlling the voltage of (Q, Qb), and one of the plurality of scan pulse output clock signals SCCLKs and one of the plurality of carry pulse output clock signals CRCLKs An output for receiving a clock signal for outputting a carry pulse of It is configured to include a portion (20).

As shown in FIG. 3 , the output unit 20 includes a carry signal output unit 21 and a scan signal output unit 22 .

The carry signal output unit 21 includes a carry pulse output clock signal terminal CRCLK(n) to which one carry pulse output clock signal among a plurality of carry clock signals CRCLKs is applied, and a first gate low voltage terminal VGL1 ) and a first pull-up transistor (Tpc) and a first pull-down transistor (Tdc) connected in series between.

The first pull-up transistor Tpc is turned on/off according to the voltage level of the first node Q, and the first pull-down transistor Tdc is turned on/off according to the voltage level of the second node Qb. to output the carry signal C(n).

The scan signal output unit 22 includes a scan pulse output clock signal terminal SCCLK(n) to which one of a plurality of scan pulse output clock signals SCCLKs is applied, and a second gate low voltage terminal. A second pull-up transistor Tp1 and a second pull-down transistor Td1 connected in series between VGL2, and a first for boosting connected between the gate electrode and the source electrode of the second pull-up transistor Tp1 Consists of a capacitor (C1).

The second pull-up transistor Tp1 is turned on/off according to the voltage level of the first node Q, and the second pull-down transistor Td1 is turned on/off according to the voltage level of the second node Qb. to output the scan signal SCOUT(n).

A repair method in the gate driving circuit according to the present invention configured as described above will be described as follows.

7 is a block diagram of a gate driving circuit for explaining a repair method according to an embodiment of the present invention.

7 illustrates a case in which the carry signal C(n) is not output due to a defect in the carry signal output unit (refer to 21 of FIG. 3 ) of the (n)th stage.

In FIG. 7 , if the carry signal C(n) is not output in the (n)th stage, the (n+2)th stage ((n+2)th stage) and (n+ 3) th stage ((n+3)th stage) is not set, (n-4)th stage ((n-4)th stage) and (n-3)th stage ((n-3)th stage ) is not reset, so the gate driving circuit does not operate.

As such, when the gate driving circuit does not operate because the carry signal C(n) is not output in the (n)th stage, as indicated by the arrow in FIG. 7 , the ( A laser is irradiated to a portion where the carry signal output terminal of the n)th stage ((n)th stage) and the carry signal output terminal of the (n+1)th stage ((n+1)th stage) are overlapped by irradiating the (n) ) the carry signal output terminal of the (n)th stage and the carry signal output terminal of the (n+1)th stage ((n+1)th stage) are electrically connected.

Then, the (n) th stage is cut off between the carry signal output terminal of the (n) th stage and the (n) th stage.

Accordingly, the (n+2)th stage ((n+2)th stage) and the (n+3)th stage ((n+3)th stage) are the (n+1)th stage ((n+1)th stage ) th stage) is set by the carry signal C(n+1)), and the (n-4)-th stage ((n-4)th stage) and (n-3)-th stage ((n) -3)th stage) is reset by the carry signal C(n+1) output from the (n+1)th stage ((n+1)th stage).

As such, even if the carry signal C(n) is not output in the (n)th stage, the (n+2)th stage ((n+2)th stage) and (n) +3) th stage ((n+3)th stage) is set by the carry signal C(n+1) output from the (n+1)th stage ((n+1)th stage), The (n-4)th stage ((n-4)th stage) and the (n-3)th stage ((n-3)th stage) are the (n+1)th stage ((n+1)th stage) stage) is reset by the carry signal C(n+1)), so the gate driving circuit is driven.

The operation of the gate driving circuit according to the present invention configured as described above will be described below.

8 shows clock signals SCCLK1 to SCCLK6, scan signals SCOUT(n-3) to SCOUT(n+4), and a Q node Q(n) for a scan pulse output of a gate driving circuit according to an embodiment of the present invention. to Q(n+1)), and FIG. 9 is a clock signal (CRCLK1 to CRCLK6) and a carry signal (C(n-3)) for outputting carry pulses of the gate driving circuit according to the first embodiment of the present invention. ~C(n+4)) and Q nodes (Q(n)~Q(n+1)) are output waveform diagrams.

As shown in FIGS. 8 and 9 , the clock signals SCCLK1 to SCCLK6 for the scan pulse output are sequentially shifted clock signals overlapping the 1/2H section (1/2 horizontal section).

Similarly, the clock signals CRCLK1 to CRCLK6 for the carry pulse output are also sequentially shifted clock signals overlapping the 1/2H section (1/2 horizontal section).

In addition, the clock signals SCCLK1 to SCCLK6 for outputting scan pulses and the clock signals CRCLK1 to CRCLK6 for outputting carry pulses have the same phase.

That is, the scan pulse output clock signal SCCLK1 and the carry pulse output clock signal CRCLK1 have the same phase, the scan pulse output clock signal SCCLK2 and the carry pulse output clock signal CRCLK2 have the same phase, and the scan pulse output clock signal SCCLK2 has the same phase. The output clock signal SCCLK3 and the carry pulse output clock signal CRCLK3 have the same phase, the scan pulse output clock signal SCCLK4 and the carry pulse output clock signal CRCLK4 have the same phase, and the scan pulse output clock signal ( SCCLK5 and the clock signal CRCLK5 for outputting the carry pulse have the same phase, and the clock signal SCCLK6 for outputting the scan pulse and the clock signal CRCLK6 for outputting the carry pulse have the same phase.

In addition, the clock signal SCCLK1 for outputting the first scan pulse and the clock signal CRCLK1 for outputting the first carry pulse are (n-3)th stage ((n-3)th stage) and (n+3)th stage (( n + 3) th stage), the clock signal SCCLK2 for outputting the second scan pulse and the clock signal CRCLK2 for outputting the second carry pulse are applied to the (n-2) th stage ((n-2) th stage) and The (n+4)th stage is applied, and the clock signal SCCLK3 for outputting the third scan pulse and the clock signal CRCLK3 for outputting the third carry pulse are applied to the (n-1)th stage ( (n-1)th stage) is applied.

The clock signal SCCLK4 for outputting the fourth scan pulse and the clock signal CRCLK4 for outputting the fourth carry pulse are applied to the (n)th stage ((n2)th stage), and the clock signal SCCLK5 for outputting the fifth scan pulse and the clock signal CRCLK4 for outputting the fifth scan pulse The clock signal CRCLK5 for outputting the 5 carry pulse is applied to the (n+1)th stage, and the clock signal SCCLK6 for outputting the sixth scan pulse and the clock signal CRCLK6 for outputting the sixth carry pulse ) is applied to the (n+2)th stage.

At this time, as described above, the (n)th stage ((n)th stage) and the (n+1)th stage ((n+1)th stage) are the (n-2)th stage ((n− 2) set by the carry signal C(n-2) of the th stage), and set by the carry signal C(n+4) of the (n+4)th stage ((n+4)th stage) is reset

Accordingly, the first node Q of the (n)-th stage ((n)th stage) and the (n+1)-th stage ((n+1)th stage) is the (n-2)-th stage (( In synchronization with the carry signal C(n-2) of the n-2)th stage, the gate high voltage VGH is entered, and the carry of the (n+4)th stage ((n+4)th stage) is synchronized with the carry signal C(n-2). In synchronization with the signal C(n+4), the gate low voltage VGL state.

In addition, the first node Q of the (n)th stage is boost-trapped by the clock signal SCCLK4 for outputting the fourth scan pulse and the clock signal CRCLK4 for outputting the fourth carry pulse. It becomes a high voltage (2VGH) higher than the gate high voltage (VGH). In addition, the first node Q of the (n+1)th stage ((n+1)th stage) is connected to the clock signal SCCLK5 for outputting the fifth scan pulse and the clock signal CRCLK5 for outputting the fifth carry pulse. It is boost-strapped by the gate high voltage (VGH) to a higher high voltage (2VGH) than the state (VGH).

In the state in which the first node Q is bootstrapped in this way, the (n)th stage (n)th stage generates the clock signal SCCLK4 for outputting the fourth scan pulse and the clock signal for outputting the fourth carry pulse. (CRCLK4) is output as a scan signal SCOUT(n) and a carry signal C(n), respectively, and the (n+1)th stage ((n+1)th stage) is for outputting the fifth scan pulse The clock signal SCCLK5 and the clock signal CRCLK5 for outputting the fifth carry pulse are output as the scan signal SCOUT(n+1) and the carry signal C(n+1), respectively.

Therefore, the carry signal output stage of all stages operates normally, and the carry signal output from the odd-numbered (or even-numbered) stage sets the two subsequent stages, resets the two previous stages, and the even-numbered (or odd-numbered) stage. The carry signal output from the stage sequentially drives each gate line of the display panel as a scan signal and a carry signal are normally output without setting the rear stage or resetting the previous stage.

In addition, as described with reference to FIG. 7 , the carry signal is not output from the carry signal output terminal of the (n)-th stage, so the carry signal output from the (n+1)-th stage ((n+1)th stage) Even if C(n+1)) is repaired, the (n+2)th stage ((n+2)th stage) and (n+3)th stage ((n+3)th stage) ) is set by the carry signal C(n+1) output from the (n+1)th stage, and the (n-4)th stage ((n-4)th stage) and (n Since the -3)th stage ((n-3)th stage) is reset by the carry signal C(n+1) output from the (n+1)th stage ((n+1)th stage), There is no problem in driving the display panel.

Meanwhile, FIG. 10 shows clock signals CRCLK1 to CRCLK3 for outputting carry pulses, carry signals C(n-3) to C(n+4)) and Q nodes of the gate driving circuit according to the second embodiment of the present invention. This is an output waveform diagram of Q(n) to Q(n+1)).

As described in FIG. 8 , the clock signal SCCLK1 for outputting the first scan pulse is the scan signal output terminal 22 of the (n-3)th stage and the (n+3)th stage ( is applied to the scan signal output terminal 22 of (n+3)th stage), and the clock signal SCCLK2 for outputting the second scan pulse is the scan signal output terminal of the (n-2)th stage ((n-2)th stage) It is applied to the scan signal output terminal 22 of the (22) and (n+4)th stage ((n+4)th stage), and the clock signal SCCLK3 for outputting the third scan pulse is the (n-1)th stage ( (n-1) is applied to the scan signal output terminal 22 of the th stage), and the clock signal SCCLK4 for outputting the fourth scan pulse is applied to the scan signal output terminal 22 of the (n) th stage ((n2) th stage). and the clock signal SCCLK5 for outputting the fifth scan pulse is applied to the scan signal output terminal 22 of the (n+1)th stage, and the clock signal SCCLK6 for outputting the sixth scan pulse ) is applied to the scan signal output terminal 22 of the (n+2) th stage, so that the scan signal is sequentially output as described in FIG. 8 .

On the other hand, as shown in FIG. 10 , the clock signals CRCLK1 to CRCLK3 for outputting carry pulses use three-phase clock signals shifted so as not to overlap each other.

That is, the clock signals SCCLK1 to SCCLK6 for the scan pulse output use the six-phase clock signal as described in FIG. 8, and the clock signals CRCLK1 to CRCLK3 for the carry pulse output use a three-phase clock signal shifted so as not to overlap each other. .

Accordingly, the clock signal CRCLK1 for outputting the first carry pulse is the (n-2)th stage ((n-2)th stage), the (n-1)th stage ((n-1)th stage), and (n+) 4) is applied to the (n+4)th stage, and the clock signal CRCLK2 for outputting the second carry pulse is applied to the (n)th stage ((n)th stage) and the (n-1)th stage (( n-1)th stage), and the clock signal CRCLK3 for outputting the third carry pulse is (n-4)th stage ((n-4)th stage), (n-3)th stage ((n− 3) th stage), (n+2) th stage ((n+2) th stage), and (n+3) th stage ((n+3) th stage).

Accordingly, the (n)th stage ((n)th stage) and the (n+1)th stage ((n+1)th stage) are the (n-2)th stage ((n-2)th stage) It is set by the carry signal C(n-2), and reset by the carry signal C(n+4) of the (n+4)th stage.

Therefore, the first node Q of the (n)-th stage ((n)th stage) and the (n+1)-th stage ((n+1)th stage) is the (n-2)-th stage (( In synchronization with the carry signal C(n-2) of the n-2)th stage, the gate high voltage VGH is entered, and the carry of the (n+4)th stage ((n+4)th stage) is synchronized with the carry signal C(n-2). In synchronization with the signal C(n+4), the gate low voltage VGL state.

In addition, the first node Q of the (n)th stage ((n)th stage) and the (n+1)th stage ((n+1)th stage) receives the clock signal CRCLK2 for outputting the second carry pulse. is boost-trapped by , and becomes a high voltage (2VGH) higher than the gate high voltage (VGH).

In this way, in the state in which the first node Q is bootstrapped, the (n)th stage ((n)th stage) and the (n+1)th stage ((n+1)th stage) are The clock signal CRCLK2 for outputting two carry pulses is output as carry signals C(n) and C(n+1), respectively.

Therefore, the carry signal output stage of all stages operates normally, and the carry signal output from the odd-numbered (or even-numbered) stage sets the two subsequent stages, resets the two previous stages, and the even-numbered (or odd-numbered) stage. The carry signal output from the stage sequentially drives each gate line of the display panel as a scan signal and a carry signal are normally output without setting the rear stage or resetting the previous stage.

In addition, as described with reference to FIG. 7 , the carry signal is not output from the carry signal output terminal of the (n)-th stage, so the carry signal output from the (n+1)-th stage ((n+1)th stage) Even if it is repaired with C(n+1)), there is no problem in driving.

That is, since the carry signal C(n) of the (n)-th stage and the carry signal C(n+1) of the (n+1)-th stage have the same phase, it is the same as when the normal operation is performed even after repair. run the same

Although FIG. 10 illustrates a clock pulse for outputting a three-phase carry pulse, the present invention is not limited thereto.

That is, the clock signal for outputting scan pulses is an 8-phase clock signal that is sequentially shifted by overlapping 1/2H section (1/2 horizontal section) as described with reference to FIG. 8, and the clock signal for outputting carry pulses is shifted so as not to overlap with each other It may be a four-phase clock signal. It can be applied in various ways in the same way as above.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention pertains that various substitutions, modifications, and changes are possible without departing from the technical spirit of the present invention. It will be clear to those who have the knowledge of

1: Display panel 2: Gate driving circuit
3: Data driving circuit 4: Timing controller

Claims (8)

a plurality of stages connected dependently and each having a carry signal output unit and a scan signal output unit to output a carry signal and a scan signal;
One carry signal output from the odd-numbered (or even-numbered) stage is a gate driving circuit that sets two subsequent stages at the same time and resets the two previous stages at the same time. The method of claim 1,
The carry signal output from the even (or odd) stage is not used to set or reset the other stage in the gate drive circuit. The method of claim 1,
and an output end of the carry signal output unit of the even (or odd) stage overlaps an output end of the carry signal output unit of the odd (or even) stage. 4. The method of claim 3,
When the carry signal is not output from the carry signal output unit of the odd (or even) stage, the output terminal of the carry signal output unit of the even (or odd) stage and the odd-numbered ( or even-numbered) a gate driving circuit for repairing by electrically connecting the output terminal of the carry signal output unit of the stage. The method of claim 1,
The carry signal output from the carry signal output unit of the (n)-th stage sets the (n+2)-th stage and the (n+3)-th stage simultaneously, and the (n-4)-th stage and (n-3)-th stage A gate driving circuit that resets the second stage at the same time. The method of claim 1,
A gate driving circuit in which the carry signal output unit and the scan signal output unit of each stage are driven by a clock signal of the same phase having the same phase. The method of claim 1,
The scan signal output unit of each stage is driven by a clock signal for outputting the k-phase scan pulse that is sequentially shifted by overlapping 1/2H period,
A gate driving circuit driven by a clock signal for outputting a k/2-phase carry pulse that is shifted so that the carry signal output unit of each stage does not overlap each other. 8. The method of claim 7,
A gate driving circuit in which the same clock signal among the clock signals for outputting the k/2-phase carry pulse is applied to two adjacent stages.

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