KR20170080304A - Display panel with integrated gate driver and display apparatus using the same - Google Patents

Abstract

An object of the present invention is to provide a display panel in which a gate driver is incorporated and a display device using the same, which can control the turn-off time of a switching transistor turned on by a gate pulse supplied by a single feeding method. To this end, a display panel in which a gate driver according to the present invention is embedded includes a display region and non-display regions having gate lines and data lines. Here, the first gate driver is built in the first non-display area of the first non-display area and the second non-display area facing each other, and the second gate driver is built in the second non-display area. The stages constituting the first gate driver output gate pulses to the odd gate lines among the gate lines and the stages constituting the second gate driver output gate pulses to the even gate lines among the gate lines. The first switching unit is connected to the end of each of the odd-numbered gate lines, and the second switching unit is connected to the end of each of the even-numbered gate lines. The first switching unit is connected to the first low voltage line, the first control line, and the odd gate line provided in the second non-display area. The second switching unit includes a second low voltage line provided in the first non-display area, Line and an even-numbered gate line.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a display panel having a gate driver,

The present invention relates to a display panel, and more particularly to a display panel in which a gate driver is incorporated and a display device using the same.

Flat panel displays are used in various types of electronic products including mobile phones, tablet PCs, and notebook computers. 2. Description of the Related Art Liquid crystal displays and organic light emitting display devices are widely used in flat panel display devices (hereinafter simply referred to as 'display devices').

The display device includes a gate driver, a data driver, a panel, and a control unit. The panel may be an organic light emitting panel or a liquid crystal panel.

1 is a diagram illustrating waveforms of gate pulses output by a conventional single feeding method.

A gate-in-panel type gate driver includes a plurality of stages, and each stage outputs a gate signal (Vg) to a gate line. The gate signal Vg includes a gate pulse.

The gate-in-panel type gate driver may be configured as a single-feeding type or a double-feeding type.

In a display panel to which a single feeding type gate driver is applied, as shown in FIG. 1, stages are provided in non-display regions provided on both sides of a display region where pixels P are arranged.

In this case, the n-th stage (Stage #n) arranged on the left side of the display region supplies the n-th gate pulse (GPn) to the n-th gate line provided in the display region, The n + 1th stage Stage # n + 1 outputs the (n + 1) -th gate pulse GPn + 1 to the (n + 1) th gate line.

The nth gate pulse GPn is applied to the nth gate line GPn by the load of the nth gate line while the nth gate pulse GPn outputted from the nth stage Stage #n is transferred from the left side to the right side of the display area, ) Changes gradually. Th gate line (GPn + 1) output from the (n + 1) th stage (Stage # n + 1) is transferred from the right side to the left side of the display region, The characteristics of the (n + 1) -th gate pulse GPn + 1 gradually change.

This change in the characteristics is caused because the gate pulse is delayed by various loads of the display panel. In particular, the delay of the gate pulse is severely generated at both ends of the display panel.

Therefore, the waveform of the n-th gate pulse GPn and the waveform of the (n + 1) -th gate pulse GPn + 1 measured at the left side of the display region have different characteristics as shown in Fig. 1 . Accordingly, a difference in image quality occurs between the right side and the left side of the display panel to which the single feeding type gate driver is applied.

In other words, when a single feeding type gate driver is applied, a luminance difference may occur between the odd gate lines and the even gate lines, and a horizontal line defect may occur. This defect occurs because the next data signal and the gate pulse cause interference due to the delay of the gate pulse.

For example, the delay width (B) of the (n + 1) -th gate pulse (GPn + 1) measured at the left side of the display panel is smaller than the delay width (A). The delay width B of the n-th gate pulse GPn measured on the right side of the display panel is determined by the delay width A of the (n + 1) -th gate pulse GPn + 1 measured at the right side of the display panel ).

When the delay width B of the n-th gate pulse GPn increases from the right side of the display panel, the transistor which is provided on the right side of the display panel and is to be turned off by the n-th gate pulse GPn, Quot; state " In this case, the transistor connected to the n-th gate line is kept on by the n-th gate pulse GPn until the (n + 1) -th gate pulse GPn + 1 is supplied to the (n + . Therefore, a data voltage to be supplied to the pixels connected to the (n + 1) th gate line may be supplied to the pixels connected to the right end of the nth gate line. Accordingly, a defect such as a stain may occur in the pixels connected to the right end of the nth gate line.

Also, when a single feeding type gate driver is applied, a luminance difference may occur between pixels due to the voltage difference of the gate pulse.

2 is a diagram showing an example of a structure of a display panel in which a conventional double-feeding type gate driver is incorporated.

In the display panel to which the double feeding type gate driver is applied, as shown in FIG. 2, stages are provided in non-display regions provided on both sides of the display region where the pixels P are arranged.

In this case, a first stage (Stage # 1) arranged on the left side of the display area and a first stage (Stage # 1) arranged on the right side of the display area are connected to the same gate line (GP1) .

Since the first gate pulse GP1 having the same phase and waveform from two first stages arranged on the left side of the display area is supplied to one gate line, the pixels arranged at the left end of the gate line The characteristics of the supplied gate pulse are the same or similar to those of the gate pulse supplied to the pixels disposed at the right end. Therefore, there is no difference in image quality between the right side and the left side of the display panel.

However, the stage applied to the double-feeding type gate driver as described above must be provided for each gate line. Therefore, the number of stages applied to the double-feeding gate driver is greater than the number of stages applied to the single-feeding gate driver. Accordingly, the size of the non-display area provided with the double-feeding type gate driver is larger than the size of the non-display area provided with the single-feeding type gate driver.

An object of the present invention proposed to solve the above problems is to provide a display panel in which a gate driver is incorporated and which can control the turning off point of a switching transistor turned on by a gate pulse supplied by a single feeding method, And a display device.

According to an aspect of the present invention, there is provided a display panel including a gate driver, the display panel including gate lines and data lines, and non-display regions provided at a periphery of the display region. A first gate driver is embedded in the first non-display area and a second gate driver is embedded in the first non-display area and the second non-display area of the non-display areas, . The stages constituting the first gate driver output gate pulses to odd gate lines among the gate lines, and the stages constituting the second gate driver output gate pulses to the even gate lines among the gate lines. . Numbered gate lines, a first switching unit provided in the second non-display area is connected to an end of each of the odd-numbered gate lines, and a second switching unit connected to an end of each of the even- do. Wherein the first switching unit is connected to a first low-voltage line provided in the second non-display area, a first control line provided in the second non-display area, and the odd-numbered gate line, A second low voltage line provided in the non-display area, a second control line provided in the second non-display area, and the even gate line.

According to an aspect of the present invention, there is provided a display device including a display panel having gate lines and data lines, a data driver supplying data voltages to the data lines, and a controller controlling the data driver, . Here, a first gate driver is embedded in the first non-display area of the first non-display area and the second non-display area disposed on the outer periphery of the display area of the display panel and facing each other, A second gate driver is incorporated. The stages constituting the first gate driver sequentially output gate pulses to odd gate lines among the gate lines, and the stages constituting the second gate driver are connected to the even gate lines among the gate lines And sequentially outputs gate pulses. Numbered gate lines are connected to the first low-voltage line in accordance with a first control signal, and the first switching unit provided at the end of each of the odd-numbered gate lines connects the odd- 2 switching unit connects the even-numbered gate line to the second low-voltage line according to a second control signal.

According to the present invention, even if a single feeding type gate driver is used, the delay of the gate pulse at the end of the gate line is delayed by the delay of the gate pulse at the end of the gate line when the double- Can be reduced to an equivalent level. Thus, the voltage difference between the pixels can be eliminated, and thus the image quality can be improved.

Further, since the present invention uses the single feeding method, the width of the non-display area of the present invention can be reduced from the width of the non-display area of the display device using the double feeding method.

1 is a diagram illustrating waveforms of gate pulses output by a conventional single feeding method;
Fig. 2 is an exemplary view showing a configuration of a display panel in which a conventional double-feeding type gate driver is incorporated. Fig.
3 is an exemplary view showing a configuration of a display device according to the present invention.
4 is a view showing an example of a part of a display panel having a built-in gate driver according to the present invention;
5 is an exemplary view showing a configuration of the first switching unit shown in FIG.
Fig. 6 is an equivalent circuit of the first switching unit shown in Fig. 5; Fig.
FIG. 7 is an exemplary view showing waveforms of clocks applied to a display device according to the present invention; FIG.
8 is an exemplary view showing a width of a non-display area of a display panel in which a gate driver according to the present invention is incorporated and a width of a non-display area of a conventional display panel.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is an exemplary view showing a configuration of a display device according to the present invention.

3, the display device according to the present invention includes a display panel (a display panel) having gate lines GL1 to GLg (g is an even number) and data lines DL1 to DLd (d is a natural number) A data driver 300 for supplying data voltages to the data lines DL1 to DLd, a controller 400 for controlling the data driver 300, The first gate driver 210 and the second non-display area NAA2 embedded in the first non-display area NAA1 among the first non-display area NAA1 and the second non-display area NAA2 facing each other, And a second gate driver 220 embedded in the second gate driver 220. The first gate driver 210 and the second gate driver 220 are controlled by the controller 400.

First, the display panel 100 is a display panel (hereinafter simply referred to as 'display panel') having a built-in gate driver according to the present invention.

The display panel 100 includes a display region 110 in which the gate lines GL1 to GLg and the data lines DL1 to Dld are embedded, Regions.

Among the non-display areas, the first non-display area NAA1 and the second non-display area NAA2 face each other with the display area 110 therebetween.

The first gate driver 210 is embedded in the first non-display area NAA1 and the second gate driver 220 is embedded in the second non-display area NAA2.

The display panel 100 includes a plurality of gate lines GL1 to GLg and data lines DL1 to DLd, and a plurality of pixels P are provided.

The structure of the pixel P may be variously changed depending on the type of the display device.

For example, when the display device is an organic light emitting display, each pixel P includes an organic light emitting diode, switching transistors connected to a data line DL and a gate line GL, Driving transistors for controlling the current flowing to the light emitting diode, and the like.

When the display device is a liquid crystal display device, each pixel P may be configured to include a liquid crystal, a pixel electrode, and a switching transistor. The switching transistor is connected to the gate line, the data line and the pixel electrode.

The transistors included in the display device according to the present invention may be thin film transistors.

In order to drive the switching transistors, the first gate driver 210 or the second gate driver 220 is supplied with a gate signal to the switching transistors.

The gate signal includes a gate pulse for turning on the switching transistor and a pull-down signal for turning off the switching transistor. In this case, the gate pulse and the pull-down signal are generically referred to as a gate signal.

The gate pulse turns on the switching transistor.

While the gate pulse is not supplied, the pull-down signal for turning off the switching transistor is supplied to the gate line. The pulldown signal is also supplied to each gate line through the first gate driver 210 or the second gate driver 220.

The transistors and various elements constituting the first gate driver 210 and the second gate driver 220 are connected to the switching transistors and various elements constituting the pixels P And is provided in the first non-display area NAA1 and the second non-display area NAA2 when the display area 110 is provided. The method of embedding the gate driver in the non-display area of the display panel 100 is referred to as a gate-in-panel (GIP) method. The present invention is applied to the display panel 100 manufactured by the gate-in-panel method.

Second, the controller 400 controls the first gate driver 210 and the second gate driver 210 using a timing signal input from an external system, that is, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, The data driver 300 generates a gate control signal GCS for controlling the operation timing of the data driver 220 and a data control signal DCS for controlling the operation timing of the data driver 300, And generates data.

For this, the control unit 400 includes a receiving unit for receiving input image data and timing signals from the external system, a control signal generating unit for generating various control signals, and rearranging the input image data, And an output unit for outputting the control signals and the image data Data to the data driver 300, the first gate driver 210, and the second gate driver 220 .

The controller 400 rearranges input image data input from the external system according to the structure and characteristics of the panel 100 and transmits the rearranged image data Data to the data driver 300. [ Such a function can be executed in the data arrangement section.

The controller 400 controls the data driver 300 and the first gate driver 210 and the second gate driver 200 using the timing signals transmitted from the external system, 220 and the second gate driver 220 and transmits the control signals to the data driver 300, the first gate driver 210 and the second gate driver 220 do. This function can be executed in the control signal generation unit.

Third, the data driver 300 converts digital image data (Data) transmitted from the control unit 400 into analog data voltages, and supplies data for one horizontal line per period during which the gate pulses are supplied to the gate lines And supplies voltages to the data lines DL1 to DLd. The data driver 300 converts the image data Data into the data voltage using the gamma voltages supplied from the gamma voltage generator, and supplies the data voltage to the data lines. The data driver 300 may be formed as one integrated circuit (IC) together with the controller 400. [

Fourth, the first gate driver 210 and the second gate driver 220 may be arranged in the first non-display area NAA1 and the second non-display area NAA2 of the display panel 100, Area NAA2, and this method is referred to as a gate-in-panel (GIP) method.

The first gate driver 210 and the second gate driver are connected to the gate lines GL1 to GLg of the display panel 100 in response to the gate control signal GCS input from the controller 400. [ ) Sequentially. Accordingly, the switching transistors TFT formed on each pixel of the corresponding horizontal line to which the gate pulse is input are turned on, and the image can be output to each pixel.

The first gate driver 210 may sequentially transmit the gate pulse to the odd gate lines among the gate lines GL1 to GLg as shown in FIG. 3. In this case, The gate driver 220 sequentially transfers the gate pulses to even-numbered gate lines among the gate lines GL1 to GLg, as shown in FIG.

In addition, the first gate driver 210 may sequentially transmit the gate pulse to even-numbered gate lines among the gate lines GL1 to GLg. In this case, the second gate driver 220 , And sequentially transmits the gate pulse to the odd gate lines among the gate lines GL1 to GLg.

3, the first gate driver 210 and the second gate driver 210, which sequentially transmit the gate pulse to the odd gate lines among the gate lines GL1 to GLg, And the second gate driver 220 for sequentially transferring the gate pulses to the even-numbered gate lines GL1 to GLg are described as an example of the present invention.

The first gate driver 210 includes stages 211 for sequentially supplying gate pulses to the odd gate lines, and the second gate driver 210 includes stages 211 for supplying gate pulses to the odd gate lines, And stages 221 for sequentially supplying pulses.

In other words, the stages 211 constituting the first gate driver 210 sequentially output gate pulses to the odd gate lines among the gate lines, and the second gate driver 220 The stages constitute sequentially output gate pulses to even-numbered gate lines among the gate lines.

The first switching unit X1 provided at the end of each of the odd-numbered gate lines is connected to the odd-numbered gate line according to the first control signal CS1 transmitted from the control signal generator of the controller 400 And the second switching unit X2 provided at the end of each of the even gate lines is connected to the first low voltage line VSSL1, Numbered gate line to the second low-voltage line VSSL2 in accordance with the second low-voltage line CS2.

The first switching unit X1 is provided in the second non-display area NAA2 and the second switching unit X2 is provided in the first non-display area NAA1.

The first switching unit X1 is connected to the first low voltage line VSSL1 provided in the second non-display area NAA2, the first control line CL1 provided in the second non-display area NAA2, Numbered gate lines.

The second switching unit X2 is connected to the second low voltage line VSSL2 provided in the first non-display area NAA1, the second control line CL2 provided in the second non-display area NAA2, And connected to the even-numbered gate lines.

The controller 400 transmits the first control signal CS1 to the first switching unit X1 at a time point when odd-numbered switching transistors connected to the odd-numbered gate lines are to be turned off, To the second switching unit (X2), the second control signal (SC2) at a time when the even-numbered switching transistors connected to the even-numbered gate lines are to be turned off.

Specific configurations and functions of the first switching unit X1 and the second switching unit X2 will be described in detail below with reference to FIGS. 4 to 7. FIG.

FIG. 4 is a diagram illustrating a portion of a display panel in which a gate driver according to the present invention is incorporated, and FIG. 5 is a diagram illustrating an exemplary configuration of the first switching unit shown in FIG.

As described above, a display panel (hereinafter, simply referred to as a 'display panel') 100 in which the first and second gate drivers 210 and 220 are embedded has gate lines GL1 to GLg, A display region 110 having data lines DL1 to DLd, and non-display regions NAA1 and NAA2 provided at the periphery of the display region.

The first gate driver (210) is embedded in the first non-display area (NAA1) of the first non-display area (NAA1) and the second non-display area (NAA2) And the second gate driver 220 is embedded in the second non-display area NAA2.

The stages 211 constituting the first gate driver 210 output gate pulses to, for example, odd gate lines among the gate lines, and the stages 211 constituting the second gate driver 220 (221) output gate pulses to even-numbered gate lines among the gate lines.

Numbered gate lines, the first switching unit X1 provided in the second non-display area NAA2 is connected to the end of each of the odd-numbered gate lines, and the first non-display area X1 is connected to the end of each of the even- And the second switching unit X2 provided in the area NAA1 is connected.

The first switching unit X1 is connected between the first low voltage line VSSL1 provided in the second non-display area NAA2 and the first control line CL1 provided in the second non-display area NAA2, ) And the odd-numbered gate lines.

The second switching unit X2 is connected to the second low voltage line VSSL2 provided in the first non-display area NAA1, the second control line CL2 provided in the second non-display area NAA2, And the even-numbered gate lines.

For example, in the display panel 100 shown in FIG. 4, the n-th stage (Stage #n) 211 constituting the first gate driver 210 is connected to the n-th gate line GLn , The end of the nth gate line GLn is connected to the first switching unit X1 in the second non-display area NAA2 as shown in FIG.

In this case, the (n + 1) th stage 221 of the second gate driver 220 is connected to the (n + 1) th gate line, and the end of the And is connected to the second switching unit X2 in the first non-display area NAA1.

The (n + 2) -th gate line is connected to the (n + 2) -th gate line and the (n + 2) -th gate line is connected to the And is connected to the first switching unit X1 in the non-display area NAA2.

The (n + 3) -th stage of the second gate driver 220 is connected to the (n + 3) -th gate line, and the end of the (n + And is connected to the second switching unit X2 in the non-display area NAA1.

All the stages 211 constituting the first gate driver 210 and all the stages 222 constituting the second gate driver 220 are connected to each other in the n stages (Stage #n) to and is provided on the display panel 100 in the same manner as the n + 3 stages Stage # n + 3.

The first control signal CS1 is transmitted to the first switching unit X1 through the first control line CL1 and the second control signal CS2 is transmitted through the second control line CL2 And is transmitted to the second switching unit X2.

The first low voltage VSS1 is transmitted to the first switching unit X1 through the first low voltage line VSSL1 and the second low voltage VSS2 is transmitted through the second low voltage line VSSL2 to the first switching unit X1, 2 switching unit X2.

6 shows an equivalent circuit of the first switching unit shown in Fig.

The first switching unit X1 may be a first transistor including a first terminal, a second terminal, and a third terminal, and the second switching unit X2 may include a first terminal, a second terminal, And a second transistor including a terminal.

For example, as shown in FIG. 6, the first terminal, which is the gate of the first transistor ST, is connected to the first control line CL1, and the second terminal of the first transistor ST Numbered gate line, and the third terminal of the first transistor is connected to the first low-voltage line (VSSL1).

In this case, the odd-numbered gate lines may be the n-th gate lines GLn described in Figs. 4 and 5). The n-th gate line GLn may be the n-th stage (Stage #n) constituting the first gate driver 210.

The first transistor ST is connected to an end of the nth gate line GLn and the auxiliary line AL is connected between the third terminal of the first transistor ST and the first low voltage line VSSL1. And the auxiliary line AL and the first low voltage line VSSL1 are electrically connected through a contact hole CH.

The first switching unit X1 provided in the second non-display area NAA2 has the same structure as the first switching unit X1 described with reference to FIGS. 5 and 6. FIG.

Also, all the second switching units X2 provided in the first non-display area NAA1 have the same structure as the first switching unit X1 described with reference to FIGS. 5 and 6. FIG.

Therefore, the first terminal, which is the gate of the second transistor, is connected to the second control line CL2, the second terminal of the second transistor is connected to the even gate line, And the third terminal is connected to the second low voltage line VSSL2.

The second transistor is connected to an end of the even gate line, an auxiliary line is connected between the third terminal of the second transistor and the second low voltage line (VSSL2), and the auxiliary line and the second low voltage The line VSSL2 is electrically connected through the contact hole.

7 is a diagram illustrating waveforms of clocks applied to a display device according to the present invention. A driving method of a display apparatus according to the present invention will be described with reference to FIG.

First, for example, the n-th stage Stage #n shown in FIG. 4 outputs the n-th gate pulse for one horizontal period to the n-th gate line GLn. In this case, the n-th gate pulse may be generated by the n-th clock CLKn among the clocks shown in FIG. 7 transmitted to the first gate driver 210. The clocks shown in FIG. 7 are supplied to the stages 211 constituting the first gate driver 210, and the stages 211 generate gate pulses to be outputted to odd-numbered gate lines Are sequentially generated.

In addition, the clocks shown in FIG. 7 are supplied to the stages 221 constituting the second gate driver 220, and the stages 221 are output to even-numbered gate lines using the clocks And sequentially generates gate pulses.

Second, switching transistors connected to the nth gate line GLn are turned on by the nth gate pulse, and data voltages are charged to the pixel electrodes PE connected to the switching transistors. Accordingly, light is output through the pixels P connected to the nth gate line GLn.

Third, at the time when the one horizontal period has elapsed and the switching transistors should be turned off, the controller 200 controls the first control line CL1 constituting the first switching unit X1, And transmits the control signal CS1.

To be more specific, the first control signal CS1 is supplied through the first control line CL1 at a time point when the odd-numbered switching transistors connected to the odd-numbered gate lines are to be turned off.

The first control signal CS1 may be the (n + 3) -th clock CLKn + 3 of the clocks shown in FIG. For example, the rising time of the (n + 3) -th clock (CLKn + 3) is the same as that of the n-th clock (CLKn).

Fourth, the first switching unit X1 is turned on in response to the first control signal CS1 transmitted through the first control line CL1 to turn on the n-th gate line GLn to the first low- (VSSL1).

The first low voltage VSS1 is supplied to the gates of the switching transistors connected to the nth gate line GLn via the first low voltage line VSSL1. Thus, the switching transistors are turned off.

1, the delay width B of the n-th gate pulse, which is output from the n-th stage Stage #n and supplied to the right end of the display panel 100, is increased, Even if the polling time is increased, the turn-off time of the switching transistors is not increased.

In other words, regardless of the delay width B of the n-th gate pulse, the switching transistors connected to the n-th gate line are turned off by the first low voltage VSS1. Therefore, the turn-off time of the switching transistors provided on the right side of the display panel 100 may be the same as or similar to the turn-off time of the switching transistors provided on the left side of the display panel 100. [ Accordingly, the image quality on the left and right sides of the display panel 100 can be uniformly maintained.

The second switching unit X2 may also be driven in the same manner as the first switching unit X1.

For example, the second control signal CS2 is supplied through the second control line CL2 when the even-numbered switching transistors connected to the even-numbered gate lines are to be turned off.

In this case, the second switching unit X2 connects the even-numbered gate line to the second low-voltage line VSSL2 according to the second control signal CS2 transmitted through the second control line CL2 .

Therefore, the turn-off time of the switching transistors provided on the right side of the even-numbered gate line may be the same as or similar to the turn-off time of the switching transistors provided on the left side of the even-numbered gate line. Accordingly, the image quality on the left and right sides of the display panel 100 can be uniformly maintained.

8 is an exemplary view showing a width of a non-display area of a display panel in which a gate driver according to the present invention is incorporated and a width of a non-display area of a conventional display panel. 8A is an exemplary view showing a non-display region (Bezel, NAA) of a display panel using a double feeding method and a gate-in panel method, and FIG. 8B is a cross- Fig. 8 is a diagram showing a width of a non-display area of a display panel.

As described above, in the present invention, the quality of the image on the left and right sides of the display panel 100 can be uniformly maintained even if the single feeding method is used.

Generally, the vertical length of the stages using the single feeding method and the gate-in panel method is twice the vertical length of the stages using the double feeding method and the gate-in-panel method.

Therefore, as shown in Fig. 8 (b), the transverse lengths of the stages 211 applied to the present invention using the single feeding method and the gate in-panel method are, as shown in Fig. 8 (a) The length of the stages using the double feeding method and the gate-in-panel method can be reduced.

Therefore, the width of the non-display area of the display panel according to the present invention using the single feeding method and the gate-in panel method can be reduced more than the width of the non-display area of the conventional display panel using the double- have.

For example, when the width of the non-display area of the conventional display panel using the double feeding method and the gate-in panel method shown in FIG. 8A is 2.8 mm, The width of the non-display area of the display panel according to the present invention may be 2.01 mm.

To be more specific, even if the width of the seal provided on the display panel shown in (a) is the same as the width of the seal provided on the display panel shown in (b) The width of the non-display area shown in (a) is larger than the width of the non-display area shown in (b) because the widths of the stages are larger than the widths of the stages 211 shown in (b).

Therefore, the width of the non-display area of the display panel using the single feeding method according to the present invention may be smaller than the width of the non-display area of the conventional display panel using the double feeding method.

In particular, the width of the non-display area NAA of the display panel according to the present invention is larger than the width of the non-display area of the display panel using the conventional double feeding method, (K) minus the width of the stage of the single feeding type shown in (b).

Accordingly, the present invention can be used for manufacturing a display device having a narrow non-display area.

The present invention is briefly summarized as follows.

First, the present invention uses a single feeding method and a gate-in-panel method, and particularly controls a polling time of a gate pulse using a low voltage (VSS). As the low voltage (VSS), a gate voltage (VGL) used for generation of a gate pulse may be used.

The present invention supplies the low voltage (VSS) to the gate line at the end of the gate line in order to prevent the polling time of the gate pulse from being increased by the load of the gate line.

Thus, the switching transistors connected to the gate line can be turned off at the normal timing. Therefore, the turn-off points of the switching transistors provided on the left and right sides of the gate line can be the same or similar, so that the quality of the left and right images of the display panel can be uniform.

Second, since the vertical length of the stages using the single feeding method and the gate-in-panel method is twice the vertical length of the stages using the double feeding method and the gate-in-panel method, The transverse length may be less than the transverse length of the stages using the double feed method and the gate in panel method.

Therefore, the width of the non-display area of the display panel according to the present invention using the single feeding method and the gate-in panel method can be reduced more than the width of the non-display area of the conventional display panel using the double- have. Accordingly, the present invention can be used for manufacturing a display device having a narrow non-display area.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: display panel 210: first gate driver
220: second gate driver 300: data driver
400: control unit X1: first switching unit
X2: the second switching unit

Claims (7)

A display area having gate lines and data lines; And
And non-display areas provided on an outer periphery of the display area,
Wherein a first gate driver is embedded in the first non-display area and a second gate driver is embedded in the second non-display area of the first non-display area and the second non- And,
The stages constituting the first gate driver output gate pulses to odd gate lines among the gate lines, and the stages constituting the second gate driver output gate pulses to the even gate lines among the gate lines. Respectively,
Numbered gate lines, a first switching unit provided in the second non-display area is connected to an end of each of the odd-numbered gate lines, and a second switching unit connected to an end of each of the even- And,
Wherein the first switching unit is connected to a first low-voltage line provided in the second non-display area, a first control line provided in the second non-display area, and the odd-numbered gate line, A second low voltage line provided in a non-display area, a second control line provided in the second non-display area, and a gate driver connected to the even gate line. The method according to claim 1,
The first switching unit is a first transistor including a first terminal, a second terminal, and a third terminal,
The second switching unit is a second transistor including a first terminal, a second terminal and a third terminal,
The first terminal being the gate of the first transistor being connected to the first control line, the second terminal of the first transistor being connected to the odd gate line, and the third terminal of the first transistor being A second low voltage line connected to the first low voltage line,
The first terminal being the gate of the second transistor is connected to the second control line, the second terminal of the second transistor is connected to the even gate line, and the third terminal of the second transistor is connected to the even- And a gate driver connected to the second low voltage line. The method according to claim 1,
Wherein the first switching unit connects the odd gate line to the first low voltage line according to a first control signal transmitted through the first control line,
And the second switching unit has a gate driver for connecting the even-numbered gate line to the second low-voltage line according to a second control signal transmitted through the second control line. The method of claim 3,
Wherein the first control signal is supplied through the first control line at a time when odd-numbered switching transistors connected to the odd-numbered gate lines are to be turned off,
Wherein the second control signal includes a gate driver that is supplied through the second control line at a time point when the even-numbered switching transistors connected to the even-numbered gate lines are to be turned off. A display panel in which gate lines and data lines are embedded;
A data driver for supplying data voltages to the data lines; And
And a control unit for controlling the data driver,
A first gate driver is embedded in the first non-display area of the first non-display area and the second non-display area which are arranged on the outer periphery of the display area of the display panel and facing each other, 2 gate driver is built in,
The stages constituting the first gate driver sequentially output gate pulses to odd gate lines among the gate lines, and the stages constituting the second gate driver are connected to the even gate lines among the gate lines Sequentially outputs gate pulses,
Numbered gate lines are connected to the first low-voltage line in accordance with a first control signal, and the first switching unit provided at the end of each of the odd-numbered gate lines connects the odd- 2 switching unit connects the even-numbered gate line to a second low-voltage line in accordance with a second control signal. 6. The method of claim 5,
Wherein the first switching unit is provided in the second non-display area, the second switching unit is provided in the first non-display area,
Wherein the first switching unit is connected to the first low voltage line provided in the second non-display area, the first control line provided in the second non-display area, and the odd gate line, 1) non-display region, a second control line provided in the second non-display region, and the even gate line. 6. The method of claim 5,
The control unit transmits the first control signal to the first switching unit at a time when odd-numbered switching transistors connected to the odd-numbered gate lines are to be turned off,
Wherein the control unit transmits the second control signal to the second switching unit at a time point when the even-numbered switching transistors connected to the even-numbered gate lines are to be turned off.

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