KR102040659B1 - Scan Driver and Display Device Using the same - Google Patents

Abstract

The invention provides a level shifter for outputting start signals, clock signals, and reset clock signals; And a shift register configured to shift and output the scan signal in response to the start signal, the clock signals, and the reset clock signals, wherein the Nth stages of the stages receive the Nth clock signal in response to the potential of the Q node. A pull-up transistor for outputting to the N-th stage output terminal, a pull-down transistor for outputting a low potential voltage to the output terminal of the N-th stage corresponding to the potential of the QB node, a Q-node charging and discharging unit for charging and discharging the Q node, and QB QB node charge and discharge unit for charging and discharging the node, the QB node charge and discharge unit may maintain the QB node at a voltage between logic high and logic low after the low potential voltage is output through the output terminal of the N-th stage.

Description

Scan driver and display device using the same {Scan Driver and Display Device Using the same}

The present invention relates to a scan driver and a display device using the same.

With the development of information technology, the market for a display device, which is a connection medium between a user and information, is growing. Accordingly, the use of display devices such as organic light emitting display (OLED), liquid crystal display (LCD), plasma display panel (PDP), and the like is increasing.

Some of the aforementioned display devices, for example, a liquid crystal display or an organic light emitting display device, include a display panel including a plurality of subpixels arranged in a matrix form and a driving unit for driving the display panel. The driver includes a scan driver for supplying a scan signal (or gate signal) to the display panel and a data driver for supplying a data signal to the display panel.

When the display device is supplied with a scan signal and a data signal to subpixels arranged in a matrix form, the display device emits light so that an image can be displayed.

On the other hand, the scan driver for outputting the scan signal is divided into an external circuit mounted on an external substrate of the display panel in the form of an integrated circuit and an embedded type formed in the display panel in the form of a gate in panel formed with a thin film transistor process.

The built-in scan driver is made of amorphous silicon, an oxide thin film transistor, or the like. In the case of the oxide thin film transistor, the current transfer characteristics are superior to that of the amorphous silicon thin film transistor, thereby reducing the circuit size. However, the oxide thin film transistor has a disadvantage in that the threshold voltage recovery characteristic due to the stress bias is lower than that of the amorphous silicon thin film transistor.

Therefore, when the built-in scan driver is formed of an oxide thin film transistor and the display panel is driven, the time for reaching the limit lifetime is shorter than that of the amorphous silicon thin film transistor. Therefore, the embedded scan driver is required to increase the reliability and life of the circuit.

The present invention for solving the above-mentioned problems of the background art is to provide a scan driver and a display device using the same to reduce the positive bias stress to improve the life and reliability of the scan driver.

The present invention as a means for solving the above problems is a level shifter for outputting a start signal, clock signals and reset clock signals; And a shift register configured to shift and output the scan signal in response to the start signal, the clock signals, and the reset clock signals, wherein the Nth stages of the stages receive the Nth clock signal in response to the potential of the Q node. A pull-up transistor for outputting to the N-th stage output terminal, a pull-down transistor for outputting a low potential voltage to the output terminal of the N-th stage corresponding to the potential of the QB node, a Q-node charging and discharging unit for charging and discharging the Q node, and QB QB node charge and discharge unit for charging and discharging the node, the QB node charge and discharge unit may maintain the QB node at a voltage between logic high and logic low after the low potential voltage is output through the output terminal of the N-th stage.

The QB node charging and discharging unit may maintain the QB node at a voltage between logic high and logic low when the N-th reset clock signal of the logic low is supplied.

The QB node charging and discharging unit discharges the QB node in response to the potential of the Q node, and at least one charges the QB node in response to the Nth reset clock signal or sets the QB node between a logic high and a logic low. A mirror transistor may be maintained at a voltage, but the QB node may be maintained at a voltage level corresponding to the threshold voltage of one of the mirror transistors.

The mirror type transistor includes a first side transistor having a gate electrode and a first electrode connected to an Nth reset clock signal terminal supplied with an Nth reset clock signal, and a second electrode connected to a QB node, and a gate electrode and a first electrode connected to a QB node. The second electrode may include a second side transistor connected to an electrode and a second electrode connected to an N-th reset clock signal terminal.

The mirror type transistor includes a first side transistor having a gate electrode and a first electrode connected to an Nth reset clock signal terminal supplied with an Nth reset clock signal, and a second electrode connected to a QB node, and a gate electrode and a first electrode connected to a QB node. A second-first transistor connected to an electrode; a second-second transistor connected to a second electrode of the second-first transistor; and a second electrode connected to an N-th reset clock signal terminal. It may include.

The Q node charging and discharging unit includes a first transistor having a gate electrode and a first electrode connected to a start signal terminal supplied with a start signal or an output terminal of an N-1 stage, and a second electrode connected to a Q node, and a gate electrode connected to a QB node. A second transistor having a first electrode connected to the low potential voltage terminal supplied with the low potential voltage and a second electrode connected to the Q node, and a gate electrode connected to the output terminal of the N + 2 stage and having a low potential voltage The terminal may include a Q node discharge transistor having a first electrode connected to the terminal and a second electrode connected to the Q node.

In another aspect, the present invention is a display panel; A data driver connected to data lines of the display panel; And a level shifter connected to the scan lines of the display panel and outputting start signals, clock signals, and reset clock signals, and stages for shifting and outputting scan signals corresponding to the start signals, clock signals, and reset clock signals. And a N-th stage of the stages, the pull-up transistor outputting the N-th clock signal to the output terminal of the N-th stage corresponding to the potential of the Q node, and a low potential voltage corresponding to the potential of the QB node. A pull-down transistor for outputting to the output terminal of the Nth stage, a Q node charging and discharging unit for charging and discharging a Q node, and a QB node charging and discharging unit for charging and discharging a QB node, wherein the QB node charging and discharging unit is an output terminal of the Nth stage. After the low potential voltage is output through the display to provide a display device characterized in that the QB node is maintained at a voltage between logic high and logic low All.

The QB node charging and discharging unit may maintain the QB node at a voltage between logic high and logic low when the N-th reset clock signal of the logic low is supplied.

The QB node charging and discharging unit discharges the QB node in response to the potential of the Q node, and at least one charges the QB node in response to the Nth reset clock signal or sets the QB node between a logic high and a logic low. A mirror transistor may be maintained at a voltage, but the QB node may be maintained at a voltage level corresponding to the threshold voltage of one of the mirror transistors.

The mirror type transistor includes a first side transistor having a gate electrode and a first electrode connected to an Nth reset clock signal terminal supplied with an Nth reset clock signal, and a second electrode connected to a QB node, and a gate electrode and a first electrode connected to a QB node. The second electrode may include a second side transistor connected to an electrode and a second electrode connected to an N-th reset clock signal terminal.

The mirror type transistor includes a first side transistor having a gate electrode and a first electrode connected to an Nth reset clock signal terminal supplied with an Nth reset clock signal, and a second electrode connected to a QB node, and a gate electrode and a first electrode connected to a QB node. A second-first transistor connected to an electrode; a second-second transistor connected to a second electrode of the second-first transistor; and a second electrode connected to an N-th reset clock signal terminal. It may include.

The Q node charging and discharging unit includes a first transistor having a gate electrode and a first electrode connected to a start signal terminal supplied with a start signal or an output terminal of an N-1 stage, and a second electrode connected to a Q node, and a gate electrode connected to a QB node. A second transistor having a first electrode connected to the low potential voltage terminal supplied with the low potential voltage and a second electrode connected to the Q node, and a gate electrode connected to the output terminal of the N + 2 stage and having a low potential voltage The terminal may include a Q node discharge transistor having a first electrode connected to the terminal and a second electrode connected to the Q node.

The present invention has the effect of providing a scan driver and a display device using the same to lower the voltage applied to the QB node and reduce the positive bias stress of the node to improve the life and reliability of the scan driver. In addition, the present invention has the effect of providing a scan driver that can self-refresh the node by the voltage applied to the QB node by the mirror transistor to automatically vary, and a display device using the same.

1 is a schematic block diagram of a display device;
FIG. 2 is a diagram illustrating a configuration of a subpixel illustrated in FIG. 1. FIG.
3 is a block diagram of a shift register according to the first embodiment of the present invention;
4 is a circuit diagram of an N-th stage according to the first embodiment of the present invention.
FIG. 5 is a diagram illustrating some components for explaining the operation of the N-th stage shown in FIG. 4. FIG.
6 is an operation timing diagram of an Nth stage illustrated in FIG. 4.
7 is a circuit diagram of an Nth stage according to a second embodiment of the present invention;
FIG. 8 is a schematic view illustrating the operation of the N-th stage shown in FIG. 7; FIG.
9 is an operation timing diagram of an Nth stage illustrated in FIG. 7.

Hereinafter, with reference to the accompanying drawings, the specific content for the practice of the present invention will be described.

<First Embodiment>

FIG. 1 is a schematic block diagram of a display device, and FIG. 2 is a diagram illustrating a configuration of a subpixel illustrated in FIG. 1.

As shown in FIG. 1, the display device includes a display panel 100, a timing controller 110, a data driver 120, and scan drivers 130 and 140.

The display panel 10 includes subpixels separated from and connected to the data lines DL and the scan lines GL. The display panel 10 includes a display area 100A in which subpixels are formed and a non-display area 100B in which various signal lines or pads are formed outside the display area 100A. The display panel 100 may be implemented as a liquid crystal display (LCD), an organic light emitting display (OLED), an electrophoretic display (EPD), or the like.

As shown in FIG. 2, one sub-pixel SP is supplied in response to a scan signal supplied through the switching transistor SW and the switching transistor SW connected to the scan line GL1 and the data line DL1. Pixel circuit PC that operates in response to the data signal DATA is included. The subpixel SP is implemented as a liquid crystal display panel including a liquid crystal element or an organic light emitting display panel including an organic light emitting element according to the configuration of the pixel circuit PC.

When the display panel 100 is configured as a liquid crystal display panel, it is a twisted nematic (TN) mode, a vertical alignment (VA) mode, an in plane switching (IPS) mode, a fringe field switching (FFS) mode, or an electrically controlled wired fringefringence (ECB). Implemented in mode. When the display panel 100 is configured as an organic light emitting display panel, the display panel 100 may be implemented in a top-emission method, a bottom-emission method, or a dual-emission method.

The timing controller 110 receives a timing signal such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock through an LVDS or TMDS interface receiving circuit connected to the image board. The timing controller 110 generates timing control signals for controlling operation timings of the data driver 120 and the scan drivers 130 and 140 based on the input timing signal.

The data driver 120 includes a plurality of source drive integrated circuits (ICs). The source drive ICs receive the digital video data RGB and the source timing control signal DDC from the timing controller 110. The source drive ICs convert the digital video data RGB into a gamma voltage in response to the source timing control signal DDC to generate a data voltage, and transmit the data voltage through the data lines DL of the display panel 100. Supply. The source drive ICs are connected to the data lines DL of the display panel 100 by a chip on glass (COG) process or a tape automated bonding (TAB) process.

The scan driver 130, 140 includes a level shifter 130 and a shift register 140. The scan drivers 130 and 140 are formed by a gate in panel (GIP) method in which the level shifter 130 and the shift register 140 are divided. The level shifter 130 is formed on an external substrate connected to the display panel 100 in the form of an IC.

The level shifter 130 shifts the level of the clock signals clk, the reset clock signals reset_clk, and the start signal vst under the control of the timing controller 11, and supplies the shift signal to the shift register 140. The shift register 140 is formed in the form of a thin film transistor (hereinafter, TFT) in the non-display area 100B of the display panel 100 by the GIP method. The shift register 140 includes stages for shifting and outputting a scan signal in response to the clock signals clk, the reset clock signals reset_clk, and the start signal vst. Stages included in the shift register 140 sequentially output scan signals through output terminals.

Meanwhile, the shift register 140 is formed of thin film transistors. The oxide thin film transistor has an advantage in that the current can be reduced in size compared to the amorphous silicon thin film transistor, thereby reducing the circuit size. However, the oxide thin film transistor has a disadvantage in that the threshold voltage recovery characteristic due to the stress bias is lower than that of the amorphous silicon thin film transistor. This is because in the case of amorphous silicon thin film transistors, the threshold voltage is kept constant over time (clamping voltage saturation), but in the case of oxide thin film transistors, the threshold voltage is continuously shifted in the positive direction over time. (Clamping Voltage Not Saturation).

The present invention proposes a method of reducing the effective stress time of a pull-down transistor subjected to a positive bias stress in order to improve the lifetime and reliability of the shift register 140 embedded in the GIP method. . According to this method, when the shift register 140 is implemented with oxide thin film transistors, lifespan and reliability may be improved. According to this method, the shift register 140 may be implemented not only as an oxide thin film transistor but also as an amorphous silicon thin film transistor.

Hereinafter, the shift register of the GIP method which can improve the lifetime and reliability is demonstrated.

3 is a block diagram of a shift register according to a first embodiment of the present invention, FIG. 4 is a circuit diagram of an N-th stage according to the first embodiment of the present invention, and 5 is an N shown in FIG. FIG. 6 is a configuration diagram for explaining the operation of the stage. FIG. 6 is an operation timing diagram of the N-th stage shown in FIG. 4.

As shown in FIGS. 3 to 6, the shift register according to the first embodiment of the present invention includes a plurality of stages STG [n] to STG [n + 2]. The plurality of stages STG [n] to STG [n + 2] include four-phase clock signals clk1 to clk4, four-phase reset clock signals reset_clk1 to reset_clk4, a low potential voltage and a start signal vst. Is supplied.

The Nth stage STG [n] is an output terminal of the start signal vst, the first clock signal clk1, the first reset clock signal reset_clk1, and the N + 2th stage STG [n + 2]. It operates based on the scan signal Vg_out [n + 2] output from Gout [n + 2]. The Nth stage STG [n] outputs the Nth scan signal Vg_out [n] through its output terminal Gout [n].

The N + 1th stage STG [n + 1] is the scan signal Vg_out [n] output from the output terminal Gout [n] of the Nth stage STG [n], and the second clock signal clk2. ), The second reset clock signal reset_clk2 and the scan signal output from the output terminal of the N + 3th stage. The N + 1th stage STG [n + 1] outputs the N + 1th scan signal Vg_out [n + 1] through its output terminal Gout [n + 1].

The N + 2th stage STG [n + 2] is a scan signal Vg_out [n + 1] output from the output terminal Gout [n + 1] of the N + 1th stage STG [n + 1]. ), The third clock signal clk3, the third reset clock signal reset_clk3, and the scan signal output from the output terminal of the N + 4th stage. The N + 2th stage STG [n + 12] outputs the N + 2th scan signal Vg_out [n + 2] through its output terminal Gout [n + 2].

The plurality of stages STG [n] to STG [n + 2] are cascaded so that the rear end uses the scan signal output from the front end as above. For example, the scan signal Vg_out [n] output from the output terminal Gout [n] of the Nth stage STG [n] is the start signal terminal of the N + 1st stage STG [n + 1]. VST). Also, the plurality of stages STG [n] to STG [n + 2] are connected to use a scan signal output from an output terminal positioned two steps later than the stage as a reset signal (reset signal of the Q node). do. For example, the scan signal Vg_out [n + 2] output from the output terminal Gout [n + 2] of the N + 2th stage STG [n + 2] is connected to the Nth stage STG [n]. It is supplied to the reset terminal Vnext.

Hereinafter, a configuration of a circuit for the plurality of stages STG [n] to STG [n + 2] will be described in detail using the Nth stage STG [n] as an example.

The N-th stage STG [n] includes a pull-up transistor Tpu, a pull-down transistor Tpd, Q node charge / discharge units T1, T2, and T8, QB node charge and discharge units T3, T4, and T5, and a first capacitor. C1) and the second capacitor C2 are included.

First, the pull-up transistor Tpu, the pull-down transistor Tpd, the Q node charge / discharge units T1, T2, and T8, the QB node charge and discharge units T3, T4, and T5, the first capacitor C1, and the second capacitor C2. ) And the connection relationship between them are as follows.

The pull-up transistor Tpu outputs the Nth clock signal to the output terminal Gout [n] of the Nth stage in response to the potential of the Q node Q. Hereinafter, for convenience of description, the Nth clock signal is defined as a first clock signal clk1. However, in the case of the clock signal, another signal (eg, the second clock signal, the third clock signal, etc.) may be selected and input according to the position of the stage. In the pull-up transistor Tpu, a gate electrode is connected to the Q node Q, and a first electrode is connected to the first clock signal terminal CLK [n] for supplying the first clock signal clk1. The second electrode is connected to the terminal Gout [n].

The pull-down transistor Tpd outputs a low potential voltage to the output terminal Gout [n] of the Nth stage in response to the potential of the QB node QB. The pull-down transistor Tpd has a gate electrode connected to the QB node QB, a first electrode connected to a low potential voltage terminal VGL (or VSS) for supplying a low potential voltage, and an output terminal Gout [of the Nth stage. n]) is connected to the second electrode.

The Q node charging / discharging portions T1, T2, and T8 charge or discharge the Q node Q in response to the potential of the start signal vst or the output terminal Gout [n-1] of the N-1 stage, which is the front end. do. The Q node charging and discharging parts T1, T2, and T8 include a first transistor T1, a second transistor T2, and a Q node discharge transistor T8.

The first transistor T1 is turned on in response to the start signal vst or the potential of the output terminal Gout [n-1] of the N-th stage, and charges the Q node Q. Hereinafter, for convenience of description, the first transistor T1 follows an electric potential of the start signal vst. However, in the case of the first transistor T1, the start signal may be directly received or a signal corresponding to the start signal may be supplied from the output terminal of the stage (or two stages before) according to the position of the stage. In the first transistor T1, the gate electrode and the first electrode are commonly connected to the output terminal Gout [n-1] of the N-1 stage, and the second electrode is connected to the Q node Q.

The second transistor T2 is turned on in response to the potential of the QB node QB and discharges the Q node Q to a low potential voltage. In the second transistor T2, a gate electrode is connected to the QB node QB, a first electrode is connected to the low potential voltage terminal VGL supplying a low potential voltage, and a second electrode is connected to the Q node Q. .

The Q node discharge transistor T8 is turned on in response to the potential of the output terminal Gout [n + 2] of the N + 2th stage and discharges the Q node Q to a low potential voltage. The Q node discharge transistor T8 maintains the discharge level of the Q node Q at a low potential voltage. In the Q-node discharge transistor T8, a gate electrode is connected to the output terminal Gout [n + 2] of the N + 2th stage, and a first electrode is connected to the low potential voltage terminal VGL supplying a low potential voltage. The second electrode is connected to the Q node Q.

The QB node charging and discharging units T3, T4, and T5 charge the QB node QB in response to the first reset clock signal clk1 or discharge the QB node QB at a voltage between logic high and logic low. do. The QB node charge and discharge portions T3, T4, and T5 include mirror transistors T3 and T4 and QB node discharge transistors T5.

At least one of the mirror transistors T3 and T4 charges the QB node QB in response to the N-th reset clock signal or maintains the QB node QB at a voltage between logic high and logic low. Hereinafter, for convenience of description, the N-th reset clock signal is defined as a first reset clock signal reset_clk1. However, in the case of the reset clock signal, other signals (eg, the second reset clock signal, the third reset clock signal, etc.) may be selected and input according to the position of the stage.

The mirror transistors T3 and T4 include a first side transistor T3 and a second side transistor T4. In the first transistor T3, the gate electrode and the first electrode are connected to the first reset clock signal terminal Reset_CLK1 to which the first reset clock signal reset_clk1 is supplied, and the second electrode is connected to the QB node QB. . In the second transistor T4, a gate electrode and a first electrode are connected to the QB node QB, and a second electrode is connected to the first reset clock signal terminal Reset_CLK1.

The QB node discharge transistor T5 is turned on in response to the potential of the Q node Q and discharges the QB node QB to a low potential voltage. The QB node discharge transistor T5 serves to maintain the discharge level of the QB node QB at a low potential voltage.

When the Q node Q is electrically floating, the first capacitor C1 holds a voltage of a node as a logic low voltage. One end of the first capacitor C1 is connected to the Q node Q and the other end thereof is connected to the low potential voltage terminal VGL. When the QB node QB is electrically floating, the second capacitor C2 holds a voltage of the node as a logic low voltage. One end of the second capacitor C2 is connected to the QB node QB and the other end of the second capacitor C2 is connected to the low potential voltage terminal VGL.

Meanwhile, in the above description, the shift register is configured as an N-type transistor, but the present invention is not limited thereto. In the above description, the drain electrode and the source electrode of the N-type transistor have been described as the first electrode and the second electrode, which may be replaced with the second electrode and the first electrode.

Next, a scheme of clock signals and reset clock signals will be described.

Looking at the system of the four-phase clock signals clk1 to clk4, the first to fourth clock signals clk1 to clk4 are sequentially formed to switch from a logic high state to a logic low state. In this case, the first to fourth clock signals clk1 to clk4 are formed to have non-overlapping sections.

Looking at the scheme of the four-phase reset clock signals reset_clk1 to reset_clk4, the first to fourth reset clock signals reset_clk1 to reset_clk4 are sequentially formed to switch from a logic high state to a logic low state. In this case, the first to fourth reset clock signals reset_clk1 to reset_clk4 have a non-overlapping section of the logic high state and are spaced apart from each other. In addition, the logic high section of the first to fourth reset clock signals reset_clk1 to reset_clk4 is formed to precede the logic high section of the first to fourth clock signals clk1 to clk4. That is, the rising edges of the first to fourth reset clock signals reset_clk1 to reset_clk4 are formed to precede the rising edges of the first to fourth clock signals clk1 to clk4. The reason why the rising edges of the first to fourth reset signals (reset_clk1 to reset_clk4) are formed before the rising edges of the first to fourth clock signals (clk1 to clk4) is minimized and the coupling between them is consumed. This is to lower the power.

Hereinafter, the operating characteristics of the Nth stage will be described.

The Q node Q is charged in response to the potential of the start signal vst corresponding to the logic high H, and the output terminal Gout [+2] of the N + 2th stage corresponding to the logic low L is charged. Corresponding to the discharge. When the Q node Q is in a charged state, a scan signal corresponding to the logic high H of the first clock signal clk1 is output. When the Q node Q is in a discharged state, a logic having a low potential voltage is output. The scan signal corresponding to the row L is output.

Specifically, the Q node Q is charged as the first transistor T1 is turned on in response to the potential of the start signal vst corresponding to the logic high H. At this time, the QB node QB is temporarily charged as the first and second side transistors T3 and T4 are temporarily turned on in response to the potential of the first reset clock signal reset_clk1 of logic high H (FIG. See (1) of 6). However, since Vgs1 (see FIG. 5) of the QB node discharge transistor T5 is increased than Vgs2 (see FIG. 5) of the second side transistor T4, the pull-down transistor Tpd is reset without turning on.

In order to configure the optimum conditions under which the mirror transistors T3 and T4 can operate as described above, it is preferable to make the width of the channel of the QB node discharge transistor T5 larger than the width of the channel of the first side transistor T3. good.

As the Q node Q is charged, the pull-down transistor Tpu outputs the first clock signal clk1 of logic high H through the output terminal Gout [n] of the Nth stage. After the first clock signal clk1 of logic high H is output, the Q node Q is discharged by the first capacitor C1.

Thereafter, the first transistor T1 is turned off in response to the potential of the start signal vst corresponding to the logic low L, and corresponds to the potential of the output terminal Gout [n + 2] of the N + 2th stage. As the Q node discharge transistor T8 is turned on, the Q node Q is discharged. The QB node QB is reset through the second side transistor T4 turned on in response to the potential of the first reset clock signal reset_clk1 corresponding to the logic high H. At this time, the QB node QB is maintained at a voltage corresponding to the threshold voltage Vth of the second side transistor T4 (see (2) in FIG. 6).

During this period, the stresses applied to the gate electrodes of the second side transistor T4 and the pull-down transistor Tpd become similar, and thus, their threshold voltage shifts will be similar. Accordingly, when the threshold voltage of the second side transistor T4 is shifted in the positive direction, the level of the voltage applied to the QB node QB increases correspondingly. That is, the QB node QB receives a voltage corresponding to the threshold voltage of the second side transistor T4.

Typically, the QB node QB receives a positive bias stress as the logic high H is continuously applied after the scan signal of the logic low L is output. However, when the mirror type transistors T3 and T4 and the QB node discharge transistor T5 configured as in the present invention are applied, the threshold voltage of the second side transistor T4 after the scan signal of the logic low L is output. Since the voltage of the QB node QB is maintained at the voltage corresponding to Vth), it is possible to reduce the positive bias stress.

Second Embodiment

7 is a circuit diagram of the N-th stage according to the second embodiment of the present invention, 8 is a partial configuration diagram for explaining the operation of the N-th stage shown in FIG. The operation timing diagram of the N stage.

3, 7 to 9, the shift register according to the second embodiment of the present invention also includes a plurality of stages STG [n] to STG [n + 2]. The plurality of stages STG [n] to STG [n + 2] include four-phase clock signals clk1 to clk4, four-phase reset clock signals reset_clk1 to reset_clk4, a low potential voltage and a start signal vst. Is supplied.

Since the shift register according to the second embodiment of the present invention also has a plurality of stages (STG [n] to STG [n + 2]) also have a dependent connection relationship as in the first embodiment, description thereof will be omitted. The configuration of a circuit for the plurality of stages STG [n] to STG [n + 2] will be described in detail with the example of the Nth stage STG [n].

The N-th stage STG [n] includes a pull-up transistor Tpu, a pull-down transistor Tpd, Q node charge / discharge units T1, T2, and T8, QB node charge and discharge units T3, T4, and T5, and a first capacitor. C1) and the second capacitor C2 are included.

First, the pull-up transistor Tpu, the pull-down transistor Tpd, the Q node charge / discharge units T1, T2, and T8, the QB node charge and discharge units T3, T4, and T5, the first capacitor C1, and the second capacitor C2. ) And the connection relationship between them are as follows.

The pull-up transistor Tpu outputs the Nth clock signal to the output terminal Gout [n] of the Nth stage in response to the potential of the Q node Q. Hereinafter, for convenience of description, the Nth clock signal is defined as a first clock signal clk1. However, in the case of the clock signal, another signal (eg, the second clock signal, the third clock signal, etc.) may be selected and input according to the position of the stage. In the pull-up transistor Tpu, a gate electrode is connected to the Q node Q, and a first electrode is connected to the first clock signal terminal CLK [n] for supplying the first clock signal clk1. The second electrode is connected to the terminal Gout [n].

The pull-down transistor Tpd outputs a low potential voltage to the output terminal Gout [n] of the Nth stage in response to the potential of the QB node QB. The pull-down transistor Tpd has a gate electrode connected to the QB node QB, a first electrode connected to a low potential voltage terminal VGL (or VSS) for supplying a low potential voltage, and an output terminal Gout [of the Nth stage. n]) is connected to the second electrode.

The Q node charging / discharging portions T1, T2, and T8 charge or discharge the Q node Q in response to the potential of the start signal vst or the output terminal Gout [n-1] of the N-1 stage, which is the front end. do. The Q node charging and discharging parts T1, T2, and T8 include a first transistor T1, a second transistor T2, and a Q node discharge transistor T8.

The first transistor T1 is turned on in response to the start signal vst or the potential of the output terminal Gout [n-1] of the N-th stage, and charges the Q node Q. Hereinafter, for convenience of description, the first transistor T1 follows an electric potential of the start signal vst. However, in the case of the first transistor T1, the start signal may be directly received or a signal corresponding to the start signal may be supplied from the output terminal of the stage (or two stages before) according to the position of the stage. In the first transistor T1, the gate electrode and the first electrode are commonly connected to the output terminal Gout [n-1] of the N-1 stage, and the second electrode is connected to the Q node Q.

The second transistor T2 is turned on in response to the potential of the QB node QB and discharges the Q node Q to a low potential voltage. In the second transistor T2, a gate electrode is connected to the QB node QB, a first electrode is connected to the low potential voltage terminal VGL supplying a low potential voltage, and a second electrode is connected to the Q node Q. .

The Q node discharge transistor T8 is turned on in response to the potential of the output terminal Gout [n + 2] of the N + 2th stage and discharges the Q node Q to a low potential voltage. The Q node discharge transistor T8 maintains the discharge level of the Q node Q at a low potential voltage. In the Q-node discharge transistor T8, a gate electrode is connected to the output terminal Gout [n + 2] of the N + 2th stage, and a first electrode is connected to the low potential voltage terminal VGL supplying a low potential voltage. The second electrode is connected to the Q node Q.

The QB node charging and discharging units T3, T4, and T5 charge the QB node QB in response to the first reset clock signal clk1 or discharge the QB node QB at a voltage between logic high and logic low. do. The QB node charge / discharge units T3, T4, and T5 include mirror transistors T3, T4-1, and T4-2, and a QB node discharge transistor T5.

At least one of the mirror transistors T3, T4-1, and T4-2 charges the QB node QB in response to the Nth reset clock signal, or sets the QB node QB to a voltage between logic high and logic low. Keep it. Hereinafter, for convenience of description, the N-th reset clock signal is defined as a first reset clock signal reset_clk1. However, in the case of the reset clock signal, other signals (eg, the second reset clock signal, the third reset clock signal, etc.) may be selected and input according to the position of the stage.

The mirror transistors T3, T4-1, and T4-2 include a first side transistor T3, a second-first transistor T4-1, and a second-second transistor T4-2. In the first transistor T3, the gate electrode and the first electrode are connected to the first reset clock signal terminal Reset_CLK1 to which the first reset clock signal reset_clk1 is supplied, and the second electrode is connected to the QB node QB. . In the second-first transistor T4-1, a gate electrode and a first electrode are connected to the QB node QB. In the second-to-second transistor T4-2, the first electrode and the gate electrode are connected to the second electrode of the second-first transistor T4-1, and the second electrode to the first reset clock signal terminal Reset_CLK1. This is connected.

In the second embodiment of the present invention, it is assumed that the second side transistors T4-1 and T4-2 are composed of two transistors. However, the second side transistors T4-1 and T4-2 may be configured with N (N is an integer of 2 or more) to increase the voltage applied to the QB node QB. That is, the voltage applied to the QB node QB increases when the number of second side transistors T4-1 and T4-2 increases, and the number of second side transistors T4-1 and T4-2 decreases. Will decrease. As such, the voltage applied to the QB node QB may be adjusted by changing the number of the second side transistors T4-1 and T4-2, and the second side transistors T4-1 and T4-2. ) May be set in response to the positive bias stress received by the QB node QB. For example, as in the second embodiment of the present invention, when the second side transistors T4-1 and T4-2 are configured with two, the QB node QB is connected to the second side transistors T4-1 and T4-2. The voltage corresponding to the threshold voltage (eg 2 * Vth) is applied.

The QB node discharge transistor T5 is turned on in response to the potential of the Q node Q and discharges the QB node QB to a low potential voltage. The QB node discharge transistor T5 serves to maintain the discharge level of the QB node QB at a low potential voltage.

When the Q node Q is electrically floating, the first capacitor C1 holds a voltage of a node as a logic low voltage. One end of the first capacitor C1 is connected to the Q node Q and the other end thereof is connected to the low potential voltage terminal VGL. When the QB node QB is electrically floating, the second capacitor C2 holds a voltage of the node as a logic low voltage. One end of the second capacitor C2 is connected to the QB node QB and the other end of the second capacitor C2 is connected to the low potential voltage terminal VGL.

Meanwhile, in the above description, the shift register is configured as an N-type transistor, but the present invention is not limited thereto. In the above description, the drain electrode and the source electrode of the N-type transistor have been described as the first electrode and the second electrode, which may be replaced with the second electrode and the first electrode.

Next, a scheme of clock signals and reset clock signals will be described.

Looking at the system of the four-phase clock signals clk1 to clk4, the first to fourth clock signals clk1 to clk4 are sequentially formed to switch from a logic high state to a logic low state. In this case, the first to fourth clock signals clk1 to clk4 are formed to have non-overlapping sections.

Looking at the scheme of the reset clock signals reset_clk1 to reset_clk4 of the four phases, the first to fourth reset clock signals reset_clk1 to reset_clk4 are sequentially formed to switch from a logic high state to a logic low state. In this case, the first to fourth reset clock signals reset_clk1 to reset_clk4 have a non-overlapping section of the logic high state and are spaced apart from each other. In addition, the logic high period of the first to fourth reset clock signals reset_clk1 to reset_clk4 is formed to precede the logic high period of the first to fourth clock signals clk1 to clk4. That is, the rising edges of the first to fourth reset clock signals reset_clk1 to reset_clk4 are formed to precede the rising edges of the first to fourth clock signals clk1 to clk4. The reason why the rising edges of the first to fourth reset signals (reset_clk1 to reset_clk4) are formed before the rising edges of the first to fourth clock signals (clk1 to clk4) is to minimize coupling and consume them. This is to lower the power.

Hereinafter, the operating characteristics of the Nth stage will be described.

The Q node Q is charged in response to the potential of the start signal vst corresponding to the logic high H, and the output terminal Gout [+2] of the N + 2th stage corresponding to the logic low L is charged. Corresponding to the discharge. When the Q node Q is in a charged state, a scan signal corresponding to the logic high H of the first clock signal clk1 is output. When the Q node Q is in a discharged state, a logic having a low potential voltage is output. The scan signal corresponding to the row L is output.

Specifically, the Q node Q is charged as the first transistor T1 is turned on in response to the potential of the start signal vst corresponding to the logic high H. At this time, the QB node QB corresponds to the potentials of the first reset clock signal reset_clk1 of the logic high H, and the first, second-first, and second-second transistors T3, T4-1, and T4. -2) is temporarily charged as it is turned on temporarily (see part (1) of FIG. 9). However, since Vgs1 (see FIG. 8) of the QB node discharge transistor T5 is increased than Vgs2 (see FIG. 8) of the 2-1 and 2-2 side transistors T4-1 and T4-2, the pull-down transistor ( Tpd) is not turned on and is reset.

In order to configure the optimum conditions under which the mirror transistors T3, T4-1, and T4-2 can operate as described above, the width of the channel of the QB node discharge transistor T5 is changed to the channel of the first side transistor T3. It is better to make it larger than the width of.

As the Q node Q is charged, the pull-down transistor Tpu outputs the first clock signal clk1 of logic high H through the output terminal Gout [n] of the Nth stage. After the first clock signal clk1 of the logic high H is output, the Q node Q is discharged by the first capacitor C1.

Thereafter, the first transistor T1 is turned off in response to the potential of the start signal vst corresponding to the logic low L, and corresponds to the potential of the output terminal Gout [n + 2] of the N + 2th stage. As the Q node discharge transistor T8 is turned on, the Q node Q is discharged. QB node QB through second-first and second-second transistors T4-1 and T4-2 turned on in response to the potential of first reset clock signal reset_clk1 corresponding to logic high H. Is reset. At this time, the QB node QB is maintained at a voltage corresponding to the threshold voltage Vth of the second-first and second-second transistors T4-1 and T4-2 (see (2) in FIG. 9). ).

During this period, the stresses applied to the gate electrodes of the 2-1 and 2-2 side transistors T4-1 and T4-2 and the pull-down transistor Tpd become similar, so that their threshold voltage shifts ( Vth Shift) will be similar. Accordingly, when the threshold voltages of the 2-1 and 2-2 transistors T4-1 and T4-2 are shifted in the positive direction, the level of the voltage applied to the QB node QB increases correspondingly. . That is, the QB node QB receives a voltage corresponding to the threshold voltages of the 2-1 and 2-2 transistors T4-1 and T4-2.

Typically, the QB node QB receives a positive bias stress as the logic high H is continuously applied after the scan signal of the logic low L is output. However, when the mirror transistors T3, T4-1 and T4-2 and the QB node discharge transistor T5 configured as in the present invention are applied, the second-1 and Since the voltage of the QB node QB is maintained at a voltage corresponding to the threshold voltage Vth of the second-second transistors T4-1 and T4-2, the positive bias stress can be reduced.

The present invention has the effect of providing a scan driver and a display device using the same to lower the voltage applied to the QB node and reduce the positive bias stress of the node to improve the life and reliability of the scan driver. In addition, the present invention has the effect of providing a scan driver that can self-refresh the node by the voltage applied to the QB node by the mirror transistor to automatically vary, and a display device using the same.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above may be modified in other specific forms by those skilled in the art to which the present invention pertains without changing its technical spirit or essential features. It will be appreciated that it may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is shown by the claims below, rather than the above detailed description. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

100: display panel 110: timing controller
120: data driver 130, 140: scan driver
130: level shifter 140: shift register
Tpu: Pull Up Transistor Tpd: Pull Down Transistor
T1: first transistor T2: second transistor
T3, T4: mirror transistor T4-1: 2-1 side transistor
T4-2: 2-2nd side transistor

Claims (13)

A level shifter for outputting start signals, clock signals, and reset clock signals; And
And a shift register including stages for shifting and outputting a scan signal corresponding to the start signal, the clock signals, and the reset clock signals.
Nth stage of the stages
A pull-up transistor for outputting an Nth clock signal to an output terminal of the Nth stage corresponding to the potential of the Q node;
A pull-down transistor for outputting a low potential voltage to an output terminal of the Nth stage corresponding to the potential of the QB node;
Q node charging and discharging unit for charging and discharging the Q node,
It includes a QB node charge and discharge unit for charging and discharging the QB node,
The QB node charging and discharging unit maintains the QB node at a voltage between logic high and logic low when the N-th reset clock signal of a logic low is supplied after the low potential voltage is output through the output terminal of the Nth stage. A scan driver characterized in that. delete The method of claim 1,
The QB node charge and discharge unit
A QB node discharge transistor configured to discharge the QB node corresponding to the potential of the Q node;
And at least one mirror transistor configured to charge the QB node or to maintain the QB node at a voltage between logic high and logic low in response to an Nth reset clock signal.
And the QB node is maintained at a voltage level corresponding to the threshold voltage of one of the mirror transistors. The method of claim 3,
The mirror transistor
A first side transistor having a gate electrode and a first electrode connected to an N-th reset clock signal terminal supplied with the N-th reset clock signal, and a second electrode connected to the QB node;
And a second side transistor having a gate electrode and a first electrode connected to the QB node, and a second electrode connected to the N-th reset clock signal terminal. The method of claim 3,
The mirror transistor
A first side transistor having a gate electrode and a first electrode connected to an N-th reset clock signal terminal supplied with the N-th reset clock signal, and a second electrode connected to the QB node;
A 2-1 side transistor having a gate electrode and a first electrode connected to the QB node;
And a second-side transistor connected to a second electrode of the second-side transistor and a second electrode connected to the N-th reset clock signal terminal. The method of claim 1,
The Q node charging and discharging unit
A first transistor having a gate electrode and a first electrode connected to a start signal terminal to which the start signal is supplied or an output terminal of an N-1 stage, and a second electrode connected to the Q node;
A second transistor having a gate electrode connected to the QB node, a first electrode connected to a low potential voltage terminal supplied with the low potential voltage, and a second electrode connected to the Q node;
And a Q node discharge transistor connected to an output terminal of the N + 2th stage, a first electrode connected to the low potential voltage terminal, and a second electrode connected to the Q node. Display panel;
A data driver connected to data lines of the display panel; And
A level shifter connected to the scan lines of the display panel and outputting start signals, clock signals, and reset clock signals, and shifting and outputting scan signals corresponding to the start signals, clock signals, and reset clock signals; Including a shift register consisting of stages,
Nth stage of the stages
A pull-up transistor for outputting an Nth clock signal to an output terminal of the Nth stage corresponding to the potential of the Q node;
A pull-down transistor for outputting a low potential voltage to an output terminal of the Nth stage corresponding to the potential of the QB node;
Q node charging and discharging unit for charging and discharging the Q node,
It includes a QB node charge and discharge unit for charging and discharging the QB node,
The QB node charging and discharging unit maintains the QB node at a voltage between logic high and logic low when the N-th reset clock signal of a logic low is supplied after the low potential voltage is output through the output terminal of the Nth stage. Display device characterized in that. delete The method of claim 7, wherein
The QB node charge and discharge unit
A QB node discharge transistor configured to discharge the QB node corresponding to the potential of the Q node;
And at least one mirror transistor configured to charge the QB node or to maintain the QB node at a voltage between logic high and logic low in response to an Nth reset clock signal.
And the QB node is maintained at a voltage level corresponding to a threshold voltage of one of the mirror transistors. The method of claim 9,
The mirror transistor
A first side transistor having a gate electrode and a first electrode connected to an N-th reset clock signal terminal supplied with the N-th reset clock signal, and a second electrode connected to the QB node;
And a second side transistor having a gate electrode and a first electrode connected to the QB node, and a second electrode connected to the N-th reset clock signal terminal. The method of claim 9,
The mirror transistor
A first side transistor having a gate electrode and a first electrode connected to an N-th reset clock signal terminal supplied with the N-th reset clock signal, and a second electrode connected to the QB node;
A 2-1 side transistor having a gate electrode and a first electrode connected to the QB node;
And a second-second transistor connected to a second electrode of the second-one transistor and a second electrode connected to the N-th reset clock signal terminal. The method of claim 7, wherein
The Q node charging and discharging unit
A first transistor having a gate electrode and a first electrode connected to a start signal terminal to which the start signal is supplied or an output terminal of an N-1 stage, and a second electrode connected to the Q node;
A second transistor having a gate electrode connected to the QB node, a first electrode connected to a low potential voltage terminal supplied with the low potential voltage, and a second electrode connected to the Q node;
And a Q node discharge transistor having a gate electrode connected to the output terminal of the N + 2th stage, a first electrode connected to the low potential voltage terminal, and a second electrode connected to the Q node. The method of claim 12,
Nth stage of the stages
A first capacitor having one end connected to the Q node and the other end connected to the low potential voltage terminal to hold the voltage of the Q node at a logic low voltage when the Q node is electrically floated;
And a second capacitor having one end connected to the QB node and the other end connected to the low potential voltage terminal to hold the voltage of the QB node at a logic low voltage when the QB node is electrically floated. .

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