KR102175905B1 - Scan driver and display device using thereof - Google Patents

Abstract

The scan driver according to an embodiment of the present invention includes a shift register comprising a plurality of stages for shifting and outputting a scan signal in response to clock signals, and the Nth stage of the plurality of stages drives a pull-up transistor. By following the voltage on the Q node and maintaining the voltage of the QH node having a lower potential than the voltage on the Q node, the voltage on the Q node can be stably maintained and a high voltage is prevented from being applied to the transistor. A driving unit can be provided.

Description

Scan driver and display device using the same {SCAN DRIVER AND DISPLAY DEVICE USING THEREOF}

The present invention relates to a scan driver and a display device using the same.

With the development of information technology, the market for display devices, which is a connection medium between users and information, is growing. Accordingly, the use of display devices such as an organic light emitting display (OLED), a liquid crystal display (LCD), and a plasma display panel (PDP) is increasing. Some of the above-described display devices, for example, a liquid crystal display device or an organic light emitting display device, include a display panel including a plurality of sub-pixels arranged in a matrix form and a driver driving the display panel. The driver includes a scan driver that supplies a scan signal (or a gate signal) to the display panel and a data driver that supplies a data signal to the display panel.

In the above display device, when a scan signal and a data signal are supplied to sub-pixels arranged in a matrix form, the selected sub-pixel emits light, so that an image can be displayed.

Meanwhile, the scan driver outputting the scan signal is divided into an external type mounted on an external substrate of the display panel in the form of an integrated circuit, and an embedded type formed on the display panel in a gate in panel type formed with a thin film transistor process.

The built-in scan driver basically includes a pull-up transistor and a discharge transistor for discharging the gate terminal and the source terminal of the pull-up transistor, and sends a clock signal to the output terminal as a scan signal using a bootstrap on the Q node, which is the gate terminal of the pull-up transistor. It will be output sequentially. After that, the discharge transistor is turned on to discharge the Q node and the output terminal. Meanwhile, before the discharging transistor is turned on, it is necessary to stably maintain the turn-off state to stably maintain the voltage of the Q node and the output terminal. That is, when the transistor for discharging is stably maintained in a turn-off state, the voltage can be maintained without discharging the Q node and the output terminal. However, when the threshold voltage Vth has a negative value due to a shift phenomenon of the threshold voltage Vth according to the characteristics of the transistor, there is a problem that the discharging transistor does not stably maintain the turn-off state. There is a problem in that the gate insulating layer of the transistors break down due to the high voltage and current applied, so that the voltage of the Q node and the output signal of the output terminal do not reach a required level.

An embodiment of the present invention may provide a scan driver capable of stably maintaining a q-node voltage even when a threshold voltage is shifted to a negative value, and a display device using the same.

In addition, an embodiment of the present invention may provide a scan driver capable of stably maintaining a voltage of a Q node by compensating for a leakage current of a transistor and a display device using the same.

In addition, another embodiment according to the present invention may provide a scan driver capable of solving a problem of a failure of a transistor due to a breakdown by lowering a level of a voltage supplied to a gate terminal of a transistor and a display device using the same.

The scan driver according to an embodiment of the present invention includes a shift register composed of a plurality of stages for shifting and outputting a scan signal in response to clock signals, and an Nth stage of the plurality of stages is a gate of a pull-up transistor. A terminal voltage of a Q node, a QH node following the Q node voltage, and a 2-1 transistor and a 4-1 transistor connected to the QH node, and the 2-1 transistor and the 4-1 transistor when charging the Q node The QH node voltage, which is the source terminal voltage of, is higher than the gate terminal voltage of the 2-1 transistor and the 4-1 transistor, that is, the voltage of the logic low that is the output of the N+2 stage, which is two stages after the Nth stage Thus, even if the threshold voltages of the 2-1 transistors and the 4-1 transistors shift in the negative direction, the 2-1 transistors and the 4-1 transistors may stably maintain the scan driver. Can provide. In addition, a 2-2 transistor and a 4-2 transistor may be further included, and the leakage current of the 2-2 transistor and the 4-2 transistor may be reinforced by a high-potential power supply so that a voltage lower than the Q node is It is possible to provide a scan driver capable of preventing a high voltage from being applied to a transistor by maintaining a voltage of a QH node having a.

In the embodiment of the present invention, even when the threshold voltage is shifted to a negative value, the q-node voltage can be stably maintained, the leakage current of the transistor can be compensated, and the level of the voltage supplied to the gate terminal of the transistor can be adjusted. By adjusting downward, a scan driver capable of solving a problem of a defect of a transistor due to a breakdown and a display device using the same can be provided.

1 is a schematic block diagram of a display device.
2 is a diagram illustrating an exemplary configuration of a sub-pixel shown in FIG. 1.
3 is a block diagram of a shift register according to an embodiment of the present invention.
4 is a circuit diagram of an Nth stage according to an embodiment of the present invention.
5 is a diagram showing an operation waveform of an Nth stage.
6 is a waveform diagram showing a Q node voltage and a voltage on a QB node.

Hereinafter, with reference to the drawings of the scan driver and the display device using the same according to an embodiment of the present invention will be described in detail. The following embodiments are provided as examples in order to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In addition, in the drawings, the size and thickness of the device may be exaggerated for convenience. Throughout the specification, the same reference numbers indicate the same elements.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only these embodiments make the disclosure of the present invention complete, and common knowledge in the technical field to which the present invention pertains. It is provided to completely inform the scope of the invention to those who have, and the invention is only defined by the scope of the claims. The same reference numerals refer to the same elements throughout the specification. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity of description.

The terms used in the present specification are for describing exemplary embodiments, and therefore, are not intended to limit the present invention. In this specification, the singular form also includes the plural form unless specifically stated in the phrase. As used in the specification, "comprise" and/or "comprising" refers to the presence of one or more other components, steps, actions and/or elements, and/or elements, steps, actions and/or elements mentioned. Or does not exclude additions.

1 is a schematic block diagram of a display device, and FIG. 2 is an exemplary configuration diagram of a sub-pixel illustrated in FIG. 1.

As shown in FIG. 1, the display device includes a display panel 100, a timing controller 110, a data driver 120, and a scan driver 130 and 140.

The display panel 100 includes data lines DL that may cross each other and subpixels divided and connected to the scan lines GL. The display panel 100 includes a display area 100A in which subpixels are formed and a non-display area 100B in which various signal lines or pads are formed outside the display area 100A. The display panel 100 may be implemented as a liquid crystal display (LCD), an organic light emitting display (OLED), an electrophoretic display (EPD), or the like.

As shown in FIG. 2, one sub-pixel SP is supplied in response to a scan signal supplied through a switching transistor SW and a switching transistor SW connected to the scan line GL1 and the data line DL1. A pixel circuit PC that operates in response to the data signal DATA is included. The sub-pixel SP may be implemented as a liquid crystal display panel including a liquid crystal device or an organic light emitting display panel including an organic light emitting device, depending on the configuration of the pixel circuit PC.

When the display panel 100 is composed of a liquid crystal display panel, it is a TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, FFS (Fringe Field Switching) mode, or ECB (Electrically Controlled Birefringence). Can be implemented in mode. When the display panel 100 is composed of an organic light emitting display panel, this may be implemented in a top-emission method, a bottom-emission method, or a dual-emission method.

The timing controller 110 receives timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock through an LVDS or TMDS interface receiving circuit connected to the image board. The timing controller 110 may generate timing control signals for controlling operation timings of the data driver 120 and the scan drivers 130 and 140 based on the input timing signal.

The data driver 120 includes a plurality of source drive integrated circuits (ICs). The source drive ICs receive digital video data RGB and a source timing control signal DDC from the timing controller 110. The source drive ICs convert digital video data RGB into a gamma voltage in response to a source timing control signal DDC to generate a data voltage, and transmit the data voltage through the data lines DL of the display panel 100. Supply. The source drive ICs are connected to the data lines DL of the display panel 100 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The scan drivers 130 and 140 include a level shifter 130 and a shift register 140. The scan drivers 130 and 140 are formed in a gate-in panel (GIP) method in which the level shifter 130 and the shift register 140 are separated. The level shifter 130 is formed on an external substrate connected to the display panel 100 in the form of an IC.

The level shifter 130 shifts the levels of the clock signals clk, the reset clock signals reset_clk, and the start signal vst under the control of the timing controller 110 and supplies them to the shift register 140. . The shift register 140 may be formed in the form of a thin film transistor (hereinafter, referred to as TFT) in the non-display area 100B of the display panel 100 by the GIP method. The shift register 140 may include stages for shifting and outputting a scan signal in response to clock signals clk, reset clock signals reset_clk, and start signal vst. Stages included in the shift register 140 sequentially output scan signals through output terminals.

<Shift register block diagram>

3 is a block diagram of a shift register according to an embodiment of the present invention.

As shown in FIG. 3, a plurality of stages STn-2 to STn+1 may be included in the shift register according to the embodiment of the present invention. Four-phase clock signals clk1 to clk4, high potential voltage VDD, first low potential voltage VSS1, and second low potential voltage VSS2 are provided in the plurality of stages STn-2 to STn+1. Can be supplied.

In addition, each of the plurality of stages STn-2 to STn+1 may receive an output signal of a previous stage and an output signal of a next stage.

The N-2th stage STn-2 includes the scan signal Vg[n-4] output from the N-4th stage STn-4, the first clock signal clk1, and the Nth stage STn. It operates based on the scan signal Vg[n] output from the output terminal Gout[n]. The N-2th stage STGn-2 may output the N-2th scan signal Vg[n-2] through its own output terminal Gout[n-2].

The N-1th stage STn-1 is the scan signal output from the N-3th stage, the second clock signal clk2, and the output terminal Gout[n+1] of the N+1th stage STn+1. It operates based on the scan signal (Vg[n+1]) output from ). The N-1th stage STGn-1 may output the N-1th scan signal Vg[n-1] through its output terminal Gout[n-1].

The Nth stage STn includes the scan signal Vg[n-1] output from the N-2th stage STn-1, the third clock signal clk3, and the N+2th stage STn+2. It operates based on the scan signal Vg[n+2] output from the output terminal Gout[n+2]. The Nth stage STGn may output the Nth scan signal Vg[n] through its own output terminal Gout[n].

The N+1th stage STn+1 includes the scan signal Vg[n-2] output from the N-2th stage STn-2, the fourth clock signal clk4, and the N+3th stage STn. It operates based on the scan signal Vg[n+3] output from the output terminal Gout[n+3] of +3). The N+1th stage STGn+1 may output the N+1th scan signal Vg[n+1] through its own output terminal Gout[n+1].

As described above, the plurality of stages STn-2 to STn+1 are subordinately connected so that the subsequent stages use the scan signals output from the output stages before the two stages. For example, the scan signal Vg_out[n] output from the output terminal Gout[n] of the Nth stage STn is supplied to the start signal terminal VST of the N+2th stage STn+2. In addition, the plurality of stages STn-2 to STn+1 are connected to use a scan signal output from an output terminal located two stages after themselves as a reset signal (reset signal of a Q node) as above. For example, the scan signal Vg[n] output from the output terminal Gout[n] of the Nth stage STn is supplied to the reset terminal Reset of the N-2th stage STn-2.

Meanwhile, the first and second low potential voltages VSS1 and VSS2 may be low potential voltages having different potentials or low potential voltages identical to each other.

4 is a circuit diagram of an Nth stage according to an embodiment of the present invention, and FIG. 5 is a view showing an operation waveform of the Nth stage.

Hereinafter, a circuit configuration for the plurality of stages STn-2 to STn+1 will be described in detail with reference to FIGS. 4 and 5 as an example of the N-th stage STn.

<The operation relationship of the Nth stage>

The N-th stage STn includes a capacitor C, a pull-up transistor T8, a pull-down transistor T9, an inverter unit 210; T5, T6, T7a, T7b, a Q-node charging unit T1, and a stabilizing unit 220; T2a, T2b, T3, T4a, T4b) and the QB node discharge unit T10 may be included.

First, a pull-up transistor (T8), a pull-down transistor (T9), an inverter unit 210 (T5, T6, T7a, T7b), a Q node charging unit (T1), a stabilization unit 220; T2a, T2b, T3, T4a, T4b). And the role of the QB node discharge unit T10 and a connection relationship therebetween are as follows.

The pull-up transistor T8 outputs the Nth clock signal to the output terminal Gout[n] of the Nth stage in response to the potential of the Q node Q. Hereinafter, for convenience of description, the N-th clock signal is defined as a first clock signal clk1. However, in the case of a clock signal, it should be noted that other signals (eg, a second clock signal, a third clock signal, etc.) may be selected and input according to the position of the stage. The pull-up transistor T8 has a gate electrode connected to the Q node Q, a first electrode connected to the first clock signal terminal CLK[n] supplying the first clock signal clk1, and the output of the Nth stage. The second electrode is connected to the terminal Gout[n]. The first electrode may be a drain electrode, and the second electrode may be a source electrode, but the present invention is not limited thereto and may vary according to the direction of current. In addition, the first and second electrodes of the transistor to be described below may be described in the same manner.

The pull-down transistor T9 outputs the second low potential voltage VSS2 to the output terminal Gout[n] of the Nth stage in response to the potential of the QB node QB. The pull-down transistor T9 has a gate electrode connected to the QB node QB, a second electrode connected to the low potential voltage terminal VSS supplying a low potential voltage, and the output terminal Gout[n] of the Nth stage. The first electrode is connected.

The fifth transistor T5 of the inverter unit 210 converts the high potential voltage from the high potential voltage terminal VDD to which the first electrode (drain electrode) is connected to the second electrode (source electrode) in response to the voltage on the gate electrode. The QB node may be charged by supplying it to the connected QB node, and the sixth transistor T6 corresponds to the voltage on the gate electrode connected to the QH node, and the second electrode (source) is connected to the QB node to which the first electrode (drain electrode) is connected. The QB node may be discharged by supplying the first low potential voltage on the first low potential voltage terminal VSS1 to which the electrode) is connected. In addition, in the 7-1 transistor T7a, the gate terminal and the first electrode (drain electrode) are commonly connected to the high potential supply terminal VDD, and the second electrode (source electrode) is connected to the fifth transistor T5. It can always be turned on with a diode connection. In addition, the 7-2th transistor T7b operates in response to the voltage on the gate electrode connected to the QH node, the first electrode (drain electrode) is connected to the gate terminal of the fifth transistor T5, and the second electrode (source electrode) It can be connected to this low potential supply terminal (VSS). In addition, the second electrode of the 7-1th transistor T7a and the first electrode of the 7-2th transistor Tb may be connected to each other, and may be commonly connected to the gate terminal of the fifth transistor T5.

In the inverter unit 210, the voltage of the source terminal of the 7-2th transistor T7b, that is, the voltage of the gate terminal of the fifth transistor T5, is supplied to the gate terminal of the 7-2th transistor T7b. When the voltage on the GH node is increased, it may be lowered, and conversely, when the voltage on the GH node increases, it may be increased. At this time, when the voltage on the GH node increases and the voltage of the gate terminal of the fifth transistor T5 decreases, the fifth transistor T5 is turned off, and conversely, the voltage on the GH node decreases and the fifth When the voltage of the gate terminal of the transistor T5 increases, the fifth transistor T5 may be turned on.

The Q-node charging unit T1 (first transistor) operates by the output voltage Vg[n-2] of the N-2th stage STn-2, which is the previous stage of the Nth stage STn, The gate electrode is connected to the output terminal Gout[n-2] of the N-2th stage STn-2 so that the high potential voltage on the supply terminal VDD can be supplied to the Q node to charge the Q node. The first electrode may be connected to the high potential supply terminal VDD and the second electrode may be connected to the Q node.

The tenth transistor T10, which is the QB node discharge unit, is operated by the output voltage Vg[n-2] of the N-2th stage STn-2, which is the previous stage of the Nth stage STn. The voltage on the QB node to which the electrode (drain electrode) is connected may be discharged to the first low potential supply terminal VSS1 to which the second electrode (source electrode) is connected. Meanwhile, the tenth transistor T10 and the sixth transistor T6 of the inverter unit 210 are configured to discharge QB nodes from each other. Even if one of them is not completely turned on due to deterioration, the other Can be turned on. That is, the tenth and sixth transistors T10 and T6 may operate complementary to each other to stably discharge the QB node.

The 2-1 transistor T2a and the 2-2 transistor T2b of the stabilization unit 220 are connected in series with each other, and their gate electrodes are common to the N-th stage, which is the next stage next to the N-th stage STn. It is connected to the output terminal Gout[n+2] of the +2 stage STn+2, the second electrode (source electrode) of the 2-1 transistor T2a and the second electrode of the 2-2 transistor T2b. The first electrode (drain electrode) is connected to each other and is commonly connected to the QH node, the first electrode of the 2-1 transistor T2a is connected to the Q node, and the second electrode of the 2-2 transistor T2b It may be connected to the second low potential supply terminal VSS2, and the 2-1 transistor T2a and the 2-2 transistor T2b are output terminals Gout[ of the N+2 stage STn+2]. By operating by the output voltage Vg[n+2]) of n+2]), the Q node and the QH node can be discharged. In addition, the 4-1 transistor T4a and the 4-2 transistor T4b are connected in series with each other, their gate electrodes are commonly connected to the QB node, and the second electrode (source) of the 4-1 transistor T4a Electrode) and the first electrode (drain electrode) of the 4-2 transistor T4b are connected to each other and commonly connected to the QH node, the first electrode of the 4-1 transistor T4a is connected to the Q node, A second electrode (source electrode) of the 4-2 transistor T4b may be connected to a second low potential supply terminal VSS2, and the 4-1 transistor T4a and the 4-2 transistor T4b Can discharge the Q node and QH node by operating by the voltage on the QB node. In addition, in the third transistor T3, the gate electrode is connected to the Q node, the first electrode is connected to the high potential supply terminal (VDD), the second electrode is connected to the QH node, and is operated by the voltage of the Q node. Thus, a high potential voltage can be supplied to the QH node. At this time, the voltage of the QH node may also change according to the voltage of the Q node.

Meanwhile, in the above description, the shift register is configured of an N-type transistor as an example, but the present invention is not limited thereto.

Next, the system of clock signals will be described as follows.

Looking at the system of the four-phase clock signals clk1 to clk4, the first to fourth clock signals clk1 to clk4 are sequentially formed to transition from a logic high state to a logic low state. In this case, the first to fourth clock signals clk1 to clk4 may be formed to have a non-overlapping section. However, the clock signals may be extended to a 6 to 8 phase system instead of a 4 phase system.

Meanwhile, in the case of the first and second stages in which the previous stage does not exist, a separate start signal VST can be supplied.

<Operation characteristics of the Nth stage>

Hereinafter, the operation characteristics of the Nth stage will be described.

The Q node is charged in response to the potential of the output voltage Vg[n-2] of the N-2th stage STn-2, which is the two stages preceding the Nth stage STn, which is a logic high. It may be discharged in response to the output terminal Gout[n+2] of the N+2th stage corresponding to the row. When the Q node is in a charged state, a scan signal corresponding to the logic high of the first clock signal clk1 is output, whereas when the Q node is in a discharged state, the scan signal corresponding to the logic low of the second low potential voltage VSS2 is output. A scan signal can be output.

Specifically, as the first transistor T1 is turned on, the Q node corresponds to the output voltage Vg[n-2] of the N-2th stage STn-2 corresponding to the logic high (H). Can be charged.

In addition, the third transistor T3 of the stabilization unit 220 is turned on by the voltage on the Q node, so that the high potential power of the high potential supply terminal VDD can charge the QH node. Accordingly, the potential of the QH node may be logic high when the Q node has a logic high potential, so that the potential of the QH node approximately follows the potential of the Q node at the same timing (Timming). That is, when the Q node voltage changes from the first low level LL 1 to the first high level HL 1 at the first time point t1, the QH node voltage is at the second low level LL at the first time point t1. 2) to a second high level (HL2), and the Q node voltage is changed from the first high level (HL1) to a second time (t2) after the first time (t1). 3 When the voltage changes from the high level (HL 3) to the first low level (LL 1), the QH node voltage is at the second high level (HL 2) at the second time point (t2) to the second low level (LL 2). At this time, the QH node voltage fluctuates from the second low level LL 2 to the second high level HL 2 until it fluctuates back to the second low level LL 2. That is, from time t1 to time t2, the second high level 2 may be maintained. In addition, the second high level HL2 is formed to be lower than the maximum voltage of the voltage on the Q node.

In this case, since the voltage Vgs between the gate and source terminals of the 2-1 transistor T2a and the 4-1 transistor T4a has a value less than 0, their threshold voltage Vth is shifted. Thus, even if the value is less than 0, the potential of the Q node can be stably maintained by maintaining turn-off. Also, the voltage Vgs between the gate and source terminals of the 2-2 transistors T2b and 4-2 transistors T4b may be 0, and their leakage current is supplied by the third transistor T3. A high potential power source may be supplied to the QH, thereby reinforcing the voltage of the QH node according to the reinforcement of leakage currents of the 2-2 transistors T2b and 4-2 transistors T4b.

In addition, the QB node may be discharged to a low potential voltage by turning on the sixth transistor T6 by a voltage on the QH node of logic high. In addition, since the QB node has a low potential voltage, the pull-down transistor T9 may not be turned on. In this state, since the voltage on the QH node follows the voltage of the Q node at the same timing, the voltage of the QH node is maintained until the Q node is discharged, thereby stably discharging the QB node.

Meanwhile, when the Q node is charged and the first clock signal clk1 becomes logic high by the capacitor C, the Q node is bootstrapped and the pull-up transistor T8 is completely turned on, and the output terminal of the Nth stage The first clock signal clk1 of logic high is output through (Gout[n]). After the logic high first clock signal clk1 is output, the Q node may be discharged by the stabilization unit 220.

Thereafter, in response to the potential of the output voltage Vg[n-2] of the N-2th stage STn-2, which is a previous stage of the Nth stage STn corresponding to the logic low, the first transistor T1 is Is turned off, and Q according to the turn-on operation of the second transistors T2a and Tab and the fourth transistors T4a and T4b in response to the potential of the output terminal Gout[n+2] of the N+2th stage. Nodes can be discharged. In addition, the high potential power from the fifth transistor T5 of the inverter unit 210 is supplied to the QB node according to the Q node discharge, and the pull-down transistor T9 is turned on accordingly, so that the output terminal Gout of the Nth stage STn is turned on. [n]) may be discharged to the second low potential power source VSS2.

6 is a waveform diagram showing a Q node voltage and a voltage on a QB node.

In FIG. 6, Vgs denotes a voltage on the gate electrode compared to the low potential voltage (VSS) of the transistor using the Q node as the gate electrode or the voltage on the gate electrode compared to the low potential voltage (VSS) of the transistor using the QH node as the gate electrode.

Referring to FIG. 6, the voltage on the QH node is a voltage having the same timing as the voltage on the Q node, and in the case of the Q node, it can be increased to 50V by bootstrap, but the voltage of the QH node is the maximum high potential power supply (VDD; for example, 24V). Therefore, since the QH node voltage, not the Q node voltage, is applied to the gate electrode of the sixth transistor T6 and the 7-2th transistor T7b, a voltage relatively lower than the Q node voltage is applied, and the sixth transistor T6 And the voltage Vgs between the gate and the source terminal of the 7-2th transistor T7b is a voltage difference between the first low-potential power supply VSS1; for example, -14V and the high-potential power supply VDD. A voltage smaller than the voltage difference between the node voltage and the first low-potential power supply VSS1 is applied. Therefore, it is possible to prevent a high voltage from being applied to the transistor, thereby preventing a breakdown of the gate insulating layer.

Meanwhile, when charging the Q node, the voltages at the source terminals of the 2-1 transistors T2a and 4-1 transistors T4a, that is, the voltage at the QH node, are the 2-1 transistors T2a and the 4-1 transistors T4a. ), that is, the voltage of the logic low, which is the output of the N+2th stage, which is two stages after the Nth stage STn, the 2-1th transistor T2a and the 4-1th transistor ( Even if the voltage Vgs between the gate and the source electrode of T4a is negative, and the threshold voltages of the 2-1 transistor T2a and the 4-1 transistor T4a shift in the negative direction The 2-1 transistor T2a and the 4-1 transistor T4a may be stably turned off. In this case, the level of the high potential power supply VDD may be determined in consideration of the shifting of the threshold voltages of the 2-1 transistor T2a and the 4-1 transistor T4a.

In addition, the leakage current of the 2-2 transistor T2b and the 4-2 transistor T4b can be reinforced by the high potential power supply (VDD) via the third transistor T3 and maintain the voltage of the QH node. I can.

In the detailed description of the present invention described above, it has been described with reference to preferred embodiments of the present invention, but those skilled in the art or those of ordinary skill in the relevant technical field of the present invention described in the claims to be described later It will be understood that various modifications and changes can be made to the present invention without departing from the spirit and technical scope. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

100 display panel
100A display area
100B non-display area
110 timing controller
120 data driver
130 level shifter
130, 140 scan driver
140 shift register

Claims (9)

Including; a shift register composed of a plurality of stages for shifting and outputting the scan signal in response to the clock signals,
The Nth stage of the plurality of stages,
A pull-up transistor configured to output an Nth clock signal to an output terminal in response to the voltage of the Q node;
A pull-down transistor configured to output a low potential voltage from a low potential supply terminal to the output terminal in response to the voltage of the QB node;
A third transistor driven by the voltage of the Q node to provide a high potential voltage from a high potential supply terminal to the QH node;
A 2-1 transistor having a source electrode connected to the QH node, a drain electrode connected to the Q node, and a gate electrode connected to an output terminal of a next stage of the Nth stage;
A 4-1th transistor having a source electrode connected to the QH node, a drain electrode connected to the Q node, and a gate electrode connected to the QB node;
A gate electrode is connected to an output terminal of the next stage of the Nth stage, a drain electrode is connected to the QH node, a source electrode is connected to the low potential supply terminal, and operates by the output voltage of the previous stage, so that the Q A 2-2 transistor discharging the voltage on the node and the QH node to the low potential supply terminal; And
A gate electrode is connected to the QB node, a drain electrode is connected to the QH node, a source electrode is connected to the low potential supply terminal, and operated by a voltage on the QB node, A 4-2th transistor discharging a voltage to the low potential supply terminal;
Including,
A scan driver in which a voltage between the gate electrode and the source electrode of the 2-2 transistor and the 4-2 transistor is zero. delete The method of claim 1,
A first transistor having a gate electrode connected to the output terminal of the previous stage of the Nth stage and providing the high potential voltage to the Q node; And
A tenth transistor having a gate electrode connected to the output terminal of the previous stage of the Nth stage and providing the low potential voltage to the QB node. The method of claim 3,
A sixth transistor having a gate electrode connected to the QH node and providing the low potential voltage to the QB node. The method of claim 4,
A 7-1th transistor having drain and gate electrodes connected to the high potential supply terminal;
A 7-2th transistor having a gate electrode connected to the QH node, a drain electrode connected to the source electrode of the 7-1th transistor, and a source electrode connected to the low potential supply terminal; And
A fifth transistor having a gate electrode connected to the source electrode of the 7-1th transistor, and connected between the high potential supply terminal and the QB node. The method of claim 1,
When the Q node voltage fluctuates from a first low level to a first high level, the QH node voltage fluctuates from a second low level to a second high level,
When the Q node voltage fluctuates from a third high level changed from the first high level to the first low level, the QH node voltage fluctuates from a second high level to a second low level. The method of claim 6,
The scan driver configured to maintain a voltage lower than a maximum voltage of the voltage on the Q node until the QH node voltage changes from the second low level to the first low level and changes back to the second low level. The method of claim 5,
A scan driver having a negative voltage between a gate terminal and a source terminal of the 2-1 transistor and the 4-1 transistor. A scan driver according to claim 1; And
And a display panel including a plurality of scan lines connected to the scan driver.

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