CN109493783B - GOA circuit and display panel - Google Patents
GOA circuit and display panel Download PDFInfo
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- CN109493783B CN109493783B CN201811570666.5A CN201811570666A CN109493783B CN 109493783 B CN109493783 B CN 109493783B CN 201811570666 A CN201811570666 A CN 201811570666A CN 109493783 B CN109493783 B CN 109493783B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
According to the GOA circuit and the display panel provided by the embodiment of the application, the source electrode of the eighth transistor and the source electrode of the ninth transistor are electrically connected with the second clock signal, the time that the voltage difference between the voltage of the grid electrode terminal and the voltage of the source electrode terminal is zero is compressed to half of the original time through the second clock signal, the probability that the potential of the second node is pulled down is further reduced, and the GOA circuit works normally.
Description
Technical Field
The application relates to the technical field of display, in particular to a GOA circuit and a display panel.
Background
The GOA (Gate Driver on Array, chinese) technology integrates a Gate driving circuit on an Array substrate of a display panel, so that the Gate driving integrated circuit part can be omitted to reduce the product cost from both the material cost and the manufacturing process.
The conventional GOA circuit is sensitive to transistors, so that the threshold voltage of the transistors is easy to be negatively biased, and the GOA circuit is abnormal.
Disclosure of Invention
An object of the embodiments of the present application is to provide a GOA circuit and a display panel, which can solve the technical problem that the threshold voltage of a transistor is biased negatively easily due to the sensitivity of the transistor in the conventional GOA circuit, and thus the GOA circuit is abnormal.
The embodiment of the application provides a GOA circuit, includes: the multistage GOA unit that cascades, each grade GOA unit all includes: the circuit comprises an input module, a first output module, a second output module, a pull-down module, an inverting module, a pull-down maintaining module and a bootstrap capacitor;
the input module is connected with a previous scanning signal and a previous transmission signal, is electrically connected with a first node, and is used for outputting the previous scanning signal to the first node under the control of the previous transmission signal;
the first output module is connected to a first clock signal, electrically connected to the first node, and used for outputting a current-level transmission signal under the control of the potential of the first node;
the second output module is connected to the first clock signal, electrically connected to the first node, and configured to output a current-level scan signal under the control of a potential of the first node;
the pull-down module is connected to a next-stage transmission signal, a first reference low-level signal and a second reference low-level signal, is electrically connected to the first node and the current-stage scanning signal, and is used for pulling down the potential of the first node to the potential of the second reference low-level signal and pulling down the potential of the current-stage scanning signal to the potential of the first reference low-level signal under the control of the next-stage transmission signal;
the phase inversion module is connected to the first clock signal, the second clock signal and the current-stage transmission signal, electrically connected to a second node, and configured to output the first clock signal or the second clock signal to the second node under the control of the first clock signal, the second clock signal and the current-stage transmission signal;
the pull-down maintaining module is connected to the first reference low level signal and the second reference low level signal, and is electrically connected to the first node, the second node, the current stage transmission signal and the current stage scanning signal, and configured to maintain the potential of the first node and the potential of the current stage transmission signal at the potential of the second reference low level signal and maintain the potential of the current stage scanning signal at the potential of the first reference low level signal under the control of the potential of the second node;
one end of the bootstrap capacitor is electrically connected to the first node, and the other end of the bootstrap capacitor is electrically connected to the current-stage scanning signal.
In the GOA circuit described in this application, the input module includes: a first transistor;
the gate of the first transistor is electrically connected to the previous-stage transmission signal, the source of the first transistor is electrically connected to the previous-stage scanning signal, and the drain of the first transistor is electrically connected to the first node.
In the GOA circuit described in this application, the first output module includes: a second transistor;
the gate of the second transistor is electrically connected to the first node, the source of the second transistor is electrically connected to the first clock signal, and the drain of the third transistor is electrically connected to the current-stage transmission signal.
In the GOA circuit described in this application, the second output module includes: a third transistor;
the gate of the third transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the first clock signal, and the drain of the third transistor is electrically connected to the current-stage scan signal.
In the GOA circuit described in this application, the pull-down module includes: a fourth transistor and a fifth transistor;
the grid electrode of the fourth transistor and the grid electrode of the fifth transistor are both electrically connected to the next-stage transmission signal; a source of the fourth transistor is electrically connected to the second reference low-level signal, and a source of the fifth transistor is electrically connected to the first reference low-level signal; the drain of the fourth transistor is electrically connected to the first node, and the drain of the fifth transistor is electrically connected to the present-stage scanning signal.
In the GOA circuit described in this application, the inverting module includes: a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor;
the gate and the source of the sixth transistor and the source of the seventh transistor are electrically connected to the first clock signal, the drain of the sixth transistor, the gate of the seventh transistor and the drain of the eighth transistor are electrically connected, the drain of the seventh transistor and the source of the ninth transistor are electrically connected to the second node, the gate of the eighth transistor and the gate of the ninth transistor are electrically connected to the local-level transmission signal, the source of the eighth transistor is electrically connected to the second reference low-level signal, and the source of the ninth transistor is electrically connected to the first reference low-level signal.
In the GOA circuit of the present application, the pull-down maintaining module includes: a tenth transistor, an eleventh transistor, and a twelfth transistor;
a gate of the tenth transistor, a gate of the eleventh transistor, and a gate of the twelfth transistor are electrically connected to the second node, a source of the tenth transistor and a source of the eleventh transistor are electrically connected to the second reference low level signal, a source of the twelfth transistor is electrically connected to the first reference low level signal, a drain of the tenth transistor is electrically connected to the present-stage scanning signal, a drain of the eleventh transistor is electrically connected to the first node, and a drain of the twelfth transistor is electrically connected to the present-stage scanning signal.
In the GOA circuit described herein, the polarity of the first clock signal is opposite to the polarity of the second clock signal.
In the GOA circuit described in this application, the potential of the first reference low level signal is less than the potential of the second reference low level signal.
The embodiment of the application also provides a display panel, which comprises the GOA circuit.
According to the GOA circuit and the display panel provided by the embodiment of the application, the source electrode of the eighth transistor and the source electrode of the ninth transistor are electrically connected with the second clock signal, the time that the voltage difference between the voltage of the grid electrode terminal and the voltage of the source electrode terminal is zero is compressed to half of the original time through the second clock signal, the probability that the potential of the second node is pulled down is further reduced, and the GOA circuit works normally.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a GOA circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic circuit diagram of a GOA unit in a GOA circuit according to an embodiment of the present disclosure;
fig. 3 is a timing diagram of a signal of a GOA unit in the GOA circuit according to the embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and drain of the transistors used herein are symmetrical, the source and drain may be interchanged. In the embodiment of the present application, to distinguish two poles of a transistor except for a gate, one of the two poles is referred to as a source, and the other pole is referred to as a drain. The form in the drawing provides that the middle end of the switching transistor is a grid, the signal input end is a source, and the output end is a drain. In addition, the transistors used in the embodiments of the present application may include a P-type transistor and/or an N-type transistor, where the P-type transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, and the N-type transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a GOA circuit according to an embodiment of the present disclosure. As shown in fig. 1, the GOA circuit provided in the embodiment of the present application includes multiple cascaded GOA units. Fig. 1 illustrates an n-3 th level GOA unit, an nth level GOA unit, and an n +3 th level GOA unit in cascade.
When the nth-grade GOA unit works, the scanning signal output by the nth-grade GOA unit is high potential and is used for turning on a transistor switch of each pixel in a row in a display panel and charging a pixel electrode in each pixel through a data signal; the nth level signal is used for controlling the work of the (n +3) th level GOA unit; when the n +3 th-level GOA unit works, the scanning signal output by the n +3 th-level GOA unit is at a high potential, and the scanning signal output by the n-level GOA unit is at a low potential.
Further, referring to fig. 2, fig. 2 is a circuit schematic diagram of a GOA unit in a GOA circuit according to an embodiment of the present disclosure. As shown in fig. 2, the GOA circuit includes: the input module 101, the first output module 102, the second output module 103, the pull-down module 104, the inverting module 105, the pull-down maintaining module 106, and the bootstrap capacitor Cb.
The input module 101 is connected to the previous-stage scanning signal G (n-3) and the previous-stage transmission signal ST (n-3), and is electrically connected to the first node q (n) for outputting the previous-stage scanning signal G (n-3) to the first node q (n) under the control of the previous-stage transmission signal ST (n-3).
The first output module 102 is coupled to the first clock signal CK1, and is electrically connected to the first node q (n) for outputting the current-stage transmission signal st (n) under the control of the potential of the first node q (n).
The second output module 103 is connected to the first clock signal CK1, and is electrically connected to the first node q (n) for outputting the current-stage scanning signal g (n) under the control of the potential of the first node q (n).
The pull-down module 104 is connected to the next-stage transmission signal ST (n +3), the first reference low-level signal VSSG and the second reference low-level signal VSSQ, and is electrically connected to the first node q (n) and the current-stage scanning signal g (n), and is configured to pull down the potential of the first node q (n) to the potential of the second reference low-level signal VSSQ and pull down the potential of the current-stage scanning signal g (n) to the potential of the first reference low-level signal VSSG under the control of the next-stage transmission signal ST (n + 3).
The inverting module 105 is coupled to the first clock signal CK1, the second clock signal CK2, and the current stage transmission signal st (n), and is electrically connected to the second node k (n) for outputting the first clock signal CK1 or the second clock signal CK2 to the second node k (n) under the control of the first clock signal CK1, the second clock signal CK2, and the current stage transmission signal st (n).
The pull-down maintaining module 106 is electrically connected to the first node q (n), the second node k (n), the current-stage transmission signal st (n), and the current-stage scanning signal g (n), and is configured to maintain the potential of the first node q (n) and the potential of the current-stage transmission signal st (n) at the potential of the second reference low-level signal VSSQ and maintain the potential of the current-stage scanning signal g (n) at the potential of the first reference low-level signal VSSG under the potential control of the second node k (n).
One end of the bootstrap capacitor Cb is electrically connected to the first node q (n), and the other end of the bootstrap capacitor Cb is electrically connected to the current-stage scan signal g (n).
It should be noted that, since the eighth transistor T8 and the ninth transistor T9 in the GOA circuit of the embodiment of the present application are turned on when the level of the current-stage transmission signal st (n) is high, and are turned off for a long time. That is, the eighth transistor T8 and the ninth transistor T9 have a voltage difference between the voltage of the gate terminal and the voltage of the source terminal of zero for a long period of time. When the high temperature or the threshold voltage drifts negatively, the leakage current is increased, which causes the potential of the second node k (n) to be easily pulled down, and further causes the potential of the first node q (n) and the potential of the current-stage scanning signal g (n) to be pulled down and fail.
Based on this, the difference between the GOA circuit provided by the embodiments of the present application and the existing GOA circuit is: in the GOA circuit of the embodiment of the present application, the source of the eighth transistor T8 and the source of the ninth transistor T9 are both electrically connected to the second clock signal CK2, and the time when the voltage difference between the voltage at the gate terminal and the voltage at the source terminal is zero is compressed to half of the original time by the second clock signal CK2, so that the probability that the potential of the second node k (n) is pulled down is reduced. It is understood that the second clock signal CK2 is an ac signal.
Continuing to refer to fig. 2, in some embodiments, the input module 101 includes: a first transistor T1; the gate of the first transistor T1 is electrically connected to the previous-stage transmission signal ST (n-3), the source of the first transistor T1 is electrically connected to the previous-stage scanning signal G (n-3), and the drain of the first transistor T1 is electrically connected to the first node q (n).
Continuing to refer to fig. 2, in some embodiments, the first output module 102 includes: a second transistor T2; the gate of the second transistor T2 is electrically connected to the first node q (n), the source of the second transistor T2 is electrically connected to the first clock signal CK1, and the drain of the third transistor T3 is electrically connected to the current-stage transmission signal st (n).
Continuing to refer to fig. 2, in some embodiments, the second output module 103 includes: a third transistor T3; the gate of the third transistor T3 is electrically connected to the first node q (n), the source of the third transistor T3 is electrically connected to the first clock signal CK1, and the drain of the third transistor T3 is electrically connected to the current-stage scan signal g (n).
Continuing to refer to fig. 2, in some embodiments, the pull-down module 104 includes: a fourth transistor T4 and a fifth transistor T5; the gate of the fourth transistor T4 and the gate of the fifth transistor T5 are both electrically connected to the next-stage transmission signal ST (n + 3); a source of the fourth transistor T4 is electrically connected to the second reference low level signal VSSQ, and a source of the fifth transistor T5 is electrically connected to the first reference low level signal VSSG; the drain of the fourth transistor T4 is electrically connected to the first node q (n), and the drain of the fifth transistor T5 is electrically connected to the present-stage scan signal g (n).
Continuing with fig. 2, in some embodiments, the inversion module 105 includes: a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9; the gate and the source of the sixth transistor T6 and the source of the seventh transistor T7 are electrically connected to the first clock signal CK1, the drain of the sixth transistor T6, the gate of the seventh transistor T7 and the drain of the eighth transistor T8 are electrically connected, the drain of the seventh transistor T7 and the source of the ninth transistor T9 are electrically connected to the second node k (n), the gate of the eighth transistor T8 and the gate of the ninth transistor T9 are electrically connected to the current-stage signal st (n), the source of the eighth transistor T8 is electrically connected to the second reference low-level signal VSSQ, and the source of the ninth transistor T9 is electrically connected to the first reference low-level signal VSSG.
Continuing to refer to fig. 2, in some embodiments, the pull-down maintaining module 106 includes: a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12; a gate of the tenth transistor T10, a gate of the eleventh transistor T11, and a gate of the twelfth transistor T12 are electrically connected to the second node k (n), a source of the tenth transistor T10 and a source of the eleventh transistor T11 are electrically connected to the second reference low level signal VSSQ, a source of the twelfth transistor T12 is electrically connected to the first reference low level signal VSSG, a drain of the tenth transistor T10 is electrically connected to the present-stage transmission signal st (n), a drain of the eleventh transistor T11 is electrically connected to the first node q (n), and a drain of the twelfth transistor T12 is electrically connected to the present-stage scanning signal g (n).
Specifically, please refer to fig. 2 and fig. 3, and fig. 3 is a signal timing diagram of a GOA circuit in the GOA circuit according to the embodiment of the present disclosure. Wherein, the period of the first clock signal CK1 is the same as that of the second high frequency clock signal, and the polarity of the first high frequency clock signal is opposite to that of the second high frequency clock signal. The potential of the first reference low level signal VSSG is less than the potential of the second reference low level signal VSSQ.
At the first time period T1, the previous stage signal ST (n-3) is at a high level, the first transistor T1 is turned on, since the previous stage scan signal G (n-3) inputted to the source of the first transistor T1 is at a high level, the potential of the first node q (n) is raised, and the second transistor T2 and the third transistor T3 are turned on; at this time, since the first clock signal CK1 is at a low voltage level, the stage pass signal st (n) and the stage scan signal g (n) are both at a low voltage level.
In the second time period T2, the previous stage transmission signal ST (n-3) is at a low level, the first transistor T1 is turned off, the potential of the first node q (n) continues to be maintained at a high level, and the second transistor T2 and the third transistor T3 are still turned on. At this time, the first clock signal CK1 is high, so the stage pass signal ST (n) and the stage scan signal G (n) are both high. At this stage, the scanning signal g (n) of the current stage is at a high level, so that the scanning line corresponding to the GOA circuit of the current stage is charged, a row of pixels corresponding to the scanning line of the current stage is turned on, and the row of pixels is turned on.
Meanwhile, in this stage, since the present-stage scan signal g (n) is at a high potential, the potential of the first node q (n) is further raised under the action of the bootstrap capacitor Cb, so as to ensure that the second transistor T2 and the third transistor T3 are turned on, and the present-stage scan signal g (n) and the present-stage scan signal st (n) are both high-potential signals.
In the third time period T3, since the next stage pass signal ST (n +3) is a high level signal, the fourth transistor T4 and the fifth transistor T5 are turned on, the first node q (n) is directly communicated with the second reference low level signal VSSQ, and the present stage scan signal g (n) is communicated with the first reference low level signal VSSG. That is, at this time, the potential of the current-stage scan signal g (n) is pulled down to the potential of the first reference low-level signal VSSG, and the potential of the first node q (n) is pulled down to the potential of the second reference low-level signal VSSQ.
During the fourth time period T4, the first clock signal CK1 is at a high level, the sixth transistor T6 and the seventh transistor T7 are turned on, the high level of the first clock signal CK1 is outputted to the second node k (n), so that the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 are turned on, the level of the first node q (n) and the level of the present stage transmission signal st (n) are maintained at the level of the second reference low level signal VSSQ, and the level of the present stage scanning signal g (n) is maintained at the level of the first reference low level signal VSSG.
In the embodiment of the present application, by electrically connecting the source of the eighth transistor T8 and the source of the ninth transistor T9 to the second clock signal CK2, the time when the voltage difference between the gate terminal voltage and the source terminal voltage is zero is compressed to half of the original time by the second clock signal CK2, so that the probability that the potential of the second node k (n) is pulled down is reduced.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. As shown in fig. 4, the display panel includes a display area 100 and a GOA circuit 200 integrally disposed on an edge of the display area 100; the structure and principle of the GOA circuit 200 are similar to those of the above-mentioned GOA circuit, and are not described herein again.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (7)
1. A GOA circuit, comprising: the multistage GOA unit that cascades, each grade GOA unit all includes: the circuit comprises an input module, a first output module, a second output module, a pull-down module, an inverting module, a pull-down maintaining module and a bootstrap capacitor;
the input module is connected with a previous scanning signal and a previous transmission signal, is electrically connected with a first node, and is used for outputting the previous scanning signal to the first node under the control of the previous transmission signal;
the first output module is connected to a first clock signal, electrically connected to the first node, and used for outputting a current-level transmission signal under the control of the potential of the first node;
the second output module is connected to the first clock signal, electrically connected to the first node, and configured to output a current-level scan signal under the control of a potential of the first node;
the pull-down module is connected to a next-stage transmission signal, a first reference low-level signal and a second reference low-level signal, is electrically connected to the first node and the current-stage scanning signal, and is used for pulling down the potential of the first node to the potential of the second reference low-level signal and pulling down the potential of the current-stage scanning signal to the potential of the first reference low-level signal under the control of the next-stage transmission signal;
the phase inversion module is connected to the first clock signal, the second clock signal and the current-stage transmission signal, electrically connected to a second node, and configured to output the first clock signal or the second clock signal to the second node under the control of the first clock signal, the second clock signal and the current-stage transmission signal;
the pull-down maintaining module is connected to the first reference low level signal and the second reference low level signal, and is electrically connected to the first node, the second node, the current stage transmission signal and the current stage scanning signal, and configured to maintain the potential of the first node and the potential of the current stage transmission signal at the potential of the second reference low level signal and maintain the potential of the current stage scanning signal at the potential of the first reference low level signal under the control of the potential of the second node;
one end of the bootstrap capacitor is electrically connected to the first node, and the other end of the bootstrap capacitor is electrically connected to the current-stage scanning signal;
the polarity of the first clock signal is opposite to the polarity of the second clock signal; the inverting module includes: a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor;
a gate and a source of the sixth transistor and a source of the seventh transistor are electrically connected to the first clock signal, a drain of the sixth transistor, a gate of the seventh transistor and a drain of the eighth transistor are electrically connected, a drain of the seventh transistor and a source of the ninth transistor are electrically connected to the second node, a gate of the eighth transistor and a gate of the ninth transistor are electrically connected to the local-stage transmission signal, a source of the eighth transistor is electrically connected to the second clock signal, and a source of the ninth transistor is electrically connected to the second clock signal; the time during which the voltage difference between the voltage of the gate terminal and the voltage of the source terminal is zero is compressed to half of the original time by the second clock signal.
2. The GOA circuit of claim 1, wherein the input module comprises: a first transistor;
the gate of the first transistor is electrically connected to the previous-stage transmission signal, the source of the first transistor is electrically connected to the previous-stage scanning signal, and the drain of the first transistor is electrically connected to the first node.
3. The GOA circuit of claim 1, wherein the first output module comprises: a second transistor;
the gate of the second transistor is electrically connected to the first node, the source of the second transistor is electrically connected to the first clock signal, and the drain of the third transistor is electrically connected to the current-stage scan signal.
4. The GOA circuit of claim 1, wherein the second output module comprises: a third transistor;
the gate of the third transistor is electrically connected to the first node, the source of the third transistor is electrically connected to the first clock signal, and the drain of the third transistor is electrically connected to the current-stage scan signal.
5. The GOA circuit of claim 1, wherein the pull-down module comprises: a fourth transistor and a fifth transistor;
the grid electrode of the fourth transistor and the grid electrode of the fifth transistor are both electrically connected to the next-stage transmission signal; a source of the fourth transistor is electrically connected to the second reference low-level signal, and a source of the fifth transistor is electrically connected to the first reference low-level signal; the drain of the fourth transistor is electrically connected to the first node, and the drain of the fifth transistor is electrically connected to the present-stage scanning signal.
6. The GOA circuit of claim 1, wherein the pull-down maintenance module comprises: a tenth transistor, an eleventh transistor, and a twelfth transistor;
a gate of the tenth transistor, a gate of the eleventh transistor, and a gate of the twelfth transistor are electrically connected to the second node, a source of the tenth transistor and a source of the eleventh transistor are electrically connected to the second reference low level signal, a source of the twelfth transistor is electrically connected to the first reference low level signal, a drain of the tenth transistor is electrically connected to the present-stage scanning signal, a drain of the eleventh transistor is electrically connected to the first node, and a drain of the twelfth transistor is electrically connected to the present-stage scanning signal.
7. A display panel comprising the GOA circuit of any one of claims 1-6.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811570666.5A CN109493783B (en) | 2018-12-21 | 2018-12-21 | GOA circuit and display panel |
| PCT/CN2019/078417 WO2020124822A1 (en) | 2018-12-21 | 2019-03-18 | Goa circuit and display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811570666.5A CN109493783B (en) | 2018-12-21 | 2018-12-21 | GOA circuit and display panel |
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| CN109493783A CN109493783A (en) | 2019-03-19 |
| CN109493783B true CN109493783B (en) | 2020-10-13 |
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| CN110007628B (en) * | 2019-04-10 | 2022-02-01 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| CN110570799B (en) * | 2019-08-13 | 2022-10-04 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| CN110767175A (en) * | 2019-10-08 | 2020-02-07 | 武汉华星光电半导体显示技术有限公司 | Drive circuit and display panel |
| CN112071250B (en) * | 2020-09-04 | 2021-11-02 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit |
| CN112967652B (en) * | 2021-03-08 | 2023-05-02 | 武汉天马微电子有限公司 | Scanning signal circuit, display panel, display device and driving method |
| CN112951142B (en) * | 2021-03-29 | 2022-02-22 | 深圳市华星光电半导体显示技术有限公司 | Gate drive circuit, display panel and display device |
| CN113593460A (en) * | 2021-07-19 | 2021-11-02 | Tcl华星光电技术有限公司 | GOA circuit |
| CN115050338B (en) * | 2022-06-15 | 2023-07-25 | Tcl华星光电技术有限公司 | Gate driving circuit, display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101527109B (en) * | 2008-03-03 | 2012-11-21 | 奇美电子股份有限公司 | Flat panel display and drive method thereof |
| KR101340197B1 (en) * | 2011-09-23 | 2013-12-10 | 하이디스 테크놀로지 주식회사 | Shift register and Gate Driving Circuit Using the Same |
| TWI425473B (en) * | 2011-12-29 | 2014-02-01 | Au Optronics Corp | Gate driving circuit |
| CN104505036B (en) * | 2014-12-19 | 2017-04-12 | 深圳市华星光电技术有限公司 | Gate driver circuit |
| KR102175905B1 (en) * | 2014-12-22 | 2020-11-09 | 엘지디스플레이 주식회사 | Scan driver and display device using thereof |
| KR102413874B1 (en) * | 2015-07-02 | 2022-06-29 | 삼성디스플레이 주식회사 | Emissioin driver and display device including the same |
| CN106205528B (en) * | 2016-07-19 | 2019-04-16 | 深圳市华星光电技术有限公司 | A kind of GOA circuit and liquid crystal display panel |
| KR102649203B1 (en) * | 2016-12-15 | 2024-03-20 | 엘지디스플레이 주식회사 | Shift register with inverter and display device using the same |
| TWI618042B (en) * | 2017-05-19 | 2018-03-11 | 友達光電股份有限公司 | Driving circuit and display panel |
| TWI623926B (en) * | 2017-08-15 | 2018-05-11 | 友達光電股份有限公司 | Gate driving circuit |
| CN107909971B (en) * | 2017-11-03 | 2020-06-30 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit |
| CN108320717B (en) * | 2018-02-06 | 2020-12-22 | 深圳市华星光电技术有限公司 | GOA driving circuit and liquid crystal display panel prepared by same |
| CN108962178B (en) * | 2018-09-03 | 2020-02-18 | 深圳市华星光电技术有限公司 | GOA circuit and liquid crystal panel |
-
2018
- 2018-12-21 CN CN201811570666.5A patent/CN109493783B/en active Active
-
2019
- 2019-03-18 WO PCT/CN2019/078417 patent/WO2020124822A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| CN109493783A (en) | 2019-03-19 |
| WO2020124822A1 (en) | 2020-06-25 |
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