TWI623926B - Gate driving circuit - Google Patents

Abstract

A gate driving circuit includes an n + k-th stage shift temporary storage circuit and an n-th stage shift temporary storage circuit. The n + k-th stage shift temporary storage circuit includes an n + k-th stage voltage stabilizing node. The n-th stage temporary storage circuit includes an n-th output circuit, an n-th voltage stabilizing circuit, an n-th control circuit, and a working circuit. The n-th output circuit is used to output an n-th output voltage. The n-th voltage stabilizing circuit is used to provide a second regulated voltage to the n-th operating node. The n-th stage control circuit is used to provide a second regulated voltage to the n-th stage main voltage regulation node. The working circuit is used to provide the first operation voltage to the n-th stage operation node and the n + k-th stage shift storage circuit at the same time. The voltage levels of the n-th primary voltage stabilizing node and the n + k-th secondary voltage stabilizing node are substantially the same.

Description

Gate drive circuit

The embodiments described in this disclosure are related to a gate driving circuit.

In the existing display technology, gate driver on array (GOA) technology has been used to achieve the narrow frame effect of the display panel. However, in the prior art, the charging capabilities of two adjacent stages are inconsistent, which makes it easy to generate bright and dark lines between the two stages in the gate driving circuit.

An embodiment of the present disclosure relates to a gate driving circuit. The gate driving circuit includes an n + k-th stage shift register circuit and an n-th stage shift register circuit. The n + k-th stage shift temporary storage circuit includes an n + k-th stage voltage stabilizing node. The n-th stage temporary storage circuit includes an n-th output circuit, an n-th voltage stabilizing circuit, an n-th control circuit, and a working circuit. The n-th output circuit is configured to output an n-th output voltage according to a first operating voltage of an n-th operating node. The n-th voltage stabilizing circuit is configured to provide a second voltage stabilizing voltage to the n-th level operating node according to a first stabilizing voltage of an n-th level main stabilizing node. The n-th stage control circuit is used to operate the first node according to the n-th stage. The operating voltage provides a second regulated voltage to the n-th stage main regulated node. The working circuit is used to provide the first operation voltage to the n-th stage operation node and the n + k-th stage shift temporary storage circuit at the same time. The n + k-stage shift temporary storage circuit outputs an n + k-stage output voltage according to the first operating voltage of the n + k-stage operating node. The voltage levels of the n-th primary voltage stabilizing node and the n + k-th secondary voltage stabilizing node are substantially the same.

An embodiment of the present disclosure relates to a gate driving circuit. The gate driving circuit includes a first shift register circuit, a second shift register circuit, and a working circuit. The first shift temporary storage circuit includes a first output circuit, a first voltage stabilization circuit, and a first control circuit. The first output circuit is configured to output a first output voltage according to a first operating voltage of a first operating node. The first voltage stabilization circuit is configured to provide a second voltage stabilization voltage to the first operation node according to a first voltage stabilization voltage of a first main voltage stabilization node. The first control circuit is configured to provide a second regulated voltage to the first main regulated node according to the first operating voltage of the first operating node. The second shift register circuit includes a second output circuit, a second voltage stabilization circuit, and a second control circuit. The second output circuit is configured to output a second output voltage according to a first operating voltage of a second operating node. The second voltage stabilizing circuit is configured to provide a second voltage stabilizing voltage to the second operation node according to the second voltage stabilizing voltage of a second main voltage stabilizing node. The second control circuit is configured to provide a second regulated voltage to the first main regulated node according to the first operating voltage of the first operating node. The working circuit is used to provide the first operating voltage to the first operating node and the second operating node at the same time.

In summary, the working circuit simultaneously provides the first operating voltage to the first operating node (for example, the n-th operating node) and the second operating node (for example, (Eg: n + kth level operation node). In this way, the voltage difference between the first output voltage (eg, the n-th stage output voltage) and the second output voltage (eg, the n + k-th stage output voltage) can be reduced, thereby reducing the problem of bright and dark lines between the two stages.

100‧‧‧Gate driving circuit

120 [1] ~ 120 [16], 120 [n], 120 [n + k], 120 [i] ‧‧‧ shift temporary storage circuit

HC (1) ~ HC (16), HC (i), HC (n), HC (n + k), HC (17) ‧‧‧ clock signal

LC1, LC2‧‧‧Control signal

G (1) ~ G (16), G (i), G (n), G (n + k), G (n + k + 3), G (n + k + 4), G (13), G (14) ‧‧‧ output voltage

ST, ST (n), ST (n-2), ST (n + k), ST (n + k + 3), ST (n + k + 4), ST (11), ST (12), ST (16), ST (17) ‧‧‧Trigger signal

220‧‧‧output circuit

240‧‧‧Regulator

260‧‧‧Control circuit

280‧‧‧Working circuit

T12, T21, T41, T31, T43, T33, T35, T42, T32, T34, T55, T56, T52, T54, T51, T53, T11, T13, T44‧‧‧ switches

C1‧‧‧capacitor

P (n), P (n + k), P (13), P (14) ‧‧‧Regulatory nodes

Q (n), Q (n + k), Q (13), Q (14) ‧‧‧ operation nodes

VGH, VSSQ, VSSG, VH, VL, V1, V2‧‧‧ voltage

T1 ~ T7‧‧‧Time

In order to make the above and other objects, features, advantages, and embodiments of the present disclosure more comprehensible, the description of the drawings is as follows: FIG. 1 is a gate driving circuit according to some embodiments of the present disclosure. FIG. 2A is a circuit diagram of a stage shift register circuit in the gate driving circuit of FIG. 1 according to some embodiments of the present disclosure; and FIG. 2B is a first diagram of the first-stage shift register circuit according to some embodiments of the present disclosure. 1 is a circuit diagram of another stage of the temporary storage circuit in the gate driving circuit; and FIG. 3 is a timing diagram of some signals in the gate driving circuit of FIG. 1 according to some embodiments of the present disclosure.

The following is a detailed description with examples and the accompanying drawings, but the examples provided are not intended to limit the scope covered by this disclosure, and the description of the structure operation is not intended to limit the order of its execution, and any recombination of components The structure of the device and the device with the same effect are all covered by the present disclosure. In addition, the drawings are for illustrative purposes only, and are not drawn to the original dimensions. In order to facilitate understanding, the same elements or similar elements in the following description will be described with the same symbols.

The terms used throughout the specification and the scope of patent applications, unless otherwise specified, usually have the ordinary meaning of each term used in this field, in the content disclosed here, and in special content.

Please refer to Figure 1. FIG. 1 is a schematic diagram of a gate driving circuit 100 according to an embodiment of the present disclosure. In some embodiments, the gate driving circuit 100 includes a complex-stage shift register circuit 120 [1] to 120 [i], where i is a positive integer. Taking the first stage shift register circuit 120 [1] as an example, the first stage shift register circuit 120 [1] receives the first stage clock signal HC (1), and according to the first stage clock signal HC (1) 1) Output the first stage output voltage G (1). The other stage shift temporary storage circuits have similar architectures, and will not be repeated here.

Please refer to Figure 2A and Figure 2B together. FIG. 2A is a circuit diagram of the n-th stage shift register circuit 120 [n] in the gate driving circuit 100 of FIG. 1 according to some embodiments of the present disclosure. FIG. 2B is a circuit diagram of the n + k-th stage shift register circuit 120 [n + k] in the gate driving circuit 100 of FIG. 1 according to some embodiments of the present disclosure. In some embodiments, both n and k are positive integers. In some embodiments, k is equal to 1, but the disclosure is not limited thereto. In these embodiments where k is equal to 1, the n-th stage shift register circuit 120 [n] in FIG. 2A and the n + k-stage shift register circuit 120 [n + k] in FIG. 2B are adjacent Two-stage shift register circuit.

Taking the example in FIG. 2A, the shift temporary storage circuit 120 [n] includes an n-th stage output circuit 220, an n-th stage voltage stabilization circuit 240, an n-th stage control circuit 260, and an operating circuit 280. In some other embodiments, the working circuit 280 is configured outside the n-th stage shift register circuit 120 [n].

In some embodiments, the n-th output circuit 220 is used for The first operating voltage VGH transmitted to the n-th stage operation node Q (n) outputs the n-th stage output voltage G (n). In some embodiments, the n-th voltage stabilization circuit 240 is configured to provide a first voltage Two regulated voltages VSSQ to the n-th stage operation node Q (n). In some embodiments, the n-th stage control circuit 260 is configured to provide a second regulated voltage VSSQ to the n-th stage main voltage regulation node P (according to the first operation voltage VGH transmitted to the n-th stage operation node Q (n). n).

Specifically, the n-th stage output circuit 220 includes a switch T21 and a switch T12. The first terminal of switch T21 is used to receive the n-th stage clock signal HC (n), the second terminal of switch T21 is used to output the n-th stage output voltage G (n), and the control terminal of switch T21 is electrically connected to the n-th stage Operate node Q (n). The first terminal of the switch T12 is used to receive the n-th clock signal HC (n), the second terminal of the switch T12 is used to output the n-th trigger signal ST (n), and the control terminal of the switch T12 is electrically connected to the n-stage Operate node Q (n).

In operation, the switches T21 and T12 are turned on or off according to the voltage level of the n-th stage operation node Q (n). For example, when the operating circuit 280 transmits the first operation voltage VGH to the n-th stage operation node Q (n), the switch T21 and the switch T12 are turned on. When the switch T21 is turned on, the switch T21 transmits the n-th stage clock signal HC (n) as the n-th stage output voltage G (n). When the switch T12 is turned on, the switch T12 transmits the n-th clock signal HC (n) as the n-th trigger signal ST (n).

The n-th voltage stabilizing circuit 240 includes a switch T42, a switch T32, a switch T34, a switch T43, and a switch T33 to switch T35. The control terminals of the switch T42, the switch T32, and the switch T34 are electrically connected to the n-th stage main voltage stabilizing node P (n). The control terminals of the switch T43, the switch T33, and the switch T35 are electrically connected to the nth level voltage stabilizing section. Point P (n + k). The first ends of the switches T42 and T43 are electrically connected to the n-th stage operation node Q (n), and the second ends of the switches T42 and T43 are used to receive the second regulated voltage VSSQ. The first ends of the switches T32 and T33 are electrically connected to the capacitor C1 and are used to receive the n-th stage output voltage G (n). The second ends of the switches T32 and T33 are used to receive the third stabilized voltage VSSG. The first ends of the switches T34 and T35 are used to receive an n-th level trigger signal ST (n), and the second ends of the switches T34 and T35 are used to receive a second regulated voltage VSSQ.

In operation, the switches T42, T32, and T34 are turned on or off according to the voltage level of the n-th stage main voltage regulation node P (n). For example, when the n-th stage control circuit 260 transmits the control signal LC1 having a high voltage level to the n-th stage main voltage stabilization node P (n), the switches T42, T32, and T34 are turned on. The switch T43 and the switch T33 are turned on or off with the switch T35 according to the voltage level of the n-th voltage regulation node P (n + k). For example, when the control circuit 260 in FIG. 2B transmits the control signal LC2 with a high voltage level to the n + k-th stage main voltage stabilization node P (n + k), the switches T43, T33, and The switch T35 is turned on. When the switch T42 or the switch T43 is turned on, the second regulated voltage VSSQ is provided to the n-th stage operation node Q (n) through the switch T42 or the switch T43. Equivalently, the switch T42 or the switch T43 pulls down the voltage level of the n-th operating node Q (n) to the second regulated voltage VSSQ. When the switch T32 or the switch T33 is turned on, the switch T32 or the switch T33 pulls down the voltage level of the n-th stage output voltage G (n) to the third regulated voltage VSSG. When the switch T34 or the switch T35 is turned on, the switch T34 or the switch T35 pulls down the voltage level of the n-th trigger signal ST (n) to the second regulated voltage VSSQ. In some embodiments, the third regulated voltage VSSG is substantially the same as the second regulated voltage VSSQ.

The n-th stage control circuit 260 includes a switch T51, a switch T53, a switch T55, a switch T56, a switch T52, and a switch T54. The first end and the control end of the switch T51 are used to receive the control signal LC1, and the second end of the switch T51 is electrically connected to the control end of the switch T53. The switch T51 forms a diode-connected transistor. The first terminal of the switch T53 is used to receive the control signal LC1, and the second terminal of the switch T53 is electrically connected to the n-th stage main voltage stabilization node P (n). The control terminals of the switches T55 and T56 are electrically connected to the n + k-th operating node Q (n + k). The control terminals of the switches T52 and T54 are electrically connected to the n-th stage operation node Q (n). A first terminal of the switch T55 and the switch T52 is electrically connected to a control terminal of the switch T53, and a second terminal of the switch T55 and the switch T52 is used to receive a second regulated voltage VSSQ. The first ends of the switches T56 and T54 are electrically connected to the n-th stage main voltage stabilizing node P (n), and the second ends of the switches T56 and T54 are used to receive a second regulated voltage VSSQ.

In operation, the switch T51 is turned on or off according to the control signal LC1. When the switch T51 is turned on according to the control signal LC1 having a high voltage level, the switch T51 transmits the control signal LC1 to the control terminal of the switch T53. The switch T53 is turned on according to a control signal LC1 having a high voltage level. When the switch T53 is turned on, the switch T53 transmits the control signal LC1 with a high voltage level to the n-th stage main voltage stabilization node P (n). The switches T52 and T54 are turned on or off according to the voltage level of the n-th stage operation node Q (n). For example, when the operating circuit 280 transmits the first operation voltage VGH to the n-th stage operation node Q (n), the switch T52 or the switch T54 is turned on. The switches T55 and T56 are turned on or off according to the voltage level of the n + k-th operating node Q (n + k). When the switch T52 or the switch T55 is turned on, the switch T52 or the switch T55 pulls down the voltage level of the control terminal of the switch T53 to the second regulated voltage VSSQ. When the switch T54 or the switch T56 is turned on, the second regulated voltage VSSQ is provided to the n-th stage regulated voltage node P (n) through the switch T54 or the switch T56. Equivalently, the switch T54 or the switch T56 pulls down the voltage level of the n-th main regulator node P (n) to the second regulated voltage VSSQ.

In some embodiments, the working circuit 280 simultaneously provides the first operation voltage VGH to the n-th stage operation according to the (n-2) th stage trigger signal ST (n-2) from the (n-2) th shift register circuit. The node Q (n) and the n + k-th stage operate the node Q (n + k). Specifically, the working circuit 280 includes a first switch T11 and a second switch T13. The first terminals of the first switch T11 and the second switch T13 are used to receive a first operating voltage VGH. In some embodiments, the voltage level of the first operating voltage VGH is higher than the voltage level of the second regulated voltage VSSQ or the third regulated voltage VSSG. The control terminals of the first switch T11 and the second switch T13 are used to receive the (n-2) th level trigger signal ST (n-2). The second terminal of the first switch T11 is electrically connected to the n-th stage operation node Q (n). The second terminal of the second switch T13 is electrically connected to the n + k-th operating node Q (n + k) (shown in FIG. 2B).

In operation, the first switch T11 and the second switch T13 are turned on or off according to the (n-2) th level trigger signal ST (n-2). When the first switch T11 is turned on, the first switch T11 transmits the first operation voltage VGH to the n-th stage operation node Q (n). When the second switch T13 is turned on, the second switch T13 transmits the first operation voltage VGH to the (n + k) -th stage operation node Q (n + k). Since the control terminal and the first terminal of the first switch T11 and the second switch T13 receive the same signal, the n-th operating node Q (n) and the (n + k) -level operating node Q (n + k) The voltage levels are essentially the same. The n-th stage shift temporary storage circuit 120 [n] outputs the n-th stage output voltage according to the first operation voltage VGH transmitted to the n-th stage operation node Q (n). G (n). The n + k-stage shift temporary storage circuit 120 [n + k] outputs the n + k-stage output voltage G (n +) according to the first operation voltage VGH transmitted to the n + k-stage operation node Q (n + k). k).

As described above, since the voltage levels of the n-th operation node Q (n) and the (n + k) -th operation node Q (n + k) are substantially the same, the n-th shift temporary storage circuit 120 [n] The charging capacity of the n + k-th stage shift temporary storage circuit 120 [n + k] tends to be the same or similar. In this way, the voltage difference between the n-th stage output voltage G (n) and the n + k-th stage output voltage G (n + k) is reduced, thereby reducing the problem of bright and dark lines between the two stages.

In some embodiments, the n-th stage temporary storage circuit 120 [n] further includes a switch T44, a switch T41, and a switch T31. The first terminal of the switch T44 is electrically connected to the n-th stage operation node Q (n), the control terminal of the switch T44 is used to receive the trigger signal ST, and the second terminal of the switch T44 is used to receive the second regulated voltage VSSQ. The first terminal of the switch T41 is electrically connected to the n-th stage operation node Q (n). The control terminal of the switch T41 is used to receive the n + k + 3 level trigger signal ST (n + k + 3). The second of the switch T41 is The terminal is used for receiving the second regulated voltage VSSQ. The first terminal of the switch T31 is used to receive the nth stage output voltage G (n), the control terminal of the switch T31 is used to receive the n + k + 3 stage output signal G (n + k + 3), and the second of the switch T31 is The terminal is used for receiving the third regulated voltage VSSG.

In operation, the switch T41 is turned on or off according to the n + k + 3 level trigger signal ST (n + k + 3). When the switch T41 is turned on, the switch T41 pulls down the voltage level of the n-th stage operation node Q (n) to the second regulated voltage VSSQ. The switch T31 is turned on or off according to the n + k + 3 level output signal G (n + k + 3). When the switch T31 is turned on, the switch T31 pulls down the n-th stage output voltage G (n) to the third regulated voltage Press VSSG.

In some embodiments, in addition to the working circuit 280, the n + k-stage shift register circuit 120 [n + k] of FIG. 2B and the n-stage shift register circuit 120 [n] of FIG. 2A have Similar circuit architecture. For ease of understanding, similar elements in Figure 2B as in Figure 2A will be assigned the same reference numerals. The following only describes the main differences between Figure 2B and Figure 2A.

The switch T42, the switch T32, and the switch T34 in FIG. 2A are turned on or off according to the voltage level of the n-th stage main voltage regulation node P (n). The switch T42, the switch T32, and the switch T34 in FIG. 2B are turned on or off according to the voltage level of the n + k-th main voltage regulation node P (n + k).

The switch T43, the switch T33, and the switch T35 in FIG. 2A are turned on or off according to the voltage level of the n-th level voltage stabilizing node (that is, the n + k-th level voltage stabilizing node P (n + k)). In other words, the voltage level of the n-th secondary voltage stabilization node is substantially the same as the voltage level of the n + k-th primary voltage stabilization node P (n + k).

The switches T43, T33, and T35 of FIG. 2B are turned on or off according to the voltage level of the n + k-th secondary voltage stabilization node (that is, the n-th primary voltage stabilization node P (n)). In other words, the voltage level of the n + k-th secondary voltage stabilization node is substantially the same as the voltage level of the n-th primary voltage stabilization node P (n).

According to this, when the voltage level of the n-th stage main voltage stabilizing node P (n) is high (for example: logic value 1), the switches T42, T32, and T34 in FIG. 2A are turned on, so that the The n-level operating node Q (n), the n-th output voltage G (n), and the n-th trigger signal ST (n) are pulled down to the second regulated voltage VSSQ or the third regulated voltage VSSG. At the same time, the switches T43, T33, and T35 in FIG. 2B are turned on, so that the n + k-th operating node Q (n + k), the The output voltage G (n + k) of the n + k stage and the trigger signal ST (n + k) of the n + k stage are pulled down to the second regulated voltage VSSQ or the third regulated voltage VSSG. Equivalently, the voltage level of the n-th stage main stabilizing node P (n) can simultaneously control the n-th stage shift temporary storage circuit 120 [n] in Fig. 2A and the n + k-stage shift in Fig. 2B The pull-down operation of the bit temporary storage circuit 120 [n + k] is to achieve the effects of shared nodes and dual control pull-down operation.

Similarly, when the voltage level of the main voltage regulation node P (n + k) of the n + kth stage is high, the switch T42, the switch T32, or the switch T34 in FIG. 2B will be turned on to turn the n + kth Stage operation node Q (n + k), n + k stage output voltage G (n + k) or n + k stage trigger signal ST (n + k) is pulled down to the second stabilized voltage VSSQ or the third stabilized voltage Voltage VSSG. At the same time, the switch T43, the switch T33, or the switch T35 in FIG. 2A will be turned on, so as to respectively switch the nth operating node Q (n), the nth output voltage G (n), or the nth trigger signal ST (n) Pull down to the second regulated voltage VSSQ or the third regulated voltage VSSG. Equivalently, the voltage level of the main regulator node P (n + k) at the n + k stage can control the nth stage temporary storage circuit 120 [n] in Fig. 2A and the nth stage in Fig. 2B. The pull-down operation of the + k-stage temporary storage circuit 120 [n + k] is to achieve the effects of shared nodes and dual control of the pull-down operation.

How the control circuit 260 in FIG. 2A controls the voltage level of the n-th stage main regulator node P (n) will be described below. When the voltage level of the control signal LC1 is high, the switch T51 is turned on. The switch T51 transmits the control signal LC1 to the control terminal of the switch T53. When the switch T53 is turned on, the switch T53 transmits the control signal LC1 to the n-th stage main voltage stabilizing node P (n).

Since the control circuit 260 in FIG. 2B controls the voltage level of the n + k-th main voltage stabilizing node P (n + k), the content is similar to that described above. No longer.

Please refer to Figure 3. FIG. 3 is a timing diagram of some signals in the gate driving circuit 100 shown in FIG. 1 according to some embodiments of the present disclosure. For ease of understanding, the following description will be made by taking n equal to 13 and k equal to 1. In other words, in these examples, the n-th stage shift register circuit 120 [n] in FIG. 2A is the 13th-stage shift register circuit, and the n + k-stage shift register circuit 120 in FIG. 2B n + k] is a 14th stage shift temporary storage circuit.

Figure 3 shows the clock signal HC (1) from level 1 to HC (17) from level 17, the trigger signals ST (11) and ST (12), and the node Q (13) at level 13 And the voltage signal of the 14th-level operation node Q (14), the voltage signal of the 13th-level main voltage regulation node P (13) and the 14th-level main voltage-regulation node P (14), and the 13th-level output signal G (13 ), Level 14 output signal G (14), trigger signal ST (16) and ST (17). The above-mentioned clock signals correspond to the voltage VH and the voltage VL. In addition, the above-mentioned clock signals are in units of 8 levels. For example, the first-stage clock signal HC (1) and the ninth-stage clock signal HC (9) are substantially synchronized or the same.

At time T1, the voltage level of the trigger signal ST (11) is changed to a high voltage level. The first switch T11 and the second switch T13 of the working circuit 280 of the thirteenth stage temporary storage circuit are turned on according to the trigger signal ST (11). The first operating voltage VGH is transmitted to the thirteenth-level operation node Q (13) and the fourteenth-level operation node Q (14) through the first switch T11 and the second switch T13, respectively. Accordingly, the voltage levels of the operation node Q (13) at the 13th level and the operation node Q (14) at the 14th level rise to the first operation voltage VGH. Equivalently, from time T1 to time T2, the 13th level operation node Q (13) and the 14th level operation node Q (14) are simultaneously The second regulated voltage VSSQ is changed to the first operation voltage VGH.

In addition, from time T1 to time T2, since the switch T54 in FIG. 2A and the switch T56 in FIG. 2B are gradually turned on according to the voltage level of the 13th-level operation node Q (13), the 13th-level voltage stabilization node P ( 13) The pull-down switch T54 is pulled down and the fourteenth-stage regulated node P (14) is pulled down to the second regulated voltage VSSQ through the switch T56. In other words, the 13th-level voltage stabilization node P (13) and the 14th-level voltage stabilization node P (14) are changed from the first stabilized voltage V1 (for example, the high voltage level of the control signal LC1) to the second stabilized voltage VSSQ . Since the voltage level of the voltage regulator node P (14) at the 14th stage is pulled down, the switch T43 in FIG. 2B is turned off. The working circuit 280 continuously provides the first operation voltage VGH to the fourteenth stage operation node Q (14), so that the fourteenth stage operation node Q (14) is changed from the second stabilized voltage VSSQ to the first operation voltage VGH.

At time T3, the voltage level of the 13th-stage clock signal HC (13) is turned to a high voltage level. At this time, the switch T21 of the 13th-stage shift temporary storage circuit is turned on according to the voltage level of the 13th-stage operation node Q (13). The thirteenth stage clock signal HC (13) is transmitted through the switch T21 as the thirteenth stage output voltage G (13). Accordingly, the thirteenth stage output voltage G (13) starts to rise. On the other hand, the thirteenth stage output voltage G (13) is coupled to the thirteenth stage operation node Q (13) through the capacitor C1 or other parasitic capacitance. Therefore, the voltage level at the 13th-level operation node Q (13) continues to rise. The voltage level at the 13th-level operating node Q (13) rises to a voltage V2.

Similarly, at time T4, the voltage level of the 14th-stage clock signal HC (14) is changed to a high voltage level. At this time, the switch T21 of the 14th stage shift temporary storage circuit is turned on according to the voltage level of the 14th stage operation node Q (14). The 14th stage clock signal HC (14) is transmitted as the 14th stage output voltage through switch T21. G (14). Accordingly, the 14th stage output voltage G (14) starts to rise. On the other hand, the 14th stage output voltage G (14) is coupled to the 14th stage operation node Q (14) through the capacitor C1 or other parasitic capacitance. Therefore, the voltage level of the operation node Q (14) at the 14th stage continues to rise. The voltage level at the 14th-level operation node Q (14) rises to a voltage V2.

At time T5, the voltage level of the 13th-stage clock signal HC (13) is turned to a low voltage level. Accordingly, with the switch T21 of the 13th stage shift register circuit, the 13th stage output voltage G (13) starts to decrease. At the same time, due to the coupling effect of the capacitor C1 or other parasitic capacitance in the 13th stage shift register circuit, the voltage level at the 13th stage operation node Q (13) starts to decrease accordingly.

Similarly, at time T6, the voltage level of the 14th-stage clock signal HC (14) is changed to a low voltage level. Accordingly, with the switch T21 of the 14th stage shift register circuit, the 14th stage output voltage G (14) starts to decrease. At the same time, due to the coupling effect of the capacitor C1 or other parasitic capacitances in the 14th stage shift register circuit, the voltage level at the 14th stage operation node Q (14) starts to decrease. In addition, because the switch T12 of the 16th stage shift temporary storage circuit is turned on according to the voltage level of the 16th stage operation node Q (16), the switch T12 transmits the 16th stage clock signal HC (16) as the 16th stage trigger Signal ST (16).

At time T7, the voltage level of the 17th-stage clock signal HC (17) is turned to a high voltage level. Accordingly, by the switch T21 of the 17th stage shift register circuit, the 17th stage output voltage G (17) is increased accordingly. At this time, the switch T31 in the 13th stage shift temporary storage circuit is turned on according to the 17th stage output voltage G (17). Accordingly, the switch T31 pulls down the thirteenth stage output voltage G (13) to the third stabilized voltage VSSG. In addition, since the switch T12 of the 17th-stage shift register circuit operates at the 17th stage, The voltage level of the node Q (17) is turned on, and the switch T12 transmits the 17th stage clock signal HC (17) as the 17th stage trigger signal ST (17).

In some embodiments, the switches are implemented by N-type transistors. In some other embodiments, the switches may be implemented by P-type transistors.

In summary, the working circuit simultaneously provides the first operating voltage to the first operating node (eg, the n-th level operating node) and the second operating node (eg, the n + k-th level operating node). In this way, the voltage difference between the first output voltage (eg, the n-th stage output voltage) and the second output voltage (eg, the n + k-th stage output voltage) can be reduced, thereby reducing the problem of bright and dark lines between the two stages.

Although this disclosure has been disclosed as above in the form of implementation, it is not intended to limit this disclosure. Any person with ordinary knowledge in the field can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, this disclosure The scope of protection shall be determined by the scope of the attached patent application.

Claims (10)

A gate driving circuit includes: an n + k-th stage shift temporary storage circuit including an n + k-th stage voltage stabilizing node, wherein n and k are positive integers; and an n-th stage shift temporary The storage circuit includes: an n-th output circuit for outputting an n-th output voltage according to a first operating voltage of an n-th operation node; an n-th voltage stabilizing circuit for an n-th output circuit A first stabilized voltage of the main voltage stabilizing node of the first stage to provide a second stabilized voltage to the nth level operation node; an nth level control circuit for controlling the first operating voltage according to the nth level operation node Providing the second regulated voltage to the n-th stage main voltage stabilizing node; and a working circuit for simultaneously providing the first operating voltage to the n-th stage operation node and the n + k-th stage shift temporary storage An n + k-th stage operating node of the circuit, wherein the n + k-th stage shift temporary storage circuit outputs an n + k-th stage output voltage according to the first operating voltage of the n + k-th stage operating node, wherein the The voltage levels of the n-th primary voltage stabilization node and the n + k-th secondary voltage stabilization node are substantially the same. The gate driving circuit according to claim 1, wherein the n + k-stage shift temporary storage circuit includes: an n + k-stage output circuit for operating the first node of the n + k-stage operation node Operating voltage, outputting an n + k level output voltage; an n + k level stabilizing circuit for providing the second voltage stabilization according to the first stabilizing voltage of an n + k level main stabilizing node Voltage to the n + k-th operating node; and an n + k-level control circuit for providing the second regulated voltage to the n-th operating voltage based on the first operating voltage of the n + k-level operating node + k-level main voltage regulation node. The gate driving circuit according to claim 1, wherein the working circuit is further configured to provide an n-2 level trigger signal from a n-2 level shift register circuit from the gate driving circuit, and simultaneously provide The first operation voltage reaches the n-th stage operation node and the n + k-th stage operation node of the n + k-stage shift register circuit. The gate driving circuit according to claim 3, wherein the working circuit includes: a first switch, wherein a first terminal of the first switch is used to receive the first operating voltage, and a second of the first switch The terminal is electrically connected to the n-th level operation node, and a control end of the first switch is used to receive the n-2th level trigger signal; and a second switch, wherein a first end of the second switch is used for After receiving the first operating voltage, a second terminal of the second switch is electrically connected to the n + k-th operation node, and a control terminal of the second switch is used to receive the n-2th trigger signal. The gate driving circuit according to claim 1, wherein the n-th output circuit is further configured to receive an n-th clock signal, and according to the first operating voltage of the n-th operating node, use the n-th The level clock signal is used as an n-th level trigger signal. The gate driving circuit according to claim 1, wherein the n-th operating node and the n + k-th operating node are simultaneously changed from the second regulated voltage to the first operating voltage. The gate driving circuit according to claim 1, wherein the n + k-th operating node is changed by the n-th-level operating voltage while the n-th level of the main voltage-stabilizing node is changed from the first voltage to the second voltage. The second regulated voltage is changed to the first operating voltage. A gate driving circuit includes: a first shift temporary storage circuit including: a first output circuit for outputting a first output voltage according to a first operating voltage of a first operating node; a first A voltage stabilizing circuit for providing a second voltage stabilizing voltage to the first operation node based on a first stabilizing voltage of a first main stabilizing node; and a first control circuit for stating the first operation The first operating voltage of the node provides the second stabilized voltage to the first main voltage stabilizing node; a second shift temporary storage circuit includes: a second output circuit, which is based on a second operating node The first operating voltage outputs a second output voltage; a second voltage stabilizing circuit is configured to provide the second voltage stabilizing voltage to the second operation according to the second voltage stabilizing voltage of a second main voltage stabilizing node. Node; and a second control circuit for providing the second voltage regulation voltage to the first main voltage regulation node according to the first operating voltage of the first operation node; and a working circuit for simultaneously providing the First operating voltage to the first operation And the second node point operation. The gate driving circuit according to claim 8, wherein the first operating node and the second operating node are simultaneously changed from the second regulated voltage to the first operating voltage. The gate driving circuit according to claim 8, wherein, while the first main voltage regulation node is changed from the first voltage regulation voltage to the second voltage regulation voltage, the second operation node is regulated by the second voltage regulation The voltage is changed to the first operating voltage.