KR102023547B1 - Display device and driving method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, a pull-up signal for turning on switching transistors formed in a gate line driven by a first selection signal, and a first pull-down signal for turning off the switching transistors. Another object of the present invention is to provide a display device and a method of driving the same, which are driven by a second selection signal to output a second pull-down signal for turning off the switching transistors. To this end, the display device according to the present invention includes a panel in which pixels are formed at intersection regions of 2n gate lines and data lines, and switching transistors are formed in each pixel corresponding to the gate line; A gate driver including stages for turning on or off switching transistors formed in each of the gate lines; And a display driver for controlling the gate driver, wherein each of the stages is driven by a first selection signal transmitted from the display driver, and the switching transistors are formed in a gate line corresponding to the stage. A first driver configured to output the pull-up signal for turning on and a first pull-down signal for turning off the switching transistors; And a second driver driven by a second selection signal transmitted from the display driver to output a second pull-down signal for turning off the switching transistors.

Description

Display device and its driving method {DISPLAY DEVICE AND DRIVING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device in which two pull-down transistors are used in a stage constituting a gate driver and a driving method thereof.

Flat panel displays (FPDs) are used in various types of electronic products, including mobile phones, tablet PCs, and notebook computers. The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic electroluminescent display (OLED), and more recently, an electrophoretic display ( EPD: ELECTROPHORETIC DISPLAY) is also widely used.

In general, a gate driver constituting the flat panel display device (hereinafter, simply referred to as a display device) sequentially supplies output signals to gate lines using a shift register.

The shift register includes stages including a plurality of thin film transistors, and the stages are cascaded to sequentially generate the output signal (scan signal).

Each of the stages includes switch circuits for charging and discharging Q and QB node voltages in response to a carry signal input from a previous stage, a carry signal input from a next stage, and a clock signal CLK.

The output signals of each of the stages are scan signals applied to the gate lines of the display device, and serve as carry signals transmitted to the previous stage and the next stage.

1 is an exemplary diagram showing a circuit configuration of each stage of a conventional shift register.

Each of the conventional stages, as shown in Figure 1, the pull-up transistor (PU) for outputting the output signal for turning on the switching transistor formed in each pixel of the panel and the output signal for turning off the switching transistor It may be configured to include a pull-down transistor (PD) for outputting.

That is, the output signal output from the stage is transmitted to one gate line to turn on or off the switching transistor connected to the gate line, also referred to as a scan signal.

The scan signal further includes a pull-up signal for turning on the switching transistor and a pull-down signal for turning off the switching transistor. Here, the pull-up signal is expressed in the form of a pulse.

The pull-up signal is output only during one horizontal period during which the data voltage is applied to the panel during one vertical period, and the pull-down signal is transmitted to the gate line during most of the one vertical period.

On the other hand, in each stage of the general gate driver, one pull-down transistor PD is used to transmit the pull-down signal to the gate line.

As described above, since the pull-down signal is output for most of one vertical period, when the pull-down transistor is used for a long time, the pull-down transistor PD may deteriorate, in which case the reliability of the circuit is deteriorated. Can be.

In particular, in the case of the pull-down transistor (PD) manufactured by using the oxide, the above-mentioned deterioration phenomenon is more severely generated.

Therefore, recently, a gate driver in which two pull-down transistors are alternately driven has been developed.

However, even when two pull-down transistors are used alternately, deterioration may occur severely in a pull-down transistor made of oxide.

That is, due to various advantages, in recent years, a pull-down transistor has been developed using oxide. However, since the oxide is weak in deterioration, even if two pull-down transistors made of oxide are alternately used every frame, the deterioration phenomenon may occur. Difficult to prevent

In addition, since the circuit area of the conventional stage composed of two pull-down transistors made of oxide is larger than that of the conventional stage composed of two pull-down transistors made of amorphous, many problems arise in the manufacturing process.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-described problem, and is driven by a first selection signal to pull up a signal for turning on switching transistors formed in a gate line, and a first pulldown for turning off the switching transistors. It is a technical object of the present invention to provide a display device and a driving method thereof, which output a signal and can be driven by a second selection signal to output a second pull-down signal for turning off the switching transistors.

In the display device according to the present invention for achieving the above technical problem, a pixel is formed at each intersection area of 2n gate lines and data lines, and a switching transistor is formed at each pixel corresponding to the gate line. panel; A gate driver including stages for turning on or off switching transistors formed in each of the gate lines; And a display driver for controlling the gate driver, wherein each of the stages is driven by a first selection signal transmitted from the display driver, and the switching transistors are formed in a gate line corresponding to the stage. A first driver configured to output the pull-up signal for turning on and a first pull-down signal for turning off the switching transistors; And a second driver driven by a second selection signal transmitted from the display driver to output a second pull-down signal for turning off the switching transistors.

According to an aspect of the present invention, there is provided a method of driving a display device, comprising: a stage connected to an n-th gate line from a first gate line among 2n gate lines formed in a panel in a half frame period; And, transmitting the first selection signal and transmitting the second selection signal from the n + 1th gate line to the stages connected to the second nth gate line; In the 1/2 frame period, each of the stages receiving the first selection signal includes a pull-up signal for turning on switching transistors formed in a gate line corresponding to the stage, and turning off the switching transistors. Outputting a first pull-down signal for outputting a second pull-down signal for turning off switching transistors each of the stages receiving the second selection signal on a gate line corresponding to the stage; In the remaining 1/2 frame period, the second selection signal is transmitted from the first gate line to the stages connected to the n-th gate line, and is connected to the second n-th gate line from the n + 1th gate line. Transmitting to said stages, said first selection signal; And in the remaining 1/2 frame period, each of the stages receiving the first selection signal outputs the pull-up signal and the first pull-down signal to a gate line corresponding to the stage, and the second selection signal. And receiving each of the stages, outputting the second pull-down signal to a gate line corresponding to the stage.

According to the present invention, since two pull-down transistors provided in one stage are alternately driven every 1/2 frame, deterioration of the pull-down transistor can be prevented.

In addition, according to the present invention, since the application time of the clock CLK, which occupies most of the power consumption, is cut in half, power consumption may also be reduced.

1 is an exemplary diagram showing a circuit configuration of each stage of a conventional shift register.
2 is an exemplary view showing a configuration of a display device according to the present invention.
3 is a circuit diagram of an embodiment of a stage applied to a display device according to a first embodiment of the present invention.
4 is an exemplary diagram illustrating a connection relationship between gate lines and stages applied to a display device driving method according to a first embodiment of the present invention.
5 is an exemplary diagram illustrating a connection relationship between stages and gate lines applied to a display device driving method according to a second exemplary embodiment of the present invention.
6 to 11 are exemplary views for explaining a method of operating a stage applied to the display device according to the first embodiment of the present invention.
12 is a circuit diagram of an embodiment of a stage applied to a display device according to a second embodiment of the present invention.
13 to 18 are exemplary diagrams for describing a method of operating a stage applied to a display device according to a second exemplary embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

The present invention can be applied to various kinds of display devices using a panel composed of switching transistors turned on by a scan signal supplied through a gate line. However, below, the liquid crystal display device is demonstrated as an example of this invention for convenience of description.

2 is an exemplary view showing a configuration of a display device according to the present invention.

In the display device according to the present invention, a panel 100 in which a switching transistor composed of a thin film transistor (hereinafter referred to as TFT) is formed at an intersection of a data line DL and a gate line GL. ), Gate drivers 200a and 200b including stages 210a and 210b for turning on or off switching transistors formed in each of the gate lines, and data lines DL of the panel 100. And a display driver 300 for supplying a data voltage OUTPUT to the gate and controlling the gate drivers 200a and 200b.

First, the panel 100 may be manufactured in various forms. When the panel 100 is a liquid crystal panel, the panel 100 includes two glass substrates, and liquid crystal is injected between the two glass substrates. Pixels are formed at intersections of the data lines DL and the gate lines GL formed in the panel 100. The switching transistor TFT provided in each pixel supplies a data voltage applied from the display driver to the pixel electrode provided in each pixel in response to a pull-up signal applied from the gate drivers 200a and 200b.

As shown in FIG. 2, in the display area A of the panel 100, an image is output, for every intersection area of 2n gate lines GL1 to GL2n and m data lines DL1 to DLm. A pixel is formed, and a switching transistor is formed in each pixel corresponding to the gate line. The display driver 300 and the gate drivers 200a and 200b may be formed in the non-display area B in which no image is output among the panel 100.

Next, the display driver 300 receives a driving voltage from an external system such as a personal computer or a television, and receives timing signals and input image data from the external system. The gate drivers 200a and 200b may be formed in the display driver 300, or may be formed separately from the display driver 300 as shown in FIG. 2. The data driver for outputting the data voltage to the data lines may also be formed separately from the display driver 300, but may be configured inside the display driver 300 as shown in FIG. 2.

In the following description, a display device in which the data driver is included in the display driver 300 and the gate drivers 200a and 200b is independent of the display driver 300 will be described as an example of the present invention. However, the present invention is not limited thereto.

The display driver 300 aligns the input image data of red (R), green (G) and blue (B) transmitted from the external system according to the panel, and then supplies the aligned image data to the data driver. do. The data driver supplies a data voltage to each data line according to a pull-up signal output from the gate driver 200.

The display driver 300 controls the gate drivers 200a and 200b by generating a dot clock Dclk and various gate control signals using a horizontal / vertical synchronization signal (timing signal) input from the external system. .

The gate control signal is supplied to each of the stages 210a and 210b constituting the gate driver 200a or 200b. The first selection signal Vselect1, the second selection signal Vseclet2, and the gate start signal Vst) and a reset signal Vrst. The function of each of the signals is described in detail below with reference to FIGS. 6 to 18.

Lastly, the gate drivers 200a and 200b may include a shift register that sequentially generates the pull-up signal in response to a gate start signal Vst input from the display driver 300. As shown in FIG. 2, the plurality of stages 210a and 210b are included.

As described above, the gate drivers 200a and 200b may be formed inside the display driver 300 or may be formed on the panel separately from the display driver 300.

The gate drivers 200a and 200b may be formed in only one non-display area of the panel 100, but may be formed in each of the two non-display areas facing each other as shown in FIG. 2.

The stages 210a and 210b provided in the gate drivers 200a and 200b to transmit pull-up signals and pull-down signals to the respective gate lines are displayed on two non-displays of the panel 100 facing each other. The gate lines may be connected through a region, or may be connected to the gate lines through one non-display area.

An exemplary circuit diagram of the stages 210a and 210b constituting the gate drivers 200a and 200b is shown in FIG. 3.

FIG. 3 is a circuit diagram of an exemplary stage applied to the display device according to the first exemplary embodiment of the present invention, and illustrates a circuit configuration of each of the stages 210a and 210b illustrated in FIG. 2.

Each of the stages 210a and 210b applied to the first embodiment of the present invention is driven by the first selection signal Vselect1 transmitted from the display driver 300 as shown in FIG. 3. A first driver 211 and a display driver 300 outputting the pull-up signal for turning on the switching transistors formed in the gate line corresponding to the stage, and a first pull-down signal for turning off the switching transistors; And a second driver 212 which is driven by the second selection signal Vselect2 transmitted from the second signal and outputs a second pull-down signal for turning off the switching transistors.

The first driver 211 includes first to fifth transistors T5, a pull-up transistor PU, and a first pull-down transistor PD1.

The first transistor T1 is connected between a node connected to a first selection signal terminal supplied with the first selection signal and a node connected to a gate terminal of the fifth transistor T5 and the pull-up transistor PU. The gate terminal of the first transistor T1 is connected to a start signal terminal to which the gate start signal is supplied.

The second transistor T2 is connected between a node connected to the first selection signal terminal supplied with the first selection signal and a node connected to the gate terminal of the third transistor and the gate terminal of the first pull-down transistor PD1. The gate terminal of the first transistor is connected to the first selection signal terminal.

The third transistor T3 is connected between the first transistor T1 and the low level driving voltage terminal supplied with the low level driving voltage VSS, and the gate terminal of the third transistor T3 is pulled down. It is connected to the gate terminal of the transistor PD1.

The fourth transistor T4 is connected between the gate terminal of the third transistor and the first pull-down transistor PD1 and the low level driving voltage terminal, and the gate terminal of the fourth transistor T4 is pulled up. It is connected to the gate terminal of the transistor PU.

The fifth transistor T5 is connected between the low level driving voltage terminal and the first transistor T1, and the gate terminal of the fifth transistor T5 is a reset signal terminal supplied with the reset signal Vrst. Connected with

The pull-up transistor PU is connected between the clock terminal supplied with the clock CLK and the first pull-down transistor PD1, and the gate terminal of the pull-up transistor is connected to the first transistor.

The first pull-down transistor PD1 is connected to the pull-up transistor PU and the low level driving voltage terminal, and the gate terminal of the first pull-down transistor PD1 is connected to the gate terminal of the third transistor.

An output node between the pull-up transistor PU and the first pull-down transistor PD1 is connected to the gate line. The output node may include a pull-up signal output from the pull-up transistor PU, a first pull-down signal output from the first pull-down transistor PD1, and a second pull-down transistor PD2 included in the second driver 212. The second pull-down signal outputted from) is output.

The second driver 212 includes a sixth transistor T6, a seventh transistor T7, and a second pull-down transistor PD2.

The sixth transistor T6 is connected between the node connected to the gate terminal of the third transistor and the gate terminal of the first pull-down transistor PD1 and the low level driving voltage terminal, and the sixth transistor T6. The gate terminal of is connected to the second selection signal terminal to which the second selection signal Vselect2 is supplied.

The seventh transistor T7 is connected between the gate terminal of the first transistor, the node connected to the gate terminal of the pull-up transistor PU, and the low level driving voltage terminal, and the gate terminal of the seventh transistor T7. Is connected to the second selection signal terminal.

The second pull-down transistor PD2 is connected between the output terminal and the low potential driving voltage terminal, and the gate terminal of the second pull-down transistor PD2 is connected to the second selection signal terminal.

The display driver 300 transmits the first selection signal to the stage in a half frame period to drive the first driver 211. The first driver 211 outputs the pull-up signal to the gate line, and outputs the first pull-down signal to the gate line during a period other than a period during which the pull-up signal is output during the half frame period.

The display driver 300 transmits the second selection signal to the stage in the remaining half frame period to drive the second driver 212. The second driver 212 outputs the second pull-down signal to the gate line in the remaining 1/2 frame period.

4 is an exemplary diagram illustrating a connection relationship between gate lines and stages applied to a display device driving method according to a first embodiment of the present invention.

In the method of driving the display device according to the first embodiment of the present invention, as shown in FIG. 4, the first group stages LS1 to LSn of the stages 210a and 210b are formed of the panel 100. The second group stages RS1 to RSn among the stages are formed in the second side non-display area facing the first side non-display area.

The display driver 300 is a stage connected to an nth gate line GLn from a first gate line GL1 among the gate lines in a half frame period, and includes the first selection signal Vselect1. ), And transmits the second selection signal Vselect2 from the n + 1th gate line GLn + 1 to the stages GL2n connected to the second nth gate line. The display driver 300 transmits the second selection signal Vselect2 to stages connected to the nth gate line GLn from the first gate line GL1 in the remaining half frame period. The first select signal Vselect1 is transmitted from the n + 1th gate line GLn + 1 to the stages connected to the second nth gate line GL2n.

In this case, the display driver 300 may include the first stage SL1 and the second group stages RS1 to RSn among the first group stages LS1 to LSn when the 1/2 frame period starts. Transmits the gate start signal Vst to the first stage RS1, and when the remaining half frame period starts, the ((n / 2) +1) th stage LS of the first group stages (n / 2 + 1) and the gate start signal Vst is transmitted to the ((n / 2) +1) stage RS (n / 2 + 1) of the second group stages.

That is, in the 1/2 frame period, the display driver 300 is connected to the n-th gate line GLn from the first gate line GL1 among the 2n gate lines formed in the panel 100. Stages LS that transmit the first selection signal to the stages LS1 to RS (n / 2) and are connected to the second nth gate line GL2n from the n + 1th gate line GLn + 1 (n / 2 + 1), a second selection signal is transmitted.

During the 1/2 frame period, each of the stages receiving the first selection signal includes a pull-up signal for turning on switching transistors formed in a gate line corresponding to the stage, and turning off the switching transistors. A first pull-down signal for outputting the second pull-down signal, and each of the stages receiving the second selection signal outputs a second pull-down signal for turning off switching transistors formed in a gate line corresponding to the stage.

In addition, in the remaining 1/2 frame period, the display driver 300 transmits the second selection signal to the stages connected to the n-th gate line from the first gate line, and the n + 1th stage. The first selection signal is transmitted from the gate line to the stages connected to the second n-gate line.

During the remaining 1/2 frame period, each of the stages receiving the first selection signal outputs the pull-up signal and the first pull-down signal to a gate line corresponding to the stage, and outputs the second selection signal. Each of the received stages outputs the second pull-down signal to a gate line corresponding to the stage.

That is, in the first embodiment of the present invention as described above, each stage receives the first selection signal in a half frame period, so that the pull-up transistor PU and the first pull-down transistor PD1 are used. ) To output the pull-up signal and the first pull-down signal. In the other half frame period, the second selection signal is received, and the second pull-down transistor PD2 is driven to output the second pull-down signal.

The driving method of each stage according to the first embodiment as described above is described with reference to FIGS. 6 to 11.

5 is an exemplary diagram illustrating a connection relationship between gate lines and stages applied to a display device driving method according to a second exemplary embodiment of the present invention.

In the method of driving the display device according to the second exemplary embodiment of the present invention, as shown in FIG. 5, the first group stages LS1 to LSn of the stages 210a and 210b are formed of the panel 100. The second group stages RS1 to RSn among the stages are formed in the second side non-display area facing the first side non-display area.

First group stages of the stages are formed in a first side non-display area of the panel 100 and are connected to odd-numbered gate lines, and second group stages of the stages are non-display area of the first side. It is formed in the second side non-display area facing the gate and is connected to the even-numbered gate lines.

The display driver 300 transmits the first selection signal to the first group stages, transmits the second selection signal to the second group stages, and performs the remaining 1 / in a 1/2 frame period. In the two frame periods, the second selection signal is transmitted to the first group stages, and the first selection signal is transmitted to the second group stages. The display driver 300 transmits a gate start signal to a first stage of the first group stages when the remaining half frame period starts, and when the remaining half frame period starts, the first The gate start signal is transmitted to the first stage of the group stages.

That is, when the 1/2 frame period starts, the display driver 300 is formed of first group stages formed in the first side non-display area of the panel 100 and connected to odd-numbered gate lines. The first select signal is transmitted, and the second select signal is transmitted to second group stages formed in the second non-display area facing the first non-display area and connected to even-numbered gate lines.

During the 1/2 frame period, each of the first group stages receiving the first selection signal includes a pull-up signal for turning on switching transistors formed in a gate line corresponding to the stage, and the switching transistors. A second pull-down signal for outputting a first pull-down signal for turning off, and each of the second group stages receiving the second selection signal for turning off switching transistors formed in a gate line corresponding to the stage; Outputs

The display driver 300 transmits the second selection signal to the first group stages and transmits the first selection signal to the second group stages during the remaining 1/2 frame period.

During the 1/2 frame period, each of the second group stages receiving the first selection signal includes a pull-up signal for turning on switching transistors formed in a gate line corresponding to the stage, and the switching transistors. A second pull-down signal for outputting a first pull-down signal for turning off, and each of the first group stages receiving the second selection signal for turning off switching transistors formed in a gate line corresponding to the stage; Outputs

That is, in the first embodiment of the present invention, shown in Figure 4, after the stages connected to the gate lines formed on the upper end of the panel 100 is sequentially driven in the half frame period, the remaining 1 / In the two frame periods, stages connected to gate lines formed at the lower end of the panel 100 are sequentially driven.

However, in the second embodiment of the present invention shown in FIG. 5, after the first group stages connected to the odd-numbered gate lines formed in the panel 100 are sequentially driven in a half frame period, In the other half frame period, second group stages connected to even-numbered gate lines formed in the panel 100 are sequentially driven.

Although not shown in the drawings, the display device driving method according to the third exemplary embodiment of the present invention may be executed in a state in which the stages are all formed in one of the non-display areas. That is, the display device driving method according to the third exemplary embodiment of the present invention is driven in a state in which all the stages are sequentially connected to the gate lines in one non-display area.

In this case, the display driver 300 transmits the first selection signal to stages connected to the nth gate line from the first gate line among the gate lines in a half frame period. a stage connected to the n-th gate line from the n + 1 gate line, and transmitting the second selection signal, and in the remaining half-frame period, the stage connected to the n-th gate line from the first gate line For example, the second selection signal may be transmitted, and the first selection signal may be transmitted from the n + 1th gate line to the stages connected to the second nth gate line.

That is, each of the stages is driven by a first selection signal to turn off the switching transistors and the pull-up signal for turning on the switching transistors formed in each of the 2n gate lines formed in the panel. Outputs a first pull-down signal for the second pull-down signal and is driven by a second selection signal to output a second pull-down signal for turning off the switching transistors.

The third embodiment of the present invention as described above is the display according to the second or second embodiment of the present invention as described above, except that the stages are formed in either non-display area. It is driven in a form similar to the device driving method.

In order to execute the display device driving method according to the first to third embodiments of the present invention as described above, a specific operation method of the stage (210a, 210b) driven in accordance with the first selection signal and the second selection signal Will be described in detail with reference to FIGS. 6 to 18. That is, the display device driving method according to the first to third embodiments of the present invention can be executed in the display device according to the first embodiment of the present invention shown in FIG.

6 to 11 are exemplary views for explaining a method of operating a stage applied to the display device according to the first embodiment of the present invention. 6 to 11, a node denoted by Q is a node connected to the gate terminal of the pull-up transistor PU, and a node denoted by Qb is a node connected to the gate terminal of the first pull-down transistor PD1.

First, referring to FIG. 6, when the 1/2 frame starts, the first select signal Vselect1 of high level, the second select signal Vselect2 of low level, the gate start signal Vst of low level, and the low level The reset signal Vrst is input to the stage.

The third transistor T3 is turned on by the first selection signal, and a low potential driving voltage VSS is supplied to the gate terminal of the pull-up transistor PU. Thus, the pull-up transistor PU is turned off.

The second transistor and the first pull-down transistor PD1 are turned on by the high selection first selection signal. When the first pull-down transistor PD1 is turned on, a low level driving voltage VSS is induced to the first pull-down transistor PD1, and the output node has a first pull-down signal Vg_out having a low level (low level). Is output. The first pull-down signal is supplied to a gate line connected to the stage to turn off switching transistors connected to the gate line.

Next, referring to FIG. 7, after the 1/2 frame starts, the gate start signal Vst having a high level is sequentially input to the stages.

When the high level gate start signal Vst is input, the first transistor and the pull-up transistor PU are turned on. When the pull-up transistor PU starts the turn-on process, a high level voltage is charged in the gate terminal of the pull-up transistor PU.

The high level signal induced to the fourth transistor T4 through the first transistor T1 turns on the fourth transistor T4. Accordingly, the low level driving voltage VSS is induced to the first pull-down transistor, and the first pull-down transistor PD1 is turned off. In this case, the size of the second transistor T2 is very small compared to the third transistor T3 or the first pull-down transistor PD1, and thus does not operate because the influence on the circuit is very small. That is, since the second transistor T2 is always on, the Qb node does not go down exactly to VSS, but is voltage-divided by the second transistor T2 to have a voltage slightly higher than VSS. However, since it is close to Low, no current flows. Therefore, the second transistor T2 operates only in a section where Qb becomes high.

Next, referring to FIG. 8, when the gate start signal Vst is changed to the low level, the pull-up transistor PU is turned on by the high level signal charged in the gate terminal of the pull-up transistor PU. At this time, a high level clock CLK is output to the output terminal through the pull-up transistor PU. Accordingly, the high level pull-up signal Vg_out is output to the gate line to turn on the switching transistors connected to the gate line.

At this time, the first pull-down transistor PD1 is turned off by the low level driving voltage VSS induced through the fourth transistor T4.

Next, referring to FIG. 9, a high level reset signal Vrst is input.

The fifth transistor T5 is turned on by the high level reset signal, and the low level driving voltage VSS is supplied to the gate terminal of the pull-up transistor PU. In addition, the low level driving voltage VSS is also supplied to the gate terminal of the pull-up transistor PU through the third transistor. Accordingly, the pull-up transistor PU is turned off and a pull-up signal of a high level is no longer issued.

Since the high level signal is supplied to the first pull-down transistor PD1 through the second transistor T2, the first pull-down transistor PD1 is turned on. Accordingly, a low pull first pull-down signal Vg_out is output to the output terminal by the low level driving voltage VSS to turn off the switching transistors connected to the gate line.

Next, referring to FIG. 10, the processes described in FIG. 9 continue.

Accordingly, the first pull-down transistor PD1 is turned on by the first selection signal Vselect, and the low-level first pull-down signal Vg_out is continuously output through the first pull-down transistor PD1.

In this case, since the reset signal Vrst is converted to the low level, the fifth transistor T5 is turned off.

Finally, referring to FIG. 11, when the other half frame is started, the first selection signal Vselect1 is changed to the low level, and the second selection signal Vselect2 is changed to the high level.

The sixth transistor T6 and the seventh transistor T7 are turned on by the second selection signal Vselect2 so that a low potential driving voltage VSS is applied to the pull-up transistor PU and the first pull-down transistor. It is supplied to the gate terminal of PD1. Therefore, the pull-up transistor PU and the first pull-down transistor PD1 are turned off.

The second pull-down transistor PD2 is turned on by the second select signal Vselect2, and a low potential driving voltage VSS is supplied to the second pull-down transistor PD2. Therefore, the second pull-down signal Vg_out having a low level is output to the output terminal through the second pull-down transistor PD2 by the low level driving voltage VSS, thereby turning on the switching transistors connected to the gate line. Turn it off.

The display device driving method according to the first to third embodiments of the present invention as described above may be executed in the display device according to the second embodiment of the present invention shown in FIG. A method of operating the display device according to the second exemplary embodiment of the present invention illustrated in FIG. 12 will be described in detail with reference to FIGS. 13 to 18.

FIG. 12 is a circuit diagram of an exemplary stage applied to the display device according to the second exemplary embodiment of the present invention, and illustrates a circuit configuration of each of the stages 210a and 210b illustrated in FIG. 2. 13 to 18 are exemplary diagrams for describing a method of operating a stage applied to a display device according to a second exemplary embodiment of the present invention.

Each of the stages 210a and 210b applied to the second exemplary embodiment of the present invention is driven by the first selection signal Vselect1 transmitted from the display driver 300 as shown in FIG. 12. A first driver 211 and the display driver 300 outputting the pull-up signal for turning on the switching transistors formed in the gate line corresponding to the stage, and a first pull-down signal for turning off the switching transistors; And a second driver 212 which is driven by the second selection signal Vselect2 transmitted from and outputs a second pull-down signal for turning off the switching transistors.

The first driver 211 includes first to fifth transistors T5, a pull-up transistor PU, and a first pull-down transistor PD1. Since the structure of the said 1st drive part 211 is the same as the structure of the 1st drive part applied to the 1st Example, detailed description is abbreviate | omitted.

The second driver 212 includes a sixth transistor T6 and a second pull-down transistor PD2.

The sixth transistor T6 is connected between the gate terminal of the pull-up transistor PU and the gate terminal of the first pull-down transistor PD1, and the gate terminal of the sixth transistor T6 is connected to the gate terminal of the pull-up transistor PU1. It is connected to the second selection signal terminal.

The second pull-down transistor PD2 is connected between the output terminal and the low potential driving voltage terminal, and the gate terminal of the second pull-down transistor PD2 is connected to the second selection signal terminal.

The display driver 300 transmits the first selection signal to the stage in a half frame period to drive the first driver 211. The first driver 211 outputs the pull-up signal to the gate line, and outputs the first pull-down signal to the gate line during a period other than a period during which the pull-up signal is output during the half frame period.

The display driver 300 transmits the second selection signal to the stage in the remaining half frame period to drive the second driver 212. The second driver 212 outputs the second pull-down signal to the gate line in the remaining 1/2 frame period.

The driving method of the stage applied to the second embodiment of the present invention as described above will be described with reference to FIGS. 13 to 18.

First, referring to FIG. 13, when the 1/2 frame starts, the first select signal Vselect1 of high level, the second select signal Vselect2 of low level, the gate start signal Vst of low level, and the low level The reset signal Vrst is input to the stage.

The third transistor T3 is turned on by the first selection signal, and a low potential driving voltage VSS is supplied to the gate terminal of the pull-up transistor PU. Thus, the pull-up transistor PU is turned off.

The second transistor and the first pull-down transistor PD1 are turned on by the high selection first selection signal. When the first pull-down transistor PD1 is turned on, a low level driving voltage VSS is induced to the first pull-down transistor PD1, and the output node has a first pull-down signal Vg_oug having a low level (low level). Is output. The first pull-down signal is supplied to a gate line connected to the stage to turn off switching transistors connected to the gate line.

Next, referring to FIG. 14, after the 1/2 frame starts, the gate start signal Vst having a high level is sequentially input to the stages.

When the high level gate start signal Vst is input, the first transistor and the pull-up transistor PU are turned on. When the pull-up transistor PU starts the turn-on process, a high level voltage is charged in the gate terminal of the pull-up transistor PU.

The high level signal induced to the fourth transistor T4 through the first transistor T1 turns on the fourth transistor T4. Accordingly, the low level driving voltage VSS is induced to the first pull-down transistor, and the first pull-down transistor PD1 is turned off. The high level signal induced through the second transistor T2 is discharged through the fourth transistor T4.

Next, referring to FIG. 15, when the gate start signal Vst is changed to the low level, the pull-up transistor PU is turned on by the high level signal charged in the gate terminal of the pull-up transistor PU. At this time, a high level clock CLK is output to the output terminal through the pull-up transistor PU. Accordingly, the high level pull-up signal Vg_out is output to the gate line to turn on the switching transistors connected to the gate line.

At this time, the first pull-down transistor PD1 is turned off by the low level driving voltage VSS induced through the fourth transistor T4.

Next, referring to FIG. 16, the high level reset signal Vrst is input.

The fifth transistor T5 is turned on by the high level reset signal, and the low level driving voltage VSS is supplied to the gate terminal of the pull-up transistor PU. In addition, the low level driving voltage VSS is also supplied to the gate terminal of the pull-up transistor PU through the third transistor. Accordingly, the pull-up transistor PU is turned off and a pull-up signal of a high level is no longer issued.

Since the high level signal is supplied to the first pull-down transistor PD1 through the second transistor T2, the first pull-down transistor PD1 is turned on. Accordingly, a low pull first pull-down signal Vg_out is output to the output terminal by the low level driving voltage VSS to turn off the switching transistors connected to the gate line.

Next, referring to FIG. 17, the processes described in FIG. 16 continue.

Accordingly, the first pull-down transistor PD1 is turned on by the first selection signal Vselect, and the low-level first pull-down signal Vg_out is continuously output through the first pull-down transistor PD1.

In this case, since the reset signal Vrst is converted to the low level, the fifth transistor T5 is turned off.

Finally, referring to FIG. 18, when the remaining 1/2 frame starts, the first select signal Vselect1 is changed to the low level, and the second select signal Vselect2 is changed to the high level.

The sixth transistor T6 is turned on by the second selection signal Vselect2 so that the low potential driving voltage VSS is turned on through the third transistor PU1 and the first pull-down transistor PD1. Is supplied to the gate terminal. Therefore, the pull-up transistor PU and the first pull-down transistor PD1 are turned off.

The second pull-down transistor PD2 is turned on by the second select signal Vselect2, and a low potential driving voltage VSS is supplied to the second pull-down transistor PD2. Therefore, the second pull-down signal Vg_out having a low level is output to the output terminal through the second pull-down transistor PD2 by the low level driving voltage VSS, thereby turning on the switching transistors connected to the gate line. Turn it off.

In this case, the gate and the drain of the third transistor are connected by the sixth transistor T6, and the third transistor T3 performs an operation as a diode. That is, the third transistor operates a diode when Vgd = 0, operates on a state when Vgs> Vth, and turns off when Vgs ≤ 0. Therefore, since the third transistor T3 keeps the On state and flows current until the voltage of the Qb node becomes the threshold voltage of the third transistor T3, the Qb node also falls to Low.

The present invention as described above is to improve the reliability of the panel using the oxide semiconductor.

That is, while the panel 100 is divided into two parts and the pull-up signal is supplied to the first area, the second pull-down for turning off the switching transistor through the second pull-down transistor added in the second area. The signal is supplied to the gate line.

In addition, while the pull-up signal is supplied to the second region, the second pull-down signal VSS is supplied to the gate line through the second pull-down transistor added in the first region.

That is, in the present invention, two pull-down transistors are alternately driven in respective stages connected to gate lines formed in two divided regions of the panel.

Those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

100: panels 210a, 210b: stages
200a, 200b: gate driver 300: display driver

Claims (10)

A panel in which pixels are formed at intersections of 2n gate lines and data lines, and a switching transistor is formed in each pixel corresponding to the gate line;
A gate driver including stages for turning on or off switching transistors formed in each of the gate lines; And
A display driver for controlling the gate driver;
Each of the stages,
A pull-up signal for turning on the switching transistors formed on a gate line corresponding to the stage and driven by a first selection signal transmitted from the display driver, and a first pull-down signal for turning off the switching transistors; An outputting first driver; And
A second driver driven by a second selection signal transmitted from the display driver to output a second pull-down signal for turning off the switching transistors;
The display driving unit transmits the first selection signal to the stage in a half frame period, and transmits the second selection signal to the stage in a remaining half frame period.
Display. delete The method of claim 1,
First group stages of the stages are formed in a first side non-display area of the panel, and second group stages of the stages are in a second side non-display area facing the first side non-display area. Formed,
The display driver,
In the 1/2 frame period, the first selection signal is transmitted to stages connected to the n-th gate line among the gate lines, and the n-th gate line is connected to the n-th gate line from the n + 1 th gate line. Transmitting the second selection signal to connected stages,
In the remaining half frame period, the second selection signal is transmitted from the first gate line to the stages connected to the n-th gate line, and is connected to the second n-th gate line from the n + 1th gate line. And transmitting the first selection signal to the present stages. The method of claim 3, wherein
The display driver,
When the 1/2 frame period begins, a gate start signal is transmitted to a first stage of the first group stages and a first stage of the second group stages,
When the remaining half frame period starts, gate to the ((n / 2) +1) stage of the first group stages and the ((n / 2) +1) stage of the second group stages. A display device, characterized by transmitting a start signal. The method of claim 1,
First group stages of the stages are formed in a first side non-display area of the panel and are connected to odd-numbered gate lines, and second group stages of the stages face the first non-display area. Formed in the second non-display area of the second side and connected to the even-numbered gate lines
The display driver,
In the 1/2 frame period, the first selection signal is transmitted to the first group stages, and the second selection signal is transmitted to the second group stages.
And transmitting the second selection signal to the first group stages and transmitting the first selection signal to the second group stages during the remaining 1/2 frame period. The method of claim 5,
The display driver,
When the 1/2 frame period begins, a gate start signal is transmitted to a first stage of the first group stages,
And a gate start signal is transmitted to a first one of the first group stages when the remaining half frame period begins. The method of claim 1,
The display driver,
In the 1/2 frame period, the first selection signal is transmitted to stages connected to the n-th gate line among the gate lines, and the n-th gate line is connected to the n-th gate line from the n + 1 th gate line. Transmitting the second selection signal to connected stages,
In the remaining half frame period, the second selection signal is transmitted from the first gate line to the stages connected to the n-th gate line, and is connected to the second n-th gate line from the n + 1th gate line. And transmitting the first selection signal to the present stages. In a 1/2 frame period, the first selection signal is transmitted from the first gate line to the stages connected to the n-th gate line among the 2n gate lines formed in the panel, and from the n + 1 gate line. Transmitting a second selection signal to stages connected to the second n gate line;
In the 1/2 frame period, each of the stages receiving the first selection signal includes a pull-up signal for turning on switching transistors formed in a gate line corresponding to the stage, and turning off the switching transistors. Outputting a first pull-down signal for outputting a second pull-down signal for turning off switching transistors each of the stages receiving the second selection signal on a gate line corresponding to the stage;
In the remaining 1/2 frame period, the second selection signal is transmitted from the first gate line to the stages connected to the n-th gate line, and is connected to the second n-th gate line from the n + 1th gate line. Transmitting to said stages, said first selection signal; And
In the remaining 1/2 frame period, each of the stages receiving the first selection signal outputs the pull-up signal and the first pull-down signal to a gate line corresponding to the stage, and outputs the second selection signal. And each of the received stages outputs the second pull-down signal to a gate line corresponding to the stage. In a 1/2 frame period, a first selection signal is transmitted to first group stages formed in a first side non-display area of the panel and connected to odd-numbered gate lines, and face the first non-display area. Transmitting a second selection signal to second group stages formed in the second side non-display area that are connected to the even-numbered gate lines;
In the 1/2 frame period, each of the first group stages receiving the first selection signal includes a pull-up signal for turning on switching transistors formed in a gate line corresponding to the stage, and the switching transistors. A second pull-down signal for outputting a first pull-down signal for turning off, and each of the second group stages receiving the second selection signal for turning off switching transistors formed in a gate line corresponding to the stage; Outputting;
Transmitting the second selection signal to the first group stages and transmitting the first selection signal to the second group stages during the remaining half frame period; And
In the 1/2 frame period, each of the second group stages receiving the first selection signal includes a pull-up signal for turning on switching transistors formed in a gate line corresponding to the stage, and the switching transistors. A second pull-down signal for outputting a first pull-down signal for turning off, and each of the first group stages receiving the second selection signal for turning off switching transistors formed in a gate line corresponding to the stage; Display device driving method comprising the step of outputting. A pull-up signal for turning on the switching transistors formed on each of the 2n gate lines formed in the panel by a first selection signal during a half frame period, and a turn-off signal for turning off the switching transistors; Outputting one pull-down signal; And
And outputting a second pull-down signal driven by a second selection signal during the remaining half frame period to turn off the switching transistors.

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