KR20140075962A - Display device and driving method thereof - Google Patents

Abstract

The present invention relates to a display device. More specifically, the objective of the present invention is to provide a display device and a method for driving the same, capable of: outputting a pull-up signal to turn on switching transistors formed on gate lines, and a first pull-down signal to turn off the switching transistors by being driven by a first selection signal; and outputting a second pull-down signal to turn off the switching transistors by being driven by a second selection signal. To achieve the objective, the display device comprises: a panel having pixels which are formed in every cross section of second n number of gate lines and data lines and switching transistors which are respectively formed on the pixels corresponding to the gate lines; a gate driving unit including stages to turn on or turn off the switching transistors which are respectively formed on the gate lines; and a display driving unit to control the gate driving unit. Each of the stages includes a first driving unit which is driven by a first selection signal transmitted from the display driving unit, and outputs a pull-up signal to turn on the switching transistors formed on the gate lines corresponding to the stage, and a first pull-down signal to turn off the switching transistors; and a second driving unit which is driven by a second selection signal transmitted from the display driving unit and outputs a second pull-down signal to turn off the switching transistors.

Description

DISPLAY DEVICE AND DRIVING METHOD THEREOF [0002]

The present invention relates to a display device, and more particularly, to a display device using two pull-down transistors on a stage constituting a gate driver and a driving method thereof.

Flat panel displays (FPDs) are used in various types of electronic products including mobile phones, tablet PCs, and notebook computers. The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), and an organic electroluminescence display (OLED). Recently, an electrophoretic display device EPD: ELECTROPHORETIC DISPLAY) is also widely used.

The gate driver constituting the flat panel display device (hereinafter simply referred to as a 'display device') sequentially supplies output signals to the gate lines by using a shift register.

The shift register includes stages including a plurality of thin film transistors, and the stages are cascade-connected to sequentially generate the output signal (scan signal).

Each of the stages includes switch circuits for charging the Q node and the QB node voltage in response to a carry signal input from a previous stage, a carry signal input from the next stage, and a clock signal (CLK).

The output signals of each of the stages are scan signals applied to the gate lines of the display device, and also serve as carry signals to be transferred to the previous stage and the next stage.

Fig. 1 is an exemplary diagram showing a circuit configuration of each stage of a conventional shift register.

Each of the conventional stages includes a pull-up transistor (PU) for outputting an output signal capable of turning on a switching transistor formed in each pixel of the panel, as shown in Fig. 1, and an output signal And a pull-down transistor PD for outputting the pull-down transistor PD.

That is, the output signal output from the stage is transferred to one gate line, turning on or off the switching transistor connected to the gate line, and is also referred to as a scan signal.

The scan signal again includes a pull-up signal for turning on the switching transistor and a pull-down signal for turning off the switching transistor. Here, the pull-up signal is expressed in a pulse form.

The pull-up signal is output during one horizontal period during which the data voltage is applied to the panel during one vertical period, and the pull-down signal is transmitted to the gate line during most of the remaining vertical periods.

On the other hand, in each stage of a general gate driver, the pull-down signal is transmitted to the gate line by using one pull-down transistor PD.

As described above, since the pull-down signal is outputted during most of the one vertical period, when the pull-down transistor is used for a long time, the pull-down transistor PD may be deteriorated. In this case, .

Particularly, in the case of a pulldown transistor (PD) manufactured using oxide, the above-described deterioration phenomenon occurs more severely.

Therefore, in recent years, a gate driver in which two pull-down transistors are alternately driven has been developed.

However, even when two pull-down transistors are alternately used, deterioration may be severely generated in a pull-down transistor made of oxide.

That is, due to various advantages, recently, a pull-down transistor using oxide has been developed. However, since the oxide is weak against deterioration, even if two pull-down transistors made of oxide are alternately used every frame, It is difficult to prevent.

In addition, since the circuit area of a conventional stage composed of two pull-down transistors made of oxide is larger than that of a conventional stage composed of two pull-down transistors made of amorphous, many problems have arisen in the manufacturing process.

SUMMARY OF THE INVENTION The present invention has been proposed in order to solve the above-mentioned problems. It is an object of the present invention to provide a pull-up signal driven by a first selection signal for turning on switching transistors formed on a gate line, And outputting a second pull-down signal for turning off the switching transistors by being driven by a second selection signal, and a driving method thereof.

According to an aspect of the present invention, there is provided a display device including pixels formed at intersecting regions of 2n gate lines and data lines, and each pixel corresponding to the gate line has a switching transistor panel; A gate driver including stages for turning on or off switching transistors formed in each of the gate lines; And a display driver for controlling the gate driver, wherein each of the stages is driven by a first selection signal transmitted from the display driver, so that the switching transistors formed in the gate line corresponding to the stage A first driver for outputting the pull-up signal for turning on the first transistor and the first pull-down signal for turning off the switching transistors; And a second driver driven by a second selection signal transmitted from the display driver to output a second pull-down signal for turning off the switching transistors.

According to another aspect of the present invention, there is provided a method of driving a display device, including: driving a first stage of a 2 < th > gate line, Transferring a first selection signal from the (n + 1) th gate line to the stages connected to the second n gate line from the (n + 1) th gate line; Each of the stages receiving the first selection signal includes a pull-up signal for turning on switching transistors formed in a gate line corresponding to the stage, and a pull-up signal for turning off the switching transistors And outputting a second pull-down signal for turning off the switching transistors formed in the gate line corresponding to the stage, each of the stages receiving the second selection signal; And transfers the second selection signal from the first gate line to the stages connected to the n-th gate line in the remaining half frame period, and from the (n + 1) -th gate line to the second n-gate line Transmitting the first selection signal to the stages; And each of the stages receiving the first selection signal outputs the pull-up signal and the first pull-down signal to a gate line corresponding to the stage in the remaining half frame period, Each of the stages receiving the second pulldown signal outputting the second pull down signal to a gate line corresponding to the stage.

According to the present invention, since the two pull-down transistors provided in one stage are alternately driven every 1/2 frame, deterioration of the pull-down transistors can be prevented.

Further, according to the present invention, since the application time of the clock CLK, which occupies most of the power consumption, is reduced to half, the power consumption can also be reduced.

1 is an exemplary view showing a circuit configuration of each stage of a conventional shift register.
2 is an exemplary view showing a configuration of a display device according to the present invention;
3 is a circuit diagram of an embodiment of a stage applied to a display device according to the first embodiment of the present invention.
4 is an exemplary view showing a connection relationship between gate lines and stages applied to the method of driving a display device according to the first embodiment of the present invention;
FIG. 5 is an exemplary view showing a connection relationship between gate lines and stages applied to a display device driving method according to a second embodiment of the present invention; FIG.
6 to 11 are diagrams for explaining a method of operating a stage applied to a display device according to the first embodiment of the present invention;
12 is a circuit diagram of an embodiment of a stage applied to a display device according to a second embodiment of the present invention.
13 to 18 are diagrams for explaining a method of operating a stage applied to a display device according to a second embodiment of the present invention;

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention can be applied to various kinds of display devices using a panel composed of a switching transistor turned on by a scan signal supplied through a gate line. However, in the following, for convenience of explanation, a liquid crystal display device is described as an example of the present invention.

2 is an exemplary view showing a configuration of a display device according to the present invention.

A display device according to the present invention includes a panel 100 (hereinafter referred to as a TFT) in which a data line DL and gate lines GL intersect and a switching transistor formed of a thin film transistor A gate driver 200a and 200b including stages 210a and 210b for turning on or off switching transistors formed on the gate lines and data lines DL of the panel 100, And a display driver 300 for supplying the data voltage OUTPUT to the gate drivers 200a and 200b and controlling the gate drivers 200a and 200b.

First, the panel 100 may be manufactured in various forms. When the panel 100 is a liquid crystal panel, the panel 100 is composed of two glass substrates, and liquid crystal is injected between the two glass substrates. Pixels are formed at the intersections of the data lines DL and the gate lines GL formed on the panel 100. [ The switching transistor TFT provided in each pixel supplies the data voltage applied from the display driver to the pixel electrode provided in each pixel in response to a pull-up signal applied from the gate drivers 200a and 200b.

As shown in FIG. 2, in the panel 100, a display region A in which an image is output is divided into a plurality of gate lines GL1 to GL2n and m data lines DL1 to DLm Pixels are formed, and a switching transistor is formed in each of the pixels corresponding to the gate line. The display driver 300 and the gate drivers 200a and 200b may be formed in the non-display area B of the panel 100 in which no image is output.

Next, the display driver 300 receives a driving voltage from an external system such as a personal computer or a television, and receives a timing signal and input image data from the external system. The gate driving units 200a and 200b may be formed on the display driving unit 300 or separately from the display driving unit 300 as shown in FIG. The data driver for outputting the data voltage to the data lines may be formed separately from the display driver 300, but may be formed within the display driver 300, as shown in FIG.

In the following description, a display device in which the data driver is included in the display driver 300 and the gate drivers 200a and 200b are independent of the display driver 300 will be described as an example of the present invention , But the present invention is not limited thereto.

The display driver 300 aligns input image data of red (R), green (G), and blue (B) transmitted from the external system to the panel, and supplies the aligned image data to the data driver do. The data driver supplies a data voltage to each of the data lines in response to a pull-up signal output from the gate driver 200.

The display driver 300 generates the dot clock Dclk and various gate control signals using the horizontal / vertical synchronization signals (timing signals) input from the external system to control the gate drivers 200a and 200b .

The gate control signal includes a first selection signal Vselect1, a second selection signal Vseclet2, a gate start signal (Vselect2), and a second selection signal Vselect2 supplied to the respective stages 210a and 210b constituting the gate drivers 200a and 200b Vst and a reset signal Vrst. The function of each of the above signals will be described below in detail with reference to Figs. 6 to 18.

Lastly, the gate drivers 200a and 200b include a shift register that sequentially generates the pull-up signal in response to a gate start signal Vst input from the display driver 300, As shown in FIG. 2, a plurality of stages 210a and 210b are included.

The gate driving units 200a and 200b may be formed in the display driving unit 300 or may be formed on the panel separately from the display driving unit 300 as described above.

The gate drivers 200a and 200b may be formed on only one of the non-display areas of the panel 100, but may be formed on the two non-display areas facing each other, as shown in FIG.

The stages 210a and 210b provided in the gate drivers 200a and 200b for transmitting a pull-up signal and a pull-down signal to the respective gate lines are connected to two non- And may be connected to the gate lines through one non-display region.

A circuit diagram of one embodiment of the stages 210a and 210b constituting the gate drivers 200a and 200b is shown in FIG.

FIG. 3 is a circuit diagram of a stage applied to a display device according to the first embodiment of the present invention, and is an example of a circuit configuration of each stage 210a and 210b shown in FIG. 2. Referring to FIG.

Each of the stages 210a and 210b applied to the first embodiment of the present invention is driven by a first selection signal Vselect1 transmitted from the display driver 300, A first driver 211 for outputting the pull-up signal for turning on the switching transistors formed on the gate line corresponding to the stage and the first pull-down signal for turning off the switching transistors, And a second driving unit 212 driven by a second selection signal Vselect2 transmitted from the second switching unit 210 to output a second pull-down signal for turning off the switching transistors.

The first driver 211 includes a first transistor T1 through a fifth transistor T5, a pull-up transistor PU and a first pull-down transistor PD1.

The first transistor T1 is connected between a node connected to the first selection signal terminal to which the first selection signal is supplied and a node connected to the gate terminal of the fifth transistor T5 and the gate terminal of the pull- And a gate terminal of the first transistor T1 is connected to a start signal terminal to which the gate start signal is supplied.

The second transistor T2 is connected between the node connected to the first selection signal terminal to which the first selection signal is supplied and the node connected to the gate terminal of the third transistor and the gate terminal of the first pull- And a gate terminal of the first transistor is connected to the first selection signal terminal.

The third transistor T3 is connected between the first transistor T1 and a low-level driving voltage terminal to which a low-level driving voltage VSS is supplied. The gate terminal of the third transistor T3 is connected to the first pull- And is connected to the gate terminal of the transistor PD1.

The fourth transistor T4 is connected between the gate terminals of the third transistor and the first pull-down transistor PD1 and the low-level driving voltage terminal, and the gate terminal of the fourth transistor T4 is connected to the pull- And is connected to the gate terminal of the transistor PU.

The fifth transistor T5 is connected between the low level driving voltage terminal and the first transistor T1 and the gate terminal of the fifth transistor T5 is connected to the reset signal terminal .

The pull-up transistor PU is connected between the clock terminal to which the clock signal CLK is supplied and the first pull-down transistor PD1, and the gate terminal of the pull-up transistor P is connected to the first transistor.

The first pull-down transistor PD1 is connected to the pull-up transistor PU and the low-level driving voltage terminal, and the gate terminal of the first pull-down transistor PD1 is connected to the gate terminal of the third transistor.

An output node between the pull-up transistor PU and the first pull-down transistor PD1 is connected to the gate line. The output node includes a pull-up signal output from the pull-up transistor PU, a first pull-down signal output from the first pull-down transistor PD1, and a second pull-down transistor PD2 included in the second driver 212, The second pull-down signal outputted from the second pull-down signal is outputted.

The second driver 212 includes a sixth transistor T6, a seventh transistor T7 and a second pull-down transistor PD2.

The sixth transistor T6 is connected between a gate terminal of the third transistor T6 and a node connected to a gate terminal of the first pull-down transistor PD1 and the low-level driving voltage terminal, Is connected to a second selection signal terminal to which the second selection signal Vselect2 is supplied.

The seventh transistor T7 is connected between the gate terminal of the first transistor T7 and the node connected to the gate terminal of the pull-up transistor PU and the low-level driving voltage terminal, Is connected to the second selection signal terminal.

The second pull-down transistor PD2 is connected between the output terminal and the low-potential driving voltage terminal, and the gate terminal of the second pull-down transistor PD2 is connected to the second selection signal terminal.

The display driver 300 transmits the first selection signal to the stage during the 1/2 frame period, and drives the first driver 211. The first driving unit 211 outputs the pull-up signal to the gate line, and outputs the first pull-down signal to the gate line during a period other than a period during which the pull-up signal is output during the half frame period.

The display driver 300 transmits the second selection signal to the stage during the remaining half frame period to drive the second driver 212. [ The second driver 212 outputs the second pull-down signal to the gate line during the remaining half frame period.

4 is an exemplary view showing a connection relationship between gate lines and stages applied to the method of driving a display device according to the first embodiment of the present invention.

4, the first group stages LS1 to LSn of the stages 210a and 210b are arranged in the same direction as the first group stages LS1 to LSn of the panel 100, Side non-display region (B), and the second group stages (RS1 to RSn) of the stages are formed in a second side non-display region facing the first side non-display region.

The display driver 300 sequentially applies the first selection signal Vselect1 to the stages connected to the nth gate line GLn from the first gate line GL1 among the gate lines during the 1/2 frame period, And transmits the second selection signal Vselect2 to the stages GL2n connected from the (n + 1) -th gate line GLn + 1 to the second n-gate line. The display driver 300 transmits the second selection signal Vselect2 to the stages connected to the nth gate line GLn from the first gate line GL1 during the remaining half frame period And transmits the first selection signal Vselect1 to the stages connected to the second n gate line GL2n from the (n + 1) th gate line GLn + 1.

In this case, when the 1/2 frame period starts, the display driver 300 sequentially outputs the first stage SL1 and the second group stages RS1 to RSn (RS1 to RSn) of the first group stages LS1 to LSn (N / 2) +1) stages (LS) of the first group stages at the start of the remaining half frame period, and transmits the gate start signal Vst to the first stage RS1 of the first group stages (n / 2 + 1)) of the first group stages and the gate start signal Vst to the (n / 2) +1 stage (RS (n / 2 + 1)) of the second group stages.

That is, in the 1/2 frame period, the display driver 300 is connected to the nth gate line GLn from the first gate line GL1 of the 2n gate lines formed in the panel 100 And the stages LS connected to the second n gate lines GL2n from the (n + 1) -th gate line GLn + 1 to the stages LS1 to RS (n / 2) (n / 2 + 1)).

Each of the stages receiving the first selection signal includes a pull-up signal for turning on the switching transistors formed in the gate line corresponding to the stage, and a pull-up signal for turning on the switching transistors And each of the stages receiving the second selection signal outputs a second pull down signal for turning off the switching transistors formed in the gate line corresponding to the stage.

Further, in the remaining half frame period, the display driver 300 transmits the second selection signal to the stages connected to the n < th > gate line from the first gate line, And transfers the first selection signal from the gate line to the stages connected to the second n gate line.

In each of the remaining 1/2 frame periods, each of the stages receiving the first selection signal outputs the pull-up signal and the first pull-down signal to a gate line corresponding to the stage, Each of the received stages outputs the second pull-down signal to a gate line corresponding to the stage.

That is, in the first embodiment of the present invention as described above, each stage receives the first selection signal and supplies the pull-up transistor PU and the first pull-down transistor PD1 ), And outputs the pull-up signal and the first pull-down signal. In the remaining half frame period, the second select signal is received and the second pull down transistor PD2 is driven to output the second pull down signal.

The driving method of each stage according to the first embodiment as described above will be described with reference to Figs. 6 to 11. Fig.

5 is an exemplary view showing a connection relationship between gate lines and stages applied to the method of driving a display device according to the second embodiment of the present invention.

5, the first group stages LS1 to LSn of the stages 210a and 210b are arranged in the same direction as the first group stages LS1 to LSn of the panel 100, Side non-display region (B), and the second group stages (RS1 to RSn) of the stages are formed in a second side non-display region facing the first side non-display region.

The first group stages of the stages are formed in a first side non-display region of the panel 100 and are connected to odd gate lines, and the second group stages of the stages are connected to the first side non- And the second side non-display region facing the even-numbered gate lines.

The display driver 300 transmits the first selection signal to the first group stages and the second selection signal to the second group stages in a half frame period, In the two-frame period, the second select signal is transmitted to the first group stages, and the first select signal is transmitted to the second group stages. The display driver 300 transmits the gate start signal to the first one of the first group stages when the remaining half frame period starts, and when the remaining half frame period starts, And transmits the gate start signal to the first one of the group stages.

That is, when the half frame period starts, the display driver 300 sequentially applies the first group stages, which are formed in the first non-display region of the panel 100 and connected to the odd gate lines, 1 select signal and transmits the second selection signal to the second group stages formed in the second side non-display region facing the first side non-display region and connected to the even gate lines.

Wherein each of the first group stages receiving the first selection signal comprises a pull-up signal for turning on the switching transistors formed in the gate line corresponding to the stage, Down signal for turning off the switching transistors formed on the gate line corresponding to the stage, the second pull-down signal for turning off the switching transistors, and the second group stage for receiving the second selection signal, .

The display driver 300 transmits the second selection signal to the first group stages and transmits the first selection signal to the second group stages in the remaining half frame period.

Each of the second group stages receiving the first selection signal in the 1/2 frame period includes a pull-up signal for turning on switching transistors formed in a gate line corresponding to the stage, Down signal for turning off the switching transistors formed in the gate line corresponding to the stage, the first pull-down signal for turning off the first pull- .

In other words, in the first embodiment of the present invention shown in FIG. 4, the stages connected to the gate lines formed at the upper end of the panel 100 are sequentially driven in a half frame period, In the two-frame period, the stages connected to the gate lines formed at the lower end of the panel 100 are sequentially driven.

However, in the second embodiment of the present invention shown in FIG. 5, the first group stages connected to the odd gate lines formed in the panel 100 are sequentially driven in a half frame period, During the remaining half frame period, the second group stages connected to the even gate lines formed in the panel 100 are sequentially driven.

On the other hand, although not shown in the drawings, the display device driving method according to the third embodiment of the present invention can be executed in a state in which the stages are all formed in either one of the non-display areas. That is, the display device driving method according to the third embodiment of the present invention is driven in a state in which all the stages are sequentially connected to the respective gate lines in one of the non-display areas.

In this case, in the 1/2 frame period, the display driver 300 transmits the first selection signal to the stages connected to the n-th gate line from the first gate line among the gate lines, the second select signal is transmitted to the stages connected to the second n gate line from the (n + 1) th gate line, and the second select signal is transmitted to the stages connected to the nth gate line from the first gate line, To the stages connected to the second n-gate line from the (n + 1) -th gate line, and transmits the first selection signal.

That is, each of the stages includes a pull-up signal driven by a first select signal to turn on switching transistors formed in each of the 2n gate lines formed in the panel, and a pull-up signal for turning on the switching transistors And outputs a second pull-down signal for driving the switching transistors to be turned off by the second selection signal.

The third embodiment of the present invention as described above can be applied to a display according to the second embodiment or the second embodiment of the present invention as described above except that the stages are formed in either one non- And is driven in a similar manner to the device driving method.

In order to perform the method of driving the display device according to the first to third embodiments of the present invention as described above, a specific operation method of the stages 210a and 210b driven according to the first selection signal and the second selection signal Will be described in detail with reference to Figs. 6 to 18. Fig. That is, the display device driving method according to the first to third embodiments of the present invention can be implemented in the display device according to the first embodiment of the present invention shown in Fig.

6 to 11 are diagrams for explaining a method of operating a stage applied to a display device according to the first embodiment of the present invention. 6 to 11, the node Q is connected to the gate terminal of the pull-up transistor PU, and the node Qb is connected to the gate terminal of the first pull-down transistor PD1.

Referring to FIG. 6, when a half frame starts, a first selection signal Vselect1 of a high level, a second selection signal Vselect2 of a low level, a gate start signal Vst of a low level, The reset signal Vrst is input to the stage.

The third transistor T3 is turned on by the first selection signal and the low potential driving voltage VSS is supplied to the gate terminal of the pull-up transistor PU. Therefore, the pull-up transistor PU is turned off.

The second transistor and the first pull-down transistor PD1 are turned on by the first selection signal of the high level. When the first pull-down transistor PD1 is turned on, the low-level driving voltage VSS is induced to the first pull-down transistor PD1 and the first pull-down signal Vg_out having a low level (low level) Is output. The first pull-down signal is supplied to a gate line connected to the stage to turn off the switching transistors connected to the gate line.

Referring to FIG. 7, after a half frame starts, a high-level gate start signal Vst is sequentially input to the stages.

When the high level gate start signal Vst is input, the first transistor and the pull-up transistor PU are turned on. When the pull-up transistor PU starts the turn-on process, a high level voltage is charged to the gate terminal of the pull-up transistor PU.

The high level signal induced to the fourth transistor T4 through the first transistor T1 turns on the fourth transistor T4. Accordingly, the low-level driving voltage VSS is induced by the first pull-down transistor and the first pull-down transistor PD1 is turned off. In this case, the size of the second transistor T2 is much smaller than that of the third transistor T3 or the first pull-down transistor PD1, so that the circuit does not operate because its influence on the circuit is very small. That is, since the second transistor T2 is always turned on, the Qb node does not exactly fall to VSS but is voltage-divided by the second transistor T2 and has a voltage slightly higher than VSS. However, since it is close to Low, no current flows. Therefore, the second transistor T2 operates only during a period in which Qb becomes High.

8, when the gate start signal Vst is changed to a low level, the pull-up transistor PU is turned on by the high level signal charged in the gate terminal of the pull-up transistor PU. At this time, a high-level clock CLK is output to the output terminal through the pull-up transistor PU. Therefore, a pull-up signal Vg_out of a high level is outputted to the gate line to turn on the switching transistors connected to the gate line.

At this time, the first pull-down transistor PD1 is maintained in a turned off state by the low-level driving voltage VSS induced through the fourth transistor T4.

Next, referring to FIG. 9, a high level reset signal Vrst is input.

The fifth transistor T5 is turned on by the high level reset signal and the low level driving voltage VSS is supplied to the gate terminal of the pull-up transistor PU. Also, a low-level driving voltage VSS is supplied to the gate terminal of the pull-up transistor PU through the third transistor. Therefore, the pull-up transistor PU is turned off, and the pull-up signal of the high level is no longer issued.

The first pull-down transistor PD1 is turned on since a high level signal is supplied through the second transistor T2. Accordingly, a first pull-down signal Vg_out of a low level is output to the output terminal by the low-level driving voltage VSS, thereby turning off the switching transistors connected to the gate line.

Next, referring to FIG. 10, the processes described in FIG. 9 are continued.

Accordingly, the first pull-down transistor PD1 is turned on by the first select signal Vselect and the first pull-down signal Vg_out of the low level is continuously outputted through the first pull-down transistor PD1.

In this case, since the reset signal Vrst is converted to a low level, the fifth transistor T5 is turned off.

11, when the remaining half frame is started, the first selection signal Vselect1 is changed to a low level and the second selection signal Vselect2 is changed to a high level.

The sixth transistor T6 and the seventh transistor T7 are turned on by the second selection signal Vselect2 so that a low potential driving voltage VSS is applied to the pull-up transistor PU and the first pull- Is supplied to the gate terminal of the PD1. Therefore, the pull-up transistor PU and the first pull-down transistor PD1 are turned off.

The second pull-down transistor PD2 is turned on by the second selection signal Vselect2 and the low potential driving voltage VSS is supplied to the second pull-down transistor PD2. Accordingly, the second pull-down signal Vg_out of a low level is output to the output terminal through the second pull-down transistor PD2 by the low-level driving voltage VSS, and the switching transistors connected to the gate line turn Off.

The method of driving the display device according to the first to third embodiments of the present invention as described above may be executed in the display device according to the second embodiment of the present invention shown in Fig. The operation method of the display device according to the second embodiment of the present invention shown in Fig. 12 will be described in detail with reference to Figs. 13 to 18. Fig.

FIG. 12 is a circuit diagram of a stage applied to a display device according to a second embodiment of the present invention, and is an example of a circuit configuration of each of the stages 210a and 210b shown in FIG. 2. Referring to FIG. 13 to 18 are diagrams for explaining a method of operating a stage applied to a display device according to a second embodiment of the present invention.

Each of the stages 210a and 210b applied to the second embodiment of the present invention is driven by the first selection signal Vselect1 transmitted from the display driver 300, A first driver 211 for outputting the pull-up signal for turning on the switching transistors formed in the gate line corresponding to the stage and the first pull-down signal for turning off the switching transistors, And a second driving unit 212 driven by a second selection signal Vselect2 transmitted from the second switching unit 210 to output a second pull-down signal for turning off the switching transistors.

The first driver 211 includes a first transistor T1 through a fifth transistor T5, a pull-up transistor PU and a first pull-down transistor PD1. The configuration of the first driving unit 211 is the same as that of the first driving unit applied to the first embodiment, and a detailed description thereof will be omitted.

The second driver 212 includes a sixth transistor T6 and a second pull-down transistor PD2.

The sixth transistor T6 is connected between a gate terminal of the pull-up transistor PU and a gate terminal of the first pull-down transistor PD1, And is connected to the second selection signal terminal.

The second pull-down transistor PD2 is connected between the output terminal and the low-potential driving voltage terminal, and the gate terminal of the second pull-down transistor PD2 is connected to the second selection signal terminal.

The display driver 300 transmits the first selection signal to the stage during the 1/2 frame period, and drives the first driver 211. The first driving unit 211 outputs the pull-up signal to the gate line, and outputs the first pull-down signal to the gate line during a period other than a period during which the pull-up signal is output during the half frame period.

The display driver 300 transmits the second selection signal to the stage during the remaining half frame period to drive the second driver 212. [ The second driver 212 outputs the second pull-down signal to the gate line during the remaining half frame period.

The driving method of the stage applied to the second embodiment of the present invention as described above will now be described with reference to FIGS. 13 to 18. FIG.

Referring to FIG. 13, when a half frame starts, a first selection signal Vselect1 of a high level, a second selection signal Vselect2 of a low level, a gate start signal Vst of a low level, The reset signal Vrst is input to the stage.

The third transistor T3 is turned on by the first selection signal and the low potential driving voltage VSS is supplied to the gate terminal of the pull-up transistor PU. Therefore, the pull-up transistor PU is turned off.

The second transistor and the first pull-down transistor PD1 are turned on by the first selection signal of the high level. When the first pull-down transistor PD1 is turned on, a low-level driving voltage VSS is induced to the first pull-down transistor PD1 and a first pull-down signal Vg_oug having a low level (low level) Is output. The first pull-down signal is supplied to a gate line connected to the stage to turn off the switching transistors connected to the gate line.

Referring to FIG. 14, after a half frame starts, a high-level gate start signal Vst is sequentially input to the stages.

When the high level gate start signal Vst is input, the first transistor and the pull-up transistor PU are turned on. When the pull-up transistor PU starts the turn-on process, a high level voltage is charged to the gate terminal of the pull-up transistor PU.

The high level signal induced to the fourth transistor T4 through the first transistor T1 turns on the fourth transistor T4. Accordingly, the low-level driving voltage VSS is induced by the first pull-down transistor and the first pull-down transistor PD1 is turned off. The high level signal induced through the second transistor T2 is discharged through the fourth transistor T4.

15, when the gate start signal Vst is changed to a low level, the pull-up transistor PU is turned on by the high level signal charged in the gate terminal of the pull-up transistor PU. At this time, a high-level clock CLK is output to the output terminal through the pull-up transistor PU. Therefore, a pull-up signal Vg_out of a high level is outputted to the gate line to turn on the switching transistors connected to the gate line.

At this time, the first pull-down transistor PD1 is maintained in a turned off state by the low-level driving voltage VSS induced through the fourth transistor T4.

16, a high level reset signal Vrst is input.

The fifth transistor T5 is turned on by the high level reset signal and the low level driving voltage VSS is supplied to the gate terminal of the pull-up transistor PU. Also, a low-level driving voltage VSS is supplied to the gate terminal of the pull-up transistor PU through the third transistor. Therefore, the pull-up transistor PU is turned off, and the pull-up signal of the high level is no longer issued.

The first pull-down transistor PD1 is turned on since a high level signal is supplied through the second transistor T2. Accordingly, a first pull-down signal Vg_out of a low level is output to the output terminal by the low-level driving voltage VSS, thereby turning off the switching transistors connected to the gate line.

Next, referring to FIG. 17, the processes described in FIG. 16 are continued.

Accordingly, the first pull-down transistor PD1 is turned on by the first select signal Vselect and the first pull-down signal Vg_out of the low level is continuously outputted through the first pull-down transistor PD1.

In this case, since the reset signal Vrst is converted to a low level, the fifth transistor T5 is turned off.

18, when the remaining half frame is started, the first selection signal Vselect1 is changed to a low level and the second selection signal Vselect2 is changed to a high level.

The sixth transistor T6 is turned on by the second selection signal Vselect2 and a low potential driving voltage VSS is supplied to the pull-up transistor PU and the first pull- As shown in FIG. Therefore, the pull-up transistor PU and the first pull-down transistor PD1 are turned off.

The second pull-down transistor PD2 is turned on by the second selection signal Vselect2 and the low potential driving voltage VSS is supplied to the second pull-down transistor PD2. Accordingly, the second pull-down signal Vg_out of a low level is output to the output terminal through the second pull-down transistor PD2 by the low-level driving voltage VSS, and the switching transistors connected to the gate line turn Off.

In this case, the gate and the drain of the third transistor are connected by the sixth transistor T6, and the third transistor T3 operates as a diode. That is, the third transistor operates as a diode when Vgd = 0 and operates in an On state when Vgs> Vth and in an OFF state when Vgs≤0. Therefore, until the voltage of the Qb node becomes the threshold voltage of the third transistor T3, the third transistor T3 maintains the On state and flows the current, so that the Qb node also falls to Low.

The present invention as described above is intended to improve the reliability of a panel using an oxide semiconductor.

That is, while the panel 100 is divided into two and the pull-up signal is supplied to the first region, the second pull-down transistor for turning off the switching transistor through the second pull- A signal is supplied to the gate line.

Further, while the pull-up signal is supplied to the second region, the second pull-down signal VSS is supplied to the gate line through the added second pull-down transistor (Pull-Down TR) in the first region.

That is, in the present invention, in each of the stages connected to the gate lines formed in the divided two regions of the panel, two pull-down transistors are alternately driven.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: panels 210a, 210b:
200a, 200b: Gate driver 300: Display driver

Claims (10)

A pixel is formed at every intersection of the 2n gate lines and the data lines, and a switching transistor is formed in each of the pixels corresponding to the gate line;
A gate driver including stages for turning on or off switching transistors formed in each of the gate lines; And
And a display driver for controlling the gate driver,
Each of the stages includes:
A first pull-down signal driven by a first selection signal transmitted from the display driver to turn on the switching transistors formed on a gate line corresponding to the stage, and a second pull- A first driving unit for outputting a driving signal; And
And a second driver driven by a second selection signal transmitted from the display driver to output a second pull-down signal for turning off the switching transistors. The method according to claim 1,
The display driver may include:
And transmits the first selection signal to the stage in a 1/2 frame period,
And transmits the second selection signal to the stage in the remaining half frame period. The method according to claim 1,
Wherein the first group stages of the stages are formed in a first side non-display region of the panel, and the second group stages of the stages are arranged in a second side non- Lt; / RTI >
The display driver may include:
In the 1/2 frame period, the first selection signal is transmitted from the first gate line to the nth gate line, and the second selection signal is transmitted from the (n + 1) And transmits the second selection signal to the connected stages,
And transfers the second selection signal from the first gate line to the stages connected to the nth gate line during the remaining 1/2 frame period and is connected to the second n gate line from the (n + 1) And transmits the first selection signal to the stages having the first selection signal. The method of claim 3,
The display driver may include:
When the 1/2 frame period begins, transmits a gate start signal to a first one of the first group stages and to a first one of the second group stages,
(N / 2) +1) stage of the first group stages and a (n / 2) +1 stage of the second group stages at the start of the remaining half frame period, And transmits a start signal. The method according to claim 1,
Wherein the first group stages of the stages are formed in a first side non-display region of the panel and are connected to odd gate lines, and the second group stages of the stages face the first side non- Numbered gate lines connected to the even-numbered gate lines,
The display driver may include:
In the 1/2 frame period, transmitting the first selection signal to the first group stages, transmitting the second selection signal to the second group stages,
And transmits the second selection signal to the first group stages and transmits the first selection signal to the second group stages in the remaining 1/2 frame period. 6. The method of claim 5,
The display driver may include:
When the 1/2 frame period begins, transmits a gate start signal to a first one of the first group stages,
And transmits the gate start signal to the first one of the first group stages when the remaining half frame period starts. The method according to claim 1,
The display driver may include:
In the 1/2 frame period, the first selection signal is transmitted from the first gate line to the nth gate line, and the second selection signal is transmitted from the (n + 1) And transmits the second selection signal to the connected stages,
And transfers the second selection signal from the first gate line to the stages connected to the nth gate line during the remaining 1/2 frame period and is connected to the second n gate line from the (n + 1) And transmits the first selection signal to the stages having the first selection signal. In the 1/2 frame period, the first selection signal is transmitted from the first gate line to the stages connected to the n-th gate line among the 2 < n > gate lines formed in the panel, Transmitting a second selection signal to stages coupled to a second n gate line;
Each of the stages receiving the first selection signal includes a pull-up signal for turning on switching transistors formed in a gate line corresponding to the stage, and a pull-up signal for turning off the switching transistors And outputting a second pull-down signal for turning off the switching transistors formed in the gate line corresponding to the stage, each of the stages receiving the second selection signal;
And transfers the second selection signal from the first gate line to the stages connected to the n-th gate line in the remaining half frame period, and from the (n + 1) -th gate line to the second n-gate line Transmitting the first selection signal to the stages; And
Each of the stages receiving the first selection signal outputs the pull-up signal and the first pull-down signal to a gate line corresponding to the stage in the remaining half frame period, And each of the received stages outputs the second pull down signal to a gate line corresponding to the stage. In the first frame period, the first selection signal is transmitted to the first group stages formed in the first non-display region of the panel and connected to the odd gate lines, Transmitting the second selection signal to the second group stages formed in the second side non-display area to be connected and connected to the even gate lines;
Each of the first group stages receiving the first selection signal includes a pull-up signal for turning on switching transistors formed in a gate line corresponding to the stage, and a pull-up signal for turning on the switching transistors, Down signal for turning off the switching transistors formed on the gate line corresponding to the stage, the second pull-down signal for turning off the switching transistors, and the second group stage for receiving the second selection signal, ;
Transmitting the second selection signal to the first group stages and transmitting the first selection signal to the second group stages in the remaining 1/2 frame period; And
Each of the second group stages receiving the first selection signal includes a pull-up signal for turning on the switching transistors formed in the gate line corresponding to the stage, and a pull- Down signal for turning off the switching transistors formed in the gate line corresponding to the stage, the first pull-down signal for turning off the first pull- And outputting the output signal. A step of outputting a pull-up signal driven by the first selection signal to turn on the switching transistors formed in each of the 2n gate lines formed on the panel and a first pull-down signal to turn off the switching transistors, ; And
And outputting a second pull-down signal driven by a second selection signal to turn off the switching transistors.

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