KR102206374B1 - Orgaiic Light Emittiig Diode - Google Patents

Abstract

In the display device of the present invention, the gate driving unit is a Q node control unit, an output control unit that outputs a clock signal to the output terminal, and an odd QB node control unit that controls the odd QB node connected to the output control unit so that the output control unit discharges the potential of the output terminal during a first period. , An excellent QB node control unit that controls an excellent QB node connected to the output control unit so that the output control unit discharges the potential of the output terminal during the second period, and provides a recovery voltage of negative potential to the excellent QB node during the first period. And a low potential holding unit that provides the recovery voltage to the odd QB node during a second period, and during a third period in which the odd QB node is discharged to a low potential voltage, the low potential holding unit is less than the low potential voltage to the superior QB node. During the fourth period in which the low recovery voltage is provided and the superior QB node is discharged to the low potential voltage, the low potential holding unit provides the recovery voltage to the odd QB node.

Description

Organic light emitting diode display device {Orgaiic Light Emittiig Diode}

The present invention relates to an organic light emitting diode display.

Flat panel displays (FPDs) are widely used not only for desktop computer monitors, but also for portable computers such as notebook computers and PDAs, or mobile phone terminals due to their advantages in miniaturization and weight reduction. Such a flat panel display includes a liquid crystal display; LCD), Plasma Display Paiel (PDP), Field Emissioi Display; FED) and Organic Light Emittiig Diode Display (hereinafter, OLED).

In a display device, a gate driver that generates a gate pulse as a scan signal may be implemented in the form of a gate-in-panel (GIP) formed of a combination of thin film transistors in a bezel region that is a non-display region in the display panel.

The GIP-type gate driver outputs the gate pulse in a manner that controls the Q node for controlling the output timing of the gate pulse and the QB node for discharging the output terminal. In one frame period, the scan period in which the gate pulses are output is very short, and the period in which the gate pulses other than the scan period are not output is relatively very long. In order to block the output of the gate pulse, a method of charging the QB node and discharging the output terminal based on this is used. That is, the QB node is charged for a long time in one frame period, and thus, transistors connected to the QB node are subjected to severe bias stress. Accordingly, the threshold voltage Vth of the transistors connected to the QB node increases, and characteristics of the transistors deteriorate.

The present invention for solving the problems of the above-described background technology is to improve the characteristics of the transistors of the gate driver are deteriorated due to bias stress.

As a means of solving the above problems, the display device of the present invention includes a display panel having a gate line formed thereon, and a gate driver outputting a gate pulse provided to the gate line. The gate driver is a Q node control unit that controls the Q node that determines the timing of outputting the clock signal, an output control unit that outputs a clock signal to the output terminal in response to the high level potential of the Q node, and the output control unit adjusts the potential of the output terminal during the first period. An odd QB node control unit that controls the odd QB node connected to the output control unit to discharge, an excellent QB node control unit that controls the excellent QB node connected to the output control unit so that the output control unit discharges the potential of the output terminal during a second period, and a first period And a low potential holding unit that provides a recovery voltage of a negative potential to an even QB node during a second period, and provides the recovery voltage to an odd QB node during a second period, wherein the odd QB node is discharged to a low potential voltage. For 3 periods, the low potential holding unit provides a recovery voltage lower than the low potential voltage to the superior QB node, and during the fourth period when the superior QB node is discharged to the low potential voltage, the low potential holding unit provides the recovery voltage to the odd QB node. do.

In the present invention, the QB node of the gate driver is alternately driven by an odd QB node and an excellent QB node, and the non-driving QB node maintains a negative potential to recover the threshold voltage characteristics of the transistors connected to the QB node. Let it.

Since the present invention maintains different levels of the low potential voltage by dividing the driving period and the recovery period, it is possible to reduce power consumption during the driving period, and quickly recover the deviation of the threshold voltage during the recovery period.

In addition, the present invention can prevent a short-circuit phenomenon between the recovery voltage having a negative potential and the low potential voltage during the recovery period, thereby preventing the low potential voltage or the recovery voltage from shaking.

1 is a diagram showing a configuration of a display device according to the present invention.
FIG. 2 is a diagram showing an example of the pixel structure shown in FIG. 1;
3 is a block diagram showing a dependency relationship between stages of a gate driver.
4 is a circuit diagram of an ith stage according to the first embodiment.
5 and 6 are operation timing diagrams of the stage.
7 is a diagram showing a relationship between a bias stress and a threshold voltage deviation.
8 is a circuit diagram of an ith stage according to the second embodiment.
9 is a diagram showing a short-circuit phenomenon in a non-operation section.
10 is a circuit diagram of an ith stage according to the third embodiment.
11 is a circuit diagram of an i-th stage according to the fourth embodiment.

Hereinafter, exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings. The same reference numbers throughout the specification mean substantially the same elements. In the following description, when it is determined that detailed descriptions of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted.

1 is a block diagram showing the configuration of a display device according to the present invention.

Referring to FIG. 1, a display device according to the present invention includes a display panel 100, a timing controller T110, a data driver 120, and a gate driver 130 and 140.

The display panel 10 includes a display area 100A in which sub-pixels are formed and a non-display area 100B in which various signal lines or pads are formed outside the display area 100A. The display area 100A includes a plurality of pixels P, and displays an image based on a gray scale displayed by each of the pixels P. A plurality of pixels P are arranged in a matrix form on each of the horizontal lines. Each of the pixels P is connected to the data line portion DL and the gate line portion GL that are orthogonal to each other.

As shown in FIG. 2, one sub-pixel SP is supplied in response to a scan signal supplied through a switching transistor SW and a switching transistor SW connected to the scan line GL1 and the data line DL1. A pixel circuit PC that operates in response to the data signal DATA is included. The sub-pixel SP is implemented as a liquid crystal display panel including a liquid crystal device or an organic light emitting display panel including an organic light emitting device, depending on the configuration of the pixel circuit PC.

The timing controller T110 is a timing signal such as a vertical synchronization signal (Vsyic), a horizontal synchronization signal (Hsyic), a data enable signal (DE), and a dot clock (DLCK) through an LVDS or TMDS interface receiving circuit connected to the image board. It receives input. The timing controller T110 includes a data control signal DDC for controlling the operation timing of the data driver 120 and a gate control signal GDC for controlling the operation timing of the gate drivers 130 and 140 based on the input timing signal. Create

The data driver 120 includes a plurality of source drive ICs (itegrated circuits). The source drive ICs receive digital video data RGB and a source timing control signal DDC from the timing controller 110. The source drive ICs convert digital video data RGB into a gamma voltage in response to a source timing control signal DDC to generate a data voltage, and transmit the data voltage through the data lines DL of the display panel 100. Supply.

The gate drivers 130 and 140 include a level shifter 130 and a shift register 140. In the gate driver 130, the level shifter 130 and the shift register 140 are separated, and the shift register 140 is formed in the non-display area 100B of the display panel 100. Paiel; hereinafter GIP).

The level shifter 130 is formed on a printed circuit board (not shown) connected to the display panel 100 in the form of an IC. The level shifter 130 level-shifts the clock signals CLK and the start signal VST under the control of the timing controller 11 and supplies them to the shift register 140. The shift register 140 is formed by a combination of a plurality of thin film transistors (hereinafter, TFT) in the non-display area 100B of the display panel 100 by the GIP method. The shift register 140 includes stages for shifting and outputting a scan signal in response to the clock signals CLK and the start signal VST.

3 is a schematic configuration diagram for each stage of an embedded gate driver according to a first embodiment of the present invention, and FIG. 4 is a diagram illustrating an i-th stage of the embedded gate driver according to the first embodiment. 5 is a diagram showing waveforms of odd high potential voltage and excellent high potential voltage provided to a gate driver of the present invention.

Referring to FIG. 3, an embodiment of the shift register 140 of the gate drivers 130 and 140 will be described as follows. The shift register 140 includes m stages corresponding to m gate lines on a one-to-one basis, and each stage is connected dependently. 3 is an i-th stage STG[i] to STG[i+2] that outputs a gate pulse provided to an i-th gate line to an (i+2)-th gate line. have. In the following description, the "shearing stage" refers to being positioned above the standard stage. For example, based on the i-th (k is a natural number of 1<k<m) stage STGi, the front stage is one of the first stage ST1 to the k-1th stage ST[i-1]. Instruct. The "rear stage" refers to being located below the standard stage. For example, based on the kth (1<k<m) stage STi, the subsequent stage indicates any one of the i+1th stage ST[i+1] to the mth stage.

The ith stage STGi includes first to eighth terminals 1 to 8. The first terminal 1 receives the start signal VST, and the second terminal 2 receives the reset signal VRST. The third terminal 3 receives the clock signal CLK. The fourth to sixth terminals 4 to 6 are connected to a high potential voltage VDD, an odd high potential voltage VDD_O, and an even high potential voltage VDD_E, respectively. The seventh and eighth terminals 7 and 8 are connected to the low potential voltage VSS and the recovery voltage Vrec, respectively. Hereinafter, in the present specification, the same reference numerals are used for each terminal and the signal input to each terminal in order to simplify the reference numerals.

As shown in FIG. 5, the high potential voltage VDD always maintains a high level voltage. During the odd QB node operation period To, the odd high potential voltage maintains the high potential voltage except for the scan period Ts in which the clock signal CLK is provided to generate the gate pulse. The odd high potential voltage (VDD_O) and the excellent high potential voltage (VDD_E) alternately swing from logic high to logic low or logic low to logic high at a predetermined interval, for example, every few seconds.

The low potential voltage VSS may use the gate low voltage VGL and may have a voltage level of -5V to -6V. The recovery voltage Vrec has a voltage value lower than that of the low potential voltage VSS.

The i-th stage STG[i] is an i-th clock signal line CLK[i], a reset signal line VRST, a start signal line VST, a high potential voltage VDD, and an odd high potential voltage VDD_O. (Or, it operates based on the signal and power supplied through the excellent high potential voltage (VDD_E)), the low potential voltage (VSS), and the recovery voltage (Vrec). The ith stage STG[i] outputs the ith scan signal through its own output terminal Gout.

The plurality of stages STG[i] to STG[i+2] are connected to an output terminal to operate based on a scan signal output through an output terminal of a front stage or an output terminal of a rear stage. For example, the i+1th stage STG[i+1] may be connected to the output terminal Gout of the ith stage STG[i] in order to use the ith scan signal as a start signal of the input terminal. In addition, the i+2th stage STG[i+2] is the output terminal VG_OUT[i+1] of the i+1th stage STG[i+1] to use the i+1th scan signal as a start signal of the input terminal. 1]) can be connected.

In addition, a plurality of stages (STG[i] to STG[i+2]) are the output stages of the rear (next stage) stage (e.g., VG_OUT[i+1]) or the output stage of the rear stage (next stage) stage ( Example: The output terminal and the input terminal are connected to operate based on the scan signal output through the scan signal output from VG_OUT[i+2]). For example, the ith stage STG[i] is the output terminal VG_OUT of the i+2th stage STG[i+2] in order to use the i+2th scan signal as a stabilization signal (or reset signal) of the input terminal. [i+2]) can be connected. In addition, the ith stage STG[i] uses the i+2th scan signal as a stabilization signal (or reset signal) of the input terminal, and the output terminal VG_OUT[i] of the i+2th stage STG[i+2] +2]).

4, the ith stage of the gate driver according to the first embodiment includes scan direction controllers T1 and T3N, node controllers T3R, T3a, T3b, T4a, T5Fa, T5QIa, T5Qa, T3b, T4b, T5Fb. , T5QIb, T5Qb) and output control units T6, T7a, T7b.

The scan direction controllers T1 and T3N set the shift direction for the scan signal of the i-th stage in the forward or reverse direction. The node control unit (T3R, T3a, T4a, T5Fa, T5QIa, T5Qa, T3b, T4b, T5Fb, T5QIb, T5Qb) is the Q node (Q) of the ith stage, the odd QB node (QB_O), and the excellent QB node (QB_E) It serves to charge or discharge. The output control unit (T6, T7a, T7b) outputs a high-level gate pulse through the output terminal (Gout) of the ith stage or discharges the potential of the output terminal (Gout) of the ith stage to a low potential voltage according to the operation of the node controller. do.

A detailed look at the configuration of the ith stage is as follows.

The scan direction controllers T1 and T3N include a first transistor T1 and a third N transistor T3N. In the first transistor T1, a gate electrode is connected to the start signal terminal VST, a first electrode is connected to a high potential voltage source VDD to which a forward voltage is supplied, and a second electrode is connected to the Q node Q. The first transistor T1 charges the Q node Q using the high potential voltage VDD in response to the start signal VST. When the first transistor T1 is turned on, in the ith stage, the shift direction for the scan signal is set to the forward direction.

In the 3N transistor T3N, the gate electrode is connected to the rear signal terminal VNEXT, the first electrode is connected to the low potential voltage source VSS, and the second electrode is connected to the Q node Q. The 3N transistor T3N discharges the Q node Q to the low potential voltage VSS in response to the downstream signal VNEXT. When the 3N transistor T3N is turned on, the i-th stage is set in a reverse direction for the scan signal.

The node control unit includes a Q node control unit, an odd QB node control unit, an even QB node control unit, and a low potential holding unit.

The Q node control units T3R, T3a, and T3b determine the charging timing of the Q node Q. The odd-numbered QB node control units T4a, T5Fa, and T5Qa determine the charging timing of the odd-numbered QB node QB_O. The excellent QB node controllers T4b, T5Fb, and T5Qb determine the charging timing of the excellent QB node QB_E. The low-potential holding units T5QIa and T5QIb provide the recovery voltage Vrec in a period in which the odd QB node QB_O and the superior QB node QB_E do not operate.

In the T3R transistor T3R, the gate electrode is connected to the reset terminal VRST, the first electrode is connected to the low potential power source VSS, and the second electrode is connected to the Q node Q. The T3Rth transistor T3R discharges the Q node Q to the low potential voltage VSS in response to the reset signal supplied through the reset terminal VRST.

In the T3a-th transistor T3a, a gate electrode is connected to an odd QB node QB_O, a first electrode is connected to a low potential power source VSS, and a second electrode is connected to a Q node Q. The T3a-th transistor T3a discharges the power of the Q node Q to the low potential voltage VSS when the odd QB node QB_O is a high-level voltage.

In the T4ath transistor T4a, the gate electrode and the first electrode are connected to the odd high potential voltage source VDD_O, and the second electrode is connected to the odd QB node QB_O. The T4ath transistor T4a charges the odd QB node QB_O when the odd high potential voltage VDD_O of the high level is provided.

In the first odd QB node control transistor T5Fa, the gate electrode is connected to the start signal terminal VST, the first electrode is connected to the low potential power source VSS, and the second electrode is connected to the odd QB node QB_O. The first odd QB node control transistor T5Fa discharges the odd QB node QB_O to the low potential voltage VSS in response to the start signal VST.

The odd low potential holding transistor T5QIa has a gate electrode connected to the excellent high potential voltage source VDD_E, a first electrode connected to the recovery terminal Vrec, and a second electrode connected to the odd QB node QB_O. The odd low potential holding transistor T5QIa discharges the voltage of the odd QB node QB_O to the recovery voltage Vrec level in response to the excellent high potential voltage VDD_E.

In the second odd QB node control transistor T5Qa, the gate electrode is connected to the Q node Q, the first electrode is connected to the low potential power line VSS, and the second electrode is connected to the odd QB node QB_O. The T5Qa-th transistor T5Qa is turned on when the Q node Q has a high level voltage to discharge the odd QB node QB_O to the low potential voltage VSS.

In the T3b transistor T3b, the gate electrode is connected to the superior QB node QB_E, the first electrode is connected to the low potential power line VSS, and the second electrode is connected to the Q node Q. The T3b-th transistor T3b is turned on when the superior QB node QB_E is at a high level, and discharges the Q node Q to the low potential voltage VSS.

In the T4b transistor T4b, the gate electrode and the first electrode are connected to the superior high potential voltage source VDD_E, and the second electrode is connected to the superior QB node QB_E. When the high-level excellent high potential voltage VDD_E is input, the T4bth transistor T4b charges the excellent QB node QB_E.

In the first excellent QB node control transistor T5Fb, the gate electrode is connected to the start signal terminal VST, the first electrode is connected to the low potential power source VSS, and the second electrode is connected to the excellent QB node QB_E. The first good QB node control transistor T5Fb discharges the good QB node QB_E to the low potential voltage VSS in response to the start signal VST.

In the excellent low potential holding transistor T5QIb, the gate electrode is connected to the odd high potential voltage source VDD_O, the first electrode is connected to the recovery voltage source Vrec, and the second electrode is connected to the excellent QB node QB_E. The superior low potential holding transistor T5QIb discharges the superior QB node QB_E to the recovery voltage Vrec level in response to the odd high potential voltage VDD_O of the high level.

In the second excellent QB node control transistor T5Qb, the gate electrode is connected to the Q node Q, the first electrode is connected to the low potential power supply VSS, and the second electrode is connected to the even QB node QB_E. The second excellent QB node control transistor T5Qb discharges the potential of the even QB node QB_E to the low potential voltage VSS when the Q node Q is charged.

The output control units T6, T7a, and T7b include a pull-up transistor T6, an odd pull-down transistor T7a, and an even pull-down transistor T7b. The pull-up transistor T6 outputs a gate signal of a gate high voltage, and the odd pull-down transistor T7a and the excellent pull-down transistor T7b discharge the potential of the output terminal Gout to a low potential voltage.

The pull-up transistor T6 has a gate electrode connected to the Q node Q, a first electrode connected to the clock signal line CLK, and a second electrode connected to the output terminal Gout. The pull-up transistor T6 outputs the clock signal CLK to the output terminal Gout when the Q node Q is in a charged state.

In the odd pull-down transistor T7a, a gate electrode is connected to the odd QB node QB_O, a first electrode is connected to the low potential power line VSS, and a second electrode is connected to the output terminal Gout. The odd pull-down transistor T7a discharges the potential of the output terminal Gout to a low potential voltage VSS when the odd QB node QB_O is in a charged state.

In the even pull-down transistor T7b, the gate electrode is connected to the even QB node QB_E, the first electrode is connected to the low potential power line VSS, and the second electrode is connected to the output terminal Gout. The even pull-down transistor T7b discharges the potential of the output terminal Gout to the low potential voltage VSS when the superior QB node QB_E is in a charged state.

The gate driver of the present invention is provided with odd high potential voltage VDD_O and excellent high potential voltage VDD_E for alternately driving odd QB nodes QB_O and excellent QB nodes QB_E.

The odd QB node operation period To is a period in which the odd QB node QB_O is driven based on the voltage provided through the odd high potential voltage terminal VDD_O. During the odd QB node operation period To, the even QB node QB_E maintains the recovery voltage Vrec.

The excellent QB node operation period Te is a period in which the excellent QB node QB_E is driven based on the voltage provided through the excellent high potential voltage terminal VDD_E. During the even QB node operation period Te, the odd QB node QB_O maintains the recovery voltage Vrec.

The low potential voltage VSS is a ground voltage having a voltage value of '0'V, and the recovery voltage Vrec has a voltage lower than the low potential voltage VSS, that is, a negative voltage value.

The odd QB node operation period To and the even QB node operation period Te may be set in units of several seconds. As described above, odd QB nodes QB_O and even QB nodes QB_E are alternately driven at regular intervals, thereby reducing a bias stress burdened on transistors driving the QB nodes.

On the other hand, the ith stage of the built-in scan driver according to the first embodiment, as shown in Figure 6, clock signal (CLK), start signal (VST), high potential power (VDD), odd high potential power (VDD_O) And it can operate in response to the rear end signal (VNEXT). 6 shows a case in which the odd high potential voltage VDD_O is at a high level to drive the odd QB node.

Referring to FIG. 6, a change in the potential of the output terminal Gout outputting the gate pulse according to the timing of each signal is as follows.

While the start signal VST is being input, the first transistor T1 provides the high potential voltage VDD to the Q node Q. Accordingly, the Q node Q is pre-charged while the start signal VST is input.

While the clock signal CLK is being input, the potential of the first electrode of the pull-up transistor T6 is raised by the clock signal CLK, and the gate electrode is bootstrapped. Accordingly, the potential of the Q node Q precharged while the start signal VST is input becomes higher when the clock signal CLK is input and is turned on. The turned-on pull-up transistor T6 outputs the clock signal CLK to the output terminal Gout.

And during the scan period Ts in which the Q node Q is charged by the start signal VST and the clock signal CLK, the first odd QB node control transistor T5Fa reduces the potential of the odd QB node QB_O. After discharging with the potential voltage VSS, the first superior QB node control transistor T5Fb discharges the potential of the superior QB node QB_E to the low potential voltage VSS. In addition, as the Q node Q is charged during the first period t1, the second odd QB node control transistor T5QIa discharges the odd QB node QB_O to a low potential voltage VSS, and a second excellent The QB node control transistor T5QIb discharges the even QB node QB_E to a low potential voltage VSS.

That is, during the scan period Ts, the Q node Q is charged and the odd QB node QB_O and the even QB node QB_E are discharged to the low potential voltage VSS.

While the clock signal CLK is inverted to the low level and the downstream signal VNEXT is input, the T3Nth transistor T3N is turned on to discharge the potential of the Q node Q to the low potential voltage VSS. As the potential of the Q node Q is discharged to the low potential voltage VSS, the second odd QB node control transistor T5QIa and the second excellent QB node control transistor T5QIb are turned off, and the odd QB node QB_O ) And good QB nodes (QB_E) cannot maintain the low potential. Accordingly, the odd QB node QB_O is charged by the odd high potential voltage VDD_O, and the even QB node QB_E is charged by the excellent high potential voltage VDD_E.

During the odd QB node operation period To, as the odd QB node QB_O is charged, the T3ath transistor T3a is turned on to discharge the Q node Q to the low potential voltage VSS. Alternatively, during the excellent QB node operation period Te, as the even QB node QB_E is charged, the T3bth transistor T3b is turned on to discharge the Q node Q to the low potential voltage VSS.

As described above, the T3a-th transistor T3a and the odd-numbered pull-down transistor T7a control the voltage charged in the odd-numbered QB node QB_O except for the period in which the gate pulse is output during the driving of the odd-numbered QB node QB_O. It is input through the gate electrode. That is, since the T3a-th transistor T3a and the odd pull-down transistor T7a are subjected to a bias stress for a long time, the threshold voltage Vth characteristic of the transistor is changed.

Likewise, transistor characteristics of the T3b-th transistor T3b and the excellent pull-down transistor T7b are changed due to the bias resistance in the process of driving the excellent QB node QB_E.

The shift register 140 of the present invention alternately drives the odd QB node (QB_O) and the excellent QB node (QB_E), and maintains the QB node at a low potential during the non-driving period, so that the T3a-th transistor T3a and the odd pull-down transistor T7a ) Or the device characteristics of the T3b-th transistor T3b and the excellent pull-down transistor T7b are restored. In particular, during this process, the QB node in the non-driving period maintains a recovery voltage Vrec whose voltage level is lower than that of the low potential voltage. For example, while driving the odd QB node QB_O as shown in FIG. 6, the excellent low potential holding transistor T5QIb discharges the even QB node QB_E to the recovery voltage Vrec level.

7 is a diagram showing a recovery characteristic of a transistor threshold voltage Vth when the gate-source potential Vgs is a positive potential and a negative potential Vgs. As shown in FIG. 7, it can be seen that when the gate-source potential of the transistor is a negative (-) potential, the recovery of the threshold voltage becomes faster.

The gate driver of the first embodiment selectively maintains the QB node at a low potential voltage VSS or a recovery voltage Vrec according to a driving period. If the QB node is always maintained at a negative voltage, power consumption increases because the voltage swing of the QB node increases during the driving period. However, in the first embodiment, since the QB node is maintained at a low potential voltage during the driving period, power consumption is reduced, and during the non-driving period, the QB node is maintained at a negative potential to effectively perform a threshold voltage recovery function. I can.

8 is a diagram illustrating a stage according to a second embodiment.

Referring to FIG. 8, the ith stage of the gate driver according to the second embodiment includes scan direction controllers T1 and T3N, node controllers T3R, T3a, T3b, T4a, T5Fa, T5QIa, T5Qa, T3b, T4b, T5Fb. , T5QIb, T5Qb, T5F_La, T5F_Lb, T5F_Ha, T5F_Hb, T5Q_La, T5Q_Lb, T5Q_Ha, T5Q_Hb) and output control units (T6, T7a, T7b). In the second embodiment, the same reference numerals are used for configurations that are substantially the same as those of the above-described embodiment, and detailed descriptions will be omitted.

The node control unit includes a Q node control unit, an odd QB node control unit, an even QB node control unit, and a low potential holding unit.

The Q node control units T3R, T3a, and T3b determine the charging timing of the Q node Q. The odd QB node controllers T4a, T5Fa, T5Qa, T5F_Ha, and T5Q_Ha determine the charging timing of the odd QB node QB_O. The excellent QB node controllers T4b, T5Fb, T5Qb, T5F_Hb, and T5Q_Hb determine the charging timing of the excellent QB node QB_E. The low-potential holding units T5QIa and T5QIb provide the recovery voltage Vrec in a period in which the odd QB node QB_O and the superior QB node QB_E do not operate.

The short-circuit prevention units T5F_La, T5Q_La, T5F_Lb, and T5Q_Lb prevent a short-circuit phenomenon from occurring through an inactive QB node.

In the T4ath transistor T4a, a gate electrode and a first electrode are connected to the odd high potential voltage source VDD_O, and a second electrode is connected to the odd QB node Qr_O. The T4ath transistor T4a charges the odd QB node QB_O when the odd high potential voltage VDD_O of the high level is provided.

In the first odd QB node control transistor T5Fa, the gate electrode is connected to the odd start output control transistor T5F_Ha, the first electrode is connected to the low potential voltage VSS, and the second electrode is connected to the odd QB node (QB_O). do. The gate electrode of the odd start output control transistor T5F_Ha is connected to the odd high potential voltage (VDD_O), the first electrode is connected to the start signal (VST), and the second electrode is connected to the first odd QB node control transistor (T5Fa). do. That is, the first odd QB node control transistor T5Fa converts the odd QB node QB_O to the low potential voltage VSS in response to the start signal VST selectively provided only when the odd high potential voltage VDD_O is at a high level. ) To discharge.

In the first odd short-circuit prevention transistor T5F_La, the gate electrode is connected to the superior high potential voltage terminal VDD_E, the first electrode is connected to the first odd QB node control transistor T5Fa, and the second electrode is connected to the recovery voltage source Vrec. Is connected. The first odd-numbered short-circuit prevention transistor T5F_La turns off the first odd-numbered QB node control transistor T5Fa when the excellent high potential voltage VDD_E is applied, that is, during the odd-numbered QB node operation period Te.

In the T4b transistor T4b, the gate electrode and the first electrode are connected to the superior high potential voltage source VDD_E, and the second electrode is connected to the superior QB node QB_E. When the high-level excellent high potential voltage VDD_E is input, the T4bth transistor T4b charges the excellent QB node QB_E.

In the first excellent QB node control transistor T5Fb, the gate electrode is connected to the excellent start output control transistor T5F_Hb, the first electrode is connected to the low potential voltage source (VSS), and the second electrode is connected to the excellent QB node (QB_E). do. The gate electrode of the excellent start output control transistor T5F_Hb is connected to the excellent high potential voltage source VDD_E, the first electrode is connected to the start signal VST, and the second electrode is connected to the first odd QB node control transistor T5Fa. do. That is, the first excellent QB node control transistor T5Fb discharges the excellent QB node (QB_E) to a low potential voltage in response to the start signal VST selectively provided only when the excellent high potential voltage (VDD_E) is at a high level. do.

The first excellent short-circuit prevention transistor T5F_Lb has a gate electrode connected to the odd high potential voltage terminal VDD_O, a first electrode connected to the first excellent QB node control transistor T5Fb, and a second electrode to the recovery voltage source Vrec. Is connected. The first excellent short-circuit prevention transistor T5F_Lb turns off the first excellent QB node control transistor T5Fb when the odd high potential voltage VDD_O is applied, that is, during an odd QB node operation period.

In the second odd QB node control transistor T5Qa, the gate electrode is connected to the second electrode of the odd Q node switching transistor T5Q_Ha, the first electrode is connected to the odd QB node QB_O, and is connected to the low potential power line VSS. The second electrode is connected. The odd Q node switching transistor T5Q_Ha has a gate electrode connected to the odd high potential voltage terminal VDD_O, a first electrode connected to the Q node Q, and a gate electrode of the second odd QB node control transistor T5Qa. 2 electrodes are connected. That is, the second odd QB node control transistor T5Qa is turned on when the Q node Q is the high level voltage while the odd high potential voltage VDD_O is provided. The second odd QB node control transistor T5Qa discharges the odd QB node QB_O to a low potential voltage VSS while being turned on.

In the second odd short-circuit prevention transistor T5Q_La, the gate electrode is connected to the odd high potential voltage terminal VDD_O, the first electrode is connected to the second excellent QB node control transistor T5Qb, and the second electrode is connected to the recovery voltage source Vrec. Is connected. The second odd short-circuit prevention transistor T5Q_La turns off the second odd QB node control transistor T5Qb when the odd high potential voltage VDD_O is applied. That is, the second odd short-circuit prevention transistor T5Q_La turns off the second good QB node control transistor T5Qb when the odd QB node QB_O is in the operating period and the even QB node is in the inactive period.

The second excellent QB node control transistor T5Qb has a gate electrode connected to the excellent Q node switching transistor T5Q_Hb, a first electrode connected to the low potential power line VSS, and a second electrode connected to the excellent QB node QB_E. Connected. The excellent Q node switching transistor T5Q_Hb has a gate electrode connected to the excellent high potential voltage terminal VDD_E, a first electrode connected to the Q node Q, and a gate electrode of the second excellent QB node control transistor T5Qb. 2 electrodes are connected. That is, the second excellent QB node control transistor T5Qb is turned on when the Q node Q is a high level voltage while the excellent high potential voltage VDD_E is provided. The second good QB node control transistor T5Qb discharges the good QB node QB_E to the low potential voltage VSS while being turned on.

The second excellent short-circuit prevention transistor T5Q_Lb has a gate electrode connected to the excellent high potential voltage terminal VDD_E, a first electrode connected to the first odd QB node control transistor T5Fa, and a second electrode to the recovery voltage source Vrec. Is connected. The second even short-circuit prevention transistor T5Q_Lb turns off the second odd QB node control transistor T5Qa when the excellent high potential voltage VDD_E is provided. That is, the second even short-circuit prevention transistor T5Q_Lb turns off the second odd QB node control transistor T5Qa when the even QB node QB_E is an operating period and the odd QB node QB_O is a non-operating period.

Meanwhile, the i-th stage of the built-in scan driver according to the second embodiment is the clock signal CLK, the start signal VST, the high potential power supply (VDD), and the odd high potential power supply shown in FIG. 6 as in the first embodiment. It can operate in response to (VDD_O) and the rear end signal (VNEXT).

During the odd QB node operation period To, the good QB node QB_E must maintain the recovery voltage Vrec level by the operation of the good low potential holding transistor T5QIb. However, even in the odd QB node operation period (To), while the start signal VST is input, the first excellent QB node control transistor T5Fb is turned on and the Q node Q is charged. The control transistor T5Qb is also turned on. Accordingly, the low potential voltage VSS and the recovery voltage Vrec are shorted through the first excellent QB node control transistor T5Fb and the excellent low potential holding transistor T5QIb during the odd QB node operation period To. This phenomenon occurs. In addition, a phenomenon in which the low potential voltage VSS and the recovery voltage Vrec are shorted occurs through the second excellent QB node control transistor T5Qb and the excellent low potential holding transistor T5QIb. As a result, as shown in FIG. 9, a short-circuit voltage occurs within the odd QB node operation period To, and the voltage levels of the low potential voltage VSS and the recovery voltage Vrec may fluctuate.

The stage of the second embodiment includes an odd start output control transistor T5F_Ha for normally operating the first odd QB node control transistor T5Fa during the odd QB node operation period To. Further, the stage of the second embodiment includes a first excellent short-circuit prevention transistor T5F_Lb for preventing a short-circuit from occurring through the even QB node QB_E during the odd QB node operation period To.

In addition, the stage of the second embodiment includes an odd Q node switching transistor T5Q_Ha for normally operating the second odd QB node control transistor T5Qa during the odd QB node operation period To, and an excellent QB node QB_E ), and a second excellent short-circuit prevention transistor T5Q_Lb for preventing a short-circuit from occurring.

The odd start output control transistor T5F_Ha is turned on in response to the odd high potential voltage VDD_O. Therefore, the odd-numbered start output control transistor T5F_Ha turns on the first odd-numbered QB node control transistor T5Fa during the odd-numbered QB node operation period To to perform normal driving.

The first excellent short-circuit prevention transistor T5F_Lb is turned on in response to the odd high potential voltage VDD_O. That is, the first excellent short-circuit prevention transistor T5F_Lb turns off the first excellent QB node control transistor T5Fb in the odd QB node operation period To. Accordingly, the first excellent short-circuit prevention transistor T5F_Lb prevents the first excellent QB node control transistor T5Fb from being turned on even when the start signal VST is input during the odd QB node driving period To. As a result, the first excellent short-circuit prevention transistor T5F_Lb can suppress the occurrence of a short-circuit through the first excellent QB node control transistor T5Fb and the excellent low potential holding transistor T5QIb during the odd QB node driving period To. I can.

The odd Q node switching transistor T5Q_Ha is turned on in response to the odd high potential voltage VDD_O. The odd Q node switching transistor T5Q_Ha turns on the second odd QB node control transistor T5Qa during the odd QB node operation period To to perform normal driving.

The second excellent short-circuit prevention transistor T5Q_Lb is turned on in response to the odd high potential voltage VDD_O. That is, the second excellent short-circuit prevention transistor T5Q_Lb turns off the second excellent QB node control transistor T5Qb in the odd QB node operation period To. Therefore, the second excellent short-circuit prevention transistor T5Q_Lb suppresses the occurrence of a short-circuit through the second excellent QB node control transistor T5Qb and the excellent low potential holding transistor T5QIb during the odd QB node driving period To. can do.

Similarly, the stage of the second embodiment includes an excellent start output control transistor T5F_Hb for normally operating the first excellent QB node control transistor T5Fb during the excellent QB node operation period Te. In addition, the stage of the second exemplary embodiment includes a first odd short-circuit prevention transistor T5F_La for preventing a short-circuit from occurring through the odd QB node QB_O during the even QB node operation period Te.

In addition, the stage of the second embodiment includes an excellent Q node switching transistor T5Q_Hb for normally operating the second excellent QB node control transistor T5Qb during the excellent QB node operation period Te, and the odd QB node QB_O ) And a second odd-numbered short-circuit prevention transistor T5Q_La for preventing a short-circuit from occurring.

10 is a diagram showing a stage according to a third embodiment.

Referring to FIG. 10, the ith stage of the gate driver according to the second embodiment includes scan direction controllers T1 and T3N, node controllers T3R, T3a, T3b, T4a, T5Fa, T5QIa, T5Qa, T3b, T4b, T5Fb. , T5QIb, T5Qb, T5F_La, T5F_Lb, T5Q_La, T5Q_Lb) and output control units T6, T7a, T7b. In the third embodiment, the same reference numerals are used for configurations that are substantially the same as those of the second embodiment, and detailed descriptions thereof will be omitted.

The node control unit includes a Q node control unit, an odd QB node control unit, an even QB node control unit, and a low potential holding unit.

The Q node control units T3R, T3a, and T3b determine the charging timing of the Q node Q. The odd-numbered QB node control units T4a, T5Fa, and T5Qa determine the charging timing of the odd-numbered QB node (QB_O). The excellent QB node controllers T4b, T5Fb, and T5Qb determine the charging timing of the excellent QB node QB_E. The low-potential holding units T5QIa and T5QIb provide the recovery voltage Vrec in a period in which the odd QB node QB_O and the superior QB node QB_E do not operate. The short-circuit prevention units T5F_La, T5Q_La, T5F_Lb, and T5Q_Lb prevent a short-circuit phenomenon from occurring through an inactive QB node.

The first odd QB node control transistor T5Fa has a gate electrode connected to the start signal terminal VST, a first electrode connected to a low potential voltage VSS, and a second electrode of the first odd short-circuit prevention transistor T5F_La. The first electrode is connected. In the first odd short-circuit prevention transistor T5F_La, the gate electrode is connected to the even high potential voltage source VDD_E, and the first electrode is connected to the odd QB node QB_O. Therefore, during the excellent QB node operation period Te, the first odd short-circuit prevention transistor T5F_La is turned off, so that the current path between the first odd QB node control transistor T5Fa and the odd QB node QB_O is blocked. That is, the first odd short-circuit prevention transistor T5F_La can suppress the occurrence of a short circuit through the first odd QB node control transistor T5Fa and the odd low potential holding transistor T5QIa during the excellent QB node operation period Te. I can. In other words, the first odd short-circuit prevention transistor T5F_La prevents the occurrence of a short shape through the odd QB node QB_O during the even QB node operation period Te.

Similarly, the first even short-circuit prevention transistor T5F_Lb prevents a short-circuit phenomenon from occurring through the even QB node QB_E during the odd QB node operation period To.

The second odd QB node control transistor T5Qa has a gate electrode connected to the Q node Q, a second electrode connected to the low potential power line VSS, and a second electrode of the second odd short prevention transistor T5Q_La. The first electrode is connected. In the second odd short-circuit prevention transistor T5Q_La, the gate electrode is connected to the even high potential voltage VDD_E, and the first electrode is connected to the odd QB node QB_O. That is, the second odd-numbered short-circuit prevention transistor T5Q_La turns off the second odd-numbered QB node control transistor T5Qa during the even QB node operation period Te. Therefore, the second odd short-circuit prevention transistor T5Q_La can suppress the occurrence of a short circuit through the second odd QB node control transistor T5Qa and the odd low potential holding transistor T5QIa during the excellent QB node operation period Te. I can.

In the second excellent QB node control transistor T5Qb, the gate electrode is connected to the Q node Q, the first electrode is connected to the low potential power line VSS, and the second electrode is connected to the even QB node QB_E. A second even short-circuit prevention transistor T5Q_Lb is formed between the even QB node QB_O and the second electrode. The gate electrode of the second excellent short-circuit prevention transistor T5Q_Lb is connected to the odd high potential voltage VDD_O.

The second excellent short-circuit prevention transistor T5Q_Lb can suppress the occurrence of a short-circuit phenomenon through the second excellent QB node control transistor T5Qb and the excellent low potential holding transistor T5QIb during the odd QB node operation period To. .

As described above, the gate driver of the third embodiment can prevent a short circuit from occurring through the QB node having a non-driving period, similar to the second embodiment.

11 is a diagram showing a stage according to a fourth embodiment. In the fourth embodiment, the same reference numerals are used for the same configurations as those of the above-described embodiments, and detailed descriptions will be omitted.

The fourth embodiment shown in FIG. 11 is a modified example of the third embodiment. The first odd short prevention transistor T5F_La is connected between the first odd QB node control transistor T5Fa and the low potential voltage VSS. In addition, the first excellent short-circuit prevention transistor T5F_Lb is connected between the first excellent QB node control transistor and the low potential voltage VSS.

The second odd short prevention transistor T5Q_La is connected between the second odd QB node control transistor T5Qa and the low potential voltage VSS. The second excellent short-circuit prevention transistor T5Q_Lb is connected between the second excellent QB node control transistor T5Qb and the low potential voltage VSS.

The first odd short prevention transistor T5F_La, the first odd short prevention transistor T5F_Lb, the second odd short prevention transistor T5Q_La, and the second odd short prevention transistor T5Q_Lb according to the fourth embodiment are respectively implemented in the third embodiment described above. Since the operation is the same as in the example, a detailed description will be omitted.

That is, the gate driver according to the fourth embodiment can also prevent a short circuit from occurring through the QB node having a non-driving period.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above is in other specific forms without changing the technical spirit or essential features of the present invention by those skilled in the art. It will be appreciated that it can be implemented. Therefore, the embodiments described above are illustrative in all respects and should be understood as non-limiting. In addition, the scope of the present invention is indicated by the claims to be described later rather than the detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention.

Claims (9)

A display panel on which a gate line is formed; And
Including a gate driver for outputting a gate pulse provided to the gate line,
The gate driver
A Q node control unit for controlling a Q node for determining an output timing of a clock signal;
An output controller configured to output the clock signal to an output terminal in response to the high level potential of the Q node;
An odd QB node control unit for controlling the odd QB node connected to the output control unit so that the output control unit discharges the potential of the output terminal during a first period;
An excellent QB node control unit for controlling an excellent QB node connected to the output control unit so that the output control unit discharges the potential of the output terminal during a second period; And
A low potential holding unit providing a recovery voltage of a negative potential to the even QB node during the first period, and providing the recovery voltage to the odd QB node during the second period,
During a third period in which the odd QB node is discharged to a low potential voltage, the low potential holding unit provides the recovery voltage lower than the low potential voltage to the excellent QB node,
During a fourth period in which the superior QB node is discharged to the low potential voltage, the low potential holding unit provides the recovery voltage to the odd QB node. The method of claim 1,
The low potential holding part
An excellent low potential holding transistor discharging the even QB node to the recovery voltage during the first period when the odd QB node is driven and the third period when the odd QB node is discharged; And
And an odd low potential holding transistor for discharging the odd QB node to the recovery voltage during the second period when the even QB node is driven and the fourth period when the even QB node is discharged. The method of claim 2,
The odd QB node maintains the low potential voltage during the third period by a first odd QB node control transistor, and the even QB node maintains the low potential voltage during a fourth period by the first odd QB node control transistor. Keep,
The gate driver
An odd-numbered start output control transistor for controlling whether the first odd-numbered QB node control transistor is operated during the third period; And
The display device further comprises an excellent start output control transistor that controls whether or not the first excellent QB node control transistor is operated during the fourth period. The method of claim 3,
The first odd QB node control transistor discharges the odd QB node to the low potential voltage in response to a start signal provided through a start signal terminal,
The odd start output control transistor is formed between the first odd QB node control transistor and the start signal terminal to connect a current path between the first odd QB node control transistor and the start signal terminal in response to an odd high potential voltage And
The first excellent QB node control transistor discharges the excellent QB node to the low potential voltage in response to the start signal provided through the start signal terminal,
The excellent start output control transistor is formed between the first excellent QB node control transistor and the start signal terminal to connect a current path between the first excellent QB node control transistor and the start signal terminal in response to an excellent high potential voltage. Display device. The method of claim 2,
The odd QB node maintains the low potential voltage during the third period by a first odd QB node control transistor, and the excellent QB node maintains the low potential voltage during the fourth period by a first odd QB node control transistor. And
The gate driver
A first odd-numbered short-circuit prevention transistor that blocks an operation of the first odd-numbered QB node control transistor during the fourth period; And
The display device further comprises a first excellent short-circuit prevention transistor for blocking an operation of the first excellent QB node control transistor during the third period. The method of claim 2,
The odd QB node is discharged to the low potential voltage by a second odd QB node control transistor turned on in response to the Q node potential, and the even QB node is turned on in response to the Q node potential. 2 discharged to the low potential voltage by the superior QB node control transistor,
The gate driver
An odd Q node switching transistor controlling whether the second odd QB node control transistor is operated in response to an odd high potential voltage; And
The display device further comprising an excellent Q node switching transistor for controlling whether the second excellent QB node control transistor is operated in response to an excellent high potential voltage. The method of claim 2,
The odd QB node is discharged to the low potential voltage by a second odd QB node control transistor turned on in response to the Q node potential, and the even QB node is turned on in response to the Q node potential. 2 discharged to the low potential voltage by the superior QB node control transistor,
The gate driver
A second odd short-circuit prevention transistor configured to block an operation of the second odd-numbered QB node control transistor in response to an even high potential voltage; And
The display device further comprising a second excellent short-circuit prevention transistor configured to block an operation of the second superior QB node control transistor in response to an odd high potential voltage. The method of claim 2,
The odd QB node maintains the low potential voltage during the third period by a first odd QB node control transistor, and the excellent QB node maintains the low potential voltage during the fourth period by a first odd QB node control transistor. And
The gate driver
A first odd short-circuit prevention transistor connected to a drain electrode or a source electrode of the first odd QB node control transistor to turn off the first odd QB node control transistor in response to an even high potential voltage; And
The display device further comprising a first excellent short-circuit prevention transistor connected to a drain electrode or a source electrode of the first excellent QB node control transistor to turn off the first excellent QB node control transistor in response to an odd high potential voltage . The method of claim 2,
The odd QB node is discharged to the low potential voltage by a second odd QB node control transistor turned on in response to the Q node potential, and the even QB node is turned on in response to the Q node potential. 2 discharged to the low potential voltage by the superior QB node control transistor,
The gate driver
A second odd short-circuit prevention transistor connected to a drain electrode or a source electrode of the second odd QB node control transistor to turn off the second odd QB node control transistor in response to an even high potential voltage; And
A display device further comprising a second excellent short-circuit prevention transistor connected to a drain electrode or a source electrode of the second superior QB node control transistor, and turning off the second superior QB node control transistor in response to an odd high potential voltage .

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