KR101761414B1 - Gate shift register and display device using the same - Google Patents

Abstract

The present invention provides a gate shift register capable of preventing deterioration of transistors of dummy stages and a display device using the gate shift register. The gate shift register of the present invention includes a first clock terminal receiving any one of m (m is a natural number) to (m + 5) gate shift clocks whose phases are sequentially delayed, A second clock terminal receiving a gate shift clock generated after a clock, first and second input terminals receiving start signals, and third and fourth input terminals receiving reset signals, (N is a natural number) stages for sequentially outputting a second scan pulse. The gate shift register receives a gate start pulse as a start signal, charges a Q node, A first dummy pulse for receiving the first scan pulse of the first stage as a reset signal among the n stages and discharging the Q node, stage; And a second dummy pulse synchronized with the (m + 1) th gate shift clock after charging the Q1 node by receiving the gate start pulse as the start signal and inputting the second scan pulse of the first stage as the reset signal A third dummy pulse synchronized with the (m + 2) -th gate shift clock after charging the Q2 node, receiving the gate start pulse as the start signal, and outputting a third dummy pulse synchronized with the (m + A second dummy stage for receiving the first scan pulse of the second stage as the reset signal and discharging the node Q2; The second scan pulse of the (n-1) th stage is input to the start signal to charge the Q1 node, and then the fourth dummy pulse synchronized with the (m + 3) th gate shift clock is output. And a fifth dummy pulse synchronized with the (m + 4) -th gate shift clock after charging the Q2 node by receiving the first scan pulse of the n-th stage as the start signal, A third dummy stage for receiving the initialization signal and discharging the node Q2; And a second scan pulse of the n < th > stage as the start signal, charges the Q node, and outputs a sixth dummy pulse synchronized with the m + 5 gate shift clock, And a fourth dummy stage for discharging the Q node, wherein the n stages output first to second scan pulses.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate shift register,

The present invention relates to a gate shift register and a display using the gate shift register.

Various flat panel displays (FPDs) have been developed and marketed to reduce weight and volume, which are disadvantages of cathode ray tubes (Cathode Ray Tube). The scan driving circuit of the flat panel display generally supplies scan pulses to the scan lines sequentially using a gate shift register.

The gate shift register of the scan driving circuit has stages including a plurality of thin film transistors (hereinafter referred to as "TFTs "). Stages are connected in a cascade to generate output sequentially.

Such a conventional gate shift register generates a scan pulse only in the direction from the stage located at the most unidirectional side, that is, the stage located at the lowermost position. Such a gate shift register can not be applied to a display device of various models, for example, a display device that sequentially displays images in the direction of the uppermost scan line from the lowermost scan line of the display panel, it's difficult. Accordingly, a gate shift register capable of bi-directional shift operation has been recently proposed. The bi-directional gate shift register includes a bi-directional control circuit and operates in a forward shift mode or a reverse shift mode.

Each of the stages of the gate shift register capable of bi-directional shift operation includes a Q-node for controlling a pull-up transistor, and a Q-bar (QB) node for controlling a pull-down transistor. In addition, each of the stages includes switch circuits that charge and discharge the Q node and the QB node voltage in response to a carry signal input from a previous stage, a carry signal input from the next stage, and a clock signal.

In the forward mode, the reset signal for initializing the Q node is not inputted to the dummy stages located after the lowermost stage. In the forward mode, the carry signals for the Q node discharges from the next stage are not inputted to the dummy stages located after the lowermost stage. Therefore, in the forward mode, the dummy stages positioned after the lowermost stage are input with the start voltage as a carry signal for Q node discharge. However, since the start voltage is generated at intervals of one frame, the Q node of the dummy stages is not discharged immediately after outputting the dummy pulse, but is discharged in a state of being charged with the gate high voltage until a pulse of the start voltage occurs There is a problem.

In the backward mode, the reset signal for initializing the Q node is not inputted to the dummy stages located before the uppermost stage. In the backward mode, the carry signals for Q node discharges from the previous stage are not inputted to the dummy stages located before the uppermost stage. Therefore, in the backward mode, the dummy stages positioned before the uppermost stage are input with the start voltage as a carry signal for Q node discharge. However, since the start voltage is generated at intervals of one frame, the Q node of the dummy stages located before the uppermost stage in the reverse mode is not discharged immediately after outputting the dummy pulse, but when the pulse of the start voltage is generated There is a problem that the floating state is filled with the gate high voltage.

Taken together, in the forward and reverse modes, the transistors connected to the Q node of the dummy stages remain in the turn-on state due to the floating of the Q node, so that the degradation of the transistors proceeds rapidly. In addition, the output of the gate shift register becomes unstable due to deterioration of the transistors.

The present invention provides a gate shift register capable of preventing deterioration of transistors of dummy stages and a display device using the gate shift register.

The gate shift register of the present invention includes a first clock terminal receiving any one of m (m is a natural number) to (m + 5) gate shift clocks whose phases are sequentially delayed, A second clock terminal receiving a gate shift clock generated after a clock, first and second input terminals receiving start signals, and third and fourth input terminals receiving reset signals, (N is a natural number) stages for sequentially outputting a second scan pulse. The gate shift register receives a gate start pulse as a start signal, charges a Q node, A first dummy pulse for receiving the first scan pulse of the first stage as a reset signal among the n stages and discharging the Q node, stage; And a second dummy pulse synchronized with the (m + 1) th gate shift clock after charging the Q1 node by receiving the gate start pulse as the start signal and inputting the second scan pulse of the first stage as the reset signal A third dummy pulse synchronized with the (m + 2) -th gate shift clock after charging the Q2 node, receiving the gate start pulse as the start signal, and outputting a third dummy pulse synchronized with the (m + A second dummy stage for receiving the first scan pulse of the second stage as the reset signal and discharging the node Q2; The second scan pulse of the (n-1) th stage is input to the start signal to charge the Q1 node, and then the fourth dummy pulse synchronized with the (m + 3) th gate shift clock is output. And a fifth dummy pulse synchronized with the (m + 4) -th gate shift clock after charging the Q2 node by receiving the first scan pulse of the n-th stage as the start signal, A third dummy stage for receiving the initialization signal and discharging the node Q2; And a second scan pulse of the n < th > stage as the start signal, charges the Q node, and outputs a sixth dummy pulse synchronized with the m + 5 gate shift clock, And a fourth dummy stage for discharging the Q node, wherein the n stages output first to second scan pulses.

A display device of the present invention includes: a display panel including a plurality of pixels arranged in a matrix form in which data lines and scan lines intersect; A data driving circuit for supplying a data voltage to the data lines; And a scan driver circuit for sequentially supplying scan pulses to the scan lines, wherein the scan driver circuit includes a scan driver for sequentially supplying m (m is a natural number) to (m + 5) A first clock terminal receiving one input, a second clock terminal receiving a gate shift clock generated after a gate shift clock input to the first clock terminal, first and second input terminals receiving start signals, And a gate shift register including n stages (n is a natural number) stages for sequentially outputting first and second scan pulses, the gate shift register including third and fourth input terminals for receiving signals, Receives a gate start pulse as a start signal, charges a Q node, and outputs a first dummy pulse synchronized with the m-th gate shift clock, and the n A first dummy stage for receiving the first scan pulse of the first stage as a reset signal among the stages and discharging the Q node; And a second dummy pulse synchronized with the (m + 1) th gate shift clock after charging the Q1 node by receiving the gate start pulse as the start signal and inputting the second scan pulse of the first stage as the reset signal A third dummy pulse synchronized with the (m + 2) -th gate shift clock after charging the Q2 node, receiving the gate start pulse as the start signal, and outputting a third dummy pulse synchronized with the (m + A second dummy stage for receiving the first scan pulse of the second stage as the reset signal and discharging the node Q2; The second scan pulse of the (n-1) th stage is input to the start signal to charge the Q1 node, and then the fourth dummy pulse synchronized with the (m + 3) th gate shift clock is output. And a fifth dummy pulse synchronized with the (m + 4) -th gate shift clock after charging the Q2 node by receiving the first scan pulse of the n-th stage as the start signal, A third dummy stage for receiving the initialization signal and discharging the node Q2; And a second scan pulse of the n < th > stage as the start signal, charges the Q node, and outputs a sixth dummy pulse synchronized with the m + 5 gate shift clock, And a fourth dummy stage for discharging the Q node, wherein the n stages output first to second n scan pulses.

The present invention inputs a reset signal to the reset terminal of the dummy stages which can discharge the Q node immediately after the dummy stages output the dummy pulses. As a result, the present invention can prevent the floating of the Q node of the dummy stages, thereby preventing deterioration of the transistors connected to the Q node. Further, the present invention can stabilize the output of the gate shift register.

1A and 1B are block diagrams illustrating a gate shift register configuration according to an embodiment of the present invention.
2 is a circuit diagram showing the circuit configuration of the third dummy stage.
3 is a waveform diagram showing the input and output signals of the third dummy stage in the forward shift operation.
4 is a waveform diagram showing the input and output signals of the second dummy stage in the backward shift operation.
5 is a circuit diagram showing the circuit configuration of the fourth dummy stage.
6 is a waveform diagram showing the input and output signals of the fourth dummy stage in the forward shift operation.
7 is a waveform diagram showing the input and output signals of the first dummy stage in the backward shift operation.
8A and 8B are waveform diagrams showing simulation results of the fourth dummy stage in the forward shift operation.
9 is a block diagram showing a display device according to an embodiment of the present invention.
10 is a waveform diagram showing the input and output signals of the level shift shown in FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

1A and 1B are block diagrams illustrating a gate shift register configuration according to an embodiment of the present invention. Referring to FIGS. 1A and 1B, a gate shift register according to an embodiment of the present invention includes a plurality of stages (ST (1) to ST (n), n being a natural number of 2 or more) And stages (DST (1) to DST (4)). Although the gate shift register according to the embodiment of the present invention has four dummy stages DST (1) to DST (4), the present invention is not limited thereto.

Each of the stages ST (1) to ST (n) has two output channels and outputs two scan pulses. The second and third dummy stages DST (2) and DST (3) have two output channels and output two dummy pulses. The first and fourth dummy stages DST (1) and DST (4) have one output channel and output one dummy pulse.

The scan pulse is applied to the scan lines of the display device and also serves as a carry signal transmitted to the front stage and the rear stage. The dummy pulse is not applied to the scan lines of the display device but merely serves as a carry signal transmitted to the front stage and the rear stage.

In the following description, the term "front stage" means that the stage is located at the upper portion of the reference stage. For example, with respect to the stage ST (k) as the kth stage (1 <k <n, k, k is a natural number of 2 or more), the front stage is divided into the first stage ST (1) (k-1), and the first and second dummy stages DST (1) and DST (2). Quot; rear stage "refers to a stage located at the bottom of the reference stage. For example, based on the kth (1 &lt; k < n) stage ST (k), the rear stage is a k + 1 stage (ST (k + 1)) to an nth stage, (DST (3), DST (4)).

The first and second dummy stages DST (1) and DST (2) are the front stage of the first stage ST (1) and the third and fourth dummy stages DST (3), DST 4) is the rear stage of the n-th stage ST (n). The first dummy stage DST (1) and the second dummy stage (DST (2)) output a carry signal to be input to the subsequent stage. The third dummy stage (DST (3)) and the fourth dummy stage (DST (4)) output a carry signal to be inputted to the front stage.

The stages ST (1) to ST (n) are arranged in the order of the scan pulses Vout (1) to Vout (2n) in the forward shift mode in the order of the first stage ST (1) ). In the forward shift mode, each of the stages ST (1) to ST (n) includes carry signals of two different front stage stages, which are applied as start signals to the first and second input terminals VST1 and VST2, And operates in response to carry signals of two different rear stage stages applied as reset signals to the third and fourth input terminals VNT1 and VNT2.

The stages ST (1) to ST (n) are driven in the reverse shift mode in the order from the n-th stage ST (n) to the first stage ST (1) ). In the reverse shift mode, each of the stages ST (1) to ST (n) includes carry signals of two different front end stages applied as reset signals to the first and second input terminals VST1 and VST2, And operates in response to carry signals of two different rear stage stages applied as start signals to the third and fourth input terminals VNT1 and VNT2.

In the forward shift mode, the first dummy stage (DST (1)) includes a forward gate start pulse (VST) applied from the timing controller to the first input terminal (VST1) as a start signal, And operates in response to a carry signal of a subsequent stage applied as a signal. The second dummy stage DST2 receives the forward gate start pulse VST applied from the timing controller as a start signal to the first and second input terminals VST1 and VST2 and the forward gate start pulse VST1 applied to the third and fourth input terminals VNT1 , VNT2 as the reset signal. The third dummy stage DST3 receives the carry signals of two different front stage stages as the start signal to the first and second input terminals VST1 and VST2 and the carry signals of the third and fourth input terminals VNT1 and VNT2 In response to a forward gate start pulse VST applied from the timing controller as a reset signal. The fourth dummy stage (DST (4)) receives the carry signal of the previous stage as a start signal at the first input terminal (VST1) and the forward gate start pulse ( VST).

In the backward shift mode, the fourth dummy stage (DST (4)) receives the carry signal of the previous stage applied as the reset signal to the first input terminal (VST1) and the carry signal of the previous stage as the start signal to the second input terminal In response to a reverse gate start pulse VST. The third dummy stage DST3 includes carry signals of two different front stage stages applied as reset signals to the first and second input terminals VST1 and VST2 and third and fourth input terminals VNT1 , VNT2) in response to a reverse gate start pulse (VST) applied from the timing controller. The second dummy stage DST2 receives a reverse gate start pulse VST applied from the timing controller as a reset signal to the first and second input terminals VST1 and VST2 and a second gate terminal , VNT2) in response to carry signals of two different rear stage stages as a start signal. The first dummy stage DST1 is connected to the first input terminal VST1 as a reset signal by a reverse gate start pulse VST applied from the timing controller and to a second input terminal VNT1 by a start signal, Signal.

The gate shift register outputs scan pulses Vout (1) to Vout (2n) having a pulse for a predetermined time. To this end, each of the stages ST (1) to ST (n) and the second and third dummy stages DST (2) and DST (3) Two gate shift clocks are input among i (i is a positive even number) gate shift clocks. One gate shift clock is input to each of the first and fourth dummy stages DST (1) and DST (4) with a predetermined time pulse and sequential delayed i-th gate shift clocks. It is preferable that the gate shift clocks are implemented in 6 phases or more in order to secure a sufficient charge time in high-speed operation of 240 Hz or more. The six-phase gate shift clocks CLK1 to CLK6 to be described below each have a pulse width of one horizontal period and swing between the gate high voltage VGH and the gate low voltage VGL.

An initialization pulse RST is input to the initialization terminal of each of the dummy stages DST (1) to DST (4) as an initialization signal. The initialization pulse RST is a pulse for initializing the dummy stages DST (1) to DST (4). The initialization pulse RST is generated after the scan pulse and the dummy pulse are output as shown in FIGS. A gate start pulse VST is input as an initialization signal to the initialization terminal of each of the stages ST (1) to ST (n). The gate start pulse (VST) occurs with the start of the frame.

As shown in FIGS. 3 and 4, the gate high voltage VGH and the gate low voltage VGH are supplied to the stages ST (1) to ST (n) and the dummy stages DST (1) to DST (4) AC drive voltages VDD_O and VDD_E, which have a phase difference of 180 degrees and swing in opposite directions, are supplied between the voltage VGL. A low potential voltage (GND) or a gate low voltage (VGL) level is applied to each of the stages ST (1) to ST (n) and the dummy stages DST (VSS) is supplied.

3, each of the stages ST1 to STn and the dummy stages DST (1) to DST (4) has a forward drive voltage VDD_F of a gate high voltage (VGH) The reverse driving voltage VDD_R of the voltage (VGL) level is supplied. In each of the stages ST1 to STn and the dummy stages DST (1) to DST (4) in the backward shift mode, the reverse drive voltage VDD_R of the gate high voltage (VGH) The forward driving voltage VDD_F of the voltage (VGL) level is supplied. The gate high voltage VGH is set to a voltage equal to or higher than the threshold voltage of the TFTs formed in the TFT array of the display device and the gate low voltage VGL is set to a voltage lower than the threshold voltage of the TFTs formed in the TFT array of the display device. The gate high voltage VGH may be set to about 20V to 30V, and the gate low voltage VGL may be set to about -5V.

2 is an example showing the circuit configuration of the third dummy stage (DST (3)). The circuit configuration of the second dummy stage (DST (2)) and the k-th stage (ST (k)) is substantially the same as that of Fig. Referring to FIG. 2, two gate shift clocks (CLK A and CLK B) generated adjacent to each other among six-phase clocks are input to the clock terminal of the third dummy stage (DST (3)).

The third dummy stage DST3 includes an initialization section 10 for initializing the Q1 node and the Q2 node in response to an initialization signal input to the initialization terminal VRST, first and second input terminals VST1 and VST2, A scan direction controller 20 for switching scan directions in response to signals input through the third and fourth input terminals VNT1 and VNT2, Q1 and Q2 nodes and QB1 and QB2 nodes And an output unit 40 for outputting two pulses according to the voltages of the nodes Q1 and Q2 QB1 and QB2.

The initialization section 10 includes a first initialization TFT Trt1 and a second initialization TFT Trt2. The first initializing TFT Trt1 initializes the node Q1 to the low potential voltage VSS in response to the initialization signal input to the initialization terminal VRST. An initialization pulse RST is input as an initialization signal to the initialization terminals of the second and third dummy stages DST (2) and DST (3). A gate start pulse VST applied from the timing controller is input to the initialization terminal of the k-th stage ST (k) as an initialization signal. The low potential voltage VSS may be set to the ground low voltage GND or the gate low voltage VGL. The gate electrode of the first initializing TFT Trt1 is connected to the initializing terminal VRST, the drain electrode thereof is connected to the node Q1, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS.

The second initializing TFT Trt2 initializes the node Q2 to the low potential voltage VSS in response to the initialization signal input to the initialization terminal VRST. The gate electrode of the second initializing TFT Trt2 is connected to the initializing terminal VRST, the drain electrode thereof is connected to the node Q2, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS.

The scan direction controller 20 includes first through third forward TFTs TF1 through TF3 and first through third reverse TFTs TR1 through TR3. The first forward TFT TF1 applies a forward driving voltage VDD_F to the node Q1 in response to a start signal inputted through the first input terminal VST1. The second n-2 carry signal Vout (2n-2) is input to the third dummy stage DST (3) as a start signal. A gate start pulse VST applied from the timing controller is input to the first forward TFT TF1 of the second dummy stage DST (2) as a start signal. The second k-4 carry signal Vout (2k-4) is input as the start signal to the first forward TFT TF1 of the k-th stage ST (k). The gate electrode of the first forward TFT TF1 is connected to the first input terminal VST1, the drain electrode thereof is connected to the input terminal of the forward drive voltage VDD_F, and the source electrode thereof is connected to the node Q1.

The first reverse TFT (TR1) applies the reverse driving voltage (VDD_R) to the node Q1 in response to the start signal inputted through the third input terminal (VNT1). A gate start pulse (VST) applied from the timing controller is input to the first reverse TFT (TR1) of the third dummy stage (DST (3)) as a start signal. The second carry signal Vout (2) is input to the first reverse TFT (TR1) of the second dummy stage (DST (2)) as a start signal. The second k + 2 carry signal Vout (2k + 2) is input as the start signal to the first reverse TFT (TR1) of the k-th stage ST (k). The gate electrode of the first reverse TFT (TR1) is connected to the third input terminal (VNT1), the drain electrode thereof is connected to the input terminal of the reverse driving voltage (VDD_R), and the source electrode thereof is connected to the node Q1.

The second forward TFT TF2 applies the forward driving voltage VDD_F to the node Q2 in response to the start signal inputted through the second input terminal VST2. The second n-1 carry signal Vout (2n-1) is inputted as the start signal to the second forward TFT TF2 of the third dummy stage DST (3). A gate-start pulse VST applied from the timing controller is input to the second forward TFT TF2 as a start signal. The second forward TFT TF2 of the k-th stage ST (k) The gate electrode of the second forward TFT TF2 is connected to the second input terminal VST2 and the drain electrode is connected to the input terminal of the forward driving voltage VDD_F, The electrode is connected to node Q2.

The second reverse TFT (TR2) applies the reverse driving voltage (VDD_R) to the node Q2 in response to the start signal inputted through the fourth input terminal (VNT2). A gate start pulse (VST) applied from the timing controller is input to the second reverse TFT (TR2) of the third dummy stage (DST (3)) as a start signal. The third carry signal Vout (3) is input as the start signal to the second reverse TFT (TR2) of the second dummy stage (DST (2)). The second k + 3 carry signal Vout (2k + 3) is inputted as the start signal to the second reverse TFT (TR2) of the k-th stage ST (k). The gate electrode of the second reverse TFT (TR2) is connected to the fourth input terminal (VNT2), the drain electrode thereof is connected to the input terminal of the reverse driving voltage (VDD_R), and the source electrode thereof is connected to the node Q2.

The third forward TFT TF3 applies a forward driving voltage VDD_F to the second node N2 in response to a start signal input through the first input terminal VST1. The second n-2 carry signal Vout (2n-2) is input as the start signal to the third forward TFT TF3 of the third dummy stage DST3. A gate start pulse (VST) applied from the timing controller is input to the third forward TFT (TF3) of the second dummy stage (DST (2)) as a start signal. The second k-4 carry signal Vout (2k-4) is inputted as the start signal to the third forward TFT TF3 of the k-th stage ST (k). The gate electrode of the third forward TFT TF3 is connected to the first input terminal VST1, the drain electrode thereof is connected to the input terminal of the forward drive voltage VDD_F and the source electrode thereof is connected to the second node N2.

The third reverse TFT (TR3) applies the reverse driving voltage (VDD_R) to the second node (N2) in response to the start signal inputted through the fourth input terminal (VNT2). A gate start pulse (VST) applied from the timing controller is input to the third reverse TFT (TR3) of the third dummy stage (DST (3)) as a start signal. And the second carry signal Vout (2) is input as a start signal to the third reverse TFT (TR3) of the second dummy stage (DST (2)). The second k + 3 carry signal Vout (2k + 3) is inputted as the start signal to the third reverse TFT TR3 of the k-th stage ST (k). The gate electrode of the third reverse TFT (TR3) is connected to the fourth input terminal (VNT2), the drain electrode thereof is connected to the input terminal of the reverse driving voltage (VDD_R), and the source electrode thereof is connected to the second node (N2).

The node control unit 30 includes first and second TFTs T1 and T2 for controlling the Q1 node, a ninth and tenth TFTs T9 and T10 for controlling the Q2 node, Third to eighth TFTs T3 to T8, and eleventh to sixteenth TFTs T11 to T16 for controlling the QB2 node. The seventh TFT (T7) and the fifteenth TFT (T15) function as discharge TFTs for discharging the nodes QB1 and QB2, respectively. The operation deterioration of the seventh TFT T7 and the fifteenth TFT T15 is reduced to less than half because the QB1 node and the QB2 node are alternately activated in a period of a predetermined period (e.g., a frame period).

The first TFT (T1) discharges the node Q1 to the low potential voltage (VSS) according to the voltage of the node QB2. The gate electrode of the first TFT T1 is connected to the node QB2, the drain electrode thereof is connected to the node Q1, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS. The second TFT T2 discharges the node Q1 to the low potential voltage VSS according to the voltage of the node QB1. The gate electrode of the second TFT T2 is connected to the node QB1, the drain electrode thereof is connected to the node Q1, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS.

The ninth TFT (T9) discharges the node Q2 to the low potential voltage (VSS) according to the voltage of the node QB1. The gate electrode of the ninth TFT T9 is connected to the QB1 node, the drain electrode thereof is connected to the node Q2, and the source electrode thereof is connected to the input terminal of the low potential voltage (VSS). The tenth TFT (T10) discharges the node Q2 to the low potential voltage (VSS) according to the voltage of the node QB2. The gate electrode of the tenth TFT (T10) is connected to the node QB2, the drain electrode to the node Q2, and the source electrode to the input terminal of the low potential voltage (VSS).

The third TFT T3 is diode-connected to apply the odd frame AC drive voltage VDD_O to the first node N1. The gate electrode and the drain electrode of the third TFT T3 are connected to the input terminal of the odd frame AC drive voltage VDD_O and the source electrode thereof is connected to the first node N1. The fourth TFT T4 switches the current path between the input terminals of the first node N1 and the low potential voltage VSS according to the voltage of the node Q1. The gate electrode of the fourth TFT T4 is connected to the node Q1, the drain electrode thereof is connected to the first node N1, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS. The fifth TFT (T5) discharges the node QB1 to the low potential voltage (VSS) according to the voltage of the node Q1. The gate electrode of the fifth TFT (T5) is connected to the node Q1, the drain electrode is connected to the node QB1, and the source electrode is connected to the input terminal of the low potential voltage (VSS). The sixth TFT T6 charges the QB1 node to the odd frame AC drive voltage VDD_O according to the voltage of the first node N1. The gate electrode of the sixth TFT T6 is connected to the first node N1, the drain electrode thereof is connected to the input terminal of the odd frame AC drive voltage VDD_O and the source electrode thereof is connected to the node QB1. The seventh TFT T7 discharges the node QB1 to the low potential voltage VSS according to the voltage of the second node N2. The gate electrode of the seventh TFT T7 is connected to the second node N2, the drain electrode thereof is connected to the node QB1, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS. The eighth TFT T8 switches the current path between the input terminals of the first node N1 and the low potential voltage VSS according to the voltage of the node Q2. The gate electrode of the eighth TFT T8 is connected to the node Q2, the drain electrode thereof is connected to the first node N1, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS.

The eleventh TFT T11 is diode-connected to apply a well frame AC drive voltage VDD_E to the third node N3. The gate electrode and the drain electrode of the eleventh TFT T11 are connected to the input terminal of the excellent frame AC drive voltage VDD_E and the source electrode thereof is connected to the third node N3. The twelfth TFT T12 switches the current path between the input terminal of the third node N3 and the low potential voltage VSS according to the voltage of the node Q2. The gate electrode of the twelfth TFT (T12) is connected to the node Q2, the drain electrode to the third node (N3), and the source electrode to the input terminal of the low potential voltage (VSS). The thirteenth TFT (T13) discharges the node QB2 to the low potential voltage (VSS) according to the voltage of the node Q2. The gate electrode of the thirteenth TFT (T13) is connected to the node Q2, the drain electrode is connected to the node QB2, and the source electrode is connected to the input terminal of the low potential voltage (VSS). The fourteenth TFT T14 charges the QB2 node to the excellent frame AC drive voltage VDD_E according to the voltage of the third node N3. The gate electrode of the fourteenth TFT T14 is connected to the third node N3, the drain electrode thereof is connected to the input terminal of the even frame AC drive voltage VDD_E and the source electrode thereof is connected to the node QB2. The fifteenth TFT T15 discharges the node QB2 to the low potential voltage VSS according to the voltage of the second node N2. The gate electrode of the fifteenth TFT T15 is connected to the second node N2, the drain electrode thereof is connected to the node QB2, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS. The sixteenth TFT T16 switches the current path between the input terminals of the third node N3 and the low potential voltage VSS according to the voltage of the node Q1. The gate electrode of the sixteenth TFT T16 is connected to the node Q1, the drain electrode thereof is connected to the third node N3, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS.

The output section 40 of the third dummy stage DST 3 includes a first output section for generating the fourth dummy pulse Dout (4) and a second output section for generating the fifth dummy pulse Dout (5) 2 output unit. The output section 40 of the second dummy stage DST 2 includes a first output section for generating the second dummy pulse Dout (2) and a second output section for generating the third dummy pulse Dout (3) 2 output unit. The output section 40 of the k-th stage ST (k) includes a first output section for generating the second k-1 scan pulse Vout (2k-1) and a second output section for generating the second k-th scan pulse Vout (2k) Lt; / RTI &gt;

The first output section is turned on according to the voltage of the first pull-up TFT (TU1), QB1, which is turned on according to the voltage of the node Q1 to charge the first output node NO1 to the gate shift clock (CLK A) The first pull-down TFT TD11 for discharging the first output node NO1 to the low potential voltage VSS and the first pull-down TFT TD11 for turning on the first output node NO1 according to the voltage of the QB2 node, And a second pull-down TFT (TD12) for discharging the first pull-down TFT (VSS).

The first pull-up TFT TU1 is turned on due to the bootstrapping of the node Q1, thereby charging the first output node NO1 with the gate shift clock CLK A to generate the output of the first output portion. The gate electrode of the first pull-up TFT TU1 is connected to the node Q1, the drain electrode thereof is connected to the input terminal of the gate shift clock CLK A, and the source electrode thereof is connected to the first output node NO1. The 1-1 and 1-2 pull-down TFTs TD11 and TD12 are driven according to the voltages of the QB1 node and the QB2 node so that the dummy pulse or the 2k-1 scan pulse Vout (2k-1) 1 discharge node NO1 to the low potential voltage VSS. The gate electrode of the 1-1 pull-down TFT (TD11) is connected to the QB1 node, the drain electrode to the first output node (NO1), and the source electrode to the input terminal of the low potential voltage (VSS). The gate electrode of the first-second pull-down TFT (TD12) is connected to the node QB2, the drain electrode to the first output node (NO1), and the source electrode to the input terminal of the low potential voltage (VSS).

The fourth dummy pulse Dout (4) of the third dummy stage DST (3) is supplied as a carry signal to the fourth input terminal VNT2 of the (n-1) th stage ST (n-1). The second dummy pulse Dout (2) of the second dummy stage DST (2) is supplied as a carry signal to the second input terminal VST2 of the first stage ST (1). The second k-1 scan pulse Vout (2k-1) of the k-th stage ST (k) is supplied to the fourth input terminal VNT2 of the (k-2) th stage ST Is supplied as a carry signal to the second input terminal VST2 of the +1 stage ST (k + 1). The second k-1 scan pulse Vout (2k-1) generated from the k-th stage ST (k) is supplied to the corresponding scan line through the first output channel CH1.

The second output section is turned on according to the voltage of the node QB1, the second pull-up TFT (TU2) which is turned on according to the voltage of the node Q2 to charge the second output node NO2 to the gate shift clock CLK B A second -1 pull-down TFT (TD21) for discharging the second output node (NO2) to the low potential voltage (VSS), and a second output node (NO2) Pull-down TFT &lt; RTI ID = 0.0 &gt; (TD22) &lt; / RTI &gt;

The second pull-up TFT TU2 is turned on due to the bootstrapping of the Q2 node, thereby charging the second output node NO2 with the gate shift clock CLK B to generate the dummy pulse or the second k-th scan pulse Vout (2k) ). The gate electrode of the second pull-up TFT (TU2) is connected to the node Q2, the drain electrode is connected to the input terminal of the gate shift clock (CLK B), and the source electrode is connected to the second output node (NO2). The 2-1 and 2-2 pull-down TFTs TD21 and TD22 are connected to the second output node NO2 (2k) according to the voltage of the QB1 node and the QB2 node, respectively, so that the dummy pulse or the second k- ). The gate electrode of the second -1 pull-down TFT (TD21) is connected to the node QB1, the drain electrode to the second output node (NO2), and the source electrode to the input terminal of the low potential voltage (VSS). The gate electrode of the second pull-down TFT (TD22) is connected to the node QB2, the drain electrode thereof is connected to the second output node (NO2), and the source electrode thereof is connected to the input terminal of the low potential voltage (VSS).

The fifth dummy pulse Dout (5) of the third dummy stage DST (3) is supplied as a carry signal to the third input terminal VNT1 of the (n-1) th stage ST (n-1). The third dummy pulse Dout (3) of the second dummy stage DST (2) is supplied as a carry signal to the first input terminal VST1 of the second stage ST (2). The second k-th scan pulse Vout (2k) of the k-th stage ST (k) is supplied to the third input terminal VNT1 of the (k-1) th stage ST ST (k + 2)) as a carry signal to the first input terminal VST1. The second k-th scan pulse Vout (2k) generated from the k-th stage ST (k) is supplied to the corresponding scan line through the second output channel (CH2).

Fig. 3 shows the input and output signals of the third dummy stage (DST (3)) in the forward shift operation. The forward shift operation of the third dummy stage (DST (3)) will be described step by step with reference to FIGS. 2 and 3. FIG.

2 and 3, a forward gate start pulse (VST) is generated in forward shift mode, and six-phase gate shift clocks (CLK1 to CLK6) are generated from a first gate shift clock (CLK1) (CLK6). &Lt; / RTI &gt; In the forward shift mode, the forward drive voltage VDD_F is input to the gate high voltage (VGH) level, and the reverse drive voltage (VDD_R) is input to the gate low voltage (VGL) level. In the forward shift mode, "CLK A" input to the third dummy stage (DST (3)) is assumed to be "CLK 1" and "CLK B" is assumed to be "CLK 2".

First, it is explained that the third dummy stage (DST (3)) operates in odd frame in the forward shift mode. Here, the odd frame may include a single frame arranged at odd-numbered positions and a group of frames arranged at odd-numbered positions including a plurality of adjacent frames. In the odd frame, the odd frame AC drive voltage VDD_O is input to the gate high voltage (VGH) level and the even frame AC drive voltage VDD_E is input to the gate low voltage (VGL) level. Further, in the odd frame, the QB2 node continues to be maintained at the gate-low voltage (VGL) level. Therefore, the TFTs (T1, T10, TD12, and TD22) to which the gate electrode is connected to the QB2 node are kept in the turn-off state (that is, kept in the idle driving state). In Fig. 3, "VQ1" represents the potential of the Q1 node, "VQ2" represents the potential of the Q2 node, "VQB1" represents the potential of the QB1 node, and "VQB2" represents the potential of the QB2 node.

2 carry signal Vout (2n-2) is input as a start signal through the first input terminal VST1 at time T1. In response to the second n-2 carry signal Vout (2n-2) 1 and the third forward TFT TF1, TF3 are turned on. As a result, the node Q1 is charged to the gate high voltage VGH and the node QB1 is discharged to the gate low voltage VGL.

At time T2, the second n-1 carry signal Vout (2n-1) is input as a start signal via the second input terminal VST2. The second forward TFT TF2 is turned on in response to the (2n-1) -th carry signal Vout (2n-1). As a result, the node Q2 is charged with the gate high voltage VGH. The Q1 node maintains the gate high voltage (VGH), and the QB1 node maintains the gate low voltage (VGL).

At time T3, the node Q1 maintains the gate high voltage VGH and the node Q2 maintains the gate high voltage VGH. The QB1 node maintains the gate-low voltage (VGL).

At time T4, the first gate shift clock (CLK1) is applied to the drain electrode of the first pull-up TFT (TU1). The voltage of the node Q1 is raised to a voltage level VGH 'higher than the gate high voltage VGH by being bootstrapped by the parasitic capacitance between the gate-drain electrodes of the first pull-up TFT TU1, TU1). Therefore, at time T4, the voltage of the first output node NO1 rises to the gate high voltage VGH to rise the fourth dummy pulse Dout (4). The Q2 node maintains the gate high voltage (VGH), and the QB1 node maintains the gate low voltage (VGL).

At time T5, the second gate shift clock signal CLK2 is applied to the drain electrode of the second pull-up TFT TU2. The voltage of the node Q2 is raised to the voltage level VGH 'higher than the gate high voltage VGH by being bootstrapped by the parasitic capacitance between the gate-drain electrodes of the second pull-up TFT TU2, TU2). Therefore, at time T5, the voltage of the second output node NO2 rises to the gate high voltage VGH to raise the fifth dummy pulse Dout 5. The Q1 node maintains the gate high voltage VGH, The QB1 node maintains the gate-low voltage (VGL).

At times T6 and T7, the node Q1 maintains the gate high voltage VGH and the node Q2 maintains the gate high voltage VGH. The QB1 node maintains the gate-low voltage (VGL).

At time T8, the initialization pulse RST is input as the initialization signal via the initialization terminal VRST. The first initializing TFT (Trt1) is turned on in response to the initialization pulse (RST). As a result, the node Q1 is discharged to the gate-low voltage VGL. The first pull-up TFT (TU1) is turned off due to the discharge of the node Q1. Therefore, the fourth dummy pulse Dout (4) is polled to the gate low voltage VGL.

Further, the second initializing TFT (Trt2) is turned on in response to the initialization pulse (RST). As a result, the node Q2 is discharged to the gate-low voltage VGL. The second pull-up TFT (TU2) is turned off due to the discharge of the node Q2. Therefore, the fifth dummy pulse Dout (5) is polled to the gate-low voltage VGL.

The fourth TFT T4, the fifth TFT T5, the eighth TFT T8, the twelfth TFT T12, the thirteenth TFT T13 and the fourteenth TFT T14 due to the discharge of the node Q1 and the node Q2. Is turned off, the QB1 node is charged with the odd frame AC drive voltage VDD_O of the gate high voltage (VGH) level applied through the sixth TFT T6. The first and second pull-down TFTs (TD11 and TD21) are turned on due to the charging of the QB1 node. Thus, the voltage of the first output node NO1 falls to the gate low voltage VGL to keep the fourth dummy pulse Dout (4) at the gate low voltage VGL. The voltage of the second output node NO2 falls to the gate-low voltage VGL to keep the fifth dummy pulse Dout (5) at the gate-low voltage VGL.

Next, it is explained that the third dummy stage (DST (3)) operates in the even frame in the forward shift mode. Here, an even frame may include a single frame arranged at the even-numbered frame and a frame group arranged at the even-numbered frame including a plurality of adjacent frames. In the excellent frame, the excellent frame alternating drive voltage VDD_E is input to the gate high voltage (VGH) level and the odd frame alternating drive voltage VDD_O is input to the gate low voltage (VGL) level. In addition, the QB1 node continues to be maintained at the gate-low voltage (VGL) level. Therefore, the TFTs T2, T9, TD11, and TD21 to which the gate electrode is connected to the QB1 node are kept in the turn-off state (i.e., kept in the idle driving state).

The operation in the even frame is different from the operation in the odd frame only in that the voltage of the output nodes NO1 and NO2 is controlled by the QB2 node. The operation of the fourth dummy pulse Dout (4) 5 The timing of generation of the dummy pulse Dout (5) is substantially the same as in the odd frame. Therefore, detailed description of the operation in the even frame will be omitted.

In the forward shift mode, the second dummy stage DST (2) is different from the first embodiment in that the forward gate start pulse VST is input as the start signal to the first and second input terminals VST1 and VST2, And the outputs of the third dummy pulses DST (2) and DST (3) are as described in the third dummy stage DST (3).

Further, in the forward shift mode, the k-th stage ST (k) receives the second k + 2 carry signal Vout (2k + 2) as a reset signal at the third input terminal VNT3, The third dummy stage DST3 differs from the third dummy stage DST3 in that the second k + 3 carry signal Vout (2k + 3) is input as a reset signal to the third dummy stage VNT4. The kth stage ST (k) differs from the third dummy stage DST (3) in that the gate start pulse VST is input as an initialization signal to the initialization terminal VRST. Although the operation of the k-th stage ST (k) differs slightly from the operation of the third dummy stage DST (3) due to the difference of the input signals, the output of the scan pulse is supplied to the third dummy stage DST (3) Respectively.

FIG. 4 shows the input and output signals of the second dummy stage DST (2) during the backward shift operation. The backward shift operation of the second dummy stage (DST (2)) will be described step by step with reference to FIGS. 2 and 4. FIG.

2 and 4, a reverse gate start pulse VST is generated in the backward shift mode, and the six-phase gate shift clocks CLK1 to CLK6 are generated from the sixth gate shift clock CLK6 to the first gate shift clock (CLK1). &Lt; / RTI &gt; In the reverse shift mode, the reverse drive voltage VDD_R is input to the gate high voltage VGH level, and the forward drive voltage VDD_F is input to the gate low voltage VGL level. In the backward shift mode, "CLK A" input to the second dummy stage DST (2) is assumed to be "CLK 5" and "CLK B" is assumed to be "CLK 6".

First, the operation of the second dummy stage DST (2) in the odd frame in the backward shift mode will be described. Here, the odd frame may include a single frame arranged at odd-numbered positions and a group of frames arranged at odd-numbered positions including a plurality of adjacent frames. In the odd frame, the odd frame AC drive voltage VDD_O is input to the gate high voltage (VGH) level and the even frame AC drive voltage VDD_E is input to the gate low voltage (VGL) level. Further, in the odd frame, the QB2 node continues to be maintained at the gate-low voltage (VGL) level. Therefore, the TFTs (T1, T10, TD12, and TD22) to which the gate electrode is connected to the QB2 node are kept in the turn-off state (that is, kept in the idle driving state). In Fig. 3, "VQ1" represents the potential of the Q1 node, "VQ2" represents the potential of the Q2 node, "VQB1" represents the potential of the QB1 node, and "VQB2" represents the potential of the QB2 node.

At time T1, the third carry signal Vout (3) is input as a start signal via the fourth input terminal VNT2. The second and third reverse TFTs TR2 and TR3 are turned on in response to the third carry signal Vout (3). As a result, the node Q2 is charged to the gate high voltage VGH, and the node QB1 is discharged to the gate low voltage VGL.

At time T2, the second carry signal Vout (2) is input as a start signal via the third input terminal VST3. The first reverse TFT (TR1) is turned on in response to the second carry signal (Vout (2)). As a result, the node Q1 is charged to the gate high voltage VGH. The Q1 node maintains the gate high voltage (VGH), and the QB1 node maintains the gate low voltage (VGL).

At time T3, the node Q1 maintains the gate high voltage VGH and the node Q2 maintains the gate high voltage VGH. The QB1 node maintains the gate-low voltage (VGL).

At time T4, the sixth gate shift clock CLK6 is applied to the drain electrode of the second pull-up TFT TU2. The voltage of the node Q2 is raised to the voltage level VGH 'higher than the gate high voltage VGH by being bootstrapped by the parasitic capacitance between the gate-drain electrodes of the second pull-up TFT TU2, TU2). Thus, at time T4, the voltage of the second output node NO2 rises to the gate high voltage VGH to rise the third dummy pulse Dout (3). The Q1 node maintains the gate high voltage (VGH), and the QB1 node maintains the gate low voltage (VGL).

At time T5, the fifth gate shift clock (CLK5) is applied to the drain electrode of the first pull-up TFT (TU1). The voltage of the node Q1 is raised to a voltage level VGH 'higher than the gate high voltage VGH by being bootstrapped by the parasitic capacitance between the gate-drain electrodes of the first pull-up TFT TU1, TU1). Therefore, at time T5, the voltage of the first output node NO1 rises to the gate high voltage VGH to raise the second dummy pulse Dout (2). The node Q2 maintains the gate high voltage VGH, The QB1 node maintains the gate-low voltage (VGL).

At times T6 and T7, the node Q1 maintains the gate high voltage VGH and the node Q2 maintains the gate high voltage VGH. The QB1 node maintains the gate-low voltage (VGL).

At time T8, the initialization pulse RST is input as the initialization signal via the initialization terminal VRST. The second initializing TFT (Trt2) is turned on in response to the initialization pulse (RST). As a result, the node Q2 is discharged to the gate-low voltage VGL. The second pull-up TFT (TU2) is turned off due to the discharge of the node Q2. Therefore, the third dummy pulse Dout (3) is polled to the gate-low voltage VGL.

In addition, the first initializing TFT Trt1 is turned on in response to the initialization pulse RST. As a result, the node Q1 is discharged to the gate-low voltage VGL. The first pull-up TFT (TU1) is turned off due to the discharge of the node Q1. Therefore, the second dummy pulse Dout (2) is polled to the gate low voltage VGL.

The fourth TFT T4, the fifth TFT T5, the eighth TFT T8, the twelfth TFT T12, the thirteenth TFT T13 and the fourteenth TFT T14 due to the discharge of the node Q1 and the node Q2. Is turned off, the QB1 node is charged with the odd frame AC drive voltage VDD_O of the gate high voltage (VGH) level applied through the sixth TFT T6. The first and second pull-down TFTs (TD11 and TD21) are turned on due to the charging of the QB1 node. Thus, the voltage of the second output node NO2 falls to the gate low voltage VGL to keep the third dummy pulse Dout (3) at the gate low voltage VGL. The voltage of the first output node NO1 falls to the gate low voltage VGL to maintain the second dummy pulse Dout (2) at the gate low voltage VGL.

Next, it is explained that the second dummy stage DST (2) operates in the even frame in the backward shift mode. Here, an even frame may include a single frame arranged at the even-numbered frame and a frame group arranged at the even-numbered frame including a plurality of adjacent frames. In the excellent frame, the excellent frame alternating drive voltage VDD_E is input to the gate high voltage (VGH) level and the odd frame alternating drive voltage VDD_O is input to the gate low voltage (VGL) level. In addition, the QB1 node continues to be maintained at the gate-low voltage (VGL) level. Therefore, the TFTs T2, T9, TD11, and TD21 to which the gate electrode is connected to the QB1 node are kept in the turn-off state (i.e., kept in the idle driving state).

The operation in the even frame is different from the operation in the odd frame only in that the voltage of the output nodes NO1 and NO2 is controlled by the QB2 node and the second dummy pulse Dout (2) The timing of generation of the three dummy pulses (Dout (3)) is substantially the same as in the odd frame. Therefore, detailed description of the operation in the even frame will be omitted.

In the backward shift mode, the third dummy stage DST (3) differs from the third and fourth input terminals VNT1 and VNT2 in that the gate start pulse VST is input as the start signal. The output of the fifth dummy pulse DST (4), DST (5)) is as described in the second dummy stage DST (2).

Further, in the backward shift mode, the k-th stage ST (k) receives the second k-4 carry signal Vout (2k-4) as a reset signal at the first input terminal VST1, (2) is different from the second dummy stage DST (2) in that the second k-3 carry signal Vout (2k-3) is input as a reset signal to the first dummy stage VST2. The kth stage ST (k) differs from the second dummy stage DST (2) in that the gate start pulse VST is input as an initialization signal to the initialization terminal VRST. Although the operation of the second dummy stage DST (2) is slightly different from that of the second dummy stage (DST (2)) due to the difference of the inputted signals, the kth stage ST (k) ).

5 is a circuit diagram showing a circuit configuration of the fourth dummy stage (DST (4)). The circuit configuration of the first dummy stage (DST (1)) is substantially the same as that of Fig. Referring to FIG. 5, one of the six-phase clocks CLK A and CLK B is input to the clock terminal of the fourth dummy stage DST (4).

The fourth dummy stage (DST (4)) includes an initialization section (10) for initializing a Q node in response to an initialization signal input to an initialization terminal (VRST), a signal input via a first input terminal A scan direction controller 20 for switching the scan direction in response to signals input through the input terminal VNT1, a node controller 30 for controlling charging and discharging of the Q node, QB1 and QB2 nodes, And an output unit 40 for outputting a dummy pulse Dout (6) in accordance with the voltages of the transistors Q, QB1 and QB2.

The initialization unit 10 includes an initialization TFT Trt. The initialization TFT Trt initializes the Q node to the low potential voltage VSS in response to the initialization signal input to the initialization terminal VRST. The low potential voltage VSS may be set to the ground low voltage GND or the gate low voltage VGL. The gate electrode of the initialization TFT Trt is connected to the initialization terminal VRST, the drain electrode is connected to the Q node, and the source electrode thereof is connected to the input terminal of the low potential voltage (VSS).

The scan direction controller 20 includes first and second forward TFTs TF1 and TF2 and first and second reverse TFTs TR1 and TR2. The first forward TFT TF1 applies a forward driving voltage VDD_F to the Q node in response to a start signal input through the first input terminal VST1. The second n-carry signal Vout (2n) is input to the first forward TFT TF1 of the fourth dummy stage DST (4) as a start signal. A gate start pulse VST applied from the timing controller is input to the first forward TFT TF1 of the second dummy stage DST (2) as a start signal. The gate electrode of the first forward TFT TF1 is connected to the first input terminal VST1, the drain electrode thereof is connected to the input terminal of the forward driving voltage VDD_F and the source electrode thereof is connected to the Q node.

The first reverse TFT (TR1) applies a reverse driving voltage (VDD_R) to the Q node in response to a start signal inputted through the second input terminal (VNT1). A gate start pulse (VST) applied from the timing controller is input to the first reverse TFT (TR1) of the fourth dummy stage (DST (4)) as a start signal. The first carry signal Vout (1) is input as the start signal to the first reverse TFT (TR1) of the first dummy stage (DST (1)). The gate electrode of the first reverse TFT (TR1) is connected to the second input terminal (VNT1), the drain electrode thereof is connected to the input terminal of the reverse driving voltage (VDD_R), and the source electrode thereof is connected to the node Q1.

The second forward TFT TF2 applies a forward driving voltage VDD_F to the second node N2 in response to a start signal input through the first input terminal VST1. The second n-carry signal Vout (2n) is input to the second forward TFT TF2 of the fourth dummy stage DST (4) as a start signal. A gate start pulse (VST) applied from the timing controller is input to the second forward TFT (TF2) of the first dummy stage (DST (1)) as a start signal. The gate electrode of the second forward TFT TF2 is connected to the first input terminal VST1, the drain electrode thereof is connected to the input terminal of the forward drive voltage VDD_F and the source electrode thereof is connected to the second node N2.

The second reverse TFT (TR2) applies a reverse driving voltage (VDD_R) to the second node (N2) in response to a start signal inputted through the second input terminal (VNT1). A gate start pulse (VST) applied from the timing controller is input to the second reverse TFT (TR2) of the fourth dummy stage (DST (4)) as a start signal. The first carry signal Vout (1) is input to the second reverse TFT (TR2) of the first dummy stage (DST (1)) as a start signal. The gate electrode of the second reverse TFT (TR2) is connected to the second input terminal (VNT1), the drain electrode thereof is connected to the input terminal of the reverse driving voltage (VDD_R), and the source electrode thereof is connected to the second node (N2).

The node control unit 30 includes first and second TFTs T1 and T2 for controlling the Q node, third to seventh TFTs T3 to T7 for controlling the QB1 node, And the eighth to twelfth TFTs T8 to T12. The seventh TFT (T7) and the twelfth TFT (T12) function as discharge TFTs for discharging the nodes QB1 and QB2, respectively. The operation deterioration of the seventh TFT T7 and the twelfth TFT T12 is reduced to less than half because the QB1 node and the QB2 node are alternately activated in a period of a predetermined period (e.g., a frame period).

The first TFT (T1) discharges the Q node to the low potential voltage (VSS) according to the voltage of the QB2 node. The gate electrode of the first TFT (T1) is connected to the QB2 node, the drain electrode is connected to the Q node, and the source electrode is connected to the input terminal of the low potential voltage (VSS). The second TFT T2 discharges the Q node to the low potential voltage VSS according to the voltage of the QB1 node. The gate electrode of the second TFT T2 is connected to the QB1 node, the drain electrode thereof is connected to the Q node, and the source electrode thereof is connected to the input terminal of the low potential voltage (VSS).

The third TFT T3 is diode-connected to apply the odd frame AC drive voltage VDD_O to the first node N1. The gate electrode and the drain electrode of the third TFT T3 are connected to the input terminal of the odd frame AC drive voltage VDD_O and the source electrode thereof is connected to the first node N1. The fourth TFT T4 switches the current path between the input terminal of the first node N1 and the low potential voltage VSS according to the voltage of the Q node. The gate electrode of the fourth TFT T4 is connected to the Q node, the drain electrode to the first node N1, and the source electrode to the input terminal of the low potential voltage VSS. The fifth TFT (T5) discharges the QB1 node to the low potential voltage (VSS) according to the voltage of the Q node. The gate electrode of the fifth TFT (T5) is connected to the Q node, the drain electrode to the QB1 node, and the source electrode to the input terminal of the low potential voltage (VSS). The sixth TFT T6 charges the QB1 node to the odd frame AC drive voltage VDD_O according to the voltage of the first node N1. The gate electrode of the sixth TFT T6 is connected to the first node N1, the drain electrode thereof is connected to the input terminal of the odd frame AC drive voltage VDD_O and the source electrode thereof is connected to the node QB1. The seventh TFT T7 discharges the node QB1 to the low potential voltage VSS according to the voltage of the second node N2. The gate electrode of the seventh TFT T7 is connected to the second node N2, the drain electrode thereof is connected to the node QB1, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS.

The gate electrode and the drain electrode of the eighth TFT T8 are connected to the input terminal of the excellent frame alternating drive voltage VDD_E and the source electrode thereof is connected to the third node N3. The ninth TFT T9 switches the current path between the input terminal of the third node N3 and the low potential voltage VSS according to the voltage of the Q node. The gate electrode of the ninth TFT T9 is connected to the Q node, the drain electrode to the third node N3, and the source electrode to the input terminal of the low potential voltage VSS. The tenth TFT (T10) discharges the QB2 node to the low potential voltage (VSS) according to the voltage of the Q node. The gate electrode of the tenth TFT (T10) is connected to the Q node, the drain electrode to the QB2 node, and the source electrode to the input terminal of the low potential voltage (VSS). The eleventh TFT T11 charges the QB2 node to the even frame AC driving voltage VDD_E according to the voltage of the third node N3. The gate electrode of the eleventh TFT (T11) is connected to the third node (N3), the drain electrode is connected to the input terminal of the even frame AC drive voltage (VDD_E), and the source electrode is connected to the node QB2. The twelfth TFT T12 discharges the node QB2 to the low potential voltage VSS according to the voltage of the second node N2. The gate electrode of the twelfth TFT T12 is connected to the second node N2, the drain electrode thereof is connected to the node QB2, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS.

The output section 40 of the fourth dummy stage DST (4) includes an output section for generating the sixth dummy pulse Dout (6). The output section 40 of the first dummy stage DST (1) includes an output section for generating the first dummy pulse Dout (1).

The output section is a pull-up TFT (TU) which is turned on according to the voltage of the Q node to charge the output node NO to the gate shift clock (CLK A), a turn-on transistor A first pull-down TFT (TD1) for discharging to a low potential voltage (VSS) and a second pull-down TFT (TD2) for turning on the output node NO according to the voltage of the node QB2 to discharge the output node (NO) .

The pull-up TFT (TU) is turned on due to the bootstrapping of the Q node, thereby charging the output node (NO) with the gate shift clock (CLK A) to generate the output of the output section. The gate electrode of the pull-up TFT (TU) is connected to the Q node, the drain electrode thereof is connected to the input terminal of the gate shift clock (CLK A), and the source electrode thereof is connected to the output node (NO). The first and second pull-down TFTs TD1 and TD2 turn the output node NO to the low potential voltage VSS according to the voltages of the QB1 node and the QB2 node so that the sixth dummy pulse DST (6) Discharge. The gate electrode of the first pull-down TFT TD1 is connected to the node QB1, the drain electrode thereof is connected to the output node NO, and the source electrode thereof is connected to the input terminal of the low potential voltage VSS. The gate electrode of the second pull-down TFT (TD2) is connected to the node QB2, the drain electrode thereof is connected to the output node (NO), and the source electrode thereof is connected to the input terminal of the low potential voltage (VSS).

The sixth dummy pulse Dout 6 of the fourth dummy stage DST 4 is supplied as a carry signal to the fourth input terminal VNT2 of the nth stage ST (n). The first dummy pulse Dout (1) of the first dummy stage DST (1) is supplied as a carry signal to the first input terminal VST1 of the first stage ST (1).

6 is a waveform diagram showing the input and output signals of the fourth dummy stage (DST (4)) during the forward shift operation. The forward shift operation of the fourth dummy stage (DST (4)) will be described step by step with reference to FIGS. 5 and 6. FIG.

5 and 6, a forward gate start pulse VST is generated in the forward shift mode, and the six-phase gate shift clocks CLK1 to CLK6 are generated from the first gate shift clock CLK1 to the sixth gate shift clock CLK1, (CLK6). &Lt; / RTI &gt; In the forward shift mode, the forward drive voltage VDD_F is input to the gate high voltage (VGH) level, and the reverse drive voltage (VDD_R) is input to the gate low voltage (VGL) level. In the forward shift mode, "CLK A" input to the fourth dummy stage (DST (4)) is assumed to be "CLK 3".

First, it is explained that the fourth dummy stage (DST (4)) operates in odd frame in the forward shift mode. Here, the odd frame may include a single frame arranged at odd-numbered positions and a group of frames arranged at odd-numbered positions including a plurality of adjacent frames. In the odd frame, the odd frame AC drive voltage VDD_O is input to the gate high voltage (VGH) level and the even frame AC drive voltage VDD_E is input to the gate low voltage (VGL) level. Further, in the odd frame, the QB2 node continues to be maintained at the gate-low voltage (VGL) level. Therefore, the TFTs T1 and TD2 to which the gate electrode is connected to the QB2 node are kept in the turn-off state (that is, kept in the idle driving state). In Fig. 3, "VQ1" represents the potential of the Q1 node, "VQB1" represents the potential of the QB1 node, and "VQB2" represents the potential of the QB2 node.

In the T1 time, the 2n carry signal Vout (2n) is inputted as the start signal through the first input terminal VST1. In response to the 2n carry signal Vout (2n), the first and third forward TFTs TF1 , TF3 are turned on. As a result, the Q node is charged to the gate high voltage VGH, and the QB1 node is discharged to the gate low voltage VGL.

At times T2 and T3, the Q node holds the gate high voltage (VGH) and the QB1 node holds the gate low voltage (VGL).

At time T4, the third gate shift clock (CLK3) is applied to the drain electrode of the pull-up TFT (TU). The voltage of the Q node is boosted to a voltage level VGH 'higher than the gate high voltage VGH by bootstrapping by the parasitic capacitance between the gate-drain electrodes of the pull-up TFT TU, - Turn it on. Thus, at time T4, the voltage of the output node NO rises to the gate high voltage VGH and rises the sixth dummy pulse Dout (6). The QB1 node maintains the gate-low voltage (VGL).

At time T5, since the third gate shift clock signal CLK3 is no longer applied to the drain electrode of the pull-up TFT TU, the voltage of the Q node maintains the gate high voltage and the pull-up TFT TU is turned off. Thus, the sixth dummy pulse Dout (6) is polled to the gate-low voltage VGL. The QB1 node maintains the gate-low voltage (VGL).

At time T6, an initialization pulse RST is input as an initialization signal via the initialization terminal VRST. The initializing TFT Trt is turned on in response to the initialization pulse RST. As a result, the Q node is discharged to the gate low voltage VGL.

Since the fourth TFT T4, the fifth TFT T5, the ninth TFT T9 and the tenth TFT T10 are turned off due to the discharge of the Q node, the node QB1 is connected to the sixth TFT T6 (VDD_O) of the gate high voltage (VGH) level applied through the gate driver circuit (not shown). The first pull-down TFT (TD1) is turned on due to the charging of the QB1 node. Thus, the voltage of the output node NO falls to the gate-low voltage VGL to maintain the sixth dummy pulse Dout (6) at the gate-low voltage VGL.

Next, it is explained that the fourth dummy stage (DST (4)) operates in the even frame in the forward shift mode. Here, an even frame may include a single frame arranged at the even-numbered frame and a frame group arranged at the even-numbered frame including a plurality of adjacent frames. In the excellent frame, the excellent frame alternating drive voltage VDD_E is input to the gate high voltage (VGH) level and the odd frame alternating drive voltage VDD_O is input to the gate low voltage (VGL) level. In addition, the QB1 node continues to be maintained at the gate-low voltage (VGL) level. Therefore, the TFTs T2 and TD2 to which the gate electrode is connected to the QB1 node are kept in the turn-off state (i.e., kept in the idle driving state).

The operation in the even frame is different from the operation in the odd frame only in that the voltage of the output nodes NO is controlled by the QB2 node and the timing of generation of the sixth dummy pulse Dout (6) Substantially the same as in the radix frame. Therefore, detailed description of the operation in the even frame will be omitted.

In the forward shift mode, the first dummy stage DST (1) differs from the first dummy stage DST (1) only in that a gate start pulse VST is inputted as a start signal to the first input terminal VST1, ) Is the same as that described in the fourth dummy stage DST (4).

7 is a waveform diagram showing the input and output signals of the first dummy stage DST (1) in the backward shift operation. The backward shift operation of the first dummy stage (DST (1)) will be described step by step with reference to FIGS. 5 and 7. FIG.

5 and 7, a reverse gate start pulse VST is generated in the reverse shift mode, and the six-phase gate shift clocks CLK1 to CLK6 are generated from the sixth gate shift clock CLK6 to the first gate shift clock CLK6, (CLK1). &Lt; / RTI &gt; In the reverse shift mode, the reverse drive voltage VDD_R is input to the gate high voltage VGH level, and the forward drive voltage VDD_F is input to the gate low voltage VGL level. In the reverse shift mode, "CLK A" input to the first dummy stage (DST (1)) is assumed to be "CLK 3".

First, it is explained that the first dummy stage (DST (1)) operates in an odd frame in the backward shift mode. Here, the odd frame may include a single frame arranged at odd-numbered positions and a group of frames arranged at odd-numbered positions including a plurality of adjacent frames. In the odd frame, the odd frame AC drive voltage VDD_O is input to the gate high voltage (VGH) level and the even frame AC drive voltage VDD_E is input to the gate low voltage (VGL) level. Further, in the odd frame, the QB2 node continues to be maintained at the gate-low voltage (VGL) level. Therefore, the TFTs T1 and TD1 to which the gate electrode is connected to the QB2 node are kept in the turn-off state (that is, kept in the idle driving state). In Fig. 3, "VQ" represents the potential of the Q node, "VQB1" represents the potential of the QB1 node, and "VQB2" represents the potential of the QB2 node.

At time T1, the first carry signal Vout (1) is input as a start signal via the second input terminal VNT1. The second and third reverse TFTs TR2 and TR3 are turned on in response to the first carry signal Vout 1. As a result, the Q node is charged to the gate high voltage VGH, And is discharged to the low voltage VGL.

At times T2 and T3, the Q node holds the gate high voltage (VGH) and the QB1 node holds the gate low voltage (VGL).

At time T4, the third gate shift clock (CLK3) is applied to the drain electrode of the pull-up TFT (TU). The voltage of the Q node is boosted to a voltage level VGH 'higher than the gate high voltage VGH by bootstrapping by the parasitic capacitance between the gate-drain electrodes of the pull-up TFT TU, - Turn it on. Thus, at time T4, the voltage of the output node NO rises to the gate high voltage VGH and rises the sixth dummy pulse Dout (6). The QB1 node maintains the gate-low voltage (VGL).

At time T5, since the third gate shift clock signal CLK3 is no longer applied to the drain electrode of the pull-up TFT TU, the voltage of the Q node maintains the gate high voltage and the pull-up TFT TU is turned off. Thus, the sixth dummy pulse Dout (6) is polled to the gate-low voltage VGL. The QB1 node maintains the gate-low voltage (VGL).

At time T6, an initialization pulse RST is input as an initialization signal via the initialization terminal VRST. The initializing TFT Trt is turned on in response to the initialization pulse RST. As a result, the Q node is discharged to the gate low voltage VGL.

Since the fourth TFT T4, the fifth TFT T5, the ninth TFT T9 and the tenth TFT T10 are turned off due to the discharge of the Q node, the node QB1 is connected to the sixth TFT T6 (VDD_O) of the gate high voltage (VGH) level applied through the gate driver circuit (not shown). The first pull-down TFT (TD1) is turned on due to the charging of the QB1 node. Thus, the voltage of the output node NO falls to the gate-low voltage VGL to maintain the sixth dummy pulse Dout (6) at the gate-low voltage VGL.

Next, it is explained that the first dummy stage DST (1) operates in the even frame in the backward shift mode. Here, an even frame may include a single frame arranged at the even-numbered frame and a frame group arranged at the even-numbered frame including a plurality of adjacent frames. In the excellent frame, the excellent frame alternating drive voltage VDD_E is input to the gate high voltage (VGH) level and the odd frame alternating drive voltage VDD_O is input to the gate low voltage (VGL) level. In addition, the QB1 node continues to be maintained at the gate-low voltage (VGL) level. Therefore, the TFTs T2 and TD2 to which the gate electrode is connected to the QB1 node are kept in the turn-off state (i.e., kept in the idle driving state).

The operation in the even frame is different from the operation in the odd frame only in that the voltage of the output node NO is controlled by the QB2 node and the generation timing of the first dummy pulse Dout (1) As in the radix frame. Therefore, detailed description of the operation in the even frame will be omitted.

The fourth dummy stage DST4 is different from the sixth embodiment in that the gate start pulse VST is input as the start signal to the second input terminal VNT1 in the backward shift mode and the sixth dummy pulse DST )) Is the same as that described in the first dummy stage DST (1).

8A and 8B are waveform diagrams showing simulation results of the fourth dummy stage (DST (4)) in the forward shift operation. 8A, the dummy stages DST (1) to DST (4) are not input to the dummy stages DST (1) to DST (4) ) &Lt; / RTI &gt;

Referring to FIG. 8A, a sixth dummy output Dout (6) is generated while the voltage of the Q node rises from the gate high voltage VGH to the voltage level VGH 'higher than the gate high voltage VGH. However, since the reset pulse RST does not occur, the voltage of the Q node continues to be maintained at the gate high voltage VGH even after the sixth dummy output Dout (6) is generated, and is maintained at the gate low voltage (VGL) level Do not descend. As a result, the fourth dummy stage (DST (4)) has a problem that the transistors connected to the Q node are kept in the turn-on state due to the floating of the Q node. Therefore, the transistors connected to the Q node are rapidly deteriorated, and the output of the gate shift register becomes unstable due to deterioration of these transistors.

Referring to FIG. 8B, a sixth dummy output Dout (6) is generated while the voltage of the Q node rises from the gate high voltage VGH to the voltage level VGH 'higher than the gate high voltage VGH. However, since the reset pulse RST occurs after the output of the sixth dummy output Dout 6, the sixth dummy output Dout 6 is generated and then falls to the gate low voltage VGL level. Thus, the transistors connected to the Q node are turned off, thereby deteriorating the deterioration of the transistors, and the output of the gate shift register is stabilized.

8A and 8B, the simulation result for the fourth dummy stage DST (4) has been described in the forward shift operation. However, in the case of the first to third dummy stages DST (1) to DST (3) Similar results are obtained. Simulation results of the dummy stages DST (1) to DST (4) at the time of the backward shift operation are as described with reference to FIGS. 8A and 8B.

9 is a block diagram showing a display device according to an embodiment of the present invention. 10 is a waveform diagram showing the input and output signals of the level shift shown in FIG. Referring to FIG. 9, the display device of the present invention includes a display panel 100, a data driving circuit, a scan driving circuit, and a timing controller 110.

The display panel 100 includes data lines and scan lines which intersect with each other, and pixels arranged in a matrix form. The display panel 100 may be implemented as a display panel of any one of a liquid crystal display (LCD), an organic light emitting diode display (OLED), and an electrophoretic display (EPD).

The data driving circuit includes a plurality of source drive ICs 120. [ The source drive ICs 120 receive the digital video data RGB from the timing controller 110. The source driver ICs 120 convert the digital video data RGB to a gamma compensation voltage in response to a source timing control signal from the timing controller 110 to generate a data voltage, To the data lines of the display panel 100 as shown in FIG. The source drive ICs may be connected to the data lines of the display panel 100 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The scan driver circuit includes a timing controller 110 and a level shifter 150 connected between the scan lines of the display panel 100 and a gate shift register 130.

The level shifter 150 shifts the TTL (Logic-Transistor-Logic) logic level voltage of the six-phase gate shift clocks CLK1 to CLK6 input from the timing controller 110 to the gate high voltage VGH and the gate- And level-shifted to a low voltage (VGL).

The gate shift register 130 is composed of stages for shifting the gate start pulse VST to the gate shift clocks CLK1 to CLK6 and sequentially outputting the carry signal Cout and the scan pulse Gout as described above do.

The scan driver circuit may be formed directly on the lower substrate of the display panel 100 using a GIP (Gate In Panel) method or may be connected between the gate lines of the display panel 100 and the timing controller 110 in a TAB manner. In the GIP scheme, the level shifter 150 is mounted on the PCB 140, and the gate shift register 130 may be formed on the lower substrate of the display panel 100.

The timing controller 110 receives digital video data RGB from an external host computer through an interface such as a Low Voltage Differential Signaling (LVDS) interface or a Transition Minimized Differential Signaling (TMDS) interface. The timing controller 110 transmits digital video data (RGB) input from the host computer to the source drive ICs 120.

The timing controller 110 receives timing signals such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enable signal DE and a main clock MCLK from the host computer through an LVDS or TMDS interface receiving circuit And receives a signal. The timing controller 110 generates timing control signals for controlling the operation timing of the data driving circuit and the scan driving circuit based on the timing signal from the host computer. The timing control signals include a scan timing control signal for controlling the operation timing of the scan drive circuit, a data timing control signal for controlling the operation timing of the source drive ICs 120 and the polarity of the data voltage.

The scan timing control signal includes a gate start pulse VST, gate shift clocks CLK1 through CLK6, a gate output enable signal GOE (not shown), and the like. The gate start pulse VST includes a forward gate start pulse VST and a reverse gate start pulse VST. The gate start pulse VST is input to the gate shift register 130 to control the shift start timing. The gate shift clocks CLK1 to CLK6 are level shifted through the level shifter 150 and then input to the gate shift register 130 and used as a clock signal for shifting the gate start pulse VST. The gate output enable signal GOE controls the output timing of the gate shift register 130.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE) . The source start pulse SSP controls the shift start timing of the source drive ICs 120. The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source drive ICs 120 based on the rising or falling edge. The polarity control signal POL controls the polarity of the data voltage output from the source drive ICs. If the data transfer interface between the timing controller 110 and the source drive ICs 120 is a mini LVDS interface, the source start pulse SSP and the source sampling clock SSC may be omitted.

As described above, the gate shift register and the display device using the gate shift register according to the present invention are configured such that a reset signal capable of discharging the Q node immediately after the dummy stages of the gate shift register outputs the dummy pulses is inputted to the reset terminal of the dummy stages , It is possible to prevent the floating of the Q node of the dummy stages, thereby preventing deterioration of the transistors connected to the Q node, and further stabilizing the output of the gate shift register.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: timing controller
120: Source drive IC 130: Gate shift register
140: PCB 150: Level shifter

Claims (19)

A first clock terminal receiving any one of m (m is a natural number) to m + 5 gate shift clocks whose phases are sequentially delayed, a gate shift clock generated after a gate shift clock input to the first clock terminal A second clock terminal receiving a clock, first and second input terminals receiving start signals, and third and fourth input terminals receiving reset signals, wherein the first and second scan pulses are sequentially A gate shift register comprising n (n is a natural number) stages for output,
A first dummy pulse synchronized with the mth gate shift clock after the gate start pulse is received as a start signal and the Q node is charged and a first scan pulse of the first stage is input as a reset signal among the n stages A first dummy stage for discharging the Q node;
And a second dummy pulse synchronized with the (m + 1) th gate shift clock after charging the Q1 node by receiving the gate start pulse as the start signal and inputting the second scan pulse of the first stage as the reset signal A third dummy pulse synchronized with the (m + 2) -th gate shift clock after charging the Q2 node, receiving the gate start pulse as the start signal, and outputting a third dummy pulse synchronized with the (m + A second dummy stage for receiving the first scan pulse of the second stage as the reset signal and discharging the node Q2;
A second scan pulse of the (n-1) -th stage is input to the start signal to charge a node Q1, and a fourth dummy pulse synchronized with the (m + 3) th gate shift clock is output. The first scan pulse of the nth stage is input to the start signal to charge the Q2 node, and then the fifth dummy pulse synchronized with the (m + 4) th gate shift clock is output. A third dummy stage for receiving the initialization signal and discharging the node Q2; And
And a sixth dummy pulse synchronized with the (m + 5) th gate shift clock after charging the Q node and receiving the initialization pulse as the initialization signal And a fourth dummy stage for discharging the Q node,
And the n stages output first to second scan pulses. The method according to claim 1,
K &lt; / RTI &gt; of the n stages (k is a natural number less than n)
A second scan pulse of the (k-2) th stage is input to the first input terminal to charge the Q1 node, and a first scan pulse synchronized with the gate shift clock input to the first clock terminal is output. Stage scan pulse is input to a second input terminal to charge a node Q2 and then a second scan pulse synchronized with a gate shift clock input to the second clock terminal is output. A scan pulse is input to a third input terminal to discharge the Q1 node, a first scan pulse of a (k + 2) th stage is input to a fourth input terminal, and the Q2 node is discharged. The method according to claim 1,
Wherein the first dummy pulse is input to a first input terminal of the first stage,
The second dummy pulse is input to a second input terminal of the first stage,
The third dummy pulse is input to a first input terminal of the second stage,
The fourth dummy pulse is input to a fourth input terminal of the (n-1) th stage,
The fifth dummy pulse is input to the third input terminal of the n-th stage,
And the sixth dummy pulse is input to a fourth input terminal of the n-th stage. The method according to claim 1,
Wherein the mth to (m + 5) th gate shift clocks are generated by a 6-phase clock having a pulse width of one horizontal period and a phase shifted by one horizontal period. 5. The method of claim 4,
And shifted in phase from the m-th gate shift clock to the (m + 5) -th gate shift clock in a forward shift operation. 5. The method of claim 4,
And the phase shifts from the m + 5th gate shift clock to the mth gate shift clock in the reverse shift operation. The method according to claim 1,
The first dummy stage includes:
A scan direction controller for charging the Q node in response to the gate start pulse in a forward shift mode and charging the Q node in response to a first scan pulse of the first stage in a reverse shift mode;
And a discharge TFT discharging the QB1 node or the QB2 node to a low potential voltage in accordance with the shift direction switching signal, the node controller controlling charge / discharge of the Q node, the QB1 node, and the QB2 node; And
And an output unit for outputting a first dummy pulse through an output node according to a voltage of the Q node, the QB1 node, and the QB2 node. 8. The method of claim 7,
The QB1 node is charged and discharged in the odd frame as opposed to the Q node, and maintains the discharging state in the odd frame;
Wherein the QB2 node is charged and discharged in a manner opposite to the Q node in the even frame, and maintains the discharging state in the odd frame. 8. The method of claim 7,
The scan direction control unit,
A first forward TFT for applying a forward driving voltage to the Q node in response to the gate start pulse;
A second forward TFT for applying the forward driving voltage to the gate electrode of the discharge TFT as the shift direction switching signal in response to the gate start pulse;
A first reverse TFT for applying a reverse driving voltage to the Q node in response to a first scan pulse of the first stage;
And a second reverse TFT for applying the reverse driving voltage to the gate electrode of the discharge TFT as the shift direction switching signal in response to the first scan pulse of the first stage. The method according to claim 1,
Wherein the second dummy stage comprises:
Charge the Q1 and Q2 nodes in a forward shift mode in response to the gate start pulse and charge the Q1 node in response to a second scan pulse of the first stage in a reverse shift mode, A scan direction controller for charging the node Q2 in response to a scan pulse;
And a discharge TFT for discharging a QB1 node or a QB2 node to a low potential voltage according to a shift direction switching signal, and for controlling charging and discharging of the Q1 node, the Q2 node, the QB1 node and the QB2 node; And
And an output unit for outputting a second dummy pulse through a first output node and outputting a third dummy pulse through a second output node according to voltages of the Q1 node, the Q2 node, the QB1 node, and the QB2 node, Gate shift register. 11. The method of claim 10,
The QB1 node is discharged when any one of the Q1 and Q2 nodes is charged in the odd frame, the QB1 node is charged when both the Q1 and Q2 nodes are discharged, the discharge state is maintained in the good frame,
The QB2 node is discharged when any one of the Q1 and Q2 nodes is charged in the odd frame, the QB2 node is charged when both the Q1 and Q2 nodes are discharged, and the discharge state is maintained in the odd frame And a gate shift register. 11. The method of claim 10,
The scan direction control unit,
A first forward TFT for applying a forward driving voltage to the node Q1 in response to the gate start pulse;
A second forward TFT for applying the forward driving voltage to the node Q2 in response to the gate start pulse;
A third forward TFT for applying the forward driving voltage to the gate electrode of the discharge TFT as the shift direction switching signal in response to the gate start pulse;
A first reverse TFT for applying a reverse driving voltage to the node Q1 in response to a second scan pulse of the first stage;
A second reverse TFT for applying the reverse driving voltage to the node Q2 in response to a first scan pulse of the second stage; And
And a third reverse TFT for applying the reverse driving voltage to the gate electrode of the discharge TFT as the shift direction switching signal in response to the first scan pulse of the second stage. The method according to claim 1,
The third dummy stage includes:
N stage and charges the Q2 node in response to a first scan pulse of the n-th stage in a forward shift mode, and charges the Q2 node in a backward shift mode in response to a second scan pulse of the n- A scan direction controller for charging the nodes Q1 and Q2 in response to a start pulse;
And a discharge TFT for discharging a QB1 node or a QB2 node to a low potential voltage according to a shift direction switching signal, and for controlling charging and discharging of the Q1 node, the Q2 node, the QB1 node and the QB2 node; And
And an output unit for outputting a fourth dummy pulse through the first output node and outputting a fifth dummy pulse through the second output node in accordance with the voltages of the Q1 node, the Q2 node, the QB1 node, and the QB2 node, Gate shift register. 14. The method of claim 13,
The QB1 node is discharged when any one of the Q1 and Q2 nodes is charged in the odd frame, the QB1 node is charged when both the Q1 and Q2 nodes are discharged, the discharge state is maintained in the good frame,
The QB2 node is discharged when any one of the Q1 and Q2 nodes is charged in the odd frame, the QB2 node is charged when both the Q1 and Q2 nodes are discharged, and the discharge state is maintained in the odd frame And a gate shift register. 14. The method of claim 13,
The scan direction control unit,
A first forward TFT for applying a forward driving voltage to the node Q1 in response to a second scan pulse of the (n-1) th stage;
A second forward TFT for applying the forward drive voltage to the node Q2 in response to a first scan pulse of the n-th stage;
A third forward TFT for applying the forward driving voltage to the gate electrode of the discharge TFT as the shift direction switching signal in response to the second scan pulse of the (n-1) th stage;
A first reverse TFT for applying a reverse driving voltage to the node Q1 in response to the gate start pulse;
A second reverse TFT for applying the reverse driving voltage to the node Q2 in response to the gate start pulse; And
And a third reverse TFT for applying the reverse driving voltage to the gate electrode of the discharge TFT as the shift direction switching signal in response to the gate start pulse. The method according to claim 1,
The fourth dummy stage includes:
A scan direction controller for charging the Q node in response to the second scan pulse of the nth stage in the forward shift mode and charging the Q node in response to the gate start pulse in the reverse shift mode;
And a discharge TFT discharging the QB1 node or the QB2 node to a low potential voltage in accordance with the shift direction switching signal, the node controller controlling charge / discharge of the Q node, the QB1 node, and the QB2 node; And
And an output unit for outputting a sixth dummy pulse through the output node according to the voltages of the Q node, the QB1 node, and the QB2 node. 17. The method of claim 16,
The QB1 node is charged and discharged in the odd frame as opposed to the Q node, and maintains the discharging state in the odd frame;
Wherein the QB2 node is charged and discharged in a manner opposite to the Q node in the even frame, and maintains the discharging state in the odd frame. 17. The method of claim 16,
The scan direction control unit,
A first forward TFT for applying a forward driving voltage to the Q node in response to a second scan pulse of the n stage;
A second forward TFT for applying the forward driving voltage to the gate electrode of the discharge TFT as the shift direction switching signal in response to the second scan pulse of the nth stage;
A first reverse TFT for applying a reverse driving voltage to the Q node in response to the gate start pulse;
And a second reverse TFT for applying the reverse driving voltage to the gate electrode of the discharge TFT as the shift direction switching signal in response to the gate start pulse. A display panel including a plurality of pixels intersecting the data lines and the scan lines and arranged in a matrix form;
A data driving circuit for supplying a data voltage to the data lines; And
And a scan driving circuit for sequentially supplying scan pulses to the scan lines,
The scan driving circuit includes:
A first clock terminal receiving any one of m (m is a natural number) to m + 5 gate shift clocks whose phases are sequentially delayed, a gate shift clock generated after a gate shift clock input to the first clock terminal A second clock terminal receiving a clock, first and second input terminals receiving start signals, and third and fourth input terminals receiving reset signals, wherein the first and second scan pulses are sequentially And a gate shift register including n (n is a natural number) stages for output,
The gate shift register includes:
A first dummy pulse synchronized with the mth gate shift clock after the gate start pulse is received as a start signal and the Q node is charged and a first scan pulse of the first stage is input as a reset signal among the n stages A first dummy stage for discharging the Q node;
And a second dummy pulse synchronized with the (m + 1) th gate shift clock after charging the Q1 node by receiving the gate start pulse as the start signal and inputting the second scan pulse of the first stage as the reset signal A third dummy pulse synchronized with the (m + 2) -th gate shift clock after charging the Q2 node, receiving the gate start pulse as the start signal, and outputting a third dummy pulse synchronized with the (m + A second dummy stage for receiving the first scan pulse of the second stage as the reset signal and discharging the node Q2;
A second scan pulse of the (n-1) -th stage is input to the start signal to charge a node Q1, and a fourth dummy pulse synchronized with the (m + 3) th gate shift clock is output. The first scan pulse of the nth stage is input to the start signal to charge the Q2 node, and then the fifth dummy pulse synchronized with the (m + 4) th gate shift clock is output. A third dummy stage for receiving the initialization signal and discharging the node Q2; And
And a sixth dummy pulse synchronized with the (m + 5) th gate shift clock after charging the Q node and receiving the initialization pulse as the initialization signal Further comprising a fourth dummy stage for discharging the Q node,
And the n stages output first to second scan pulses.

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