KR102381627B1 - Display device - Google Patents

Abstract

An object of the present invention is to provide a display device capable of preventing an increase in the size of a level shifter. According to the present invention, when generating gate clock signals of a plurality of phases, the number of control clock signals to be generated is reduced, so that the size of the clock signal generator is reduced, and consequently the size of the entire level shifter is also reduced. Accordingly, it is possible to prevent an increase in the size of the level shifter when generating gate clock signals of multiple phases. The present invention provides a display panel in which gate lines and data lines are disposed, a gate driver supplying gate signals to the gate lines, a timing control circuit outputting an on clock signal, an off clock signal, and a driving voltage control signal, the on A level shifter comprising: a clock signal generator for outputting phase i (i is a positive integer equal to or greater than 2) control clock signals according to a clock signal and the off-clock signal; and a voltage level changer for changing a voltage level of the driving voltage control signal and a switching unit that receives the i-phase control clock signals using i pairs of switches and outputs N (N is a positive integer greater than i) phase gate clock signals to the gate driver.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms, and in recent years, a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting diode Various display devices such as an organic light emitting diode (OLED) are being used.

The display device includes a display panel, a gate driver, a data driver, and a timing control circuit. The display panel includes data lines, gate lines, and a plurality of pixels formed at intersections of data lines and gate lines to receive data voltages of the data lines when gate signals are supplied to the gate lines. The pixels emit light with a predetermined brightness according to the data voltages. The gate driver receives the gate control signal and supplies gate signals to the gate lines. The data driver receives a data control signal from the timing control circuit and supplies analog data voltages to the data lines. The timing control circuit is configured to generate a start signal, an on clock signal, and an off clock signal for controlling the operation timing of the gate driver based on the timing signals and driving timing information stored in the memory, and to control the operation timing of the data driver A data control signal is generated and supplied to the data driver.

In the case of a high-resolution display device, since the number of gate lines increases, pulse widths of gate signals supplied to pixels are shortened. In this case, the turn-on period of the transistor of each of the pixels is shortened, so that the data voltage is not properly charged may occur. In order to prevent such a problem from occurring, in a high-resolution display device, pulse widths of neighboring gate signals overlap each other and are supplied. In this case, since the pulse width of the gate signals may be increased, the turn-on period of each transistor of the pixels may be stably maintained. Meanwhile, in order to overlap the pulse widths of the neighboring gate signals, the gate clock signals must be overlapped with each other, thereby increasing the number of phases of the gate clock signals.

The present invention provides a display device capable of preventing an increase in cost due to an increase in the size of a level shifter in a display device manufactured by a gate driver in panel (GIP) method to realize a narrow bezel. would like to provide

In order to solve the above problems, the present invention provides a display panel in which gate lines and data lines are disposed, a gate driver supplying gate signals to the gate lines, an on clock signal, an off clock signal, and a driving voltage control signal. A timing control circuit for outputting an i (i is a positive integer greater than or equal to 2) phase control clock signals according to the on clock signal and the off clock signal, and a clock signal generator for outputting a voltage level of the driving voltage control signal The i-phase control clock signals are input using a level shifter including a voltage level changing unit and i switch pairs, and the i-phase control clock signals are switched using the i switch pairs to N (N is an amount greater than i) and a switching unit outputting the phase gate clock signals to the gate driver.

In an embodiment of the present invention, the clock signal generator generates the i-phase control clock signals and outputs the i-phase control clock signals as N-phase gate clock signals using the switching unit. That is, in the embodiment of the present invention, since the clock signal generator only needs to generate a smaller number of i-phase control clock signals than the N-phase gate clock signals, the size of the clock signal generator can be reduced. In addition, since the switching unit is configured with a simple circuit to include the switch pairs, the size reduction effect of the level shifter due to the decrease in the size of the clock signal generator is greater than the increase in the size of the level shifter due to the addition of the switching unit. As a result, since the embodiment of the present invention can reduce the size of the level shifter, it is possible to prevent the cost increase due to the increase in the size of the level shifter.

In addition, in the embodiment of the present invention, the size of the level shifter can be further reduced by mounting the switching unit on the circuit board.

In addition, since the embodiment of the present invention can reduce the number of output pins when the switching unit is mounted on the circuit board, the cost due to the level shifter can be further reduced.

1 is an exemplary view showing a display device according to an embodiment of the present invention.
2 is an exemplary view showing a lower substrate, source drive ICs, source flexible films, a source circuit board, a control circuit board, a timing control circuit, and a level shifter of a display device according to an embodiment of the present invention;
FIG. 3 is an exemplary view showing an example of the pixel of FIG. 1;
4 is an exemplary view showing another example of the pixel of FIG. 1;
FIG. 5 is a block diagram showing an example of the level shifter of FIG. 1 in detail;
FIG. 6 is a detailed block diagram illustrating a clock signal generator, a switch control signal generator, and a switching part of FIG. 5;
7A is a waveform diagram of an input signal and output signals of an 8-phase clock according to an embodiment of the present invention;
7B is a waveform diagram of a driving voltage generation signal, an odd driving voltage, and an even driving voltage according to an embodiment of the present invention.
FIG. 8 is a block diagram showing another example of the level shifter of FIG. 1 in detail;
9 is a detailed block diagram illustrating a clock signal generator, a switch control signal generator, and a switching part of FIG. 8;

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described with 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

"X-axis direction", "Y-axis direction", and "Z-axis direction" should not be interpreted only as a geometric relationship in which the relationship between each other is vertical, and is wider than within the scope where the configuration of the present invention can function functionally. It may mean having a direction.

The term “at least one” should be understood to include all possible combinations of one or more related items. For example, the meaning of “at least one of the first, second, and third items” means that each of the first, second, or third items as well as two of the first, second and third items It may mean a combination of all items that can be presented from more than one.

Each feature of the various embodiments of the present invention can be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be independently implemented with respect to each other or implemented together in a related relationship. may be

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an exemplary view showing a display device according to an embodiment of the present invention. 2 is an exemplary view showing a lower substrate, source drive ICs, source flexible films, a source circuit board, a control circuit board, a timing control circuit, and a level shifter of a display device according to an embodiment of the present invention.

The display device according to the embodiment of the present invention may include any display device that supplies data voltages to pixels through line scanning that supplies gate signals to the gate lines G1 to Gn. For example, a display device according to an embodiment of the present invention includes a liquid crystal display, an organic light emitting display, a field emission display, and an electrophoresis display. display) may be implemented as any one of them.

1 and 2 , a display device according to an embodiment of the present invention includes a display panel 10 , a gate driver 11 , a data driver 20 , a timing control circuit 30 , and a level shifter 40 . to provide

The display panel 10 includes an upper substrate and a lower substrate. Data lines D1 to Dm, m is a positive integer greater than or equal to 2), gate lines G1 to Gn, n is a positive integer greater than or equal to 2), data lines D1 to Dm, and gate lines are provided on the lower substrate The display area DA including the pixels P disposed in the intersection area of G1 to Gn is formed. The display panel 10 may be divided into a display area DA and a non-display area NDA. The display area DA is an area in which pixels P are provided and an image is displayed. The non-display area NDA is an area provided around the display area DA and is an area in which no image is displayed.

Each of the pixels P may be connected to any one of the data lines D1 to Dm and to any one of the gate lines G1 to Gn. For this reason, each of the pixels P receives the data voltage of the data line when the gate signal is supplied to the gate line, and emits light with a predetermined brightness according to the supplied data voltage.

When the display device is implemented as a liquid crystal display device, each of the pixels P includes a transistor T, a pixel electrode PE, a common electrode CE, a liquid crystal layer LC, and a storage capacitor Cst, as shown in FIG. 3 . ) may be included. In response to the gate signal of the kth (k is a positive integer satisfying 1≤≤k≤≤n) gate line Gk, the jth (j is 1≤≤j≤≤m) a positive integer) a data voltage of the data line Dj is supplied to the pixel electrode PE. Accordingly, each of the pixels P drives the liquid crystal of the liquid crystal layer LC by an electric field generated by a potential difference between the data voltage supplied to the pixel electrode PE and the common voltage supplied to the common electrode CE. It is possible to adjust the amount of transmission of light incident from the backlight unit. The common electrode CE receives a common voltage from the common line CL. In addition, the storage capacitor Cst is provided between the pixel electrode PE and the common electrode CE to constantly maintain a voltage difference between the pixel electrode PE and the common electrode CE.

When the display device is implemented as an organic light emitting diode display, each of the pixels P includes an organic light emitting diode OLED, a scan transistor ST, a driving transistor DT, and a storage capacitor Cst as shown in FIG. 4 . can do. The scan transistor ST supplies the data voltage of the j-th data line Dj to the gate electrode of the driving transistor DT in response to the gate signal of the k-th gate line Gk. The driving transistor DT controls a driving current flowing from the high potential voltage line VDDL to the organic light emitting diode OLED according to the data voltage supplied to the gate electrode. The organic light emitting diode OLED is provided between the driving transistor DT and the low potential voltage line VSSL, and emits light with a predetermined brightness according to the driving current. The storage capacitor Cst may be provided between the gate electrode of the driving transistor DT and the high potential voltage line VDDL to keep the voltage of the gate electrode of the driving transistor DT constant.

The gate driver 11 supplies gate signals to the gate lines G1 to Gn. Specifically, the gate driver 11 receives the gate control signal GCS, generates gate signals according to the gate control signal GCS, and supplies the generated gate signals to the gate lines G1 to Gn.

The gate driver 11 may be provided in the non-display area NDA in a gate driver-in-panel method. 1 illustrates that the gate driver 11 is provided in the non-display area NDA outside one side of the display area DA, but is not limited thereto. For example, the gate driver 11 may be provided in the non-display area NDA on both sides of the display area DA.

Alternatively, the gate driver 11 may include a plurality of gate drive integrated circuits (hereinafter, referred to as “ICs”), and the gate drive ICs may be mounted on gate flexible films. Each of the gate flexible films may be a tape carrier package or a chip on film. The gate flexible films may be attached to the non-display area (NDA) of the display panel 10 by a tape automated bonding (TAB) method using an anisotropic conductive film. It can be connected to (G1~Gn).

The data driver 20 is connected to the data lines D1 to Dm. The data driver 20 receives digital video data DATA and a data control signal DCS from the timing control circuit 30 , and converts the digital video data DATA into analog data voltages according to the data control signal DCS. convert The data driver 20 supplies analog data voltages to the data lines D1 to Dm. The data driver 20 may include at least one source drive IC 21 .

Each of the source drive ICs 21 may be manufactured as a driving chip. Each of the source drive ICs 21 may be mounted on the source flexible film 70 . Each of the source flexible films 70 may be implemented as a tape carrier package or a chip-on film, and may be bent or bent. Each of the source flexible films 70 may be attached to the non-display area of the display panel 10 in a TAB method using an anisotropic conductive film, so that the source drive ICs 21 are connected to the data lines D1 to Dm. ) can be connected to

Alternatively, each of the source drive ICs 21 may be directly attached to the lower substrate by a chip on glass (COG) method or a chip on plastic (COP) method and connected to the data lines D1 to Dm.

In addition, the source flexible films 70 may be attached to the circuit board 80 . Preferably, the source flexible films 70 may be attached on a source printed circuit board. The source printed circuit boards may be flexible printed circuit boards that may be bent or bent. One or a plurality of source printed circuit boards may be provided.

The timing control circuit 30 receives video data DATA and timing signals TS from an external system board (not shown). The timing signals may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock.

The timing control circuit 30 is a gate control signal for controlling the operation timing of the gate driver 11 based on the timing signals TS and driving timing information stored in a memory such as an electrically erasable programmable read-only memory (EEPROM). and generates a data control signal DCS for controlling the operation timing of the data driver 20 . When the gate driver 11 is formed by a gate driver in panel (GIP) method, the gate control signal GCS includes the start signal VST, the N-phase gate clock signals CLK1 to CLKN, and the radix. It may include a driving voltage VGH_ODD and an even driving voltage VGH_EVEN. The timing control circuit 30 supplies the start signal VST, the on clock signal ON_CLK, and the off clock signal OFF_CLK to the level shifter 40 . The timing control circuit 30 supplies the video data DATA and the data control signal DCS to the data driver 20 .

The level shifter 40 generates a gate control signal GCS based on a start signal VST, an on clock signal ON_CLK, and an off clock signal OFF_CLK input from the timing control circuit 30 to generate a gate driver ( 11) is supplied. Specifically, the level shifter 40 generates the N-phase gate clock signals CLK1 to CLKN by using the on clock signal ON_CLK and the off clock signal OFF_CLK. The level shifter 40 generates the driving voltage control signal EO by using the start signal VST and the off clock signal OFF_CLK, and drives the odd driving voltage VGH_ODD and the even driving according to the driving voltage control signal EO. The voltage VGH_EVEN is alternately supplied to the gate driver 11 . The odd driving voltage VGH_ODD and the even driving voltage VGH_EVEN are alternately supplied to the gate driving unit 11 to prevent deterioration of the transistor T of the gate driving unit 11 .

The level shifter 40 has a voltage swing of the start signal VST, the gate clock signals CLK1 to CLKN on N (N is a positive integer greater than or equal to 2), the odd driving voltage VGH_ODD, and the even driving voltage VGH_EVEN. The width is adjusted to a voltage swing width suitable for driving the gate driver 11 and the transistors of the pixel array PA. For example, the level shifter 40 adjusts the voltage swing widths of the start signal VST, the N-phase gate clock signals CLK1 to CLKN, the odd driving voltage VGH_ODD, and the even driving voltage VGH_EVEN to the gate low voltage. to the gate-high voltage.

When generating N-phase gate clock signals, the level shifter has one pin for outputting a start signal, N pins for outputting gate clock signals, and two pins for outputting odd driving voltage and even driving voltage, for a total of N+ Three output pins are required. As a result, since the size of the level shifter increases as the number of phases of the gate clock signals increases, there is a problem in that the cost of the level shifter increases.

5 is a detailed block diagram illustrating an example of the level shifter 40 of FIG. 1 . Referring to FIG. 5 , the level shifter 40 includes a clock signal generating unit 41 , a switching unit 42 , and first and second voltage level changing units 43 and 44 , and a switch control signal generating unit 50 . includes

The clock signal generator 41 receives the on clock signal ON_CLK and the off clock signal OFF_CLK from the timing control circuit 30 . The clock signal generator 41 generates control clock signals CCLK1 to CCLKi on i (i is a positive integer less than N) by using the on clock signal ON_CLK and the off clock signal OFF_CLK. For convenience of explanation, a case in which the clock signal generator 41 generates the first to fourth control clock signals CCLK1 to CCLK4 is exemplified in FIG. 6 and the following description. The number of control clock signals may be changed as needed.

The clock signal generator 41 increases the first to fourth clock signals CCLK1 to CCLK4 in synchronization with the rising edge or the falling edge of the on clock signal ON_CLK, and the rising edge or the falling edge of the off clock signal OFF_CLK. The first to fourth control clock signals CCLK1 to CCLK4 may be polled in synchronization with the falling edge. The falling edge refers to a period in which the on clock signal ON_CLK and the off clock signal OFF_CLK fall from the first logic level voltage V1 to the second logic level voltage V2. The rising edge refers to a period in which the on clock signal ON_CLK and the off clock signal OFF_CLK rise from the second logic level voltage V2 to the first logic voltage V1.

The clock signal generator 41 supplies the first to fourth control clock signals CCLK1 to CCLK4 to the gate driver 11 with the eight-phase clock signals whose phases are sequentially delayed in order to secure sufficient charging time during high-speed driving. ) can be created. For example, the clock signal generator 41 may generate the first to fourth control clock signals (eg, to rise on the rising edge of the on clock signal ON_CLK and fall on the falling edge of the off clock signal OFF_CLK) as shown in FIG. 7A . CCLK1 to CCLK4) can be created. The first to fourth control clock signals CCLK1 to CCLK4 may be generated such that phases are sequentially delayed.

Waveforms of at least two clock signals supplied to the gate driver 11 may be generated using each of the first to fourth control clock signals CCLK1 to CCLK4 . For example, among the eight-phase clock signals supplied to the gate driver 11 using the first control clock signal CCLK1 as shown in FIG. 7A , the waveform of the first gate clock signal CLK1 and the fifth gate clock signal ( CLK5) can be generated. The waveform of the second gate clock signal CLK2 and the waveform of the sixth gate clock signal CLK6 may be generated among the eight-phase clock signals supplied to the gate driver 11 by using the second control clock signal CCLK2. there is. The waveform of the third gate clock signal CLK3 and the waveform of the seventh gate clock signal CLK7 may be generated among the eight-phase clock signals supplied to the gate driver 11 by using the third control clock signal CCLK4. there is. The waveform of the fourth gate clock signal CLK4 and the waveform of the eighth gate clock signal CLK8 may be generated among the eight-phase clock signals supplied to the gate driver 11 by using the fourth control clock signal CCLK3. there is. When the control clock signals CCLK1 to CCLK4 pass through the switching unit 42 , waveforms of at least two gate clock signals CLK1 to CLK8 may be generated.

In addition, the clock signal generator 41 receives the gate high voltage VGH and the gate low voltage VGL from a power supply unit (not shown) to perform voltage swings of the first to fourth control clock signals CCLK1 to CCLK4 . The width is changed from the gate low voltage VGL to the gate high voltage VGH and output.

The first voltage level change unit 43 receives a start signal VST from the timing control circuit 30 and receives a gate high voltage VGH and a gate low voltage VGL from a power supply unit (not shown). The first voltage level change unit 43 outputs the start signal VST by changing the voltage swing width of the start signal VST from the gate low voltage VGL to the gate high voltage VGH.

The second voltage level change unit 44 receives the driving voltage control signal EO from the timing control circuit, and receives the gate high voltage VGH and the gate low voltage VGL from a power supply (not shown). The driving voltage control signal is output by changing the voltage swing width of the driving voltage control signal EO from the gate low voltage VGL to the gate high voltage VGH.

The switching unit 42 receives the i number of control clock signals and the driving voltage control signal, and generates N or more gate clock signals, an even driving voltage, and an odd driving voltage through a switching process. For example, as shown in FIG. 5 , i number of control clock signals may be received, and i gate clock signals may be generated twice as many.

The switching control signal generator 50 generates the switching control signals SWC1 to SWC4 and SWCEO by using the on clock signal ON_CLK and the off clock signal OFF_CLK. The switching control signal generating unit outputs the switching control signals SWC1 to SWC4 and SWCEO to the switching unit 42 . Due to this, the turn-on and turn-off of the i switch pairs of the switching unit 42 can be controlled.

5 illustrates that the switching control signal generator 50 is included in the level shifter 40, but is not limited thereto. When the switching control signal generator 50 is included in the level shifter 40 , it is not necessary to design a separate chip on the circuit board 80 . However, when the switching control signal generating unit 50 is included in the level shifter 40, since the size of the level shifter 40 may increase, in order to reduce the size of the level shifter 40, the switching control signal generating unit ( 50 may be mounted on the timing control circuit 30 or the circuit board 80 .

6 is a detailed block diagram illustrating the switching unit 42 and the switching control signal generating unit 50 of FIG. 5 .

Referring to FIG. 6 , the switching unit 42 includes i pairs of switches. 6 exemplifies the inclusion of five switch pairs SW1-1 to SW5-2 for convenience of description.

The first switch pairs include a 1-1 switch SW1-1 and a 1-2 th switch SW1-2. The first control clock signal CCLK1 is input to the 1-1 switch SW1-1 and the 1-2 switch SW1-2. The 1-1 switch SW1-1 is controlled by the first switch control signal SWC1 , and the 1-2 switch SW1-2 is controlled by an inverted signal of the first switch control signal SWC1 . . Accordingly, the 1-1 switch SW1-1 and the 1-2 switch SW1-2 may be alternately turned on. When the 1-1 switch SW1-1 is turned on, it outputs the first control clock signal CCLK1 to the first clock output pin CP1. The clock signal output to the first clock output pin CP1 is supplied to the gate driver 11 as a first gate clock signal CLK1 . When the 1-2 th switch SW1 - 2 is turned on, the first control clock signal CCLK1 is output to the fifth clock output pin CP5 . The clock signal output to the fifth clock output pin CP5 is supplied to the gate driver 11 as a fifth gate clock signal CLK5 .

The second switch pairs include a 2-1 switch SW2-1 and a 2-2 switch SW2-2. The second control clock signal CCLK2 is input to the 2-1 switch SW2-1 and the 2-2 switch SW2-2. The 2-1 switch SW2-1 is controlled by the second switch control signal SWC2, and the 2-2 switch SW2-2 is controlled by the inverted signal of the second switch control signal SWC2 . Accordingly, the second-first switch SW2-1 and the second-second switch SW2-2 may be alternately turned on. When the 2-1 th switch SW2-1 is turned on, it outputs the second control clock signal CCLK2 to the second clock output pin CP2. The clock signal output to the second clock output pin CP2 is supplied to the gate driver 11 as a second gate clock signal CLK2 . When the 2-2 switch SW2-2 is turned on, the second control clock signal CCLK2 is output to the sixth clock output pin CP6. The clock signal output to the sixth clock output pin CP6 is supplied to the gate driver 11 as a sixth gate clock signal CLK6.

The third switch pairs include a 3-1 switch SW3-1 and a 3-2 switch SW3-2. The third control clock signal CCLK3 is input to the 3-1 th switch SW3-1 and the 3-2 th switch SW3-2. The 3-1st switch SW3-1 is controlled by the third switch control signal SWC3, and the 3-2nd switch SW3-2 is controlled by the inverted signal of the third switch control signal SWC3 . Accordingly, the 3 - 1 switch SW3 - 1 and the 3 - 2 switch SW3 - 2 may be alternately turned on. When the 3-1 th switch SW3 - 1 is turned on, the third control clock signal CCLK3 is output to the third clock output pin CP3 . The clock signal output to the third clock output pin CP3 is supplied to the gate driver 11 as the third gate clock signal CLK3 . When the 3-2 th switch SW3 - 2 is turned on, the third control clock signal CCLK3 is output to the seventh clock output pin CP7 . The clock signal output to the seventh clock output pin CP7 is supplied to the gate driver 11 as a seventh gate clock signal CLK7.

The fourth switch pairs include a 4-1 th switch SW4-1 and a 4-2 th switch SW4-2. The fourth control clock signal CCLK4 is input to the 4-1 th switch SW4-1 and the 4-2 th switch SW4-2. The 4-1 th switch SW4-1 is controlled by the fourth switch control signal SWC4, and the 4-2 th switch SW4-2 is controlled by the inverted signal of the fourth switch control signal SWC4 . Accordingly, the 4-1 th switch SW4-1 and the 4-2 th switch SW4-2 may be alternately turned on. When the 4-1 th switch SW4-1 is turned on, the fourth control clock signal CCLK4 is output to the fourth clock output pin CP4. The clock signal output to the fourth clock output pin CP4 is supplied to the gate driver 11 as a fourth gate clock signal CLK4 . When the 4-2 th switch SW4 - 2 is turned on, the fourth control clock signal CCLK4 is output to the eighth clock output pin CP8 . The clock signal output to the eighth clock output pin CP8 is supplied to the gate driver 11 as the eighth gate clock signal CLK8.

The fifth switch pairs include a 5-1 th switch SW5-1 and a 5-2 th switch SW5-2. The driving voltage control signal EO is input to the 5-1 th switch SW5-1 and the 5-2 th switch SW5-2. The 5-1 th switch SW5-1 is controlled by the driving voltage switch control signal SWCEO, and the 5-2 th switch SW5-2 is controlled by the inverted signal of the driving voltage switch control signal SWCEO . Accordingly, the 5-1 th switch SW5 - 1 and the 5 - 2 th switch SW5 - 2 may be alternately turned on. When the 5-1 th switch SW5-1 is turned on, the driving voltage control signal EO is output to the even driving voltage output pin EP. The driving voltage output to the even driving voltage output pin EP is supplied to the gate driving unit 11 as an even driving voltage VGH_EVEN. The 5-2th switch SW5-2 outputs the driving voltage control signal EO to the odd driving voltage output pin OP when it is turned on. The driving voltage output to the odd driving voltage output pin OP is supplied to the gate driver 11 as an odd driving voltage VGH_ODD.

The switching control signal generator 50 supplies the first switch control signal SWC1 to the inverter INV connected to the 1-1 switch SW1-1 and the 1-2 switch SW1-2. Accordingly, the first switch control signal SWC1 is supplied to the 1-1 switch SW1-1, and an inverted signal of the first switch control signal SWC1 is supplied to the 1-2 switch SW1-2. can be

The switching control signal generator 50 supplies the second switch control signal SWC2 to the inverter INV connected to the 2-1 switch SW2-1 and the 2-2 switch SW2-2. Accordingly, the second switch control signal SWC2 is supplied to the 2-1 switch SW2-1, and the inverted signal of the second switch control signal SWC2 is supplied to the 2-2 switch SW2-2. can be

The switching control signal generator 50 supplies the third switch control signal SWC3 to the inverter INV connected to the 3-1 th switch SW3-1 and the 3-2 th switch SW3-2. Accordingly, the third switch control signal SWC3 is supplied to the 3-1 switch SW3-1, and the inverted signal of the third switch control signal SWC3 is supplied to the 3-2 switch SW3-2. can be

The switching control signal generator 50 supplies the fourth switch control signal SWC4 to the inverter INV connected to the 4-1 th switch SW4-1 and the 4-2 th switch SW4-2. Accordingly, the fourth switch control signal SWC4 is supplied to the 4-1 th switch SW4-1, and the inverted signal of the fourth switch control signal SWC4 is supplied to the 4-2 th switch SW4-2. can be

The switching control signal generator 50 supplies the driving voltage switch control signal SWCEO to the inverter INV connected to the 5-1 th switch SW5-1 and the 5-2 th switch SW5-2. Accordingly, the driving voltage switch control signal SWCEO is supplied to the 5-1 th switch SW5-1, and the inverted signal of the driving voltage switch control signal SWCEO is supplied to the 5-2 th switch SW5-2. can be

7A is a waveform diagram of an input signal and an output signal of an 8-phase clock according to an embodiment of the present invention. Hereinafter, the operation of the switching unit 42 according to an embodiment of the present invention will be described in detail with reference to FIGS. 6 and 7A .

The switch pairs SW1-1 to SW5-2 are turned on when the first to fourth switch control signals SWC1 to SWC4 and the driving voltage switch control signal SWCEO are supplied to the first logic level voltage V1. -on, and is turned off when supplied to the second logic level voltage (V2).

When the first switch control signal SWC1 of the first logic level voltage V1 is supplied, the 1-1 switch SW1-1 is turned on and the 1-2 switch SW1-2 is turned on. - is off Accordingly, as shown in FIG. 7A , the waveform of the first gate clock signal CLK1 of the first control clock signal CCLK1 may be output to the first clock output pin CP1 .

When the first switch control signal SWC1 of the second logic level voltage V2 is supplied, the 1-1 switch SW1-1 is turned off, and the 1-2 switch SW1-2 is turned on. - it comes on Accordingly, as shown in FIG. 7A , the waveform of the fifth gate clock signal CLK5 of the first control clock signal CCLK1 may be output to the fifth clock output pin CP5.

When the second switch control signal SWC2 of the first logic level voltage V1 is supplied, the 2-1 switch SW2-1 is turned on, and the second switch SW2-2 is turned on. - is off Accordingly, as shown in FIG. 7A , the waveform of the second gate clock signal CLK2 of the second control clock signal CCLK2 may be output to the second clock output pin CP2 .

When the second switch control signal SWC2 of the second logic level voltage V2 is supplied, the second-first switch SW2-1 is turned off, and the second-second switch SW2-2 is turned on. - it comes on Accordingly, as shown in FIG. 7A , the waveform of the sixth gate clock signal CLK6 of the second control clock signal CCLK2 may be output to the sixth clock output pin CP6 .

When the third switch control signal SWC3 of the first logic level voltage V1 is supplied, the 3-1 th switch SW3-1 is turned on, and the 3-2 th switch SW3-2 is turned on. - is off Accordingly, as shown in FIG. 7A , the waveform of the third gate clock signal CLK3 of the third control clock signal CCLK3 may be output to the third clock output pin CP3 .

When the third switch control signal SWC3 of the second logic level voltage V2 is supplied, the 3-1 th switch SW3-1 is turned off, and the 3-2 th switch SW3-2 is turned on - it comes on Accordingly, as shown in FIG. 7A , the waveform of the seventh gate clock signal CLK7 of the third control clock signal CCLK3 may be output to the seventh clock output pin CP7.

When the fourth switch control signal SWC4 of the first logic level voltage V1 is supplied, the 4-1 th switch SW4-1 is turned on, and the 4-2 th switch SW4-2 is turned on - is off Accordingly, as shown in FIG. 7A , the waveform of the fourth gate clock signal CLK4 of the fourth control clock signal CCLK4 may be output to the fourth clock output pin CP4 .

When the fourth switch control signal SWC4 of the second logic level voltage V2 is supplied, the 4-1 th switch SW4-1 is turned off, and the 4-2 th switch SW4-2 is turned on - it comes on Accordingly, as shown in FIG. 7A , the waveform of the eighth gate clock signal CLK8 of the fourth control clock signal CCLK4 may be output to the eighth clock output pin CP8.

When the driving voltage switch control signal SWCEO of the first logic level voltage V1 is supplied, the 5-1 th switch SW5-1 is turned on, and the 5-2 th switch SW5-2 is turned on - is off Accordingly, as shown in FIG. 7B , the even driving voltage waveform of the driving voltage control signal EO may be output to the even driving voltage output pin EP.

When the driving voltage switch control signal SWCEO of the second logic level voltage V2 is supplied, the 5-1 th switch SW5-1 is turned off, and the 5-2 th switch SW5-2 is turned on - it comes on Accordingly, as shown in FIG. 7B , the odd driving voltage waveform of the driving voltage control signal EO may be output to the odd driving voltage output pin OP.

As described above, in the first embodiment of the present invention, the clock signal generator 41 generates the control clock signals CCLK1 to CCLKi of the i-phase, and uses the switching unit 42 to generate the I-phase control clock signal. The signals CCLK1 to CCLKi are output as N-phase gate clock signals CLK1 to CLKN. That is, in the first embodiment of the present invention, the clock signal generator 41 only needs to generate a smaller number of i-phase control clock signals CCLK1 to CCLKi than the N-phase gate clock signals CLK1 to CLKN. The size of the signal generator 41 may be reduced. In addition, since the switching unit 42 is configured as a simple circuit to include the switch pairs, the level due to the decrease in the size of the clock signal generating unit 41 rather than the increase in the size of the level shifter 40 due to the addition of the switching unit 42 . The effect of reducing the size of the shifter 40 is greater. As a result, since the first embodiment of the present invention can reduce the size of the level shifter 40 , it is possible to prevent an increase in cost due to an increase in the size of the level shifter 40 .

FIG. 8 is a detailed block diagram showing another example of the level shifter 40 of FIG. 1 . 9 is a detailed block diagram illustrating a clock signal generator, a switch control signal generator, and a switching part of FIG. 8 . 8 and 9 , the level shifter 40 includes a clock signal generator 41 , first and second voltage level changers 43 and 44 , and a switch control signal generator 50 . .

Since the clock signal generating unit 41, the first and second voltage level changing units 43 and 44, and the switch control signal generating unit 50 are substantially the same as those described in connection with FIGS. 5 and 6, they are A detailed description thereof will be omitted.

The level shifter 40 no longer includes the switching unit 60 , and the switching unit 60 may be mounted on the circuit board 80 . When the switching unit 60 is mounted on the circuit board 80 as in the second embodiment than when included in the level shifter 40 as in the first embodiment, the size of the level shifter 40 can be further reduced. . Also, in the first embodiment of the present invention, the level shifter 40 includes output pins of N gate clock signals, whereas in the second embodiment of the present invention, the level shifter 40 outputs i control clock signals. Since only pins need to be included, the number of output pins can be reduced. Accordingly, the second embodiment of the present invention can further reduce the cost due to the level shifter 40 than the first embodiment.

The switching unit 60 is substantially the same as the switching unit 42 described with reference to FIGS. 5 and 6 except for being mounted on the circuit board 80 , and thus a detailed description thereof will be omitted.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: gate driver
20: data driver 21: source drive ICs
30: timing control circuit 40: level shifter
41: clock signal generating unit 43, 44: first and second voltage level changing unit
42, 60: switching unit 50: switching control signal generating unit
70: source flexible films 80: circuit board
AT: active time BT: vertical blank time
CCLK1~CCLKi: i-phase control clock signals
CLK1~CLKN: N-phase gate clock signals
CP1~8, EP, OP: Clock output pins INV: Inverter
ON_CLK: On clock signal OFF_CLK: Off clock signal
SW1-1~SWi-2: switch pairs SWC1~SWC4, SWCEO: switching control signals
T: Transistor EO: Driving voltage control signal
V1: first logic level voltage V2: second logic level voltage
VGH: Gate high voltage VGL: Gate low voltage
VGH_EVEN: Excellent driving voltage VGH_ODD: Odd driving voltage
VST: start signal

Claims (9)

a display panel on which gate lines and data lines are disposed;
a gate driver supplying gate signals to the gate lines;
a timing control circuit for outputting an on clock signal, an off clock signal, and a driving voltage control signal;
a clock signal generator for outputting phase i (i is a positive integer greater than or equal to 2) control clock signals according to the on clock signal and the off clock signal; and a voltage level changer for changing the voltage level of the driving voltage control signal; level shifter; and
The i-phase control clock signals are switched using i switch pairs to output 2i-phase gate clock signals having different phases to the gate driver, and the driving voltage control signal whose voltage level is changed using one switch pair A switching unit for outputting an odd driving voltage and an even driving voltage to the gate driving unit by switching;
Each of the i switch pairs switches any one of the i-phase control clock signals to output two gate clock signals having different phases so that gate high voltage periods do not overlap each other. The method of claim 1,
The display device further comprising: a switching control signal generator generating i+1 switching control signals to control turn-on and turn-off of the i+1 switch pairs and supplying them to the i+1 switch pairs; . 3. The method of claim 2,
The two switches of each of the i+1 switch pairs are controlled to be alternately turned on and off by the switching control signals. 4. The method of claim 3,
A display device in which the switching control signal is directly input to one switch of each of the i+1 switch pairs, and an inversion signal of the switching control signal is input to the other switch. The method of claim 1,
The switching unit is included in the level shifter. The method of claim 1,
and a circuit board on which the timing control circuit and the level shifter are mounted, wherein the switching unit is mounted on the circuit board. 3. The method of claim 2,
The switching control signal generator is included in the timing control circuit or the level shifter. 3. The method of claim 2,
and a circuit board on which the timing control circuit and the level shifter are mounted, wherein the switching control signal generator is mounted on the circuit board. The method of claim 1,
Each of the control clock signals includes pulse waveforms of two gate clock signals.

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