KR20170010221A - Display device - Google Patents

Display device Download PDF

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Publication number
KR20170010221A
KR20170010221A KR1020150101196A KR20150101196A KR20170010221A KR 20170010221 A KR20170010221 A KR 20170010221A KR 1020150101196 A KR1020150101196 A KR 1020150101196A KR 20150101196 A KR20150101196 A KR 20150101196A KR 20170010221 A KR20170010221 A KR 20170010221A
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KR
South Korea
Prior art keywords
voltage
gate
control signal
driving voltage
logic level
Prior art date
Application number
KR1020150101196A
Other languages
Korean (ko)
Inventor
이창윤
이경우
강병수
Original Assignee
엘지디스플레이 주식회사
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Priority to KR1020150101196A priority Critical patent/KR20170010221A/en
Publication of KR20170010221A publication Critical patent/KR20170010221A/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Abstract

An embodiment of the present invention relates to a display device capable of reducing the number of output pins of a timing controller. A display device according to an embodiment of the present invention includes a display panel, a gate driver, a timing controller, and a level shifter. The display panel includes data lines, gate lines, and pixels provided at intersections of the data lines and the gate lines. The gate driver supplies gate signals to the gate lines. The timing controller outputs a start signal and an off-clock signal. The level shifter generates a driving voltage control signal using the start signal and the off-clock signal, and alternately supplies the odd driving voltage and the superior driving voltage to the gate driving unit in accordance with the driving voltage control signal.

Description

Display device {DISPLAY DEVICE}

An embodiment of the present invention relates to a display device.

2. Description of the Related Art [0002] As an information-oriented society develops, there have been various demands for a display device for displaying images. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various display devices such as an OLED (Organic Light Emitting Diode) are being utilized.

The display device includes a display panel, a gate driver, a data driver, and a timing controller. The display panel includes a plurality of pixels formed at intersections of the data lines, the gate lines, the data lines and the gate lines, and supplied with the data voltages of the data lines when the gate signals are supplied to the gate lines. The pixels emit light at a predetermined brightness according to the data voltages. The gate driver supplies gate signals to the gate lines. The data driver includes a source driver IC (hereinafter referred to as " IC ") that supplies data voltages to the data lines. The timing controller controls the operation timing of the gate driver and the data driver.

In recent years, since a high-resolution display device such as UHD (ultra high definition, 3840 × 2160) has been introduced, the number of control signals of the timing controller is also increasing. In this case, since the number of input / output pins of the timing controller increases, there is a problem that the cost of the timing controller increases due to an increase in size of the timing controller. Therefore, when a part of the control signals output from the timing controller is deleted, the number of output pins of the timing controller can be reduced, thereby preventing an increase in cost due to the timing controller.

Embodiments of the present invention provide a display device capable of reducing the number of output pins of a timing controller.

A display device according to an embodiment of the present invention includes a display panel, a gate driver, a timing controller, and a level shifter. The display panel includes data lines, gate lines, and pixels provided at intersections of the data lines and the gate lines. The gate driver supplies gate signals to the gate lines. The timing controller outputs a start signal and an off-clock signal. The level shifter generates a driving voltage control signal using the start signal and the off-clock signal, and alternately supplies the odd driving voltage and the superior driving voltage to the gate driving unit in accordance with the driving voltage control signal.

In the embodiment of the present invention, the level shifter includes the driving voltage control signal generating unit, so that the driving voltage control signal generating unit can directly generate the driving voltage control signal. As a result, since the embodiment of the present invention does not need to receive the drive voltage control signal from the timing controller, it can be deleted from the timing controller. Therefore, the embodiment of the present invention can reduce the number of output pins of the timing controller, thereby preventing an increase in cost due to the timing controller.

Further, an embodiment of the present invention arranges a resistor between the driving voltage control signal line and the transistor to delay the rising of the driving voltage control signal rising from the second logic level voltage to the first logic level voltage for a predetermined time. In particular, the embodiment of the present invention can set the size of the resistor in consideration of the fact that the stages of the gate driver are all set in consideration of the pull-down time. As a result, the embodiment of the present invention can prevent the stages from malfunctioning by alternating the odd driving voltage and the superior driving voltage after the operation of the stages is completely finished.

1 is an exemplary view showing a display device according to an embodiment of the present invention.
FIG. 2 is an exemplary view showing a lower substrate, source drive ICs, source flexible films, a source circuit board, a control circuit board, and a timing controller, and a level shifter of a display device according to an embodiment of the present invention.
FIG. 3 is an exemplary view showing an example of the pixel of FIG. 1; FIG.
4 is an exemplary view showing still another example of the pixel of Fig.
5 is a block diagram showing a stage of the gate driver of FIG.
6 is a block diagram showing the level shifter of FIG. 1 in detail;
FIG. 7 is a block diagram showing the drive voltage control signal generator of FIG. 6 in detail.
8 is a flow chart showing an example of a method of operating the drive voltage control signal generator of FIG.
FIG. 9 is a timing chart showing the relationship between the start signal and the off-clock signal input to the drive voltage control signal generation unit of FIG. 7, the drive voltage control signal output from the drive voltage control signal generation unit, Waveform diagram showing excellent drive voltage.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

Where the terms "comprises," "having," "consisting of," and the like are used in this specification, other portions may be added as long as "only" is not used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

The terms "X-axis direction "," Y-axis direction ", and "Z-axis direction" should not be construed solely by the geometric relationship in which the relationship between them is vertical, It may mean having directionality.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an exemplary view showing a display device according to an embodiment of the present invention. 2 is an exemplary view showing a lower substrate, source drive ICs, source flexible films, a source circuit board, a control circuit board, and a timing controller, and a level shifter of a display device according to an embodiment of the present invention.

The display device according to the embodiment of the present invention may include any display device for supplying data voltages to the pixels by line scanning which supplies the gate signals to the gate lines G1 to Gn. For example, the display device according to an exemplary embodiment of the present invention may be applied to a liquid crystal display (LCD), an organic light emitting display, a field emission display, an electrophoresis display).

1 and 2, a display device according to an embodiment of the present invention includes a display panel 10, a gate driver 11, a data driver 20, a timing controller 30, and a level shifter 40 Respectively.

The display panel 10 includes an upper substrate and a lower substrate. The data lines D1 to Dm and m are positive integers of two or more), gate lines (G1 to Gn, n is a positive integer of 2 or more), and data lines D1 to Dm and gate lines A display area DA including pixels P arranged in an intersection area of the pixels G1 to Gn is formed. The display panel 10 may be divided into a display area DA and a non-display area NDA. The display area DA is an area where pixels P are provided to display an image. The non-display area NDA is an area provided in the periphery of the display area DA, and is an area where no image is displayed.

Each of the pixels P may be connected to any one of the data lines D1 to Dm and one of the gate lines G1 to Gn. Accordingly, each of the pixels P receives the data voltage of the data line when the gate signal is supplied to the gate line, and emits light at a predetermined brightness according to the supplied data voltage.

When the display device is implemented as a liquid crystal display device, each of the pixels P includes a transistor T, a pixel electrode 11, a common electrode 12, a liquid crystal layer 13, and a storage capacitor Cst ). The transistor T is connected to the gate of the gate line Gk at a jth (j is a positive integer satisfying 1? J? M) in response to the gate signal of the k-th gate line Gk (k is a positive integer satisfying 1? And supplies the data voltage of the data line Dj to the pixel electrode 11. [ The common electrode 12 is supplied with a common voltage from the common voltage line VcomL. Each of the pixels P drives the liquid crystal of the liquid crystal layer 13 by an electric field generated by a potential difference between the data voltage supplied to the pixel electrode 11 and the common voltage supplied to the common electrode 12 The amount of light transmitted from the backlight unit can be adjusted. The backlight unit is disposed under the display panel 10 to irradiate the display panel 10 with uniform light. The storage capacitor Cst is provided between the pixel electrode 11 and the common electrode 12 to keep the voltage difference between the pixel electrode 11 and the common electrode 12 constant.

4, each of the pixels P includes an organic light emitting diode (OLED), a scan transistor ST, a driving transistor DT, and a storage capacitor Cst can do. The scan transistor ST supplies the data voltage of the jth data line Dj to the gate electrode of the driving transistor DT in response to the gate signal of the kth gate line Gk. The driving transistor DT controls the driving current flowing from the high potential voltage line VDDL to the organic light emitting diode OLED according to the data voltage supplied to the gate electrode. The organic light emitting diode OLED is provided between the driving transistor DT and the low potential voltage line VSSL and emits light at a predetermined brightness according to the driving current. The storage capacitor Cst may be provided between the gate electrode of the driving transistor DT and the high potential voltage line VDDL in order to keep the voltage of the gate electrode of the driving transistor DT constant.

The gate driver 11 supplies gate signals to the gate lines G1 to Gn. Specifically, the gate driver 11 receives the gate control signal GCS, generates gate signals according to the gate control signal GCS, and supplies the gate signals to the gate lines G1 to Gn.

The gate driver 11 may be provided in the non-display area NDA by a gate driver in panel (GIP) scheme. In FIG. 1, the gate driver 11 is provided in the non-display area NDA outside one side of the display area DA, but the present invention is not limited thereto. For example, the gate driver 11 may be provided in the non-display area NDA outside both sides of the display area DA.

Alternatively, the gate driver 11 may include a plurality of gate drive integrated circuits (hereinafter referred to as "ICs "), and the gate drive ICs may be mounted on the gate flexible films. Each of the gate flexible films may be a tape carrier package or a chip on film. The gate flexible films can be attached to the non-display area NDA of the display panel 10 by a TAB (tape automated bonding) method using an anisotropic conductive film, 0.0 > G1-Gn. ≪ / RTI >

The data driver 20 is connected to the data lines D1 to Dm. The data driver 20 receives the digital video data DATA and the data control signal DCS from the timing controller 30 and converts the digital video data DATA into analog data voltages in accordance with the data control signal DCS do. The data driver 20 supplies the analog data voltages to the data lines D1 to Dm. The data driver 20 may include at least one source driver IC 21. [

Each of the source drive ICs 21 may be made of a drive chip. Each of the source drive ICs 21 may be mounted on the source flexible film 60. Each of the source flexible films 60 may be embodied as a tape carrier package or a chip-on film and may be bent or bent. Each of the source flexible films 60 may be attached to the non-display area of the display panel 10 in a TAB manner using an anisotropic conductive film, whereby the source drive ICs 21 are connected to the data lines D1 to Dm, Lt; / RTI >

Alternatively, each of the source drive ICs 21 may be directly connected to the data lines D1 to Dm on a lower substrate by a chip on glass (COG) method or a chip on plastic (COP) method.

In addition, the source flexible films 60 may be attached on a source printed circuit board 70. FIG. The source printed circuit boards 70 may be flexible printed circuit boards that can be bent or bent. The source printed circuit boards 70 may be provided in one or more than one.

The timing controller 30 receives video data (DATA) and timing signals (TS) from an external system board (not shown). The timing signals may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock.

The timing controller 30 generates a start signal VST for controlling the operation timing of the gate driver 11 based on timing signals TS and drive timing information stored in a memory such as an electrically erasable programmable read-only memory (EEPROM) The on-clock signal on_CLK, and the off-clock signal off_CLK and generates a data control signal DCS for controlling the operation timing of the data driver 20. [ The timing controller 30 supplies the start signal VST, the on-clock signal on_CLK, and the off-clock signal off_CLK to the level shifter 40. The timing controller 30 supplies the video data DATA and the data control signal DCS to the data driver 20.

The level shifter 40 receives the start signal VST, the on clock signal on_CLK, and the off clock signal off_CLK from the timing controller 30. [ The level shifter 40 generates the gate clock signals using the on-clock signal on_CLK and the off-clock signal off_CLK. The level shifter 40 generates a driving voltage control signal using the start signal VST and the off clock signal off_CLK and alternately shifts the odd driving voltage and the superior driving voltage to the gate driving unit 11 in accordance with the driving voltage control signal . The odd driving voltage and the superior driving voltage are alternately supplied to the gate driving unit 11 to prevent deterioration of the transistor of the gate driving unit 11. A detailed description thereof will be given later with reference to FIG.

The level shifter 40 adjusts the voltage swing width of the start signal, the gate clock signals, the odd driving voltage, and the superior driving voltage to a voltage swing width suitable for driving the transistors of the gate driving unit 11 and the pixel array PA . For example, the level shifter 40 may adjust the voltage swing width of the start signal, the gate clock signals, the odd driving voltage, and the superior driving voltage from the gate low voltage to the gate high voltage.

The level shifter 40 supplies the gate control signal GCS to the gate driver 11. When the gate driver 11 is formed in the GIP scheme, the gate control signal GCS may include a start signal, gate clock signals, a radial driving voltage, and a superior driving voltage. The level shifter 40 will be described later in detail with reference to FIG.

The timing controller 30 and the level shifter 40 may be mounted on the control printed circuit board 90 as shown in FIG. The control printed circuit board 90 and the source printed circuit board 70 may be connected through a flexible circuit board 80 such as a flexible flat cable (FFC) or a flexible printed circuit (FPC).

5 is a block diagram showing a stage of the gate driver of FIG. 5, the gate driver 11 may include stages (STAs) which are connected in a dependent manner, and the stages SATA may be designed to sequentially output the gate signals to the gate lines G1 to Gn have.

Each of the stages STA includes a pull-up node NQ, a first pull-down node NQB1, a second pull-down node NQB2, a pull-up node NQ, A first pull-down transistor TD1 which is turned on when the first pull-down node NQB1 is charged to a gate high voltage, a second pull-down transistor TD2 which is turned on when the first pull- A second pull-down transistor TD2 which is turned on when the down node NQB2 is charged to a gate high voltage and a second pull-down transistor TD2 which is turned on when the pull-up node TU and the first and second pull- And a node control unit (NC) for controlling charging and discharging of the secondary battery (TD2).

The node control unit NC includes a start signal line VSTL to which a start signal or a carry signal of the previous stage is inputted, a clock line CL to which one of the gate clock signals is input, (VDD_OL), and the superior driving voltage line (VDD_EL) to which the superior driving voltage is input. The node control unit NC includes a start signal input to the start signal line VSTL or a carry signal of the previous stage and a gate clock signal input to the clock line CL, a radix driving voltage input to the radix driving voltage line VDD_OL, Up node TU and the first and second pull-down nodes TD1 and TD2 in accordance with an even driving voltage input to the even-numbered driving voltage line VDD_EL. The node controller NC controls the first and second pull-down nodes NQB1 and NQB2 when the pull-up node NQ is charged to the gate high voltage in order to stably control the output of the stage STA. And discharges the pull-up node NQ to the gate-low voltage when either of the first and second pull-down nodes NQB1 and NQB2 is charged to the gate high voltage.

The pull-up transistor TU is turned on when the stage STA is pulled up, that is, when the pull-up node NQ is charged with the gate high voltage, and outputs the gate clock signal of the clock line CL And outputs it to the terminal OT. The first pull-down transistor TD1 is turned on when the stage STA is pulled-down, for example when the first pull-down node NQB1 is charged to the gate high voltage, To the gate-low voltage of the gate-low voltage terminal VGLT. The second pull-down transistor TD2 is turned on when the stage STA is pulled down, for example when the second pull-down node NQB2 is charged to the gate high voltage, To the gate-low voltage of the gate-low voltage terminal VGLT.

On the other hand, when the odd driving voltage having the gate high voltage is supplied to the node controller NC, an even driving voltage having the gate low voltage is supplied to the node controller NC, and the odd driving voltage having the gate low voltage is supplied to the node controller NC, a superior driving voltage having a gate high voltage is supplied to the node control unit NC. The node control unit NC controls the pull-down of the stage STA using the first pull-down node NQB1 when the odd driving voltage having the gate high voltage is supplied, Down node NQB2 is used to control the pull-down of the stage STA. This can prevent the first and second pull-down transistors TD1 and TD2, which are applied with the gate high voltage for a longer time than the pull-up transistor TU, from deteriorating. That is, according to the embodiment of the present invention, by alternately supplying the odd driving voltage and the superior driving voltage, the stage STA can be pulled out by alternately using the first pull-down node NQB1 and the second pull- - down, thereby preventing the first and second pull-down transistors TD1 and TD2 from degrading.

In addition, the radial driving voltage and the superior driving voltage play an important role in pulling down the stage STA as described above. Therefore, it is preferable that the odd driving voltage and the superior driving voltage are alternated during the vertical blank period in which the stages STA output no gate signals than the active period in which the STA outputs the gate signals. In particular, it may happen that the stages STA are pulled down by the dummy stage even though they do not output the gate signals during the vertical blank period. Therefore, it is preferable that the odd driving voltage and the superior driving voltage alternate after the delay time by the predetermined time from the last time of the active period even in the vertical blank period. A detailed description thereof will be given later with reference to FIG.

FIG. 6 is a block diagram showing the level shifter of FIG. 1 in detail. 6, a level shifter 40 according to an embodiment of the present invention includes a gate clock signal generating unit 41, a voltage level changing unit 42, a gate clock signal modulating unit 43, And a generating unit 44. The voltage level changing unit 42 includes first to third voltage level changing units 42a, 42b and 42c.

The gate clock signal generation unit 41 receives the on-clock signal on_CLK and the off-clock signal off_CLK from the timing controller 30. The gate clock signal generator 41 generates the gate clock signals CLK1 to CLK6 using the on-clock signal on_CLK and the off-clock signal off_CLK. For example, the gate clock signal generator 41 may increase the gate clock signal in synchronization with the rising edge or the falling edge of the on-clock signal on_CLK and synchronize the rising edge or the falling edge of the off-clock signal off_CLK The gate clock signal can be polled. The falling edge means a period in which the on-clock signal on_CLK and the off-clock signal off_CLK fall from the first logic level voltage to the second logic level voltage. The rising edge means a period in which the on-clock signal on_CLK and the off-clock signal off_CLK rise from the second logic level voltage to the first logic voltage. The gate clock signal generator 41 may generate the gate clock signals CLK1 to CLK6 so as to be i-phase clock signals whose phases are sequentially delayed in order to ensure a sufficient charge time during high-speed driving. have. The first logic level voltage may be a drive voltage of 3.3V and the second logic level voltage may be 0V or ground voltage.

The first voltage level changing unit 42a receives the gate clock signals CLK1 to CLK6 from the gate clock signal generating unit 41 and receives the gate high voltage VGH and the gate low voltage Vcc from the power supply unit VGL). The first voltage level changing unit 42a changes the voltage swing width of the gate clock signals CLK1 to CLK6 from the gate low voltage VGL to the gate high voltage VGH. The gate low voltage VGL may be a voltage of 0 V or less, and the gate high voltage VGH may be a voltage of 15 V or more.

The gate clock signal modulator 43 receives the gate clock signals CLK1 to CLK6 whose voltage swing widths are changed. The gate clock signal modulator 43 modulates the gate high voltage VGH and the gate low voltage VGL at the polling edge of the gate signal when the gate clock signals CLK1 to CLK6 are output as gate signals at the gate driver 11. [ The gate high voltage VGH is divided into the gate high voltage VGH and the gate low voltage VGL in order to reduce the kickback voltage caused by the voltage difference between the gate clock signals CLK1 and CLK6 Gt;). ≪ / RTI > The kickback voltage refers to the voltage that the voltage variation of the gate line affects the pixel electrode due to the parasitic capacitance or the fringe capacitance between the gate line and the pixel electrode.

The second voltage level changing unit 42b receives the start signal VST from the timing controller 30 and receives the gate high voltage VGH and the gate low voltage VGL from a power supply unit (not shown). The second voltage level changing portion 42b changes the voltage swing width of the start signal VST from the gate low voltage VGL to the gate high voltage VGH and outputs the start signal.

The driving voltage control signal generator 44 counts the start signal VST and the off clock signal off_CLK to generate the driving voltage control signal EO. The driving voltage control signal generating unit 44 outputs the driving voltage control signal EO to the third voltage level changing unit 42c. A detailed description of the drive voltage control signal EO of the drive voltage control signal generation unit 44 will be given later with reference to FIGS. 7 to 9. FIG.

The third voltage level changing unit 42c receives the driving voltage control signal EO from the driving voltage control signal generating unit 44 and receives the gate high voltage VGH and the gate low voltage VGL ). The third voltage level changing unit 42c alternately outputs the odd driving voltage VDD_O and the superior driving voltage VDD_E every time the driving voltage control signal EO is input to the first logic level voltage or the second logic level voltage Output. For example, while the third voltage level changing section 42c outputs the superior driving voltage VDD_E having the odd driving voltage VDD_O and the gate low voltage VGL having the gate high voltage VGH, (VDD_E) having a gate low voltage (VGL) and a gate high voltage (VGH) having a gate low voltage (VGL) when a drive voltage control signal EO having a logic level voltage or a second logic level voltage ). While the third voltage level changing section 42c outputs the superior driving voltage VDD_E having the odd driving voltage VDD_O and the gate high voltage VGH having the gate low voltage VGL, (VDD_E) having the odd driving voltage (VDD_O) and the gate low voltage (VGL) having the gate high voltage (VGH) is supplied to the odd driving voltage (VDD_E) having the second logic level voltage Output.

On the other hand, the timing controller 30 generates a start signal VST, an on-clock signal on_CLK, and an off-clock signal off_CLK, which swing from a gate low voltage to a gate high voltage, There is a problem that power consumption is increased. The embodiment of the present invention is characterized in that the timing controller 30 generates the start signal VST, the on-clock signal VST, and the on-clock signal VST, which swing from the first logic level voltage having the smaller voltage swing width to the second logic level voltage, on_CLK and an off clock signal off_CLK and outputs a gate control signal GCS swinging from a gate low voltage to a gate high voltage by using the level shifter 40. [ As a result, in the embodiment of the present invention, the timing controller 30 generates the start signal VST, the on-clock signal on_CLK, and the off-clock signal off_CLK that swing from the gate low voltage to the gate high voltage, It is possible to reduce power consumption as compared with the case of outputting to the driving unit 11. [

7 is a detailed block diagram of the driving voltage control signal generator of FIG. 7, the driving voltage control signal generating unit 44 includes a first counter 44a, a second counter 44b, an AND gate, an inverter INV, a transistor T, a resistor R ), And a capacitor (C).

The first counter 44a includes a power supply terminal P, an input terminal I, an output terminal O, and a reset terminal R. [ The power supply terminal P of the first counter 44a is connected to the first logic level voltage source VCC to receive the first logic level voltage and the input terminal I receives the start signal VST. The reset terminal R of the first counter 44a receives the output signal of the AND gate circuit AND. That is, the output signal of the OR gate circuit AND is input as a reset signal for resetting the first counter 44a. The output terminal O of the first counter 44a is connected to the power supply terminal P of the second counter 44b.

The first counter 44a accumulates and counts the start signal VST input to the input terminal I when the first logic level voltage VCC is input to the power supply terminal P. [ The first counter 44a outputs the first control signal having the first logic level voltage to the output terminal O when the first cumulative count number in which the start signal VST is cumulatively counted is M (M is a positive integer) . The first counter 44a outputs a first control signal having a second logic level voltage to the output terminal O when the first cumulative count number is less than M (M). The first counter 44a initializes the first cumulative count number to "0" when the output signal of the AND gate circuit AND of the first logic level voltage is input to the reset terminal R.

The second counter 44b includes a power supply terminal P, an input terminal I, an output terminal O, and a reset terminal R. The power supply terminal P of the second counter 44b receives the first control signal from the first counter 44a and the input terminal I receives the off clock signal off_CLK. That is, the reset terminal R of the second counter 44b receives the output signal of the AND gate circuit AND. That is, the output signal of the OR gate circuit AND is input as a reset signal for resetting the second counter 44b. The output terminal O of the second counter 44b is connected to the control electrode of the transistor T.

The second counter 44b is turned on when a first control signal having a first logic level voltage is input to the power supply terminal P and is turned on when a second control signal having a second logic level voltage is input. Off. The second counter 44b accumulates and counts the off-clock signal off_CLK input to the input terminal I when the first control signal having the first logic level voltage is input. The second counter 44b outputs a second control signal having a first logic level voltage to the output terminal O (N is a positive integer) when the number of the second cumulative counts which are accumulated and counted off the clock signal off_CLK is N . The second counter 44b outputs a second control signal having a second logic level voltage to the output terminal O when the second cumulative count number is smaller than N. [ The second counter 44b initializes the second cumulative count number to "0" when the output signal of the AND gate circuit AND of the first logic level voltage is input to the reset terminal R.

The transistor T includes a control electrode, a first electrode and a second electrode. The control electrode of the transistor T is connected to the output terminal O of the second counter 44b and the first electrode is connected to the first logic level voltage source VCC and the second electrode is connected to the driving voltage control signal line EOL. The driving voltage control signal line EOL is a line on which the driving voltage control signal is outputted. The transistor T may be a field effect transistor (FET).

The transistor T is turned on when the second control signal of the first logic level voltage is input to the control electrode to turn on the first logic level voltage of the first logic level voltage source VCC to the drive voltage control signal line EOL Supply. In this case, the drive voltage control signal having the first logic level voltage is output to the drive voltage control signal line EOL.

Also, the transistor T is turned off when the first control signal of the second logic level voltage is input to the control electrode. In this case, since the driving voltage control signal line EOL is connected to the second logic level voltage source VGND, the driving voltage control signal having the second logic level voltage is outputted to the driving voltage control signal line EOL.

On the other hand, a resistor R may be disposed between the driving voltage control signal line EOL and the transistor T. [ As the magnitude of the resistor R increases, the rising of the drive voltage control signal rising from the second logic level voltage to the first logic level voltage may be delayed. In addition, a capacitor C may be disposed between the driving voltage control signal line EOL and the second logic level voltage source VGND. The second logic level voltage source (VGND) may supply a second logic level voltage, and the second logic level voltage may be 0V or ground voltage.

The AND gate circuit AND performs OR operation of the driving voltage control signal and the inversion signal of the output signal of the AND gate circuit AND to output the signal to the reset terminal R of each of the first and second counters 44a and 44b do. The inverter INV outputs the output signal of the AND gate AND as an input signal to the OR gate AND.

The OR gate circuit AND outputs a second logic level voltage when a drive voltage control signal having a second logic level voltage is input. The AND gate circuit AND outputs a first logic level voltage when a drive voltage control signal having a first logic level voltage is input. However, the OR gate circuit AND outputs the second logic level voltage when the output signal of the first logic level voltage is input to the second logic level voltage by the inverter INV.

As described above, according to the embodiment of the present invention, since the level shifter 40 includes the driving voltage control signal generating unit 40, the driving voltage control signal generating unit 40 can directly generate the driving voltage control signal can do. As a result, since the embodiment of the present invention does not need to receive the drive voltage control signal from the timing controller 30, it can be deleted from the timing controller. Therefore, the embodiment of the present invention can reduce the number of output pins of the timing controller, thereby preventing an increase in cost due to the timing controller. Hereinafter, the operation of the drive voltage control signal generator will be described in detail with reference to FIGS. 8 and 9. FIG.

8 is a flowchart showing an example of a method of operating the driving voltage control signal generator of FIG. FIG. 9 is a timing chart showing the relationship between the start signal and the off-clock signal input to the drive voltage control signal generation unit of FIG. 7, the drive voltage control signal output from the drive voltage control signal generation unit, Fig. 8 is a waveform chart showing an excellent driving voltage.

In FIG. 9, for convenience of explanation, it is illustrated that the i-th (i is a positive integer) frame period is a frame period in which the start signal VST starts to be accumulated and counted, and the i- M (M is a positive integer) frame period. As shown in Fig. 9, the frame period includes an active period ACT during which the stages STA of the gate driver 11 output gate signals and a vertical blank period VBI during which the stages STA do not output gate signals.

First, the first counter 44a accumulates the start signal VST input to the input terminal I when the first logic level voltage VCC is input to the power terminal P, Thereby calculating the first cumulative count number. (S101 in Fig. 8)

Second, the first counter 44a determines whether the first cumulative count number is M or not. When the first cumulative count number is smaller than M, the first counter 44a continuously counts the start signal VST to calculate the first cumulative count number. Further, the first counter 44a outputs the first control signal having the second logic level voltage to the output terminal O when the first cumulative count number is less than M. [

When the first counter 44a cumulatively counts the start signal VST from the i-th frame period to the (i + M) frame period as shown in Fig. 9, the first cumulative count number can be calculated as M. The first counter 44a outputs the first control signal having the first logic level voltage to the output terminal O when the first cumulative count number is M. (S102 in Fig. 8)

Third, the second counter 44b is turned off when the first control signal having the first logic level voltage is input to the power supply terminal P and is supplied to the input terminal I through the off-clock signal off_CLK, To calculate the second cumulative count number. Referring to FIG. 9, the second counter 44b is turned on during the i + M frame period in which the first cumulative count number is M, so that the off-clock signal off_CLK input to the input terminal I And the second cumulative count number is calculated by cumulatively counting. (S103 in Fig. 8)

Fourth, when the second cumulative count number is smaller than N, the second counter 44b continuously counts the off-clock signal off_CLK to calculate the second cumulative count number. The second counter 44b outputs a second control signal having a second logic level voltage to the output terminal O when the second cumulative count number is smaller than N. [

The second counter 44b outputs a second control signal having a first logic level voltage to the output terminal O when the second cumulative count number is N. [ In this case, the transistor T is turned on when the second control signal of the first logic level voltage is input to the control electrode to turn on the first logic level voltage of the first logic level voltage source VCC to the driving voltage control signal line EOL). As a result, the drive voltage control signal EO having the first logic level voltage is output to the drive voltage control signal line EOL. (S104 in Fig. 8)

On the other hand, since the number of off-clock signals off_CLK generated during the active period ACT of one frame period is determined to be N, when the number of second cumulative counts is N, the last end point of the active period ACT, . However, it may happen that the stages STA of the gate driver 11 during the vertical blank period are pulled down by the dummy stages even though they do not output the gate signals. In this case, if the odd driving voltage and the superior driving voltage are alternated, the dummy stages may not be stably pulled up, and the STAs may not be pulled-down properly. Therefore, it is preferable that the odd driving voltage and the superior driving voltage alternate after the delay time by the predetermined time from the last time of the active period even in the vertical blank period.

To this end, an embodiment of the present invention provides a driving voltage control signal (R) that rises from a second logic level voltage to a first logic level voltage by placing a resistor R between the driving voltage control signal line EOL and the transistor T EO) for a predetermined time. Since the rising delay period of the drive voltage control signal EO can be increased as the size of the resistor R is larger, the size of the resistor R takes into account the time during which the stages STA of the gate driver 11 are all pulled down .

The driving voltage control signal EO having the first logic level voltage during the vertical blanking period VBI of the (i + M) -th frame period is inputted to the third voltage level changing portion 43c. In this case, the third voltage level changing unit 43c changes the odd driving voltage VDD_O supplied as the gate high voltage VGH to the gate low voltage VGL, The voltage VDD_E is changed to the gate high voltage VGH. (S105 in Fig. 8)

The OR gate circuit AND outputs a first logic level voltage when a driving voltage control signal EO having a first logic level voltage is input. In addition, the OR gate circuit AND outputs a second logic level voltage when the output signal of the first logic level voltage is input to the second logic level voltage by the inverter INV.

The first counter 44a initializes the first cumulative count number to "0" when the output signal of the AND gate circuit AND of the first logic level voltage is input to the reset terminal R. In this case, the first counter 44a outputs the first control signal of the second logic level voltage to the output terminal.

The second counter 44b initializes the second cumulative count number to "0" when the output signal of the AND gate circuit AND of the first logic level voltage is input to the reset terminal R. Further, since the first control signal of the second logic level voltage is inputted to the power supply terminal P of the second counter 44b, the second counter 44b no longer outputs the second control signal having the first logic level voltage Do not output to the output terminal (OT). Thus, the transistor T is turned off, in which case the drive voltage control signal line EOL is connected to the second logic level voltage source VGND, so that the drive voltage control signal EO with the second logic level voltage And output to the driving voltage control signal line EOL.

As described above, according to the embodiment of the present invention, since the level shifter 40 includes the driving voltage control signal generating unit 40, the driving voltage control signal generating unit 40 can directly generate the driving voltage control signal can do. As a result, since the embodiment of the present invention does not need to receive the drive voltage control signal from the timing controller 30, it can be deleted from the timing controller. Therefore, the embodiment of the present invention can reduce the number of output pins of the timing controller, thereby preventing an increase in cost due to the timing controller.

In the embodiment of the present invention, a resistor R is disposed between the driving voltage control signal line EOL and the transistor T so that the driving voltage control signal EO rising from the second logic level voltage to the first logic level voltage ) For a predetermined period of time. In particular, the embodiment of the present invention can set the size of the resistor R in consideration of the fact that the stages STA of the gate driver 11 are all set in consideration of the pull-down time. As a result, the embodiment of the present invention can prevent the STAs from malfunctioning by alternating the odd driving voltage and the superior driving voltage after the operation of the stages STA is completely terminated.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: gate driver
20: Data driver 21: Source drive IC
30: timing controller 40: level shifter
41: Gate clock signal generating unit 42: Voltage level changing unit
43: gate clock signal modulating unit 44: driving voltage control signal generating unit
44a: first counter 44b: second counter
T: transistor R: resistance
AND: OR gate circuit INV: Inverter
60: source flexible film 70: source printed circuit board
80: control printed circuit board 90: flexible circuit board

Claims (7)

A display panel including data lines, gate lines, and pixels provided at intersections of the data lines and the gate lines;
A gate driver for supplying gate signals to the gate lines; And
A timing controller for outputting a start signal and an off-clock signal; And
And a level shifter for generating a driving voltage control signal by using the start signal and the off-clock signal, and alternately supplying the odd driving voltage and the superior driving voltage to the gate driving unit in accordance with the driving voltage control signal. The method according to claim 1,
Wherein the level shifter is configured such that the superior driving voltage having the odd driving voltage and the gate low voltage having the gate high voltage supplies the gate low voltage or the superior driving voltage having the gate high voltage has the superior A display device for supplying a driving voltage. The method according to claim 1,
Wherein the odd driving voltage and the superior driving voltage are alternated during a vertical blank period. The method according to claim 1,
The level shifter includes:
And a drive voltage control signal generator for counting the start signal and the off-clock signal, respectively, to generate the drive voltage control signal. 5. The method of claim 4,
Wherein the driving voltage control signal generator comprises:
A first counter for outputting a first control signal having a first logic level voltage when the first cumulative count number in which the start signal is cumulatively counted is M (M is a positive integer);
(N is a positive integer) when the first control signal having the first logic level voltage is input, and calculates a second cumulative count number by accumulating and counting the off-clock signal when the first control signal having the first logic level voltage is input, A second counter for outputting a second control signal having the first logic level voltage if the second control signal is in the first logic level voltage;
A transistor that is turned on by the second control signal having the first logic level voltage to supply the first logic level voltage to the drive voltage control line; And
And a resistor connected between the transistor and the driving voltage control line for delaying the driving voltage control signal of the driving voltage control line from rising from the second logic level voltage to the first logic level voltage. 6. The method of claim 5,
Wherein the driving voltage control signal generator comprises:
Further comprising an OR gate circuit for outputting a reset signal for resetting the first and second counters,
And the OR gate circuit performs an OR operation on the drive voltage control signal and the inversion signal of the output signal of the OR gate circuit to output the reset signal. 6. The method of claim 5,
Wherein the driving voltage control signal generator comprises:
And a capacitor connected between the driving voltage control line and a second logic level voltage source for supplying the second logic level voltage.
KR1020150101196A 2015-07-16 2015-07-16 Display device KR20170010221A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019015073A1 (en) * 2017-07-21 2019-01-24 惠科股份有限公司 Driving method and driving device for display panel
KR20190081229A (en) * 2017-12-29 2019-07-09 엘지디스플레이 주식회사 Display device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019015073A1 (en) * 2017-07-21 2019-01-24 惠科股份有限公司 Driving method and driving device for display panel
US10971092B2 (en) 2017-07-21 2021-04-06 HKC Corporation Limited Driving method and driving device of display panel
KR20190081229A (en) * 2017-12-29 2019-07-09 엘지디스플레이 주식회사 Display device

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