KR20170003088A - Display device - Google Patents

Abstract

An embodiment of the present invention relates to a display device which can prevent a power IC connected to a clock line from being damaged by an excessive current which flows through a gate control signal line due to static electricity applied to the gate control signal line. The display device according to the embodiment of the present invention comprises a display panel, a gate drive unit, a timing control unit, a power IC, and an electrostatic discharge circuit. Pixels connected to gate lines and data lines are disposed in the display panel. The gate drive unit supplies gate signals, swinging between a gate high voltage and a gate low voltage, to the gate lines. The timing control unit outputs a gate control signal adapted to control a drive timing for the gate drive unit. The power IC is disposed between the gate drive unit and the timing control unit, and changes a swinging width of a voltage of the gate control signal. The electrostatic discharge circuit is disposed between the gate drive unit and the power IC, and discharges a gate control signal line when positive static electricity having a voltage higher than the gate high voltage is applied to the gate control signal line via which the gate control signal is provided.

Description

Display device {DISPLAY DEVICE}

An embodiment of the present invention relates to a display device.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. 2. Description of the Related Art Recently, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED) have been used.

The display device includes a display panel, a gate driver, a data driver, a timing controller, and an integrated circuit (IC). The display panel includes a plurality of pixels formed at intersections of the data lines, the gate lines, the data lines and the gate lines, and supplied with the data voltages of the data lines when the gate signals are supplied to the gate lines. The pixels emit light at a predetermined brightness according to the data voltages. The gate driver supplies gate signals to the gate lines. The data driver includes source driver ICs for supplying data voltages to the data lines. The timing control unit outputs a gate control signal for controlling the operation timing of the gate driving unit to the gate driving unit and a data control signal for controlling the operation timing of the data driving unit to the data driving unit. The power IC supplies the driving voltage to the data driving unit, changes the voltage swing width of the gate control signal from the timing control unit, and outputs it to the gate driving unit.

In recent years, the thickness of the display device has been thinned and the bezel area of the display device has been reduced in order to enhance the aesthetics. The bezel area of the display device corresponds to a non-display area covered by the cover member without displaying an image as a frame of the display device. In recent years, a borderless type display device has been introduced, in which a top case covering the top edge region of the display panel is removed in order to minimize the bezel area of the display device.

In the borderless method, the upper case covering the upper edge region of the display panel is removed, so that a part of the LOG region where the line on glass of the display panel is formed is covered with only the plastic cover member. For example, in the LOG area, the start signal line and the clock lines may be formed of line-on-glass. The start signal line is a line for supplying a start signal from the power IC to the gate driver, and the clock lines include clock lines for supplying clock signals from the power IC. The gate control signal includes a start signal and a clock signal.

As a result, some start signal lines and clock lines of the LOG region are covered only by a plastic cover member, so that there is a high probability that static electricity is introduced. In addition, when static electricity is introduced into the start signal line and the clock lines, the power IC connected to the start signal line and the clock lines due to the static electricity may be damaged.

Embodiments of the present invention provide a display device capable of preventing damage to a power IC when static electricity is applied to a gate control signal line in a borderless manner.

A display device according to an embodiment of the present invention includes a display panel, a gate driver, a timing controller, a power IC, and an electrostatic protection circuit. The display panel is provided with pixels connected to gate lines and data lines. The gate driver supplies gate signals swinging between a gate high voltage and a gate low voltage to the gate lines. The timing control unit outputs a gate control signal for controlling the driving timing of the gate driving unit. The power IC is disposed between the gate driver and the timing controller and changes a voltage swing width of the gate control signal. The static electricity protection circuit is disposed between the gate driver and the power IC and when positive static electricity having a voltage higher than the gate high voltage is applied to the gate control signal line to which the gate control signal is supplied, .

Embodiments of the present invention provide a method and system for discharging a gate control signal line to a gate high voltage through an electrostatic protection circuit when positive static electricity having a voltage greater than a gate high voltage is applied to the gate control signal line, When negative static electricity is applied, the gate control signal line can be charged to the gate low voltage through the electrostatic protection circuit. As a result, the embodiment of the present invention can prevent an overcurrent in the gate control signal line due to the static electricity applied to the gate control signal line from damaging the power IC connected to the clock line.

1 is a block diagram schematically showing a display device according to an embodiment of the present invention;
FIG. 2 is an exemplary view showing the pixel of FIG. 1; FIG.
Figure 3 is another exemplary view showing the pixel of Figure 1;
FIG. 4 is an exemplary view showing a lower substrate, a gate driver, source drive ICs, flexible films, a flexible circuit board, a timing controller, a power IC, and an electrostatic protection circuit of the display panel of FIG.
5 is a circuit diagram showing an electrostatic protection circuit according to a first embodiment of the present invention;
6A is a circuit diagram showing an electrostatic discharge path when a static electricity larger than a gate high voltage is applied.
6B is a circuit diagram showing an electrostatic discharge path when a static electricity smaller than a gate low voltage is applied.
FIGS. 7A and 7B are waveform diagrams showing a clock signal when no static electricity is applied and when a static electricity is applied. FIG.
8 is a circuit diagram showing an electrostatic protection circuit according to a second embodiment of the present invention;
9A is a circuit diagram showing an electrostatic discharge path when a static electricity larger than a gate high voltage is applied.
FIG. 9B is a circuit diagram showing an electrostatic discharge path when static electricity smaller than a gate low voltage is applied; FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

Where the terms "comprises," "having," "consisting of," and the like are used in this specification, other portions may be added as long as "only" is not used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

The terms "X-axis direction "," Y-axis direction ", and "Z-axis direction" should not be construed solely by the geometric relationship in which the relationship between them is vertical, It may mean having directionality.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically showing a display device according to an embodiment of the present invention. 1, a display device according to an embodiment of the present invention includes a display panel 10, a gate driver 20, a data driver 30, a timing controller 40, and a power integrated circuit IC ").

The display device according to the embodiment of the present invention may include any display device that supplies data voltages to pixels with line sequential scanning that sequentially supplies the gate signals to the gate lines G1 to Gn. For example, the display device according to an exemplary embodiment of the present invention may be applied to a liquid crystal display (LCD), an organic light emitting display, a field emission display, an electrophoresis display).

The display panel 10 includes an upper substrate and a lower substrate. The data lines (D1 to Dm, m is a positive integer of 2 or more) and the gate lines (G1 to Gn, n are positive integers of 2 or more) are formed on the lower substrate. A display area PA including pixels P connected to the data lines D1 to Dm and the gate lines G1 to Gn is formed on the lower substrate. The pixel P may be connected to any one of the data lines D1 to Dm and the gate lines G1 to Gn. Accordingly, the pixel P receives the data voltage of the data line when the gate signal is supplied to the gate line, and emits light at a predetermined brightness according to the supplied data voltage.

When the display device is implemented as a liquid crystal display device, each of the pixels P may include a transistor T, a pixel electrode 11, and a storage capacitor Cst as shown in FIG. The transistor T is connected to the gate of the gate line Gk at a jth (j is a positive integer satisfying 1? J? M) in response to the gate signal of the k-th gate line Gk (k is a positive integer satisfying 1? And supplies the data voltage of the data line Dj to the pixel electrode 11. [ Each of the pixels P drives the liquid crystal of the liquid crystal layer 13 by an electric field generated by a potential difference between the data voltage supplied to the pixel electrode 11 and the common voltage supplied to the common electrode 12 The amount of light transmitted from the backlight unit can be adjusted. The common electrode 12 receives a common voltage from the common voltage line VcomL and the backlight unit is disposed below the display panel 10 to irradiate the display panel 10 with uniform light. The storage capacitor Cst is provided between the pixel electrode 11 and the common electrode 12 to keep the voltage difference between the pixel electrode 11 and the common electrode 12 constant.

3, each of the pixels P includes an organic light emitting diode (OLED), a scan transistor ST, a driving transistor DT, and a storage capacitor Cst can do. The scan transistor ST supplies the data voltage of the jth data line Dj to the gate electrode of the driving transistor DT in response to the gate signal of the kth gate line Gk. The driving transistor DT controls the driving current flowing from the high potential voltage line VDDL to the organic light emitting diode OLED in accordance with the data voltage supplied to the gate electrode thereof. The organic light emitting diode OLED is provided between the driving transistor DT and the low potential voltage line VSSL and emits light at a predetermined brightness according to the driving current. The storage capacitor Cst may be provided between the gate electrode of the driving transistor DT and the high potential voltage line VDDL in order to keep the voltage of the gate electrode of the driving transistor DT constant.

The gate driver 20 receives the gate control signal GCS from the power IC 50. The gate driver 20 generates gate signals according to the gate control signal GCS and supplies the gate signals to the gate lines G1 to Gn. The gate driver 20 may be formed in a non-display region using a gate driver in panel (GIP) scheme, but the present invention is not limited thereto. The non-display area indicates an area where no image is displayed in the peripheral portion of the display area PA. 1, the gate driver 11 is provided on one side of the display area DA, but the present invention is not limited thereto. For example, the gate driver 11 may be provided on both sides of the display area DA.

The data driver 30 is connected to the data lines D1 to Dm. The data driver 30 receives the digital video data DATA and the data control signal DCS from the timing controller 40 and converts the digital video data DATA into analog data voltages in accordance with the data control signal DCS. do. The data driver 30 supplies the data voltages to the data lines D1 to Dm. The data driver 30 may include a plurality of source drive ICs 31 as shown in FIG.

The timing controller 40 receives digital video data DATA and timing signals TS from an external system board (not shown). The timing signals TS may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock. The timing control unit 40 generates a gate control signal GCS for controlling the operation timing of the gate driving unit 20 and a data control signal DCS for controlling the operation timing of the data driving unit 30 based on the timing signal do.

The gate control signal GCS may include a start signal and clock signals. The start signal is a signal for controlling the output timing of the first gate signal in one frame period. The clock signals are signals having an i-phase that is sequentially delayed.

The data control signal DCS includes a source start signal, a source sampling clock, a source output enable signal, a polarity control signal, and the like. The source start signal is a signal for controlling the data sampling start timing of the data driver 30. The source sampling clock is a clock signal for controlling the sampling operation of the data driver 30 based on the rising or falling edge. The polarity control signal is a signal for inverting the polarity of the data voltages output from the data driver 30 into L (L is a natural number) horizontal period period. The source output enable signal is a signal for controlling the output of the data driver 30. [

The timing controller 40 supplies the digital video data DATA and the data control signal DCS to the data driver 30. The timing control unit 40 supplies the gate control signal GCS to the power IC 50. [

The power IC 50 generates a driving voltage VDD necessary for driving the source drive ICs 31 of the data driver 30 and supplies the generated drive voltage VDD to the source driver ICs 31 of the data driver 30. [ The power IC 50 receives the gate control signal GCS from the timing controller 40 and changes the swing width of the gate control signal GCS from the gate low voltage VGL to the gate high voltage VGH And outputs it to the gate driver 20. Further, the power IC 50 outputs the gate high voltage VGH and the gate low voltage VGL to the gate driver 20. The gate high voltage VGH is a voltage capable of turning on the transistors of the pixels P formed in the display panel 10 and the gate low voltage VGL is a voltage capable of turning on the transistors of the pixels P formed in the display panel 10. [ Off < / RTI >

4 is an exemplary view showing a lower substrate, a gate driver, source drive ICs, source flexible films, a printed circuit board, a timing controller, a power IC, and an electrostatic protection circuit of the display panel of FIG. 4, data lines, gate lines, and pixels formed on the lower substrate 11 of the display panel 10 are omitted for convenience of explanation.

Referring to FIG. 4, the gate driver 20 may be formed in a non-display region using a gate driver in panel (GIP) scheme, but the present invention is not limited thereto. That is, the gate driver 20 is fabricated as a driving chip and mounted on the gate flexible film, and the gate flexible films are formed by an anisotropic conductive film in a tape automated bonding (TAB) 14). ≪ / RTI >

Each of the source drive ICs 31 may be fabricated as a drive chip and mounted on the source flexible film 70. Each of the source flexible films 70 may be implemented as a tape carrier package or a chip on film. The chip-on film may include a base film such as polyimide and a plurality of conductive lead wires provided on the base film. Each of the source flexible films 70 may be bent or bent. The source flexible films 70 may be attached on the lower substrate 14 in a TAB manner using an anisotropic conductive film.

In addition, the source flexible films 70 may be attached on a printed circuit board 80. The printed circuit board 80 may be embodied as a flexible printed circuit board that can be bent or bent.

Each of the timing control unit 40 and the power IC 50 may be manufactured as a driving chip and mounted on the printed circuit board 80. The timing controller 40 and the power IC 50 may be connected through the first start signal line STL1 and the first clock signal lines CLS1. The power IC 50 may be connected through the second start signal line STL2 and the second clock signal lines CLS2. The first start signal line (STL1) and the first clock signal lines (CLS1) are formed on the printed circuit board (80). On the other hand, the second start signal line STL2 and the second clock signal lines CLS2 are formed on the printed circuit board 80, the source flexible film 70, and the lower substrate 14. In particular, the second start signal line STL2 and the second clock signal lines CLS2 formed on the lower substrate 14 may be formed of line on glass in the non-display region. Since the gate control signal includes the start signal and the clock signals, the first and second start signal lines STL1 and STL2 and the first and second clock signal lines CLS1 and CLS2 are connected to the gate control signal line Can be collectively called.

The timing control section 40 supplies a start signal to the power IC 50 through the first start signal line STL1 and supplies clock signals to the power IC 50 through the clock signal lines CLS. The start signal and the clock signal output from the timing control unit 40 swing between 0 and 3.3V. Therefore, the power IC 50 changes the voltage swing width of the start signal supplied through the first start signal line STL1 to be suitable for driving the transistors of the pixels P formed on the display panel. That is, the power IC 50 changes the voltage swing width of the start signal supplied through the first start signal line STL1 from the gate low voltage to the gate high voltage. In addition, the power IC 50 changes the voltage swing width of the clock signals supplied via the first clock lines CLS1 to be suitable for driving the transistors of the pixels P formed in the display panel. That is, the power IC 50 changes the voltage swing width of the clock signals supplied through the first clock lines CLS1 from the gate low voltage to the gate high voltage.

The power IC 50 supplies the gate driver 20 with a start signal having a swing width from the gate low voltage to the gate high voltage through the second start signal line STL2. The power IC 50 supplies clock signals having a swing width from the gate low voltage to the gate high voltage to the gate driver 20 through the second clock lines CLS2. The power IC 50 supplies the gate high voltage to the gate driver 20 through the gate high voltage line VGHL and the gate low voltage VGL to the gate driver 20 through the gate low voltage line VGLL. ).

Meanwhile, a display device according to an exemplary embodiment of the present invention may be manufactured in a borderless manner in which a top case covering an upper edge region of a display panel is removed in order to enhance a sense of beauty. When the display device according to the embodiment of the present invention is manufactured by the borderless method, the bezel area of the display device can be minimized by removing the upper case. The bezel area of the display device corresponds to a non-display area covered by the cover member without displaying an image as a frame of the display device.

However, when the display device according to the embodiment of the present invention is manufactured by the borderless method, the second start signal line (line on glass) corresponding to the line on glass formed on the upper edge of the display panel due to the removal of the upper case STL2 and the second clock lines CLS2 are covered only by a plastic cover member. As a result, there is a high probability that static electricity will flow into the second start signal line (STL2) and the second clock lines (CLS2). When the static electricity flows into the second start signal line STL2 and the second clock lines CLS2, the power IC 50 connected to the second start signal line STL2 and the second clock lines CLS2 It can be damaged by static electricity.

The display device according to the embodiment of the present invention is provided with the second start signal line STL2 to prevent the power IC 50 connected to the second clock lines CLS2 from being damaged by static electricity, And electrostatic protection circuits 60a / 60b connected to the second clock lines CLS2 and STL2, respectively. The electrostatic protection circuits 60a and 60b are connected to the LOG area LA in which the printed circuit board 80, the second start signal line STL2 and the second clock lines CLS2 are formed of line-on glass . 4 illustrates that the static electricity protection circuit 60a / 60b is formed on both the printed circuit board 80 and the LOG area LA in order to enhance the electrostatic protection effect. However, the printed circuit board 80 and the LOG area LA It may be formed in only one place. On the other hand, since the printed circuit board 80 is less restrictive than the LOG area LA, while the bezel shrinks there is a restriction on enlarging the LOG area LA of the display panel, It is advantageous in that it can be designed in a larger area than when formed in the LOG area LA.

When the positive static electricity having a voltage higher than the gate high voltage is applied to the second start signal line STL2 and the second clock line CLS2 respectively, the static electricity protection circuit 60a / 60b supplies the second start signal line STL2 And the second clock lines CLS2, respectively. The static electricity protection circuit 60a / 60b is configured such that when negative static electricity having a voltage lower than the gate low voltage is applied to each of the second start signal line STL2 and the second clock lines CLS2, the second start signal line STL2 And the second clock lines CLS2, respectively. A detailed description of the electrostatic protection circuit 60a / 60b will be given later in conjunction with FIG. 5 and FIG.

5 is a circuit diagram showing an electrostatic discharge protection circuit according to the first embodiment of the present invention. 5 shows a gate high voltage line (VGHL) to which a gate high voltage is supplied, a gate low voltage line (VGLL) to which a gate low voltage is supplied, and a ground (GND) having a ground voltage. The ground voltage is a voltage having a level between the gate high voltage VGH and the gate low voltage VGL. The second start signal line STL2, the second clock lines CLS2, the gate high voltage line VGHL and the gate low voltage line VGLL are connected to the power IC 50 as shown in FIGS. And the gate driver 20 are connected to each other.

5, the power IC 50 outputs a clock signal CLK swinging between the gate low voltage VGL and the gate high voltage VGH through the clock line CL to the gate driver 20 . In Fig. 5, R _CL represents the resistance of the clock line CL. In FIG. 5, only the electrostatic protection circuit connected to one of the clock lines CL of the second clock lines CLS2 is illustrated for convenience of explanation. Therefore, the electrostatic protection circuit connected to each of the other of the second start signal line STL2 and the second clock lines CLS2 is substantially the same as that shown in Fig.

The electrostatic protection circuit 60a / 60b according to the first embodiment of the present invention includes first and second diodes D1 and D2 and first and second capacitors C1 and C2.

The anode electrode of the first diode D1 is connected to the clock line CL and the cathode electrode is connected to the gate high voltage line VGHL. The anode electrode of the second diode D2 is connected to the gate low voltage line VGLL, and the cathode electrode is connected to the clock line CL. The first capacitor C1 is connected between the gate high voltage line VGHL and the ground GND and the second capacitor C2 is connected between the gate low voltage line VGLL and the ground GND.

The electrostatic protection circuit 60a / 60b is turned on when the positive electrostatic ESD (+) having a voltage higher than the gate high voltage VGH is applied to the clock line CL as shown in FIG. Is discharged from the clock line CL to the ground GND through the first diode D1, the gate high voltage line VGHL, and the first capacitor C1 as shown in FIG. 6A. A positive static electricity ESD (+) voltage having a voltage higher than the gate high voltage VGH is generated because the anode electrode of the first diode D1 is connected to the clock line CL and the cathode electrode is connected to the gate high voltage line VGHL. ) Is applied to the clock line CL, the voltage of the clock line CL may be discharged to the gate high voltage VGH as shown in FIG. 7B.

When the negative electrostatic ESD (-) having a voltage lower than the gate low voltage VGL is applied to the clock line CL, the voltage of the clock line CL is set to a voltage level lower than the gate low voltage VGL in the electrostatic protection circuit 60a / Is charged from the ground GND to the clock line CL via the second capacitor C2, the gate low voltage line VGLL and the second diode D2. Since the anode electrode of the second diode D2 is connected to the gate low voltage line VGLL and the cathode electrode is connected to the clock line CL, a negative static electricity ESD (-) having a voltage lower than the gate low voltage VGL, ) Is applied to the clock line CL, the voltage of the clock line CL may be charged to the gate-low voltage VGL as shown in FIG. 7B.

As described above, according to the first embodiment of the present invention, when the positive electrostatic ESD (+) having a voltage higher than the gate high voltage VGH is applied to the gate control signal line, the electrostatic protection circuit 60a / (ESD (-)) having a voltage lower than the gate low voltage (VGL) is applied through the electrostatic protection circuit (60a / 60b) by discharging the gate control signal line to the gate high voltage And charges the gate control signal line to the gate low voltage (VGL). Therefore, the first embodiment of the present invention can prevent the power IC 50 connected to the clock line CL from being damaged due to the overcurrent flowing in the gate control signal line due to the static electricity applied to the gate control signal line. The gate control signal line may be either the second start signal line STL2 or the second clock signal lines CLS.

8 is a circuit diagram showing an electrostatic discharge protection circuit according to a second embodiment of the present invention. FIG. 8 shows a gate high voltage line (VGHL) to which a gate high voltage is supplied, a gate low voltage line (VGLL) to which a gate low voltage is supplied, and a ground (GND) having a ground voltage. The second start signal line STL2, the second clock lines CLS2, the gate high voltage line VGHL and the gate low voltage line VGLL are connected to the power IC 50 as shown in FIGS. And the gate driver 20 are connected to each other.

8, the power IC 50 supplies the clock signal CLK swinging between the gate low voltage VGL and the gate high voltage VGH through the clock line CL to the gate driver 20 . In FIG. 8, only the electrostatic protection circuit connected to one of the clock lines CL of the second clock lines CLS2 is shown for convenience of explanation. Therefore, the electrostatic protection circuit connected to each of the other of the second start signal line STL2 and the second clock lines CLS2 is substantially the same as that shown in Fig.

The electrostatic protection circuit 60a / 60b according to the second embodiment of the present invention includes first and second diodes D1 and D2, first and second capacitors C1 and C2, and first and second diodes D1 and D2, Transistors T1 and T2, and first to fourth resistors R1, R2, R3 and R4.

The anode electrode of the first diode D1 is connected to the clock line CL and the cathode electrode is connected to the gate high voltage line VGHL. The anode electrode of the second diode D2 is connected to the gate low voltage line VGLL, and the cathode electrode is connected to the clock line CL. The first capacitor C1 is connected between the gate high voltage line VGHL and the ground GND and the second capacitor C2 is connected between the gate low voltage line VGLL and the ground GND.

The first and second resistors R1 and R2 are connected in series between the gate high voltage line VGHL and the ground GND. The third and fourth resistors R3 and R4 are connected in series between the gate gate low voltage line VGLL and the ground GND.

The gate electrode of the first transistor T1 is connected to the first node N1 between the first and second resistors R1 and R2 and the source electrode thereof is connected to the ground GND. And is connected to the voltage line VGHL.

The voltage of the first node N1 is a voltage dropped from the gate high voltage VGH by the first resistor R1. The threshold voltage of the first transistor T1 is lower than the threshold voltage of the first node N1 and the ground voltage CL when a static electricity ESD (+) having a voltage higher than the gate high voltage VGH is not applied to the clock line CL. . The first transistor T1 is not turned on and therefore the gate high voltage line VGHL is turned on when the static electricity ESD (+) having a voltage higher than the gate high voltage is not applied to the clock line CL, The gate high voltage VGH can be stably maintained.

When ESD (+) having a voltage higher than the gate high voltage VGH is applied to the clock line CL, as shown in FIG. 7B, the ESD (+) is applied from the clock line CL through the first diode D1, Since the current flows to the gate high voltage line (VGHL), the gate high voltage line (VGHL) has a voltage higher than the gate high voltage (VGH). As a result, the voltage of the first node N1 also rises. Therefore, the threshold voltage of the first transistor T1 becomes smaller than the difference voltage between the voltage of the first node N1 and the ground voltage. As a result, when the electrostatic ESD (+) having a voltage higher than the gate high voltage is applied to the clock line CL, the first transistor T1 is turned on. Accordingly, the voltage of the clock line CL is discharged from the clock line CL to the ground GND through the first diode D1, the gate high voltage line VGHL and the first transistor T1 as shown in FIG. 9A .

As a result, in the second embodiment of the present invention, when a static electricity ESD (+) having a voltage higher than the gate high voltage is applied to the clock line CL, the voltage of the clock line CL is applied to the first transistor T1 And discharged to the ground (GND) via the first capacitor (C1). Thus, discharge can be stably performed faster than that in the first embodiment in which discharge is performed to the ground (GND) through the first capacitor (C1). On the other hand, the first transistor T1 must be turned off when no static electricity (ESD (+)) having a voltage higher than the gate high voltage VGH is applied to the clock line CL, (ESD +) is applied to the clock line CL, a current must flow from the gate high voltage line VGHL to the ground GND. Therefore, an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistors.

The gate electrode of the second transistor T2 is connected to the second node N2 between the third and fourth resistors R3 and R4 and the source electrode thereof is connected to the ground GND, And is connected to the voltage line VGLL.

The voltage of the second node N2 is a voltage dropped from the gate low voltage VGL by the third resistor R3. The threshold voltage of the second transistor T2 is higher than the threshold voltage of the second node N2 and the ground voltage of the ground line CL when no negative electrostatic ESD (-) having a voltage lower than the gate low voltage VGL is applied to the clock line CL. Is greater than the difference voltage between the voltages. As a result, the second transistor T2 is not turned on if a negative electrostatic ESD (-) having a voltage lower than the gate low voltage VGL is not applied to the clock line CL, The line VGLL can stably maintain the gate-low voltage VGL.

When a negative electrostatic ESD (-) having a voltage lower than the gate low voltage VGL is applied to the clock line CL as shown in FIG. 7B, the gate low voltage line (VL) is supplied through the second diode D2 VGLL, the gate-low voltage line VGLL has a voltage lower than the gate-low voltage VGL. As a result, the voltage of the second node N2 is also lowered. Therefore, the threshold voltage of the second transistor T2 becomes smaller than the difference voltage between the voltage of the first node N1 and the ground voltage. As a result, when the negative electrostatic ESD (-) having a voltage lower than the gate low voltage VGL is applied to the clock line CL, the second transistor T2 is turned on. Therefore, the voltage of the clock line CL is charged from the ground GND to the clock line CL via the second capacitor C2, the gate low voltage line VGLL and the second diode D2 as shown in Fig. 9B .

As a result, in the second embodiment of the present invention, when a negative electrostatic ESD (-) having a voltage lower than the gate low voltage VGL is applied to the clock line CL, It can be stably charged faster than the first embodiment in which the clock line CL is charged through the second capacitor C2. On the other hand, the second transistor T2 must be turned off when a static electricity ESD (-) having a voltage lower than the gate low voltage VGL is not applied to the clock line CL, and the gate low voltage VGL When a negative electrostatic ESD (-) having a voltage smaller than VGL is applied to the clock line CL, a current must flow from the ground GND to the gate low voltage line VGLL, .

As described above, according to the second embodiment of the present invention, when the positive electrostatic ESD (+) having a voltage higher than the gate high voltage VGH is applied to the gate control signal line, the electrostatic protection circuit 60a / (ESD (-)) having a voltage lower than the gate low voltage (VGL) is applied through the electrostatic protection circuit (60a / 60b) by discharging the gate control signal line to the gate high voltage And charges the gate control signal line to the gate low voltage (VGL). Therefore, the second embodiment of the present invention can prevent the power IC 50 connected to the clock line CL from being damaged because an overcurrent flows to the gate control signal line due to the static electricity applied to the gate control signal line. The gate control signal line may be either the second start signal line STL2 or the second clock signal lines CLS.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: pixel electrode
12: common electrode 13: liquid crystal layer
14: lower substrate 20: gate driver
30: Data driver 31: Source drive IC
40: timing controller 50: power IC
60a / 60b: electrostatic protection circuit 70: source flexible film
80: printed circuit board D1: first diode
D2: second diode C1: first capacitor
C2: second capacitor R1: first resistance
R2: second resistor R3: third resistor
R4: fourth resistor T1: first transistor
T2: second transistor CL: clock line
CLS1: First clock lines CLS2: Second clock lines
CLK: clock signal STL1: first start signal line
STL2: Second start signal line GCS: Gate control signal
DCS: data control signal

Claims (13)

A display panel provided with pixels connected to the gate lines and the data lines;
A gate driver for supplying gate signals swinging between a gate high voltage and a gate low voltage to the gate lines;
A timing controller for outputting a gate control signal for controlling a driving timing of the gate driver;
A power IC disposed between the gate driver and the timing controller for changing a voltage swing width of the gate control signal; And
And a positive electrostatic discharge protection circuit which is disposed between the gate driving part and the power IC and applies positive static electricity having a voltage higher than the gate high voltage to the gate control signal line to which the gate control signal is supplied, A display comprising a circuit. The method according to claim 1,
Wherein the static electricity protection circuit charges the gate control signal line when a negative static electricity having a voltage smaller than the gate low voltage is applied to the gate control signal line. 3. The method of claim 2,
Wherein the timing control section, the power IC, and the static electricity protection circuit are provided on a printed circuit board connected to a flexible film connected to the display panel. The method according to claim 2 or 3,
Wherein the timing control unit and the power IC are provided on a printed circuit board connected to a flexible film connected to the display panel, and the electrostatic protection circuit comprises: A display device provided in a non-display area of a panel. The method according to claim 1,
The electrostatic protection circuit includes:
A first diode having an anode electrode connected to the gate control signal line and a cathode electrode connected to a gate high voltage line to which the gate high voltage is supplied; And
And a first capacitor connected between the gate high voltage line and a ground having a ground voltage. 6. The method of claim 5,
The electrostatic protection circuit includes:
First and second resistors serially connected between the gate high voltage line and the ground; And
And a first transistor having a gate electrode connected to a first node between the first and second resistors, a source electrode connected to the ground, and a drain electrode connected to the gate high voltage line. The method according to claim 6,
Wherein the voltage at the first node is a voltage at which the gate high voltage is voltage dropped by the first resistor,
The threshold voltage of the first transistor is greater than the difference voltage between the voltage of the first node and the ground voltage when the positive static electricity is not applied to the gate control signal line,
Wherein the threshold voltage of the first transistor is smaller than the difference voltage between the voltage of the first node and the ground voltage when the positive static electricity is applied to the gate control signal line. The method according to claim 6,
Wherein the first transistor is an N-type MOSFET. 3. The method of claim 2,
The electrostatic protection circuit includes:
A second diode having an anode electrode connected to the gate low voltage line to which the gate low voltage is supplied and a cathode electrode connected to the gate control signal line; And
And a second capacitor connected between the gate low voltage line and a ground having a ground voltage. 10. The method of claim 9,
The electrostatic protection circuit includes:
Third and fourth resistors connected in series between the gate low voltage line and the ground; And
And a second transistor having a gate electrode connected to a second node between the third and fourth resistors, a source electrode connected to the ground, and a drain electrode connected to the gate low voltage line. 11. The method of claim 10,
Wherein the voltage at the second node is such that the gate-low voltage is a voltage dropped by the third resistor,
The threshold voltage of the second transistor is greater than the difference voltage between the voltage of the second node and the ground voltage when the negative static electricity is not applied to the gate control signal line,
And a threshold voltage of the second transistor is smaller than a difference voltage between the voltage of the second node and the ground voltage when the negative static electricity is applied to the gate control signal line. 11. The method of claim 10,
And the second transistor is a P-type MOSFET. The method according to claim 1,
Wherein the gate control signal is one of a start signal for controlling an output timing of a first gate signal of one frame period or a clock signal having a phase delayed sequentially.

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