CN113534551A

CN113534551A - Display substrate and display panel

Info

Publication number: CN113534551A
Application number: CN202110824655.0A
Authority: CN
Inventors: 陈伟; 王智勇; 杨刚; 邹浩伟; 田鹏程; 王强; 薛静; 王世鑫; 刘汉青; 宋勇; 李鑫; 崔军蕊
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Priority date: 2021-07-21
Filing date: 2021-07-21
Publication date: 2021-10-22
Anticipated expiration: 2041-07-21
Also published as: CN113534551B

Abstract

The present disclosure provides a display substrate, which belongs to the technical field of display and can solve the problem that the existing display panel is damaged due to static electricity. The display panel of the present disclosure includes a display substrate, which includes: the circuit board comprises a substrate base plate, a signal wire and a driving chip, wherein the signal wire is arranged on the substrate base plate; the driving chip is configured to provide a driving signal to the signal line. The display substrate further comprises a one-way conduction device, and the signal line is electrically connected with the driving chip through the one-way conduction device.

Description

Display substrate and display panel

Technical Field

The disclosure belongs to the technical field of display, and particularly relates to a display substrate and a display panel

Background

With the development of display technology, the kinds of display panels are increasing to adapt to various display devices. Such as the application of display panels in wearing products. The display panel in the wearable product is preferably of a narrow bezel design so that static electricity easily enters the display panel. Meanwhile, the refresh frequency of the display panel in the wearable product is low, a large storage capacitor is needed, the wiring density of the common electrode wire is increased, and static electricity entering the display panel easily damages components in the display panel through the common electrode wire.

The inventor finds that the phenomenon that static electricity affects the operation of the display panel exists when carrying out the static electricity test.

Disclosure of Invention

The present disclosure is directed to at least one of the problems of the prior art, and provides a display substrate and a display panel.

An embodiment of the present disclosure provides a display substrate, which includes: the circuit board comprises a substrate base plate, a signal wire and a driving chip, wherein the signal wire is arranged on the substrate base plate; the driving chip is configured to provide a driving signal for the signal line; wherein, still include: a one-way conduction device; the signal line is electrically connected with the driving chip through the one-way conduction device.

The unidirectional conducting device comprises a first transistor, a control electrode of the first transistor is electrically connected with a first electrode, the control electrode of the first transistor is electrically connected with the driving chip, and a second electrode of the first transistor is connected with the signal wire.

The display substrate comprises a display area and a peripheral area surrounding the display area; a plurality of pixel units are arranged in the display area, and a second transistor is arranged in each pixel unit; the display substrate further comprises a first metal layer, a first interlayer insulating layer and a second metal layer which are sequentially arranged on the substrate; wherein the content of the first and second substances,

the first metal layer comprises a control electrode of the second transistor and a control electrode of the first transistor;

the second metal layer comprises a first pole and a second pole of the second transistor, and is arranged in the same layer as the first pole and the second pole of the first transistor.

A second interlayer insulating layer and a first transparent conducting layer are sequentially arranged on one side, away from the substrate, of the second metal layer;

the first transparent conductive layer comprises a display electrode positioned in the pixel unit and a connecting electrode positioned in the peripheral area; the connection electrode electrically connects the first electrode of the first transistor and the control electrode through a first connection via hole penetrating the first interlayer insulating layer and the second interlayer insulating layer, and a second connection via hole penetrating the second interlayer insulating layer.

Wherein the display electrode includes a pixel electrode electrically connected to the second electrode of the second transistor through a third connection via penetrating the second interlayer insulating layer.

The signal line includes any one of a common electrode line, a gate line, a power voltage line, and a data line.

The signal lines are public electrode lines; the common electrode line comprises a first sub-signal line and a second sub-signal line which are electrically connected;

the first metal layer includes the first sub-signal line; the second metal layer includes a second sub-signal line.

The embodiment of the present disclosure further provides a display panel including the display substrate.

The display panel further comprises a color film substrate arranged opposite to the display substrate.

The display substrate is provided with a pixel electrode, and the color film substrate is provided with a common electrode.

Drawings

FIG. 1 is a schematic diagram of an exemplary conventional display substrate;

FIG. 2 is a cross-sectional view of an exemplary prior art display substrate;

FIG. 3 is an equivalent circuit diagram of an exemplary prior art display substrate;

FIG. 4 is a schematic view of a display substrate according to an embodiment of the disclosure;

FIG. 5 is a schematic diagram of a connection relationship of a unidirectional device in an embodiment of the present disclosure;

fig. 6 is a cross-sectional view of a unidirectional conducting device in an embodiment of the present disclosure.

Detailed Description

For a better understanding of the technical aspects of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

An exemplary display substrate as shown in fig. 1 includes a plurality of pixel units 10 arranged in an array along a first direction and a second direction; in the embodiments of the present disclosure, the first direction is taken as a row direction, and the second direction is taken as a column direction for description. The plurality of pixel units 10 in the embodiment of the present disclosure may include, but are not limited to, a red pixel unit, a green pixel unit, a blue pixel unit, and the like.

As shown in fig. 1, the display substrate has a display region Q1 and a peripheral region Q2 surrounding the display region Q1, the display substrate includes a display substrate and an opposite substrate which are oppositely disposed, and a liquid crystal layer 11 disposed between the display substrate and the opposite substrate, and the display substrate and the opposite substrate are fixed by a sealant 9 disposed in the peripheral region Q2. The display substrate may be an array substrate, and the opposite substrate may be a color filter substrate 13. Of course, the display substrate may also be a COA substrate (Color On Array), and the corresponding counter substrate may be a cover plate. In the disclosed embodiment, the display substrate is taken as an array substrate, and the counter substrate is taken as a color filter substrate 13.

FIG. 2 is a cross-sectional view of the display substrate of FIG. 1; referring to fig. 2, a structure of the display substrate will be specifically described; as shown in fig. 2, the display substrate includes a substrate 1, and a plurality of pixel units 10 disposed on the substrate 1, each pixel unit 10 structurally including: the liquid crystal display panel comprises a first metal layer 2, a first interlayer insulating layer 3, an active semiconductor layer 4, a second metal layer 5, a second interlayer insulating layer 6, a first transparent conducting layer, a liquid crystal layer 11 and a color film substrate 13 which are sequentially arranged on a substrate base plate 1. The first metal layer 2 is disposed on one side of the substrate 1, and the first metal layer 2 includes a control electrode of each thin film transistor TFT in the display area Q1 and a second plate of the storage capacitor Cst; the first interlayer insulating layer 3 is arranged on one side of the first metal layer 2, which is far away from the substrate base plate 1; the active semiconductor layer 4 is arranged on one side, away from the substrate base plate 1, of the first interlayer insulating layer 3, and the active semiconductor layer 4 comprises a channel region and a source-drain doped region of each Thin Film Transistor (TFT) of the display region Q1; a second metal layer 5 is provided on the active semiconductor layer 4 and the first interlayer insulating layer 3 on a side away from the substrate base plate 1, the second metal layer 5 including a first pole and a second pole of each thin film transistor TFT located in the display region Q1; the second interlayer insulating layer 6 and the first transparent conducting layer are respectively and sequentially arranged on one side, away from the substrate base plate 1, of the second metal layer 5, the first transparent conducting layer comprises pixel electrodes 7 of all pixel units 10 of the display area Q1, and the pixel electrodes 7 are connected with drain electrodes of the thin film transistors TFT through third connecting through holes penetrating through the second interlayer insulating layer 6. The color film substrate 13 is arranged opposite to the first transparent conductive layer, and is connected with the first transparent conductive layer through the frame sealing glue 9, and the frame sealing glue 9 and the liquid crystal layer 11 are arranged between the color film substrate 13 and the second interlayer insulating layer 6. A common electrode 12 is disposed on one side of the color filter substrate 13 opposite to the first transparent conductive layer.

FIG. 3 is a schematic diagram of an equivalent circuit of one pixel unit 10 in the display substrate; as shown in fig. 3, the equivalent circuit includes a thin film transistor TFT, a storage capacitor Cst, and a liquid crystal capacitor Clc; the first pole of the thin film transistor TFT is connected with a data line, the second pole of the thin film transistor TFT is connected with the first pole plate of the storage capacitor Cst and the first pole plate of the liquid crystal capacitor Clc, and the control pole of the thin film transistor TFT is connected with a grid line; the second plate of the storage capacitor Cst is connected to the common electrode line 14; the second plate of the liquid crystal capacitor Clc is connected to a common electrode line 14. When the gate line is written with a working level signal, the thin film transistor TFT is gated, and display of a corresponding gray scale is realized by a data line voltage signal written on the data line.

In addition, the transistors employed in the exemplary embodiments and the embodiments of the present disclosure may be thin film transistors TFT or field effect transistors or other switching devices having the same characteristics, and the thin film transistors TFT may include oxide semiconductor thin film transistors TFT, amorphous silicon thin film transistors TFT, polysilicon thin film transistors TFT, or the like. Each transistor comprises a first pole, a second pole and a control pole; the control electrode is used as a grid electrode of the transistor, one of the first electrode and the second electrode is used as a source electrode of the transistor, and the other electrode is used as a drain electrode of the transistor; the source and drain of the transistor may be symmetrical in structure, so that there may be no difference in physical structure. In the embodiments of the present disclosure, in order to distinguish transistors, in addition to a gate serving as a control electrode, a first electrode is directly described as a source, and a second electrode is a drain, so that the source and the drain of all or part of the transistors in the embodiments of the present disclosure may be interchanged as necessary.

In addition, the transistors can be divided into N-type and P-type according to the characteristics of the transistors, and the following exemplary embodiments and embodiments of the present disclosure are illustrated with N-type transistors, when an N-type transistor is used, the first electrode is the source of the N-type transistor, the second electrode is the drain of the N-type transistor, and when a high level is input to the gate, the transistor is turned on, and the P-type is opposite. It is contemplated that implementation with P-type transistors will be readily apparent to those skilled in the art without inventive effort and, thus, are within the scope of the disclosed embodiments.

In actual operation, the inventor finds that, since the required storage capacitor Cst is larger and the density of the common electrode line 14 connected to the storage capacitor Cst is higher in the wearable device, which is preferable for a display substrate with a low refresh rate, an external electrostatic signal is liable to enter the driving chip 20 reversely through the common electrode line 14, and damage is caused to the driving chip 20.

In view of the problems of the prior art, the inventor improves the prior art.

In a first aspect, embodiments of the present disclosure provide a display substrate, which can be applied to a wearable product. Fig. 1-6 are schematic diagrams of embodiments of the present disclosure.

The embodiment of the present disclosure provides a display substrate, which includes a substrate 1, a signal line disposed on the substrate 1, a driving chip 20, and a unidirectional conducting device 30, wherein the signal line is electrically connected to the driving chip 20 through the unidirectional conducting device 30. The driving chip 20 outputs a driving signal to the signal line through the unidirectional conducting device 30.

In fig. 4, a plurality of unidirectional conductive devices 30 and signal lines are illustrated as an example. Since the signal line and the driving chip 20 are connected by the unidirectional conducting device 30 in the embodiment of the present disclosure, and the unidirectional conducting device 30 has unidirectional conductivity, that is, only the electric signal is allowed to be transmitted from the end of the driving chip 20 to the signal line, the external electrostatic signal is prevented from being reversely input into the driving chip 20 via the signal line, and the driving chip 20 is prevented from being damaged.

Specifically, as shown in fig. 4, the one-way conduction device 30 in the display substrate includes: a first transistor 31. The gate and the source of the first transistor 31 are connected, that is, the gate and the source of the first transistor 31 are in common, and both are connected to the driving chip 20; the drain of the first transistor 31 is electrically connected to the signal line.

In this case, since the gate and the source of the first transistor 31 are connected and the driving chip 20 is connected, the driving signal output from the driving chip 20 is written to the gate and the source of the first transistor 31. When the driving signal output by the driving chip 20 is a positive voltage, the first transistor 31 is turned on, and the drain of the first transistor 31 outputs the driving signal and writes it into the signal line; at this time, the channel resistance of the first transistor 31 is very large, so that the electrostatic signal transmitted from the signal line can be blocked outside the first transistor 31, and the electrostatic signal is prevented from entering the driving chip 20 through the signal line to damage the driving chip 20. When the driving signal output by the driving chip 20 is a negative voltage, the first transistor 31 is turned off; at this time, the electrostatic signal transmitted from the signal line is consumed by the channel of the first transistor 31 when passing through the first transistor 31, so that the electrostatic signal is prevented from being transmitted into the driving chip 20 through the signal line to damage the driving chip 20.

In some examples, the driving voltage output by the driving chip 20 may be selected according to the actual requirement of the voltage on the signal line connected to the drain of the first transistor 31. For example: the signal line is a common electrode line 14, and the voltage on the common electrode line 14 is preferably less than or equal to-1V. By testing the voltage relationship between the gate and the drain when the gate and the source of the first transistor 31 are in common, it is found that the drain voltage of the first transistor 31 can reach-1V when the driving voltage is-15V. That is, the first transistor 31 can satisfy the actual operation requirement, and at the same time, the driving voltage is a negative voltage, the electrostatic signal transmitted from the common electrode line 14 is consumed by the channel of the first transistor 31 via the first transistor 31, and the requirement of the first transistor 31 for protecting the driving chip 20 is satisfied.

In some examples, as shown in fig. 4 to 6, the display substrate includes a display region Q1 and a peripheral region Q2 surrounding the display region Q1, a plurality of pixel cells 10 are disposed in the display region Q1, and each pixel cell 10 is provided with a second transistor; the display substrate further comprises a first metal layer 2, a first interlayer insulating layer 3, an active semiconductor layer 4 and a second metal layer 5 which are sequentially arranged on the substrate 1, wherein the first metal layer 2 comprises a second plate of the storage capacitor Cst, a gate of the second transistor and a gate of the first transistor 31, namely the second plate of the storage capacitor Cst, the gate of the first transistor 31 and the gate of the second transistor are arranged in the same layer; the second metal layer 5 includes a source and a drain of the second transistor and a source and a drain of the first transistor 31, that is, the source and the drain of the second transistor are disposed at the same level as the source and the drain of the first transistor 31; the first interlayer insulating layer 3 serves as a gate insulating layer of the first transistor 31 and the second transistor. I.e. the first metal layer 2, the first interlayer insulating layer 3, the active semiconductor layer 4 and the second metal layer 5 of the display substrate, are used to compose the basic structure of the first transistor 31 and the second transistor. The second plate of the storage capacitor Cst is used to interact with the pixel electrode 7, forming the structure of the storage capacitor Cst. The storage capacitor Cst is used to maintain the voltage of the pixel electrode 7 when no electric signal is input to the pixel circuit.

In such an embodiment, compared with the prior art, it can be seen that the newly formed first transistor 31 does not add an additional patterning process, that is, the first transistor 31 is added as the unidirectional conducting device 30, and at the same time, the additional patterning process is not added, that is, the additional cost is not increased.

The material of the first metal layer 2 and the second metal layer 5 is not limited to at least one of copper (Cu), aluminum (Al), molybdenum (Mo), and silver (Ag), and the thickness of the first metal layer 2 may be about 50nm to 200nm, further about 50nm to 100nm, and the thickness of the second metal layer 5 may be about 100nm to 500nm, further about 250nm to 350 nm. In the present embodiment, the material of the first metal layer 2 and the second metal layer 5 is exemplified by molybdenum. The material of the first interlayer insulating layer 3 is an inorganic insulating material. For example: the first interlayer insulating layer 3 is an inorganic insulating layer formed of silicon nitride (SiNx) or silicon oxide (SiO)₂) Inorganic insulating layer formed, or SiNx inorganic insulating layer and SiO₂Several stacked composite layers of inorganic insulating layers. The material of the first interlayer insulating layer 3 in this embodiment is silicon nitride for example.

In some examples, the voltage on the signal line connected to the drain of the first transistor 31 may be indirectly controlled by controlling the ratio of the channel width W to the length L of the first transistor 31 (channel width-to-length ratio, W/L). For example: the signal line is a common electrode line 14, and the voltage on the common electrode line 14 is preferably less than or equal to-1V. By testing the first transistors 31 with different channel width-length ratios, it is found that when the width-length ratio of the first transistor 31 is 40/6.5, the drain output voltage of the first transistor 31 meets the debugging requirement of the voltage on the common electrode line 14. That is, the first transistor 31 can satisfy the actual operation requirement, and at the same time, the driving voltage is a negative voltage, the electrostatic signal transmitted from the common electrode line 14 is consumed by the channel of the first transistor 31 via the first transistor 31, and the requirement of the first transistor 31 for protecting the driving chip 20 is satisfied.

In some examples, with continued reference to fig. 6, a second interlayer insulating layer 6 and a first transparent conductive layer are further sequentially disposed on a side of the second metal layer 5 facing away from the substrate base plate 1. The first transparent conductive layer includes the display electrode in the pixel unit 10, and the connection electrode 8 located in the peripheral region Q2. The connection electrode 8 connects the source and drain of the first transistor 31 through a first connection via hole penetrating the first interlayer insulating layer 3 and the second interlayer insulating layer 6, and a second via hole penetrating the second interlayer insulating layer 6. The second interlayer insulating layer 6 serves to protect the second metal layer 5 from oxidation.

In such an embodiment, compared with the prior art, it can be seen that no additional patterning process is added to form the gate-source common electrode structure of the first transistor 31, even if the first transistor 31 has a unidirectional turn-on function and no additional patterning process is added, that is, no additional cost is added.

The material of the first transparent conductive layer includes, but is not limited to, Indium Tin Oxide (ITO), and the connection electrode 8 and the display electrode are formed by using a one-step patterning process. I.e. the gate-source common structure of the first transistor 31 is formed without adding extra cost. In some examples, the second interlayer insulating layer 6 may be made of the same material as that of the first interlayer insulating layer 3, and thus, the description thereof is omitted.

In some examples, as shown in fig. 6, the display electrode includes a pixel electrode 7, and the pixel electrode 7 is connected to the drain electrode of the second transistor through a third connection via hole penetrating the second interlayer insulating layer 6. The pixel electrode 7 is used for the second transistor to receive a pixel signal output by the second transistor under the control of the gate line and the data line. In some examples, when the display substrate is a TN mode display substrate, that is, an electric field formed by the pixel electrode 7 and the common electrode 12 in the display substrate after power-on is a vertical electric field. In addition, in the embodiments of the present disclosure, the display substrate is not limited to the display substrate in the vertical electric field mode, and may be a display substrate in the horizontal electric field mode. For example: ADS mode, FFS mode, IPS mode, etc.

In some embodiments, the pixel electrode 7 may be a reflective electrode. Here, the reflective electrode means that a surface thereof facing the display side can be used for reflection. In one example, the reflective electrode may be made of a conductive material having a reflective function. In another example, the reflective electrode is constituted by a conductive layer and a reflective layer provided in a stacked manner, the reflective layer being located on a side of the conductive layer facing the display side. Of course, the pixel electrode 7 is not limited to the reflective electrode, and a transmissive electrode may be used, that is, light may be transmitted through the pixel electrode 7.

If the pixel electrode 7 is a reflective electrode, the display device using the display substrate is a reflective display device, and the light source assembly is a front light source disposed on the display side of the display substrate; if the pixel electrode 7 is a transmissive electrode, the display device using the display substrate is a transmissive display device, and the light source assembly is a rear light source disposed on a side of the display substrate away from the display side. In the disclosed embodiment, the pixel electrode 7 in the display substrate is taken as an example of a reflective electrode.

Note that, in some examples, the signal line includes at least one of the common electrode line 14, the gate line, the power supply voltage line, and the data line. That is, the unidirectional conducting device 30 may be connected to a common signal line, a gate line, a power voltage line, and a data line, so that the signal line connected to the unidirectional conducting device 30 has unidirectional conductivity, and an electrostatic signal reversely input along the signal line is blocked outside the unidirectional conducting device 30, thereby ensuring the performance of the display substrate.

In some examples, the signal line is a common electrode line 14, the common electrode line 14 includes a first sub-signal line and a second sub-signal line, and the first sub-signal line and the second sub-signal line are partially disposed in the frame sealing adhesive 9 in the peripheral region Q2. The first sub-signal line is used for outputting the driving voltage output by the driving chip 20 to the second plate of the storage capacitor Cst via the unidirectional conducting device 30; the second sub-signal line is used to write a drive voltage to the common electrode 12 of the display area Q1. The first sub-signal line is formed in the first metal layer 2 composition process; the second sub-signal line is formed in the second metal layer 5 patterning process. The first sub-signal line and the second sub-signal line are electrically connected.

In such an embodiment, it can be seen that the formation of the first and second sub-signal lines does not add an additional patterning process, i.e., does not add additional cost, compared to the related art.

In a second aspect, an embodiment of the present disclosure provides a display panel, where the display panel includes any one of the display substrates in the above embodiments, and of course, the display panel further includes a color filter substrate 13 disposed opposite to the array substrate, a common electrode 12 is disposed on the color filter substrate 13, and a liquid crystal layer 11 disposed between the array substrate and the color filter substrate 13. Since the display panel in the embodiment of the disclosure includes the display substrate, the display effect is ensured.

In some embodiments, the display panel of the embodiment of the present disclosure may be in a normally white mode or a normally black mode. For the normally white mode display panel, the display panel is in a dark state when powered on, and is in a bright state when not powered on. For the normally black mode, the normally white mode is opposite, and the display panel is in a bright state when the power is on and in a dark state when the power is not on.

The display device may be a liquid crystal display device or an electroluminescent display device, such as any product or component with a display function, such as a liquid crystal panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these are to be considered as the scope of the disclosure.

Claims

1. A display substrate, comprising: the circuit board comprises a substrate base plate, a signal wire and a driving chip, wherein the signal wire is arranged on the substrate base plate; the driving chip is configured to provide a driving signal for the signal line; it is characterized by also comprising: a one-way conduction device; the signal line is electrically connected with the driving chip through the one-way conduction device.

2. The display substrate according to claim 1, wherein the one-way conduction device comprises a first transistor, a control electrode of the first transistor is electrically connected to a first electrode, and the control electrode and the first electrode are electrically connected to the driving chip, and a second electrode of the first transistor is connected to the signal line.

3. The display substrate according to claim 1, wherein the display substrate comprises a display area and a peripheral area surrounding the display area; a plurality of pixel units are arranged in the display area, and a second transistor is arranged in each pixel unit; the display substrate further comprises a first metal layer, a first interlayer insulating layer and a second metal layer which are sequentially arranged on the substrate; wherein the content of the first and second substances,

4. The display substrate according to claim 3, wherein a second interlayer insulating layer and a first transparent conductive layer are further sequentially disposed on a side of the second metal layer facing away from the substrate;

5. The display substrate according to claim 4, wherein the display electrode comprises a pixel electrode electrically connected to the second electrode of the second transistor through a third connection via penetrating the second interlayer insulating layer.

6. The display substrate according to claim 3, wherein the signal line comprises any one of a common electrode line, a gate line, a power supply voltage line, and a data line.

7. The display substrate according to claim 6, wherein the signal line is a common electrode line; the common electrode line comprises a first sub-signal line and a second sub-signal line which are electrically connected;

8. A display panel comprising the display substrate according to any one of claims 1 to 7.

9. The display panel according to claim 8, further comprising a color filter substrate disposed opposite to the display substrate.

10. The display substrate according to claim 9, wherein a pixel electrode is disposed on the display substrate, and a common electrode is disposed on the color filter substrate.