CN107589612A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
- Publication number
- CN107589612A CN107589612A CN201711003577.8A CN201711003577A CN107589612A CN 107589612 A CN107589612 A CN 107589612A CN 201711003577 A CN201711003577 A CN 201711003577A CN 107589612 A CN107589612 A CN 107589612A
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- Prior art keywords
- test lead
- array base
- signal line
- protection circuit
- display area
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- 239000000758 substrate Substances 0.000 title claims abstract description 14
- 238000012360 testing method Methods 0.000 claims abstract description 138
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 238000013499 data model Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 239000000523 sample Substances 0.000 description 3
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- 238000005421 electrostatic potential Methods 0.000 description 2
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- 230000036961 partial effect Effects 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
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- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
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- 230000032683 aging Effects 0.000 description 1
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- 239000004744 fabric Substances 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000003472 neutralizing effect Effects 0.000 description 1
- 230000032696 parturition Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/04—Display protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Nonlinear Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal (AREA)
Abstract
The embodiment of the invention discloses an array substrate and a display panel. Wherein, the array substrate includes: the plurality of test leads are respectively connected with the plurality of signal lines in a one-to-one correspondence manner through the electrostatic protection circuit; the driving chip binding pads are respectively connected with the plurality of testing leads in a one-to-one correspondence mode through driving signal leads and used for inputting driving signals sent by the driving chips to the plurality of signal lines through the plurality of testing leads; and the first connecting end of the electrostatic protection circuit is electrically connected with the plurality of test leads, and the second connecting end of the electrostatic protection circuit is electrically connected with the plurality of signal wires and used for deriving electrostatic current generated by the whole array substrate when the test signals are externally filled and the driving chip is bound. The technical scheme provided by the embodiment of the invention can solve the problem that the electrostatic protection circuits of different types in the existing display panel occupy a large area of a fan-out area and influence the utilization of space.
Description
Technical field
The present embodiments relate to display technology field, more particularly to a kind of array base palte and display panel.
Background technology
Electrostatic is the positive charge or negative electrical charge that the surface of object is caused charge unbalance and formed for some reason.Work as electricity
Lotus shifts, and during the mutual phase discharge of different potentials, static discharge (Electrostatic Discharge, ESD) will occur.
When electrostatic potential is 2000V, human body then it is imperceptible it, but we produce used in electrostatic sensitive member device
Part can but be damaged by it, because CMOS IC-components can only bear 250~2000V voltage, will be made more than this voltage
Into damage.Static discharge can make IC chip dielectric breakdown, cored wire fusing, leakage current increase accelerated ageing, electrical property ginseng
Number change etc..
So ESD protection is quite important, and the correlative factor of ESD protection has：Consideration, the minimizing electrostatic production of circuit design
Electrostatic caused by giving birth to, dredge or neutralizing, and Electro-static Driven Comb.
Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display,
TFT-LCD ESD protection circuit is added in the circuit of display panel), the ESD protection circuit will play protection effect, to avoid
Component in the circuit of display panel is damaged by ESD.When ESD voltage is appeared in picture element array, the picture element number is made in
The other ESD protection circuit of group has to early to turn on to discharge esd discharge electric current.Therefore, made in ESD protection circuit
Component has to have relatively low breakdown voltage or turns on speed faster.
In order to save cost, after completing a program, we can then be detected one by one, to screen out the product of failure.When
After array base palte processing procedure terminates, we carry out one-time detection, color membrane substrates of avoiding waste with regard to array substrate.When display panel system
After journey is completed, we equally can also detect to display panel, the cost for module of avoiding waste.Complete distinct program
Afterwards, all can detection panel, give signal by different way, just have the signal pad of different model.Therefore the ESD of different model
Protection circuit just in response to and it is raw, it is necessary to different ESD protection circuits is done in certain space, with prevent different detections possibility
Caused electrostatic breakdown.
The content of the invention
The present invention provides a kind of array base palte and display panel, to solve the electrostatic of different model in existing display panel
Protection circuit takes the area of very big fan-out area, the problem of influenceing the utilization in space.
The embodiments of the invention provide a kind of array base palte, including viewing area and the non-display area around the viewing area,
Including：
It is arranged at more signal lines of the viewing area and the non-display area；The electrostatic for being arranged at the non-display area is prevented
Protection circuit；
The a plurality of test lead of the non-display area is arranged at, passes through the electrostatic discharge protection circuit and a plurality of letter respectively
Number line connects one to one；
Be arranged at the non-display area multiple driving chips binding pad, respectively by drive signal lead with it is described more
Bar test lead connects one to one, for by the drive signal that driving chip is sent by a plurality of test lead input to
More signal lines；
Wherein, the first connection end of the electrostatic discharge protection circuit electrically connects with a plurality of test lead, second connection end
Electrically connected with more signal lines, whole array base palte institute when when filling test signal outside for exporting and binding driving chip
Caused electrostatic induced current.
The embodiment of the present invention additionally provides a kind of array base palte, including viewing area and around the non-display of the viewing area
Area, including：
It is arranged at more signal lines of the viewing area and the non-display area；The electrostatic for being arranged at the non-display area is prevented
Protection circuit；
The a plurality of test lead of the non-display area is arranged at, passes through the electrostatic discharge protection circuit and a plurality of letter respectively
Number line connects one to one；
Be arranged at the non-display area multiple driving chips binding pad, respectively by drive signal lead with it is described more
Bar test lead connects one to one, for by the drive signal that driving chip is sent by a plurality of test lead input to
More signal lines；
Wherein, the first connection end of the electrostatic discharge protection circuit electrically connects with a plurality of test lead, second connection end
Electrically connected with more signal lines, whole array base palte institute when when filling test signal outside for exporting and binding driving chip
Caused electrostatic induced current；
The non-display area of the both sides of the viewing area in the first direction is respectively arranged with gate driver；
The signal wire includes the data signal line in the viewing area and driven positioned at the door of the non-display area
The drive signal line of device, the signal wire be arranged in parallel in a second direction, and the second direction is vertical with the first direction；
Testing weld pad, correspond and electrically connect with a plurality of test lead.
The embodiment of the present invention additionally provides a kind of display panel, including counter substrate, and any embodiment of the present invention institute
The array base palte stated.
Technical scheme provided in an embodiment of the present invention, a plurality of test lead of array base palte pass through electrostatic discharge protection circuit respectively
Connected one to one with more signal lines, outer filling test signal input at most signal line, multiple driving chips are bound into pad
Connected one to one respectively by drive signal lead and a plurality of test lead, by the drive signal that driving chip is sent through excessive
Bar drive signal lead, a plurality of test lead and electrostatic discharge protection circuit send at most signal line, and the of electrostatic discharge protection circuit
One connection end is electrically connected with a plurality of test lead, and second connection end electrically connects with more signal lines, and test is filled outside for exporting
Test lead, driving chip are bound caused by pad and signal wire and its institute's connected device part during signal and when binding driving chip
Electrostatic.Display panel shares an electrostatic discharge protection circuit in panel lighting test and module lighting test in this programme, and
During subsequent drive chip drives array base palte, the electrostatic discharge protection circuit can be continuing with, without in display panel
Fan-out area be separately provided panel lighting test electrostatic discharge protection circuit and module lighting test electrostatic discharge protection circuit, save
The space of fan-out area, and simplify manufacture craft.
Brief description of the drawings
Fig. 1 a are a kind of structural representations for array base palte that prior art provides；
Fig. 1 b are the structural representations for another array base palte that prior art provides；
Fig. 1 c are the structural representations for another array base palte that prior art provides；
Fig. 2 is a kind of structural representation of array base palte provided in an embodiment of the present invention；
Fig. 3 is the structural representation of another array base palte provided in an embodiment of the present invention；
Fig. 4 is the structural representation of ESD protection circuit provided in an embodiment of the present invention；
Fig. 5 is the equivalent schematic of ESD protection circuit shown in Fig. 4；
Fig. 6 is a kind of sectional structure chart of display panel provided in an embodiment of the present invention.
Embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that in order to just
Part related to the present invention rather than entire infrastructure are illustrate only in description, accompanying drawing.
, it is necessary to introduce the electrostatic protection structure in the prior art on array base palte before this embodiment scheme is introduced, ginseng
Fig. 1 a are examined, Fig. 1 a are a kind of structural representations for array base palte that prior art provides, in the manufacturing process of display panel, when
, it is necessary to carry out panel lighting test when array base palte and color membrane substrates are bonded to form a display panel；When module group procedure is complete
Into rear, it is necessary to carry out module lighting test, the test of different phase is all to pour into outer signals to pad outside, then is passed in panel
Portion, the outer action for filling signal can usually attract electrostatic, so people go to design different electrostatic according to the model of different pads
Protection circuit.Under normal circumstances, pad is bigger, it is necessary to electrostatic discharge protection circuit using bigger model.With reference to figure 1a, panel is carried out
The model of the testing weld pad 120 of lighting test is greater than the driving chip binding pad 14 for carrying out module lighting test, then sets
First electrostatic discharge protection circuit 18, the big voltage brought into for exporting testing weld pad 120, as shown in Figure 1a, the first electrostatic protection
Circuit 18 electrically connects with signal wire 13 and testing weld pad 120 respectively, for exporting when panel lighting is tested caused by array base palte
Electrostatic.
Accordingly, with reference to figure 1b, Fig. 1 b are the structural representations for another array base palte that prior art provides, in module
It is by driving chip (not shown) input test signal, as shown in Figure 1 b, driving chip binding pad 14 during lighting test
It is smaller, it is only necessary to less second electrostatic discharge protection circuit 19 of model, the big voltage brought into for exporting binding driving chip,
Second electrostatic discharge protection circuit 19 electrically connects with signal wire 13 and driving chip binding pad 14 respectively, is surveyed for exporting module lighting
Electrostatic caused by array base palte during examination.
Then generally, as illustrated in figure 1 c, Fig. 1 c are the another of prior art offer to the circuit connecting relation on array base palte
The structural representation of array base palte is planted, the first electrostatic discharge protection circuit 18 and the second electrostatic protection electricity are provided with simultaneously on display panel
Road 19.In process of the present invention is realized, inventor has found that the connection of array base palte in the prior art is complicated, and different surveys
Examination needs the electrostatic discharge protection circuit of different model, and the electrostatic discharge protection circuit of different model occupies the sky of very big fan-out area
Between.
The embodiment of the present invention provides a kind of array base palte, and with reference to figure 2, Fig. 2 is a kind of array provided in an embodiment of the present invention
The structural representation of substrate.(array base palte 1 removes non-display area of the array base palte 1 including viewing area 17 and around viewing area 17
Part beyond viewing area 17), including：It is arranged at more signal lines 13 of viewing area 17 and non-display area；It is arranged at non-
The electrostatic discharge protection circuit 12 of viewing area；
A plurality of test lead 11, connected one to one respectively by electrostatic discharge protection circuit 12 and more signal lines 13；
Multiple driving chips bind pad 14, are corresponded respectively by drive signal lead 15 and a plurality of test lead 11
Connection, for the drive signal that driving chip is sent to be inputted at most signal line 13 by a plurality of test lead 11；
Electrostatic discharge protection circuit 12, the first connection end of electrostatic discharge protection circuit 12 electrically connect with a plurality of test lead 11, and second
Connection end electrically connects with more signal lines 13, whole array base when when filling test signal outside for exporting and binding driving chip
Electrostatic induced current caused by plate 1.
In the manufacturing process of display panel, a display panel is formed when array base palte 1 and color membrane substrates are bonded, is needed
Panel lighting test is carried out, whether detection display panel can be lit, and module group procedure is no longer carried out if it can not be lit, is prevented
The only waste of module, a plurality of test lead 11 is set to pass through more signal lines 13 on electrostatic discharge protection circuit 12 and array base palte 1
Connect one to one, for by test lead 11 one-to-one with signal wire 13 more signal lines will to be poured into outside test signal
13, to light display panel, and electrostatic caused by test lead 11 is exported by electrostatic discharge protection circuit 12.
In module lighting test, display panel has bound driving chip (not shown), and driving chip passes through Fig. 2 institutes
The driving chip binding pad 14 shown, a plurality of drive for setting and being connected is corresponded by binding pad 14 with a plurality of driving chip
Dynamic signal lead 15 connects one to one with a plurality of test lead 11, and driving chip binding pad 14 passes through a plurality of test lead 11
The big voltage of input is delivered to electrostatic discharge protection circuit 12, and can be by signal wire 13 and signal wire institute when binding driving chip
Electrostatic caused by interface unit is directed at ground wire.In the present embodiment, driving chip binding pad 14, drive signal lead 15, survey
Examination lead 11 and the quantity of signal wire 13 are identical and correspond electrical connection.
First connection end of electrostatic discharge protection circuit 12 electrically connects with a plurality of test lead 11, second connection end and more bars
Line 13 electrically connects, electrostatic electricity caused by whole array base palte when when filling test signal outside for exporting and binding driving chip
Stream.The electrostatic that then either a plurality of test lead 11 introduces, or the electrostatic that driving chip binding pad 14 introduces can lead to
Electrostatic discharge protection circuit 12 is crossed to export.Again because the model for the electrostatic discharge protection circuit that panel lighting test needs is surveyed than module lighting
The electrostatic discharge protection circuit needed during examination is big, and the conduct of electrostatic discharge protection circuit 12 of the model suitable for panel lighting test can be set
Panel lighting test and the common electrostatic discharge protection circuit of module lighting test in the present embodiment, model is bigger, and core is driven in binding
More preferably protective effect can be played during piece to driving chip.And work subsequently is driven to display panel in driving chip
When, electrostatic protection still can be carried out to whole array base palte by the electrostatic discharge protection circuit 12.
With reference to figure 2, test lead 11 and driving chip binding pad 14 share an electrostatic discharge protection circuit in the present embodiment,
The space of fan-out area is greatlyd save, and only in fan-out area driving chip need to be set to bind pad 14 and test lead 11
Between drive signal lead 15, compared to Fig. 1 c, institute's cloth wire reduces a lot, and technique is simple.
Technical scheme provided in an embodiment of the present invention, a plurality of test lead of array base palte pass through electrostatic discharge protection circuit respectively
Connected one to one with more signal lines, outer filling test signal input at most signal line, multiple driving chips are bound into pad
Connected one to one respectively by drive signal lead and a plurality of test lead, by the drive signal that driving chip is sent through excessive
Bar drive signal lead, a plurality of test lead and electrostatic discharge protection circuit send at most signal line, and the of electrostatic discharge protection circuit
One connection end is electrically connected with a plurality of test lead, and second connection end electrically connects with more signal lines, and test is filled outside for exporting
Test lead, driving chip are bound caused by pad and signal wire and its institute's connected device part during signal and when binding driving chip
Electrostatic.Display panel shares an electrostatic discharge protection circuit in panel lighting test and module lighting test in this programme, and
During subsequent drive chip drives array base palte, the electrostatic discharge protection circuit can be continuing with, without in display panel
Fan-out area be separately provided panel lighting test electrostatic discharge protection circuit and module lighting test electrostatic discharge protection circuit, save
The space of fan-out area, and simplify manufacture craft.
Optionally, with reference to figure 3, Fig. 3 is the structural representation of another array base palte provided in an embodiment of the present invention, array
Substrate 1 also includes testing weld pad 120, is arranged at non-display area, corresponds and electrically connects with a plurality of test lead 11.Making
During display panel, in order to carry out panel lighting test, testing weld pad 120 is additionally provided with array base palte 1, by being filled outside probe
Enter test signal to testing weld pad 120 to light panel, the model of testing weld pad 120 is significantly larger than driving chip binding pad
14, testing weld pad 120 is adapted to probe setting, so driving chip binding pad 14 can not be used to make when panel lighting is tested
For testing weld pad, mismatched because driving chip binds pad 14 with testing probe.So electrostatic protection electricity in the present embodiment
Road 12 is adapted with testing weld pad 120, while can more preferably eliminate big voltage caused by driving chip binding pad.
In addition, after panel lighting test is completed, subsequent manufacturing processes will not use testing weld pad 120 again, can be complete
Testing weld pad 120 is cut away after being tested into panel lighting, to reduce the area of fan-out area, improves screen display rate.
Closer to easier generation electrostatic at pad, so electrostatic discharge protection circuit is set close to pad, as shown in figure 3, quiet
Electric protection circuit 12 is directly electrically connected by test lead 11 with testing weld pad 120, is welded by drive signal lead 15 and binding
Disk 14 electrically connects, for exporting electrostatic caused by testing weld pad 120 and binding pad 14.Specifically, with reference to figure 4, Fig. 4 is this hair
The structural representation for the ESD protection circuit that bright embodiment provides.Fig. 4 is a kind of example of electrostatic discharge protection circuit, this implementation
Electrostatic discharge protection circuit mentioned by example includes but is not limited to the example shown in Fig. 4.
Electrostatic discharge protection circuit 12 includes two N-type TFT T1 being connected in series and T2, T1 source electrode VGH ends connection
Power level end, T2 drain electrode VGL connection ground terminals, connection end IN electrically connect with the test lead 11 shown in Fig. 2 or Fig. 3 respectively,
Connection end OUT electrically connects with the signal wire 13 shown in Fig. 2 or Fig. 3 respectively.
The grid of each thin film transistor (TFT) and drain electrode electrically connect, and form the thin film transistor (TFT) at two ends, to a certain extent,
Thin film transistor (TFT) can be equivalent to diode, as shown in figure 5, Fig. 5 is the equivalent schematic of ESD protection circuit shown in Fig. 4.
When testing weld pad 120 or binding pad 14 input connection end IN voltage between ground terminal voltage and supply voltage, current direction
Connection end OUT, then flow to signal wire 13；When input connection end IN voltage is more than supply voltage, current direction VGH ends；It is defeated
When entering connection end IN voltage less than ground terminal voltage, current direction VGL ends.It is worth noting that, inputted by connection end IN to letter
Number test signal of line 13 and the magnitude of voltage of drive signal are between ground terminal voltage and supply voltage, so passing through connection end
OUT flows to signal wire 13, and electrostatic potential is often much larger than supply voltage or much smaller than ground terminal voltage, then electrostatic induced current can pass through
VGH ends and VGL ends flow to power supply or greatly respectively, prevent so as to which the array substrate of electrostatic discharge protection circuit 12 has carried out static discharge
Shield.
Optionally, with reference to figure 2, array base palte 1 includes viewing area 17 and non-display area, viewing area 17 in the first direction two
The non-display area of side is respectively arranged with gate driver 16；Signal wire 13 includes the He of data signal line 131 in viewing area 17
Positioned at the drive signal line 132 of the gate driver 16 of non-display area, signal wire 13 be arranged in parallel in a second direction, second direction with
First direction is vertical.
Array base palte 1 includes being provided with the viewing area 17 of data signal line 131 and raster data model line, in addition to viewing area 17
The non-display area of surrounding, the both sides of viewing area 17 in the first direction are respectively arranged with gate driver 16, and gate driver 16 is used for root
Produced according to trigger signal and be used to control viewing area 17 with raster data model number of lines identical gate drive signal, gate drive signal
The switch of interior thin film transistor (TFT).Wherein, gate driver 16 is two, is separately positioned on the both sides of viewing area 17, can carry respectively
For odd-numbered line and the gate drive signal of the raster data model line of even number line, the simplification of circuit is realized, can also be provided respectively from both sides
The gate drive signal of all raster data model lines, prevent decay of the gate drive signal in transmitting procedure.Certainly, door drives
Device 16 also can only set one in the side of viewing area 17, and the present embodiment is to this without limiting.
Signal wire 13 includes data wire size line 131 in the viewing area 17 and the gate driver 16 positioned at non-display area
Drive signal line 132, data wire size line 131 and drive signal line 132 all be arranged in parallel in a second direction, perpendicular to first party
To.
Optionally, the drive signal line 132 of gate driver 16 includes：Power line, clock cable and line trigger signal,
Respectively gate driver 16 provides power supply signal, clock signal and trigger signal.
Optionally, viewing area is arranged on along second party with reference to figure 2, a plurality of test lead 11 and driving chip binding pad 14
To the non-display area of side.Exemplary, if display panel is mobile phone screen display panel, a plurality of test lead 11 and driving
Chip bonding pad 14 is arranged at the top (side for being provided with receiver) of mobile phone display screen or lower section (is provided with Cao Zuoanjian
Side) non-display area, and drive signal line 132 is arranged on the non-display area of the left and right sides of mobile phone display screen.Above-mentioned position
The area of the non-display area for the left and right sides that mobile phone display screen can be reduced is set so that mobile phone is overall more attractive in appearance.
Optionally, with reference to figure 2 or Fig. 3, a plurality of test lead 11 divides for Part I test lead and Part II test
Lead；Part I test lead is corresponded and electrically connected with Part I data signal line and drive signal line respectively；The
Two partial test leads are corresponded and electrically connected with Part II data signal line and drive signal line respectively.
When display resolution is very big, many data signal lines 131 can be set, as shown in Fig. 2 can be by data-signal
Line 131 is divided into two parts and connected up, and accordingly, a plurality of test lead 11 can also be divided into two parts, to reduce test lead 11
Space density.With reference to figure 2, a plurality of test lead 11 divides for Part I test lead and Part II test lead, because
Gate driver 16 is respectively provided with the both sides of viewing area 17 in the first direction, then by the driving of the gate driver 16 of wherein side
The data signal line 131 of part is used as Part I data signal line and drive signal line in signal wire 132 and viewing area 17, will
The drive signal line 132 of the gate driver 16 of opposite side and the data signal line 131 of the remainder of viewing area 17 are used as second
Divided data signal wire and drive signal line.
Preferably, side where Part I test lead and Part I data signal line and drive signal line place side phase
Together, side where Part II test lead and Part II data signal line are identical with side where drive signal line, are symmetrical arranged
Length of arrangement wire is reduced, and simplifies manufacture craft.
Optionally, it is located at Part I test lead and Part II with reference to figure 2 or Fig. 3, driving chip binding pad 14
Between test lead, it is easy to reduce length of arrangement wire, and convenient binding driving chip.
Optionally, Part I test lead is identical with the quantity of Part II test lead；Part I data-signal
Line and drive signal line are identical with the quantity of Part II data signal line and drive signal line.Part I test lead and
Two partial test leads can be symmetrical arranged, and be easy to the wiring of wire, and simplification of flowsheet.
The embodiment of the present invention additionally provides a kind of array base palte, and with reference to figure 2 or 3, the array base palte 1 includes the He of viewing area 17
Non-display area (part of the array base palte 1 in addition to viewing area 17) around viewing area 17, including：It is arranged at viewing area 17
With more signal lines 13 of non-display area；It is arranged at the electrostatic discharge protection circuit 12 of non-display area；
A plurality of test lead 11, connected one to one respectively by electrostatic discharge protection circuit 12 and more signal lines 13；
Multiple driving chips bind pad 14, are corresponded respectively by drive signal lead 15 and a plurality of test lead 11
Connection, for the drive signal that driving chip is sent to be inputted at most signal line 13 by a plurality of test lead 11；
Electrostatic discharge protection circuit 12, the first connection end of electrostatic discharge protection circuit 12 electrically connect with a plurality of test lead 11, and second
Connection end electrically connects with more signal lines 13, whole array base when when filling test signal outside for exporting and binding driving chip
Electrostatic induced current caused by plate 1；
The non-display area of the both sides of viewing area 17 in the first direction is respectively arranged with gate driver 16；
Signal wire 13 includes data signal line 131 in the viewing area 17 and the gate driver 16 positioned at non-display area
Drive signal line 132, signal wire 13 be arranged in parallel in a second direction, and second direction is vertical with first direction；
Testing weld pad 120, correspond and electrically connect with a plurality of test lead 11.
The embodiment of the present invention additionally provides a kind of display panel, and with reference to figure 6, Fig. 6 is one kind provided in an embodiment of the present invention
The sectional structure chart of display panel, the display panel include counter substrate 2, and the array base described in any embodiment of the present invention
Plate 1.The display panel can be applied to the display devices such as mobile phone, TV.
In certain embodiment, display panel may be, for example, LCD display panel, OLED display panel, QLED display panels,
Curved face display panel or other display panels.Pay attention to, above are only presently preferred embodiments of the present invention and institute's application technology principle.This
Art personnel for a person skilled in the art can it will be appreciated that the invention is not restricted to specific embodiment described here
Various significantly change, readjust, be combined with each other and substitute without departing from protection scope of the present invention.Therefore, though
So the present invention is described in further detail by above example, but the present invention is not limited only to above example,
Without departing from the inventive concept, other more equivalent embodiments can also be included, and the scope of the present invention is by appended
Right determine.
Claims (10)
1. a kind of array base palte, including viewing area and the non-display area around the viewing area, it is characterised in that including：Set
In the viewing area and more signal lines of the non-display area；It is arranged at the electrostatic discharge protection circuit of the non-display area；
The a plurality of test lead of the non-display area is arranged at, passes through the electrostatic discharge protection circuit and more signal lines respectively
Connect one to one；
Multiple driving chips binding pad of the non-display area is arranged at, passes through drive signal lead and a plurality of survey respectively
Examination lead connects one to one, for the drive signal that driving chip is sent to be inputted to described by a plurality of test lead
More signal lines；
Wherein, the first connection end of the electrostatic discharge protection circuit electrically connects with a plurality of test lead, second connection end and institute
More signal line electrical connections are stated, when when filling test signal outside for exporting and binding driving chip produced by whole array base palte
Electrostatic induced current.
2. array base palte according to claim 1, it is characterised in that also include：
Testing weld pad, the non-display area is arranged at, corresponds and electrically connect with a plurality of test lead.
3. array base palte according to claim 1, it is characterised in that the non-of the both sides of the viewing area in the first direction shows
Show that area is respectively arranged with gate driver；
The signal wire includes data signal line in the viewing area and the gate driver positioned at the non-display area
Drive signal line, the signal wire be arranged in parallel in a second direction, and the second direction is vertical with the first direction.
4. array base palte according to claim 3, it is characterised in that：
The a plurality of test lead and driving chip binding pad are arranged on the non-display area of viewing area side in a second direction.
5. array base palte according to claim 4, it is characterised in that：
The a plurality of test lead is divided into Part I test lead and Part II test lead；
The Part I test lead is corresponded and electrically connected with Part I data signal line and drive signal line respectively；
The Part II test lead is corresponded and electrically connected with Part II data signal line and drive signal line respectively.
6. array base palte according to claim 5, it is characterised in that：
The Part I test lead and Part II test lead are separately positioned on the two of the driving chip binding pad
Side.
7. array base palte according to claim 5, it is characterised in that：
The Part I test lead is identical with the quantity of the Part II test lead；
The Part I data signal line and drive signal line and the Part II data signal line and drive signal line
Quantity is identical.
8. array base palte according to claim 3, it is characterised in that the drive signal line of the gate driver includes：
Power line, clock cable and line trigger signal.
9. a kind of array base palte, including viewing area and the non-display area around the viewing area, it is characterised in that including：Set
In the viewing area and more signal lines of the non-display area；It is arranged at the electrostatic discharge protection circuit of the non-display area；
The a plurality of test lead of the non-display area is arranged at, passes through the electrostatic discharge protection circuit and more signal lines respectively
Connect one to one；
Multiple driving chips binding pad of the non-display area is arranged at, passes through drive signal lead and a plurality of survey respectively
Examination lead connects one to one, for the drive signal that driving chip is sent to be inputted to described by a plurality of test lead
More signal lines；
Wherein, the first connection end of the electrostatic discharge protection circuit electrically connects with a plurality of test lead, second connection end and institute
More signal line electrical connections are stated, when when filling test signal outside for exporting and binding driving chip produced by whole array base palte
Electrostatic induced current；
The non-display area of the both sides of the viewing area in the first direction is respectively arranged with gate driver；
The signal wire includes data signal line in the viewing area and the gate driver positioned at the non-display area
Drive signal line, the signal wire be arranged in parallel in a second direction, and the second direction is vertical with the first direction；
Testing weld pad, correspond and electrically connect with a plurality of test lead.
A kind of 10. display panel, it is characterised in that including counter substrate, and the array base as described in claim 1-9 is any
Plate.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711003577.8A CN107589612B (en) | 2017-10-24 | 2017-10-24 | Array substrate and display panel |
| PCT/CN2018/078119 WO2019080433A1 (en) | 2017-10-24 | 2018-03-06 | Array substrate and display panel |
| US16/758,158 US11296125B2 (en) | 2017-10-24 | 2018-03-06 | Array substrate and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711003577.8A CN107589612B (en) | 2017-10-24 | 2017-10-24 | Array substrate and display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107589612A true CN107589612A (en) | 2018-01-16 |
| CN107589612B CN107589612B (en) | 2021-02-19 |
Family
ID=61044170
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711003577.8A Active CN107589612B (en) | 2017-10-24 | 2017-10-24 | Array substrate and display panel |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US11296125B2 (en) |
| CN (1) | CN107589612B (en) |
| WO (1) | WO2019080433A1 (en) |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060000939A (en) * | 2004-06-30 | 2006-01-06 | 엘지.필립스 엘시디 주식회사 | Liquid crystal display |
| US20070273802A1 (en) * | 2006-05-23 | 2007-11-29 | Casio Computer Co., Ltd. | Display device with static electricity protecting circuit |
| CN101097673A (en) * | 2006-06-26 | 2008-01-02 | 胜华科技股份有限公司 | Electrostatic discharge protection integrated circuit with single-sided board function testing |
| CN203117618U (en) * | 2013-02-05 | 2013-08-07 | 华映视讯（吴江）有限公司 | Faceplate inner circuit system with electrostatic protection function |
| CN105976785A (en) * | 2016-07-21 | 2016-09-28 | 武汉华星光电技术有限公司 | Goa circuit and liquid crystal display panel |
| CN106057109A (en) * | 2016-08-03 | 2016-10-26 | 武汉华星光电技术有限公司 | Display device and display panel thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101616695B1 (en) * | 2009-12-09 | 2016-05-02 | 엘지디스플레이 주식회사 | Flat panel display and testing method thereof |
| JP5917694B2 (en) * | 2012-07-20 | 2016-05-18 | シャープ株式会社 | Display device |
| CN105954899B (en) * | 2016-07-08 | 2019-07-23 | 武汉华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display |
| CN107589612B (en) | 2017-10-24 | 2021-02-19 | 惠科股份有限公司 | Array substrate and display panel |
-
2017
- 2017-10-24 CN CN201711003577.8A patent/CN107589612B/en active Active
-
2018
- 2018-03-06 US US16/758,158 patent/US11296125B2/en active Active
- 2018-03-06 WO PCT/CN2018/078119 patent/WO2019080433A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060000939A (en) * | 2004-06-30 | 2006-01-06 | 엘지.필립스 엘시디 주식회사 | Liquid crystal display |
| US20070273802A1 (en) * | 2006-05-23 | 2007-11-29 | Casio Computer Co., Ltd. | Display device with static electricity protecting circuit |
| CN101097673A (en) * | 2006-06-26 | 2008-01-02 | 胜华科技股份有限公司 | Electrostatic discharge protection integrated circuit with single-sided board function testing |
| CN203117618U (en) * | 2013-02-05 | 2013-08-07 | 华映视讯（吴江）有限公司 | Faceplate inner circuit system with electrostatic protection function |
| CN105976785A (en) * | 2016-07-21 | 2016-09-28 | 武汉华星光电技术有限公司 | Goa circuit and liquid crystal display panel |
| CN106057109A (en) * | 2016-08-03 | 2016-10-26 | 武汉华星光电技术有限公司 | Display device and display panel thereof |
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| CN108492758A (en) * | 2018-04-09 | 2018-09-04 | 京东方科技集团股份有限公司 | A kind of test control circuit and control method, display base plate, display device |
| CN108962107A (en) * | 2018-07-17 | 2018-12-07 | 上海天马有机发光显示技术有限公司 | A kind of display panel and display device |
| CN109377933A (en) * | 2018-12-26 | 2019-02-22 | 厦门天马微电子有限公司 | A kind of driving method of display panel, display panel and display device |
| CN110473464A (en) * | 2019-07-30 | 2019-11-19 | 武汉华星光电技术有限公司 | Display panel |
| US11378851B2 (en) | 2019-07-30 | 2022-07-05 | Wuhan China Star Optoelectronics Technology Co., Ltd | Display panel and display device |
| CN110867139A (en) * | 2019-11-28 | 2020-03-06 | 上海中航光电子有限公司 | Array substrate, display panel and display device |
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| CN111261055B (en) * | 2020-01-21 | 2022-02-22 | 京东方科技集团股份有限公司 | OLED display screen and OLED display device |
| CN111261055A (en) * | 2020-01-21 | 2020-06-09 | 京东方科技集团股份有限公司 | OLED display screen and OLED display device |
| TWI766612B (en) * | 2021-03-01 | 2022-06-01 | 大陸商深圳天德鈺科技股份有限公司 | Display panel |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2019080433A1 (en) | 2019-05-02 |
| CN107589612B (en) | 2021-02-19 |
| US11296125B2 (en) | 2022-04-05 |
| US20200343270A1 (en) | 2020-10-29 |
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