CN111123591A

CN111123591A - Array substrate, display panel and display device

Info

Publication number: CN111123591A
Application number: CN201911371217.2A
Authority: CN
Inventors: 王林志; 席克瑞; 秦锋; 刘金娥
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2019-12-26
Filing date: 2019-12-26
Publication date: 2020-05-08

Abstract

The invention discloses an array substrate, a display panel and a display device, wherein the array substrate comprises a display area and a non-display area surrounding the display area; the non-display area comprises a shift register, a signal wire and a bonding pad for testing the grid driving circuit; the signal line comprises a grid driving signal line electrically connected with the shift register; the pad is electrically connected with the output end of the shift register through a connecting wire, the connecting wire is not overlapped with the vertical projection of the signal wire on the substrate, the pad is positioned on one side of the signal wire, which is deviated from the substrate, and the signal wire and the pad are arranged in an insulating mode in the direction perpendicular to the substrate. Because the connecting line between the bonding pad and the output end of the shift register is not crossed with the signal line, and the antistatic weak point does not exist, any signal line can not be damaged when the static test is carried out, and the display effect of the display panel can not be influenced by the static test.

Description

Array substrate, display panel and display device

Technical Field

The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.

Background

Currently, more and more liquid crystal display panels adopt a technology of manufacturing a gate driving circuit on an array substrate to reduce the frame width of the array substrate. In order to realize the abnormity detection of the gate drive circuit, a detection end (namely a pad for testing) is arranged at the step of the array substrate, and a pad lead is connected with the output end of the gate drive circuit.

In the related art, there is a crossing between a signal line of a gate driving circuit, i.e., an ASG (Amorphous Silicon gate) signal line, and a pad wiring.

However, the crossing position is a weak point of Static electricity resistance, when an ESD (Electro-Static discharge) test is performed, Static electricity will enter the pad and enter the pad lead, and when the Static electricity reaches the crossing position, the ASG signal line will be broken down by the Static electricity, thereby affecting the display effect of the liquid crystal display panel.

Disclosure of Invention

The present invention is directed to an array substrate, a display panel and a display device, which are provided to overcome the above-mentioned disadvantages of the related art, and the object is achieved by the following means.

A first aspect of the present invention provides an array substrate, including: a display area, a non-display area surrounding the display area;

the non-display area comprises a shift register, a signal wire and a bonding pad for testing the grid driving circuit; the signal line comprises a grid driving signal line electrically connected with the shift register;

the pad is electrically connected with the output end of the shift register through a connecting wire, the connecting wire is not overlapped with the projection of the signal wire, the pad is positioned on one side of the signal wire, which is deviated from the substrate, and the signal wire is arranged in an insulating mode with the pad.

A second aspect of the present invention provides a display panel, which includes the array substrate as described in the first aspect.

A third aspect of the invention proposes a display device comprising a display panel as described in the second aspect above.

Compared with the routing design of the existing array substrate, the routing design of the array substrate provided by the invention has the following beneficial effects:

the pad on the array substrate is electrically connected with the output end of the shift register through the connecting wire, the connecting wire is not overlapped with the vertical projection of the signal wire on the substrate, the pad is positioned on one side of the signal wire deviated from the substrate, and the signal wire and the pad are arranged in an insulating mode in the direction perpendicular to the substrate, so that an antistatic weak point does not exist between the connecting wire and the signal wire, when the electrostatic test is carried out, the electrostatic damage to the signal wire can not be caused, and the display effect of the display panel can be ensured.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

fig. 1 is a schematic diagram of routing of an array substrate in the related art;

fig. 2 is a top view of an array substrate according to the present invention;

FIG. 3 is a cross-sectional view taken along line C1C2 of FIG. 2;

FIG. 4 is a top view of another array substrate according to the present invention;

FIG. 5 is a top view of another array substrate according to the present invention;

FIG. 6 is a schematic diagram illustrating a cascade relationship of a shift register according to the present invention;

FIG. 7 is a schematic diagram of a cascade relationship of another shift register according to the present invention;

FIG. 8 is a top view of one type of bond pad and break-away member shown in accordance with the present invention;

FIG. 9 is a cross-sectional view of the pad and break away piece taken along direction D1D2 before testing of FIG. 8;

FIG. 10 is a cross-sectional view of the pad and the break at the test of FIG. 8 taken along the direction D1D 2;

fig. 11 is a schematic structural diagram of a display device according to an exemplary embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the invention, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present invention. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

Fig. 1 is a schematic diagram of routing lines of an array substrate in the related art, and as shown in fig. 1, connection lines (i.e., pad leads) between pads and output terminals of a shift register are designed to intersect with ASG signal lines, that is, the connection lines and the ASG signal lines overlap in a vertical projection of a substrate, and an anti-electrostatic weak position is an overlapping position between the lines in a circuit design.

When ESD tests are carried out, the ESD gun is used for discharging the four corners and the center of the display device optionally, after static electricity enters the display device, the static electricity enters the bonding pad due to the fact that the bonding pad is made of large metal blocks which are arranged in a leaking mode on the array substrate in the display device, then the static electricity enters the bonding pad, when the static electricity reaches the overlapping position between the bonding pad and the ASG signal line, the ASG signal line at the overlapping position can be damaged, and the display effect of the display device is affected.

In order to solve the technical problem, the invention designs the signal wire to be wound off the lead of the bonding pad so as to avoid the crossing of the signal wire and the lead of the bonding pad.

Fig. 2 is a top view of an array substrate, and fig. 3 is a cross-sectional view taken along a direction C1C2 in fig. 2, referring to fig. 2 and 3, the array substrate includes: a display area AA, a non-display area BB surrounding the display area AA; the non-display area BB includes a shift register 40, a signal line 30, and a pad 50 for testing the gate driving circuit; the signal line 30 includes a gate driving signal line 301 electrically connected to the shift register 40, the pad 50 is electrically connected to an output end of the shift register 40 through a connection line 60, the connection line 60 does not overlap with a vertical projection of the signal line 30 on the substrate 00, the pad 50 is located on a side of the signal line 30 away from the substrate 00, the signal line 30 and the pad 50 are arranged in an insulating manner in a direction perpendicular to the substrate 00, fig. 3 only shows that 3 insulating layers are arranged between the signal line 30 and the pad 50, of course, as long as the signal line 30 and the pad 50 are arranged in an insulating manner, the number of layers of the specific insulating layers is not limited, and it should be noted that the gate driving circuit includes a plurality of shift registers 40 and the gate driving signal line 301 electrically connected to the shift register 40.

Here, the signal line 30 is closer to the substrate base 00 than the pad 50, and an insulating layer is provided on the signal line 30, so that direct electrostatic damage is not caused to the signal line 30 when the ESD test is performed.

The gate driving signal line 301 may include a VGL (low-level voltage) signal line, a VGH (high-level voltage) signal line, a reset signal line, a clock signal, an STV signal line, and the like.

The output terminal of the shift register 40 is also electrically connected to the gate line 10 in the display area AA to provide a gate signal to the gate line 10.

It will be understood by those skilled in the art that the substrate 00 of the present invention may be a glass substrate, or may be a transparent hard substrate or a flexible substrate, which is not limited in the present invention.

Based on the above description, since the connection line 60 between the pad 50 and the output terminal of the shift register 40 does not intersect with the signal line 30, and there is no weak point of antistatic, any signal line will not be damaged during the static test, and it is ensured that the display effect of the display panel will not be affected by the static test.

With continued reference to fig. 2, the non-display area BB surrounding the display area AA may be divided into a first non-display area 01, a second non-display area 02, a third non-display area 03, and a fourth non-display area 04, the first non-display area 01 being disposed opposite to the second non-display area 02, and the third non-display area 03 being disposed opposite to the fourth non-display area 04.

As shown in fig. 2, the first non-display area 01 may be positioned at the left side of the display area AA, the second non-display area 02 may be positioned at the right side of the display area AA, the third non-display area 03 may be positioned above the display area AA, and the fourth non-display area 04 may be positioned below the display area AA.

It can be understood by those skilled in the art that the fourth non-display area 04 may also be generally referred to as a step area of the array substrate, and for convenience of performing the electrostatic test, the pad 50 is generally disposed in the step area, that is, the pad 50 is disposed in the fourth non-display area 04, it should be noted that the pad 50 may also be disposed on one side of the second non-display area 02 as long as the pad 50 and the connection line 60 electrically connected to the pad 50 do not overlap with the signal line 30 in a projection perpendicular to the substrate.

With continued reference to fig. 2, the array substrate may further include a driving chip 70 (i.e., a driving IC) disposed in the fourth non-display area 04, and the driving chip 70 is electrically connected to the signal line 30.

Optionally, the driving chip 70 may also be bound to a Flexible Printed Circuit (FPC), the flexible printed circuit is bound to the array substrate, and the signal line 30 is electrically connected to the flexible printed circuit.

In the present invention, the signal line 30 may further include a ground line 303 and a common electrode line 302, the ground line 303 and the common electrode line 302 are both disposed around the display area AA, the common electrode line 302 may provide a common point signal for a common electrode of the display panel, and the ground line 303 may derive charges inside or outside the display panel.

In one example, the ground line 303 (i.e., GND line) is disposed at the outermost periphery of the common electrode line 302 and the gate driving signal line 301. The ground line 303 and the common electrode line 302 may be electrically connected to the driving chip 70, and may also be directly electrically connected to an FPC (flexible circuit board), which is not limited herein.

In another embodiment, as shown in fig. 4, for a two-side driving arrangement of the shift register, that is, the shift register is disposed in the first non-display area 01 and the second non-display area 02, and the same signal line 30 is disposed in the first non-display area 01 and the fourth non-display area 04, and is disposed in the second non-display area 02 and the fourth non-display area 04, the same signal line 30 is disposed in the first non-display area 01 and the fourth non-display area 04 and may have a corner, which may ensure that the bezel is reduced as much as possible when a certain number of signal lines are disposed.

Optionally, the gate driving circuit disposed in the first non-display area 01 may drive the gate lines 10 in odd rows in the display area AA, and the gate driving circuit disposed in the second non-display area 02 may drive the gate lines 10 in even rows in the display area AA.

Of course, the shift register 40 disposed in the first non-display area 01 and the shift register 40 disposed in the second non-display area 02 may also drive the same gate line 10 at the same time, especially in a high resolution product, which is not limited herein.

In another embodiment, as shown in fig. 5, each signal line 30 may include a plurality of line segments electrically connected to each other in the fourth non-display area 04, and at least two of the line segments have different extending directions, and the pad 50 is at least partially surrounded by a folding line.

That is, in order to design around the pad 50, each signal line 30 may surround the pad 50 on the inner side in a zigzag manner.

With the signal line routing design shown in fig. 5, the signal lines 30 include 3 segments electrically connected to each other in the fourth non-display area 04, and each signal line 30 is located in the fourth non-display area 04 and the segment folding line surrounds the pad 50 design.

It can be understood by those skilled in the art that the trace design of the signal line 30 in the fourth non-display area 04 shown in fig. 5 is only an exemplary illustration, as long as the signal line 30 surrounds the pad 50 on the inner side, that is, the signal line 30 and the pad 50 do not overlap in the vertical projection of the substrate, the present invention does not specifically limit the specific trace design shape of the signal line 30, and the design of the multi-segment folding line may be matched with the position of the pad 50 and the different shape of the pad 50, that is, the design of surrounding the pad 50, so that the bezel of the display panel may be further effectively reduced to implement a narrow bezel design.

In the invention, the gate driving circuit can comprise a plurality of shift register systems, and the number of the bonding pads is consistent with that of the shift register systems.

It should be noted that the gate driving circuit includes a plurality of shift register systems independent of each other, and each shift register system includes a plurality of shift registers cascaded to each other. A plurality of shift register systems are designed in the gate drive circuit, so that the power consumption of the shift register can be reduced, and the power consumption of the whole array substrate is further reduced.

It should be noted that the pad 50 is electrically connected to the output terminal of the last stage of the shift register in the shift register system, so that the pad 50 can effectively detect the signal of the entire shift register system.

The last stage shift register refers to the last stage shift register connected to the end deviating from the STV signal.

As shown in fig. 4 and fig. 5, the gate driving circuits respectively disposed at two sides of the display area AA are respectively connected to a pad 50, which means that the gate driving circuits at two sides of the display area AA each include a shift register system.

It will be understood by those skilled in the art that the pads shown in fig. 2, 4 and 5 are only exemplary, and in practical applications, the same number of pads may be provided according to the number of shift register systems.

Fig. 6 is a schematic diagram showing a cascade relationship of a shift register according to the present invention, and fig. 7 is a schematic diagram showing a cascade relationship of another shift register according to the present invention, and as shown in fig. 6, the gate driving circuit includes only one shift register system, which includes 6 cascaded ASG1 shift registers, ASG2 shift registers, ASG3 shift registers, ASG4 shift registers, ASG5 shift registers, and ASG6 shift registers, so that a pad can be provided to detect an output condition of the shift register system. The gate driving circuit in fig. 7 includes two shift register systems, one shift register system including cascaded ASG1, ASG3, and ASG5 shift registers; the other shift register system comprises an ASG2 shift register, an ASG4 shift register and an ASG6 shift register which are cascaded, so that two pads can be arranged to detect the output condition of the two shift register systems.

Referring to fig. 8, 9 and 10, fig. 8 is a top view of a bond pad and a break according to the present invention, fig. 9 is a cross-sectional view of the break taken along the direction D1D2 before the test of fig. 8, and fig. 10 is a cross-sectional view of the break taken along the direction D1D2 during the test of fig. 8; in fig. 8, a sub-connection line 601 and a disconnecting element 501 are further included between the pad 50 and the connection line 60, and the disconnecting element 501 is electrically connected to the connection line 60, where it is to be noted that, when ESD detection is performed, the pad 50 and the disconnecting element 501 are arranged in an insulating manner, as in fig. 9, the pad 50 and the disconnecting element 501 are not electrically connected, but when a gate driving circuit needs to be detected through the pad 50, the disconnecting element 501 and the pad 50 need to be electrically connected through the sub-connection line 601 by soldering or laser melting or the like before detection, and referring to fig. 10 in particular, when a test probe is pricked at the pad position, the gate driving signal can be detected, so that a technician can determine whether the gate driving signal is abnormal. The mode that the disconnecting part 501 is arranged between the bonding pad 50 and the connecting line 60 can keep a double-disconnection design before an ESD test is carried out, namely, the sub-connecting line is disconnected from both ends of the bonding pad 50 and the disconnecting part 501, so that the situation that no static electricity enters the connecting line 60 through the bonding pad 50 and then enters a signal line of a display panel can be fully guaranteed, and the problem of electrostatic damage is fully prevented.

The connection line 60 and the sub-connection line 601 are disposed at different metal layers, the connection line 60 is disposed at the same layer as the pad 50 and the break 501, alternatively, referring to fig. 9, the connection line 60 is disposed in the same layer as the disconnection member 501 and the pad 50, alternatively, the same layer is formed of the same material, and a metal material can be selected for manufacturing, so that the wiring can be manufactured through one process flow, the process and the manufacturing are simpler, the sub-connecting line 601 and the connecting line 60 are arranged in different layers, the insulating layer 003 is arranged between the connecting line 60 and the sub-connecting line 601 in fig. 9, when the disconnection member 501 and the pad 50 are electrically connected to the sub-connection line 601 by soldering or laser melting, respectively, it should be noted that the film structure in fig. 9 is merely an example, alternatively, the connection line 60 and the sub-connection line 601 are disposed on the same layer, and the connection line 60 needs to be electrically connected to the disconnection unit 501 and the connection line 60 through a via hole disposed in the insulating layer 003. Since the pads 50 need to be used in the post-test, the pads 50 are generally disposed on the outermost layer of the array substrate, i.e., the pads need to be disposed on the outermost layer away from the substrate.

In one embodiment, the display area AA as shown in fig. 2 or 4 may include a plurality of gate lines 10 and a plurality of data lines 20, the gate lines 10 and the data lines 20 crossing to define a pixel unit, and the pixel unit includes a pixel electrode 80 and a thin film transistor 90.

As shown in fig. 3, the thin film transistor includes a gate electrode 901, an active layer 902, a source electrode 904, and a drain electrode 903, wherein the gate electrode 901 is insulated from the active layer 902, the source electrode 904, and the drain electrode 903 by a gate insulating layer 001, and an insulating layer 002 and an insulating layer 003 are provided on the sides of the source electrode 904 and the drain electrode 903 facing away from the substrate 00 to insulate the source electrode 904, the drain electrode 903, and other layers.

Optionally, the insulating layer 003 is a PLN planarization layer, the drain electrode 903 is electrically connected to the pixel electrode 80, the number of thin film transistors, the number of gate lines, and the number of data lines in the drawing are merely examples, and the specific number is not limited.

Based on this, the array substrate may include a first metal layer, a second metal layer, and a third metal layer, which are sequentially disposed in an insulating manner, the gate 901 of the thin film transistor is disposed on the first metal layer, the source 904 and the drain 903 are disposed on the second metal layer, the signal line 30 is disposed on the first metal layer, optionally, the signal line 30 and the gate 901 are formed by patterning in the same process and in the same layer, and both the signal line 30 and the gate 901 are made of metal materials, so that not only is the impedance of the signal line small, but also the process is reduced in the same process, and the pad 50 is disposed on the third metal layer to ensure insulation between the signal line 30 and the pad 50.

The invention also provides a display panel, which includes the array substrate shown in fig. 2 or fig. 4.

In an embodiment, the display panel may further include a color film substrate, the color film substrate and the array substrate are bonded by frame glue, the pad 50 disposed in the non-display area is not overlapped with the frame glue, that is, the pad 50 is disposed on a side of the frame glue away from the display area, so that a technician can conveniently use the testing probe to perform a test on the pad.

In one example, the display panel may be a transparent display panel, such as a micro-LED transparent display panel or the like.

The present invention further provides a display device 100 including the display panel as described above, and fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention. Referring to fig. 11, the display device 100 includes the display panel provided in the above embodiment.

For example, the display device 100 may be an electronic device such as a mobile phone, a computer, a smart wearable device (e.g., a smart watch), and an in-vehicle display device, which is not limited in this embodiment of the invention. The display device 100 may also include an insulating support backplane.

That is, the display device is designed without an iron frame, for example, for some narrow frames or transparent display panels, the iron frame surrounds the display panel to cover the display part, which is not beneficial to the design of the narrow frames and the transparent display panel, so an insulating support backboard is needed, and when the insulating support backboard arranged in the display device is easy to be tested in electrostatic damage, the testable pad and the test line are designed to be non-overlapped, so that the electrostatic breakdown of the line on the display panel in the ESD test can be avoided.

Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. An array substrate, comprising: a display area, a non-display area surrounding the display area;

the non-display area comprises a shift register, a signal line and a pad for testing a grid driving circuit, the signal line comprises a grid driving signal line electrically connected with the shift register, and the grid driving circuit comprises the shift register and the grid driving signal line;

the pad is electrically connected with the output end of the shift register through a connecting wire, the connecting wire is not overlapped with the vertical projection of the signal wire on the substrate, the pad is positioned on one side of the signal wire, which is deviated from the substrate, and the signal wire and the pad are arranged in an insulating mode in the direction perpendicular to the substrate.

2. The array substrate of claim 1, wherein the non-display area comprises a first non-display area and a second non-display area which are oppositely arranged, a third non-display area and a fourth non-display area which are oppositely arranged;

the shift register is arranged in the first non-display area, and the same signal line is arranged in the first non-display area and the fourth non-display area.

3. The array substrate of claim 2, wherein the shift register is disposed in the first non-display area and the second non-display area, and the same signal line is disposed in the first non-display area and the fourth non-display area, and/or disposed in the second non-display area and the fourth non-display area.

4. The array substrate of claim 2, wherein the array substrate comprises: and the driving chip is arranged in the fourth non-display area and is electrically connected with the signal line.

5. The array substrate of claim 2, wherein the signal line comprises a plurality of line segments electrically connected to each other in the fourth non-display region, at least two of the line segments have different extending directions, and the folding line at least partially surrounds the pad.

6. The array substrate of claim 1, wherein the signal lines further comprise a ground line and a common electrode line;

the ground line and the common electrode line are both arranged around the display area.

7. The array substrate of claim 1, further comprising a sub-connection line and a disconnection element between the pad and the connection line, wherein the disconnection element is electrically connected to the connection line, and the disconnection element is electrically connected to the pad through the sub-connection line.

8. The array substrate of claim 7, wherein the connection lines and the sub-connection lines are disposed in different metal layers, and the connection lines, the pads, and the disconnectors are disposed in the same layer.

9. The array substrate of claim 1, wherein the gate driving circuit comprises a plurality of shift register systems, and the number of the pads is equal to the number of the shift register systems;

the shift register systems are independent from each other, and each shift register system comprises a plurality of shift registers which are cascaded with each other.

10. The array substrate of claim 9, wherein the pad is electrically connected to an output of a last stage of the shift register in the shift register system.

11. The array substrate of claim 1, wherein the display region comprises a plurality of gate lines and a plurality of data lines, the gate lines and the data lines intersect to define pixel units, the pixel units comprise pixel electrodes and thin film transistors, and the thin film transistors comprise gate electrodes, active layers, source electrodes and drain electrodes;

the array substrate comprises a first metal layer, a second metal layer and a third metal layer which are sequentially arranged in an insulating mode, the grid electrode is arranged on the first metal layer, the source electrode and the drain electrode are arranged on the second metal layer, the signal line is arranged on the first metal layer, and the bonding pad is arranged on the third metal layer.

12. A display panel comprising the array substrate according to any one of claims 1 to 11.

13. The display panel according to claim 12, further comprising a color film substrate, wherein the color film substrate and the array substrate are bonded by sealant, and the bonding pad is not overlapped with the sealant.

14. The display panel according to claim 12, wherein the display panel is a transparent display panel.

15. A display device, characterized in that it comprises a display panel as claimed in claim 12.

16. The display device of claim 15, further comprising an insulating support backplane.