CN105976745A - Array substrate test circuit, display panel and flat panel display device - Google Patents
Array substrate test circuit, display panel and flat panel display device Download PDFInfo
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- CN105976745A CN105976745A CN201610580608.5A CN201610580608A CN105976745A CN 105976745 A CN105976745 A CN 105976745A CN 201610580608 A CN201610580608 A CN 201610580608A CN 105976745 A CN105976745 A CN 105976745A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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Abstract
The invention discloses an array substrate test circuit, a display panel and a flat panel display device. The array substrate test circuit comprises a chip, a unidirectional control unit and an array substrate test unit. The chip comprises a first pin which transmits a starting voltage side signal and a second pin which transmits a shutdown voltage side signal. The array substrate test unit comprises an electrostatic protection device, a first welding disc which transmits the starting voltage side signal and a second welding disc which transmits the shutdown voltage side signal, wherein each of the first and second welding discs is connected with one pin of the electrostatic protection device. When the chip works, the unidirectional control unit is cut off, and the starting voltage side signal and the shutdown voltage side signal transmitted by the chip cannot be outputted to the first and second welding discs. When the array substrate test unit works, the unidirectional control unit is conducted, and the first and second welding discs transmit the received starting voltage side signal and the shutdown voltage side signal to the chip so as to avoid influence on the signals in the chip and then avoid increasing of product analysis time and reducing of the stability of the product.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of array base palte test circuit, show
Show panel and flat display apparatus.
Background technology
Current flat display apparatus uses scan drive circuit, namely utilizes existing thin film brilliant
Scan drive circuit is produced on array base palte by body pipe flat-panel screens array process, it is achieved to by
The type of drive of row scanning, arranges array base palte test circuit, with in battle array on array base palte simultaneously
After row substrate completes, array substrate carries out testing electrical property, but, existing array base palte is tested
The signal of circuit chips output is exposed in atmosphere by array base palte test cell, can be to chip
Interior signal impacts, and in chip, the saltus step of signal can cause the mistake of array base palte test cell
Effect, thus cause the test needing to be carried out by array base palte test cell to resolve and cannot be carried out, with
Resolve duration as increasing product and reduce the stability of product.
Summary of the invention
The technical problem that present invention mainly solves is to provide a kind of array base palte test circuit, display surface
Plate and flat display apparatus, the signal exported to solve array base palte test circuit chips passes through battle array
Row tester substrate unit is exposed to be impacted the signal in chip in atmosphere, and then increases product
Product resolve duration and reduce the problem of stability of product.
For solving above-mentioned technical problem, the technical scheme that the present invention uses is: provide a kind of battle array
Row substrate test circuit, including:
Chip, described chip includes that the first pin and the second pin, described first pin are used for transmitting
Cut-in voltage end signal, described second pin is used for transmitting closedown voltage end signal；
It is unidirectionally controlled unit, connects the first pin and second pin of described chip, be used for transmitting institute
State cut-in voltage end signal and described closedown voltage end signal；And
Array base palte test cell, described array base palte test cell include electrostatic protection device,
One pad and the second pad, described electrostatic protection device connect described in be unidirectionally controlled unit, described the
One pad and described second pad are connected respectively a pin of described electrostatic protection device, institute
Stating the first pad for transmitting cut-in voltage end signal, described second pad is used for transmitting closedown voltage
End signal；When described chip operation, described in be unidirectionally controlled unit cut-off, the first of described chip
The cut-in voltage end signal of pin transmission is unidirectionally controlled unit and described electrostatic guarantor described in can not passing through
Protect device to export to described first pad and the closedown voltage end of the second pin transmission of described chip
Signal is unidirectionally controlled unit and described electrostatic protection device exports to described described in can not passing through
Two pads；When described array base palte test cell works, described in be unidirectionally controlled unit conducting, institute
State the first pad the cut-in voltage end signal received is passed through described in be unidirectionally controlled unit and described
Electrostatic protection device is transferred to the first pin of described chip and described second pad and will receive
Close voltage end signal pass through described in be unidirectionally controlled unit and described electrostatic protection device is transferred to institute
State the second pin of chip.
Wherein, described in be unidirectionally controlled unit and include the first gate-controlled switch and the second gate-controlled switch, described
First and second gate-controlled switch includes controlling end, the first end and the second end respectively, described first controlled
The end that controls of switch is connected with the first end of described first gate-controlled switch and is connected to described chip
First pin, the second end of described first gate-controlled switch is connected to of described electrostatic protection device
Pin, the end that controls of described second gate-controlled switch is connected also with the first end of described second gate-controlled switch
Being connected to the second pin of described chip, the second end of described second gate-controlled switch is connected to described quiet
One pin of electric protective component, described first gate-controlled switch is N-type TFT, described
Two gate-controlled switches are P-type TFT, the control end of described first switch, the first end and second
Grid, source electrode and the drain electrode of end corresponding described N-type TFT respectively, described second switch
Control end, the first end and the second end grid of corresponding described P-type TFT respectively, source electrode and
Drain electrode.
Wherein, described in be unidirectionally controlled unit and include the first gate-controlled switch and the second gate-controlled switch, described
First and second gate-controlled switch includes controlling end, the first end and the second end respectively, described first controlled
The end that controls of switch is connected with the first end of described first gate-controlled switch and is connected to described chip
First pin, one of the second end described electrostatic protection device of connection of described first gate-controlled switch is drawn
Foot, the first end of described second gate-controlled switch connects the second pin of described chip, and described second can
The end that controls of control switch is connected with the second end of described second gate-controlled switch and is connected to described electrostatic
One pin of protection device, first and second gate-controlled switch described is N-type TFT,
Control end, the first end and second end of first and second switch described corresponding described N-type thin film respectively
The grid of transistor, source electrode and drain electrode.
Wherein, it is characterised in that described array base palte test cell also includes some 3rd pads,
Each 3rd pad correspondence connects a pin of described electrostatic protection device, for showing for pixel
Region and turntable driving region provide signal.
Wherein, described array base palte test circuit also includes the 4th pad and the 5th pad, described the
Four pads connect the first pin of described chip, are used for transmitting described cut-in voltage end signal, described
5th pad connects the second pin of described chip, is used for transmitting described closedown voltage end signal, institute
State covering insulant on the 4th and the 5th pad, remove when use the described 4th and five pads and cover
Cover the insulant on described 4th and the 5th pad.
For solving above-mentioned technical problem, another technical solution used in the present invention is: provide one
Display floater, described display floater includes that array base palte tests circuit, described array base palte test electricity
Road includes:
Chip, described chip includes that the first pin and the second pin, described first pin are used for transmitting
Cut-in voltage end signal, described second pin is used for transmitting closedown voltage end signal；
It is unidirectionally controlled unit, connects the first pin and second pin of described chip, be used for transmitting institute
State cut-in voltage end signal and described closedown voltage end signal；And
Array base palte test cell, described array base palte test cell include electrostatic protection device,
One pad and the second pad, described electrostatic protection device connect described in be unidirectionally controlled unit, described the
One pad and described second pad are connected respectively a pin of described electrostatic protection device, institute
Stating the first pad for transmitting cut-in voltage end signal, described second pad is used for transmitting closedown voltage
End signal；When described chip operation, described in be unidirectionally controlled unit cut-off, the first of described chip
The cut-in voltage end signal of pin transmission is unidirectionally controlled unit and described electrostatic guarantor described in can not passing through
Protect device to export to described first pad and the closedown voltage end of the second pin transmission of described chip
Signal is unidirectionally controlled unit and described electrostatic protection device exports to described described in can not passing through
Two pads；When described array base palte test cell works, described in be unidirectionally controlled unit conducting, institute
State the first pad the cut-in voltage end signal received is passed through described in be unidirectionally controlled unit and described
Electrostatic protection device is transferred to the first pin of described chip and described second pad and will receive
Close voltage end signal pass through described in be unidirectionally controlled unit and described electrostatic protection device is transferred to institute
State the second pin of chip.
Wherein, described in be unidirectionally controlled unit and include the first gate-controlled switch and the second gate-controlled switch, described
First and second gate-controlled switch includes controlling end, the first end and the second end respectively, described first controlled
The end that controls of switch is connected with the first end of described first gate-controlled switch and is connected to described chip
First pin, the second end of described first gate-controlled switch is connected to of described electrostatic protection device
Pin, the end that controls of described second gate-controlled switch is connected also with the first end of described second gate-controlled switch
Being connected to the second pin of described chip, the second end of described second gate-controlled switch is connected to described quiet
One pin of electric protective component, described first gate-controlled switch is N-type TFT, described
Two gate-controlled switches are P-type TFT, the control end of described first switch, the first end and second
Grid, source electrode and the drain electrode of end corresponding described N-type TFT respectively, described second switch
Control end, the first end and the second end grid of corresponding described P-type TFT respectively, source electrode and
Drain electrode.
Wherein, described in be unidirectionally controlled unit and include the first gate-controlled switch and the second gate-controlled switch, described
First and second gate-controlled switch includes controlling end, the first end and the second end respectively, described first controlled
The end that controls of switch is connected with the first end of described first gate-controlled switch and is connected to described chip
First pin, one of the second end described electrostatic protection device of connection of described first gate-controlled switch is drawn
Foot, the first end of described second gate-controlled switch connects the second pin of described chip, and described second can
The end that controls of control switch is connected with the second end of described second gate-controlled switch and is connected to described electrostatic
One pin of protection device, first and second gate-controlled switch described is N-type TFT,
Control end, the first end and second end of first and second switch described corresponding described N-type thin film respectively
The grid of transistor, source electrode and drain electrode.
Wherein, it is characterised in that described array base palte test cell also includes some 3rd pads,
Each 3rd pad correspondence connects a pin of described electrostatic protection device, for showing for pixel
Region and turntable driving region provide signal, described array base palte test circuit also to include the 4th pad
And the 5th pad, described 4th pad connects the first pin of described chip, be used for transmitting described in open
Opening voltage end signal, described 5th pad connects the second pin of described chip, is used for transmitting described
Close voltage end signal, described 4th and the 5th pad covers insulant, when using the described 4th
And during five pads, remove the insulant covered on described 4th and the 5th pad.
For solving above-mentioned technical problem, another technical solution used in the present invention is: provide one
Flat display apparatus, described flat display apparatus includes any of the above-described described array base palte test electricity
Road.
The invention has the beneficial effects as follows: be different from the situation of prior art, the described array of the present invention
Substrate test circuit pass through described in be unidirectionally controlled unit first and second gate-controlled switch conducting or
Cut-off so that when described chip operation, the cut-in voltage end signal of described chip output and closedown
Voltage end signal will not be transferred to the 3rd and the 4th pad of described array base palte test cell, thus
Avoid described cut-in voltage end signal and described closedown voltage end signal exposed in atmosphere, and in institute
When stating the work of array base palte test cell, will be opened by described 3rd and the 4th pad and described chip
Open voltage end signal and closedown voltage end signal is transferred to described panel, make the normal work of described panel
Make, avoid the signal in chip is impacted with this, and then increase product parsing duration and fall
The low stability of product.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the array base palte test circuit of prior art；
Fig. 2 is the circuit diagram of the first embodiment of the array base palte test circuit of the present invention；
Fig. 3 is the equivalent circuit diagram being unidirectionally controlled unit in Fig. 2；
Fig. 4 is the circuit diagram of the second embodiment of the array base palte test circuit of the present invention；
Fig. 5 is the equivalent circuit diagram being unidirectionally controlled unit in Fig. 4；
Fig. 6 is the circuit diagram of the 3rd embodiment of the array base palte test circuit of the present invention；
Fig. 7 is the circuit diagram of the 4th embodiment of the array base palte test circuit of the present invention；
Fig. 8 is the structural representation of the display floater of the present invention；
Fig. 9 is the structural representation of the flat display apparatus of the present invention.
Detailed description of the invention
Refer to Fig. 1, be the circuit diagram of array base palte test circuit in prior art.At array base
When board test unit 1 works, chip 2 no signal exports, the most described array base palte test cell
Pad 3,4 in 1 is by the cut-in voltage end signal VGH received and closes voltage end signal
VGL is transmitted to face by the corresponding cabling connected between electrostatic protection device 5 with described chip 2
The turntable driving district that other pad is described panel in plate, in described array base palte test cell 1
(GOA district) and pixel display area (AA district) provides signal；When described chip 2 works,
Without external signal on the pad 3 and 4 of described array base palte test cell 1, the most described chip 2
The cut-in voltage end signal VGH and closedown voltage end signal VGL of output are by described electrostatic protection
The pad 3 and 4 that device 5 and corresponding cabling are supplied in described array base palte test cell 1,
Cause described chip 2 when working described cut-in voltage end signal VGH and described closedown voltage end believe
Number VGL is exposed can impact the signal in described chip 2 in atmosphere, and then increases
Product resolves duration and reduces the problem of stability of product.
Refer to Fig. 2, be the circuit diagram of the first embodiment of the array base palte test circuit of the present invention.
As in figure 2 it is shown, described array base palte test circuit includes that chip 20, described chip 20 include the
One pin 21 and the second pin 22, described first pin 21 is used for transmitting cut-in voltage end signal
VGH, described second pin 22 is used for transmitting closedown voltage end signal VGL；It is unidirectionally controlled unit
30, connect the first pin 21 and the second pin 22 of described chip 20, be used for transmitting described unlatching
Voltage end signal VGH and described closedown voltage end signal VGL；Array base palte test cell 10,
Described array base palte test cell 10 includes electrostatic protection device the 13, first pad 11 and the second weldering
Dish 12, described electrostatic protection device 13 connect described in be unidirectionally controlled unit 30, described first pad
11 and described second pad 12 be connected respectively a pin of described electrostatic protection device 13,
Described first pad 11 is used for transmitting cut-in voltage end signal VGH, and described second pad 12 is used for
Voltage end signal VGL is closed in transmission；When described chip 20 works, described in be unidirectionally controlled unit
30 cut-offs, the cut-in voltage end signal VGH of the first pin 21 transmission of described chip 20 can not
It is unidirectionally controlled unit 30 and described electrostatic protection device 13 exports to described first pad by described
11 and described chip 20 second pin 22 transmission closedown voltage end signal VGL can not lead to
It is unidirectionally controlled unit 30 described in crossing and described electrostatic protection device 13 exports to described second pad
12；When described array base palte test cell 10 works, described in be unidirectionally controlled unit 30 and turn on,
Described first pad 11 is unidirectionally controlled list described in being passed through by the cut-in voltage end signal VGH received
Unit 30 and described electrostatic protection device 13 are transferred to the first pin 21 of described chip 20 and described
Second pad 12 is unidirectionally controlled unit 30 described in being passed through by the closedown voltage end signal VGL received
And described electrostatic protection device 13 is transferred to the second pin 22 of described chip 20.
In the present embodiment, it is unidirectionally controlled unit 30 described in and includes the first gate-controlled switch T1 and second
Gate-controlled switch T2, described first and second gate-controlled switch T1, T2 respectively include control end, first
End and the second end, described first gate-controlled switch T1 controls end and described first gate-controlled switch T1's
First end is connected and is connected to the first pin 21 of described chip 20, described first gate-controlled switch T1
The second end be connected to a pin of described electrostatic protection device 13, described second gate-controlled switch
The end that controls of T2 is connected with first end of described second gate-controlled switch T2 and is connected to described chip 20
The second pin 22, second end of described second gate-controlled switch T2 is connected to described electrostatic protector
One pin of part 13, described first gate-controlled switch T1 is N-type TFT, described second
Gate-controlled switch T2 is P-type TFT, described first switch the control end of T1, the first end and
Grid, source electrode and the drain electrode of the second end corresponding described N-type TFT respectively, described second opens
The control end of pass T2, the first end and the grid of the second end corresponding described P-type TFT of difference,
Source electrode and drain electrode.
Specifically, this row tester substrate unit 10 described also includes some 3rd pads 16, each
The corresponding pin connecting described electrostatic protection device 13 of 3rd pad 16, for showing for pixel
Show that (AA district) territory, district and turntable driving region (GOA district) provide signal.Specifically, described
Some 3rd pads include five, in other embodiments, can be arranged as required to the described 3rd
The quantity of pad.
Refer to Fig. 3, be the present invention array base palte test circuit first embodiment in unidirectional control
The equivalent circuit diagram of unit processed.The first and of unit 30 it is unidirectionally controlled described in as it is shown on figure 3,
Two gate-controlled switch T1, T2 are equivalent to two oppositely arranged first and second diode D1, D2,
First pin 21 of the negative electrode described chip 20 of connection of described first diode D1, described first
The anode of diode D1 connects a pin of described electrostatic protection device 13, described two or two pole
The anode of pipe D2 connects the second pin 22 of described chip 20, the moon of described second diode D2
Pole connects a pin of described electrostatic protection device 13.In the described first or described 2nd 2 pole
The when of pipe D1, D2 work, described first or second diode D1, D2 has voltage drop
Vth, therefore described array base palte test cell 10 first and two on pad 11,12 additional
During described cut-in voltage end signal VGH and described closedown voltage end signal VGL, need plus institute
State voltage drop Vth, to ensure to be supplied to described cut-in voltage end signal VGH and the institute of described panel
State closedown voltage end signal VGL and can meet the normal work requirements of described panel.
The operation principle of the circuit of the present embodiment is as follows: when described chip 20 works, because of
It is equivalent to described first diode D1, described second gate-controlled switch for described first gate-controlled switch T1
T2 is equivalent to described second diode D2, be i.e. equivalent to described first and second gate-controlled switch T1,
T2 is turned off, the described cut-in voltage end signal VGH and described of the most described chip 20 output
Close voltage end signal VGL and all can not pass through described first and second gate-controlled switch T1, T2 and institute
State first and second weldering that electrostatic protection device 13 is transferred in described array base palte test cell 10
Dish 11,12, thus avoid described cut-in voltage end signal VGH and described closedown voltage end signal
VGL is exposed when described chip 20 works causes shadow to the signal in described chip 20 in atmosphere
Ring；When described array base palte test cell 10 works, because described first gate-controlled switch T1 etc.
Imitate and be equivalent to described second diode in described first diode D1, described second gate-controlled switch T2
D2, is i.e. equivalent to described first and second gate-controlled switch T1, T2 and is both turned on, the most described array
The cut-in voltage end signal that first and second pad 11,12 of tester substrate unit 10 receives
VGH and close voltage end signal VGL by described electrostatic protection device 13 and described first and
Second gate-controlled switch T1, T2 is transferred in described panel, so that described panel normally works.
Refer to Fig. 4, be the circuit diagram of the second embodiment of the array base palte test circuit of the present invention.
Second embodiment of described array base palte test circuit is in the difference of above-mentioned first embodiment
In: described in be unidirectionally controlled unit 30 and include the first gate-controlled switch T1 and the second gate-controlled switch T2,
Described first and second gate-controlled switch T1, T2 include controlling end, the first end and the second end respectively,
The end that controls of described first gate-controlled switch T1 is connected also with first end of described first gate-controlled switch T1
Being connected to the first pin 21 of described chip 20, second end of described first gate-controlled switch T1 connects
One pin of described electrostatic protection device 13, first end of described second gate-controlled switch T2 connects
Second pin 22 of described chip 20, the control end and described second of described second gate-controlled switch T2
Second end of gate-controlled switch T2 is connected and is connected to a pin of described electrostatic protection device 13,
Described first and second gate-controlled switch T1, T2 are N-type TFT, described first and
The two switch control ends of T1, T2, the first end and the second end corresponding described N-type film crystal respectively
The grid of pipe, source electrode and drain electrode.
Refer to Fig. 5, be the present invention this row substrate test circuit the second embodiment in unidirectional control
The equivalent circuit diagram of unit 30 processed.Be unidirectionally controlled described in as it is shown in figure 5, unit 30 first and
Second gate-controlled switch T1, T2 is equivalent to two oppositely arranged first and second diode D1, D2,
First pin 21 of the negative electrode described chip 20 of connection of described first diode D1, described first
The anode of diode D1 connects a pin of described electrostatic protection device 13, described two or two pole
The anode of pipe D2 connects the second pin 22 of described chip 20, the moon of described second diode D2
Pole connects a pin of described electrostatic protection device 13.In the described first or described 2nd 2 pole
The when of pipe D1, D2 work, described first or second diode D1, D2 has voltage drop
Vth, therefore on first and second pad 11,12 of described array base palte test cell 10 outside
When adding described cut-in voltage end signal VGH and described closedown voltage end signal VGL, need to add
Described voltage drop Vth, with ensure be supplied to described panel described cut-in voltage end signal VGH and
Described closedown voltage end signal VGL can meet the normal work requirements of described panel.
The operation principle of the circuit of the present embodiment is as follows: when described chip 20 works, because of
It is equivalent to described first diode D1, described second gate-controlled switch for described first gate-controlled switch T1
T2 is equivalent to described second diode D2, be i.e. equivalent to described first and second gate-controlled switch T1,
T2 is turned off, the described cut-in voltage end signal VGH and described of the most described chip 20 output
Close voltage end signal VGL and all can not pass through described first and second gate-controlled switch T1, T2 and institute
State first and second weldering that electrostatic protection device 13 is transferred in described array base palte test cell 10
Dish 11,12, thus avoid described cut-in voltage end signal VGH and described closedown voltage end signal
VGL is exposed when described chip 20 works causes shadow to the signal in described chip 20 in atmosphere
Ring；When described array base palte test cell 10 works, because described first gate-controlled switch T1 etc.
Imitate and be equivalent to described second diode in described first diode D1, described second gate-controlled switch T2
D2, is i.e. equivalent to described first and second gate-controlled switch T1, T2 and is both turned on, the most described array
The cut-in voltage end signal that first and second pad 11,12 of tester substrate unit 10 receives
VGH and close voltage end signal VGL by described electrostatic protection device 13 and described first and
Second gate-controlled switch T1, T2 is transferred in described panel, so that described panel normally works.
Refer to Fig. 6, be the circuit diagram of the 3rd embodiment of the array base palte test circuit of the present invention.
3rd embodiment of described array base palte test circuit is in the difference of above-mentioned first embodiment
The 4th pad 14 and the 5th pad 15 is also included in: described array base palte test circuit, described the
Four pads 14 connect the first pin 21 of described chip 20, are used for transmitting described cut-in voltage end letter
Number VGH, described 5th pad 15 connects the second pin 22 of described chip 20, is used for transmitting
Described closedown voltage end signal VGL, described 4th and the 5th pad 14,15 covers insulant,
Prevent the described cut-in voltage end signal VGH when not using described 4th and the 5th pad 14,15
And described closedown voltage end signal VGL is exposed in atmosphere, and needs use the described 4th and
5th pad 14,15 measures described cut-in voltage end signal VGH and described closedown voltage end letter
During number VGL, only by external force, the insulant covered on described 4th and the 5th pad need to be gone
Except.
Refer to Fig. 7, be the circuit diagram of the 4th embodiment of the array base palte test circuit of the present invention.
4th embodiment of described array base palte test circuit is in the difference of above-mentioned second embodiment
The 4th pad and the 5th pad 14,15 is also included in: described array base palte test circuit, described the
Four pads 14 connect the first pin 21 of described chip 20, are used for transmitting described cut-in voltage end letter
Number VGH, described 5th pad 15 connects the second pin 22 of described chip 20, is used for transmitting
Described closedown voltage end signal VGL, described 4th and the 5th pad 14,15 covers insulant,
Prevent the described cut-in voltage end signal VGH when not using described 4th and the 5th pad 14,15
And described closedown voltage end signal VGL is exposed in atmosphere, and needs use the described 4th and
5th pad 14,15 measures described cut-in voltage end signal VGH and described closedown voltage end letter
During number VGL, only by external force, the insulant covered on described 4th and the 5th pad need to be gone
Except.
Refer to Fig. 8, be the structural representation of a kind of display floater of the present invention.Described display floater
Test circuit including aforesaid array base palte, be arranged on the WOA district of the bottom of described display floater,
Described display floater also includes AA district, GOA district, Fanout district, WOA district, IC district, FPC
District.Wherein, array base palte test circuit is used for after array base palte completes, array substrate
Electrically test；AA district is for the display of pixel；GOA district, i.e. Gate On Array, uses
The gate drive signal of thin film transistor (TFT) TFT in producing panel；Fanout district for chip with
The cabling of AA district data wire connects；WOA district, i.e. Wire On Array, around panel
The connection of cabling；IC district, for the welding of chip, by chip drives panel internal circuit and thin film
Transistor TFT；FPC district, for the welding of flexible PCB, connects hands by flexible PCB
Mainboard.
Refer to Fig. 9, for the structural representation of a kind of flat display apparatus of the present invention.Described plane
Display device includes aforesaid array base palte test circuit and display floater, described flat display apparatus
In other devices and function identical with the device of existing flat display apparatus and function, at this no longer
Repeat.Wherein, described flat display apparatus is LCD or OLED.
Described array base palte test circuit pass through described in be unidirectionally controlled first and second of unit controlled
The on or off of switch so that when described chip operation, the cut-in voltage of described chip output
End signal and close voltage end signal will not be transferred to described array base palte test cell the 3rd and
4th pad, thus avoid described cut-in voltage end signal and described closedown voltage end signal exposed
In air, and when described array base palte test cell works, by described 3rd and the 4th pad
And described chip by cut-in voltage end signal and closes voltage end signal and be transferred to described panel, make institute
State panel normally to work, avoid the signal in chip is impacted with this, and then increase product
Resolve duration and reduce the stability of product.
The foregoing is only embodiments of the present invention, not thereby limit the patent model of the present invention
Enclosing, every equivalent structure utilizing description of the invention and accompanying drawing content to be made or equivalence flow process become
Change, or be directly or indirectly used in other relevant technical fields, be the most in like manner included in the present invention's
In scope of patent protection.
Claims (10)
1. an array base palte test circuit, it is characterised in that described array base palte test circuit bag
Include:
Chip, described chip includes that the first pin and the second pin, described first pin are used for transmitting
Cut-in voltage end signal, described second pin is used for transmitting closedown voltage end signal；
It is unidirectionally controlled unit, connects the first pin and second pin of described chip, be used for transmitting institute
State cut-in voltage end signal and described closedown voltage end signal；And
Array base palte test cell, described array base palte test cell include electrostatic protection device,
One pad and the second pad, described electrostatic protection device connect described in be unidirectionally controlled unit, described the
One pad and described second pad are connected respectively a pin of described electrostatic protection device, institute
Stating the first pad for transmitting cut-in voltage end signal, described second pad is used for transmitting closedown voltage
End signal；When described chip operation, described in be unidirectionally controlled unit cut-off, the first of described chip
The cut-in voltage end signal of pin transmission is unidirectionally controlled unit and described electrostatic guarantor described in can not passing through
Protect device to export to described first pad and the closedown voltage end of the second pin transmission of described chip
Signal is unidirectionally controlled unit and described electrostatic protection device exports to described described in can not passing through
Two pads；When described array base palte test cell works, described in be unidirectionally controlled unit conducting, institute
State the first pad the cut-in voltage end signal received is passed through described in be unidirectionally controlled unit and described
Electrostatic protection device is transferred to the first pin of described chip and described second pad and will receive
Close voltage end signal pass through described in be unidirectionally controlled unit and described electrostatic protection device is transferred to institute
State the second pin of chip.
Array base palte the most according to claim 1 test circuit, it is characterised in that described list
Including the first gate-controlled switch and the second gate-controlled switch to control unit, described first and second controlled is opened
Close and include respectively controlling end, the first end and the second end, the control end of described first gate-controlled switch and institute
State the first end of the first gate-controlled switch be connected and be connected to the first pin of described chip, described first
Second end of gate-controlled switch is connected to a pin of described electrostatic protection device, described second controlled
The end that controls of switch is connected with the first end of described second gate-controlled switch and is connected to described chip
Second pin, the second end of described second gate-controlled switch is connected to of described electrostatic protection device
Pin, described first gate-controlled switch is N-type TFT, and described second gate-controlled switch is p-type
Thin film transistor (TFT), control end, the first end and the second end corresponding described N respectively of described first switch
The grid of type thin film transistor (TFT), source electrode and drain electrode, the control end of described second switch, the first end and
Grid, source electrode and the drain electrode of the second end corresponding described P-type TFT respectively.
Array base palte the most according to claim 1 test circuit, it is characterised in that described list
Including the first gate-controlled switch and the second gate-controlled switch to control unit, described first and second controlled is opened
Close and include respectively controlling end, the first end and the second end, the control end of described first gate-controlled switch and institute
State the first end of the first gate-controlled switch be connected and be connected to the first pin of described chip, described first
Second end of gate-controlled switch connects a pin of described electrostatic protection device, and described second controlled opens
The first end closed connects the second pin of described chip, the control end of described second gate-controlled switch and institute
The second end stating the second gate-controlled switch is connected and is connected to a pin of described electrostatic protection device,
First and second gate-controlled switch described is N-type TFT, first and second switch described
Control end, the first end and the second end grid of corresponding described N-type TFT respectively, source electrode and
Drain electrode.
4. test circuit according to the array base palte described in claim 1 or 2 or 3, it is characterised in that
Described array base palte test cell also includes that some 3rd pads, each 3rd pad correspondence connect institute
State a pin of electrostatic protection device, for providing for picture element display area and turntable driving region
Signal.
Array base palte the most according to claim 4 test circuit, it is characterised in that described battle array
Row substrate test circuit also includes that the 4th pad and the 5th pad, described 4th pad connect described core
First pin of sheet, is used for transmitting described cut-in voltage end signal, and described 5th pad connects described
Second pin of chip, is used for transmitting described closedown voltage end signal, described 4th and the 5th pad
Upper covering insulant, when using the described 4th and removing during five pads and cover the described 4th and the
Insulant on five pads.
6. a display floater, it is characterised in that described display floater includes array base palte test electricity
Road, described array base palte test circuit includes:
Chip, described chip includes that the first pin and the second pin, described first pin are used for transmitting
Cut-in voltage end signal, described second pin is used for transmitting closedown voltage end signal；
It is unidirectionally controlled unit, connects the first pin and second pin of described chip, be used for transmitting institute
State cut-in voltage end signal and described closedown voltage end signal；And
Array base palte test cell, described array base palte test cell include electrostatic protection device,
One pad and the second pad, described electrostatic protection device connect described in be unidirectionally controlled unit, described the
One pad and described second pad are connected respectively a pin of described electrostatic protection device, institute
Stating the first pad for transmitting cut-in voltage end signal, described second pad is used for transmitting closedown voltage
End signal；When described chip operation, described in be unidirectionally controlled unit cut-off, the first of described chip
The cut-in voltage end signal of pin transmission is unidirectionally controlled unit and described electrostatic guarantor described in can not passing through
Protect device to export to described first pad and the closedown voltage end of the second pin transmission of described chip
Signal is unidirectionally controlled unit and described electrostatic protection device exports to described described in can not passing through
Two pads；When described array base palte test cell works, described in be unidirectionally controlled unit conducting, institute
State the first pad the cut-in voltage end signal received is passed through described in be unidirectionally controlled unit and described
Electrostatic protection device is transferred to the first pin of described chip and described second pad and will receive
Close voltage end signal pass through described in be unidirectionally controlled unit and described electrostatic protection device is transferred to institute
State the second pin of chip.
Display floater the most according to claim 6, it is characterised in that described in be unidirectionally controlled list
Unit includes that the first gate-controlled switch and the second gate-controlled switch, first and second gate-controlled switch described wrap respectively
Including control end, the first end and the second end, the control end of described first gate-controlled switch and described first can
First end of control switch is connected and is connected to the first pin of described chip, described first gate-controlled switch
The second end be connected to a pin of described electrostatic protection device, the control of described second gate-controlled switch
End processed is connected with the first end of described second gate-controlled switch and is connected to the second pin of described chip,
Second end of described second gate-controlled switch is connected to a pin of described electrostatic protection device, described
First gate-controlled switch is N-type TFT, and described second gate-controlled switch is P-type TFT,
Control end, the first end and the second end corresponding described N-type TFT respectively of described first switch
Grid, source electrode and drain electrode, the control end of described second switch, the first end and the second end are the most right
Answer the grid of described P-type TFT, source electrode and drain electrode.
Display floater the most according to claim 6, it is characterised in that described in be unidirectionally controlled list
Unit includes that the first gate-controlled switch and the second gate-controlled switch, first and second gate-controlled switch described wrap respectively
Including control end, the first end and the second end, the control end of described first gate-controlled switch and described first can
First end of control switch is connected and is connected to the first pin of described chip, described first gate-controlled switch
Second end connect described electrostatic protection device a pin, the first of described second gate-controlled switch
End connects the second pin of described chip, and the control end of described second gate-controlled switch and described second can
Second end of control switch is connected and is connected to a pin of described electrostatic protection device, and described first
And second gate-controlled switch be N-type TFT, the control end of first and second switch described,
Grid, source electrode and the drain electrode of the first end and the second end corresponding described N-type TFT respectively.
9. according to the display floater described in claim 6 or 7 or 8, it is characterised in that described battle array
Row tester substrate unit also includes that some 3rd pads, each 3rd pad correspondence connect described electrostatic
One pin of protection device, for providing signal for picture element display area and turntable driving region,
Described array base palte test circuit also includes that the 4th pad and the 5th pad, described 4th pad connect
First pin of described chip, is used for transmitting described cut-in voltage end signal, and described 5th pad is even
Connect the second pin of described chip, be used for transmitting described closedown voltage end signal, the described 4th and
Insulant is covered, when using the described 4th and removing during five pads and cover described the on five pads
Insulant on four and the 5th pad.
10. a flat display apparatus, it is characterised in that described flat display apparatus includes such as power
Profit requires the arbitrary described array base palte test circuit of 1-5.
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