CN113643636A - Test circuit of display panel and display device - Google Patents
Test circuit of display panel and display device Download PDFInfo
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- CN113643636A CN113643636A CN202111194931.6A CN202111194931A CN113643636A CN 113643636 A CN113643636 A CN 113643636A CN 202111194931 A CN202111194931 A CN 202111194931A CN 113643636 A CN113643636 A CN 113643636A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/1306—Details
- G02F1/1309—Repairing; Testing
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Abstract
The application discloses display panel's test circuit and display device, test circuit includes: the testing device comprises a plurality of testing wires, a plurality of first active switches and a protection circuit, wherein the testing wires comprise a high-level signal testing wire, a low-level signal testing wire and at least one testing signal wire; the first active switch controls the connection and disconnection of the test signal line, the low-level signal test line and the high-level signal test line; the high-level signal test line is also connected with the control end of each first active switch; the protection circuit comprises a control signal input end and a control signal output end, the control signal input end is respectively connected with the high-level signal wiring and the low-level signal wiring, and the control signal output end is connected with the control end of each first active switch; when the display panel works normally, the protection circuit receives a low level signal output control signal on the low level signal wiring to control the first active switch to be switched off. This application is through above-mentioned scheme to the solution improves the problem of test wiring short circuit.
Description
Technical Field
The application relates to the technical field of display, in particular to a test circuit of a display panel and a display device.
Background
Flat panel displays are the mainstream displays, and among them, liquid crystal displays are widely used in electronic products such as computer screens, flat panel televisions, mobile phones, etc. because of their advantages of light weight and low power consumption. The liquid crystal display comprises a liquid crystal display panel, a backlight module, an optical film, a rubber frame and a conductive adhesive tape arranged on the side face of the display panel.
Generally, a liquid crystal display panel includes a display area and a non-display area around the display area, the non-display area is provided with a plurality of test traces, and in order to test the circuit conduction condition of each liquid crystal display panel on a large display mother board, test pads of all the liquid crystal display panels on the large display mother board are generally connected together through the test traces for testing. However, after the large display mother board is cut, the test trace is exposed in the air from the side of the liquid crystal display panel, and during normal display, because the internal circuit is directly or indirectly connected with the test trace, the exposed test trace has electrical property, and may contact with an external ground terminal to cause a short circuit problem, thereby affecting the display effect of the display panel.
Disclosure of Invention
The application aims to provide a test wire of a display panel and a display device so as to solve the problem of short circuit of the test wire.
The application discloses display panel's test circuit, display panel includes that high level signal walks line and low level signal walks the line, high level signal walk the line with low level signal walks the line and does display panel's drive circuit, test circuit includes: the testing device comprises a plurality of testing wires, a plurality of first active switches and a protection circuit; the plurality of test wires comprise a high-level signal test wire, a low-level signal test wire and at least one test signal wire, the plurality of first active switches are arranged in a one-to-one correspondence mode with the test wires, and the first active switches control the connection and disconnection of the test signal wires, the low-level signal test wire and the high-level signal test wire; the low level signal routing is connected with the low level signal testing line through the first active switch; the high-level signal routing is connected with the high-level signal testing line through a second active switch; the high-level signal test line is also connected with the control end of each first active switch; the protection circuit comprises a control signal input end and a control signal output end, the control signal input end is respectively connected with the high-level signal wiring and the low-level signal wiring, and the control signal output end is connected with the control end of each first active switch; and when the display panel works normally, the protection circuit receives the low level signal output control signal on the low level signal wiring to control the first active switch to be switched off.
Optionally, the plurality of test traces are exposed from the side surface of the display panel respectively.
Optionally, the high-level signal trace is a gate turn-on voltage trace, the high-level signal test line is a gate turn-on voltage test line, the low-level signal trace is a gate turn-off voltage trace, and the low-level signal test line is a gate turn-off voltage test line.
Optionally, the exposed position corresponding to the test trace is a test input end, and the control ends of the plurality of first active switches are connected to the test input end of the gate-on voltage test line; when the plurality of first active switches are in a display panel testing stage, receiving a grid starting voltage signal on the grid starting voltage testing line to control the first active switches to be conducted; and the protection circuit does not output a control signal to the control end of the first active switch in the display panel testing stage.
Optionally, the protection circuit includes a second active switch and a third active switch, and an input end and a control end of the second active switch are connected to the gate-on voltage trace; the output end of the second active switch is connected with the test input end of the grid turn-off voltage test line; the input end of the third active switch is connected with the grid turn-off voltage wiring, the control end of the third active switch is connected with the output end of the second active switch, and the output end of the third active switch is connected with the control end of the first active switch; when the display panel is in a test stage, the grid cut-off voltage signal on the grid cut-off voltage test line controls the third active switch to be turned off; when the display panel works normally, the grid opening voltage signal on the grid opening voltage wire controls the third active switch to be switched on, and the third active switch receives the grid closing voltage signal on the grid closing voltage wire and controls the first active switch to be switched off.
Optionally, the protection circuit further includes a fourth active switch, a control end of the fourth active switch is connected to the test input end of the gate-on voltage test line, and a control end of the third active switch is connected to the test input end of the gate-off voltage test line through the fourth active switch.
Optionally, the test signal line includes a frame scanning start signal test line, a clock signal test line, and a reset signal test line.
Optionally, the first active switch, the second active switch, the third active switch, and the fourth active switch are respectively N-type thin film transistors.
Optionally, in a test stage of the display panel, the test input end of the gate-on voltage test line and the test input end of the gate-off voltage test line respectively provide the gate-on voltage signal and the gate-off voltage signal; when the display panel works normally, the test input end of the grid opening voltage test line and the test input end of the grid closing voltage test line do not provide the grid opening voltage signal and the grid closing voltage signal.
The application also discloses a display device, including electrically conductive sticky tape and display panel, be provided with the test circuit like foretell display panel on the display panel, wherein, electrically conductive sticky tape is used for covering many test and walks the exposed position department of line.
According to the display panel testing method and device, the protection circuit is respectively connected with the high-level signal wiring and the low-level signal wiring, the high-level signal on the high-level signal testing line is used for controlling the conduction of the testing wiring in the testing stage of the display panel, and the protection circuit is used for controlling the disconnection of the testing wiring in the normal working process of the display panel; under the condition that the test is not influenced in the test stage, when the display panel works normally, the test wire does not carry charges at the end close to the exposed part after passing through the protection circuit and the first active switch, and the problems of short circuit, static electricity release and the like at the exposed part of the test wire can be prevented.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
FIG. 1 is a schematic diagram of a display motherboard according to a first embodiment of the present application;
Fig. 2 is a schematic diagram of a test circuit of a display panel according to a first embodiment of the present application;
FIG. 3 is a schematic diagram of a testing circuit of a display panel according to a second embodiment of the present application;
fig. 4 is a schematic diagram of a display device according to a third embodiment of the present application.
Wherein, 1, a display mother board; 2. cutting a line; 3. testing a common line; 10. a display panel; 11. a gate turn-on voltage trace; 12. a gate turn-off voltage trace; 100. a test circuit; 110. testing the wiring; 111. a gate turn-on voltage test line; 112. a gate turn-off voltage test line; 113. a test signal line; 130. a first active switch; 140. a protection circuit; 142. a second active switch; 151. a third active switch; 152. a fourth active switch; 200. a display device; 201. an electrically conductive tape.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The present application is described in detail below with reference to the figures and alternative embodiments.
The first embodiment is as follows:
As shown in fig. 1, as a first embodiment of the present application, a schematic plan view of a display mother board is disclosed, where the display mother board 1 includes a plurality of uncut display panels 10, the display mother board 1 is provided with a plurality of cutting lines 2 along edges of the uncut display panels 10, the display mother board 1 is provided with test ends, the test traces 110 of each uncut display panel 10 are respectively connected to the test ends (not shown in the figure), and are exposed at positions intersecting with the corresponding cutting lines 2 after being cut, specifically, the display mother board 1 is further provided with a plurality of test common lines 3, each display panel 10 is provided with a plurality of test traces 110, and the corresponding test traces 110 are respectively connected to the test common lines 3 in a one-to-one correspondence manner and are connected to the test ends through the test common lines 3. The large display mother board 1 is further provided with a plurality of cutting lines 2, the display panel 10 can be cut from the large display mother board 1 by cutting along the plurality of cutting lines 2, and the test traces 110 are exposed on the side surface of the display panel 10 at the positions of the corresponding cutting lines 2.
As shown in fig. 2, a schematic diagram of a test circuit of a display panel according to a first embodiment of the present application is shown, and a test circuit of a display panel is disclosed, in which the display panel 10 includes a high-level signal trace and a low-level signal trace, and the high-level signal trace and the low-level signal trace are a driving circuit of the display panel 10; the test circuit 100 includes: a plurality of test traces 110, a plurality of first active switches 130, and a protection circuit 140; the plurality of test traces 110 include a high-level signal test line, a low-level signal test line and at least one test signal line 113, and a plurality of first active switches 130, which are arranged in a one-to-one correspondence with the test traces 110, wherein the first active switches 130 control the conduction and the disconnection of the test signal lines 113, the low-level signal test line and the high-level signal test line; the low-level signal trace is connected with the low-level signal test line through one of the first active switches 130; the high-level signal trace is connected with the high-level signal test line through another first active switch 130; the high-level signal test line is further connected to a control end of each of the first active switches 130; the protection circuit 140 includes a control signal input terminal and a control signal output terminal, the control signal input terminal is connected to the high level signal trace and the low level signal trace, respectively, and the control signal output terminal is connected to the control terminal of each of the first active switches 130; when the display panel normally works, the protection circuit 140 receives the low level signal on the low level signal trace and outputs the control signal to control the first active switch to be turned off.
According to the application, the protection circuit 140 is respectively connected with the high-level signal wiring and the low-level signal wiring, so that the conduction of the test wiring 110 is controlled through a high-level signal on a high-level signal test line in a test stage of the display panel 10, and the disconnection of the test wiring 110 is controlled through a high-level signal and a low-level signal on the high-level signal wiring and the low-level signal wiring when the display panel 10 normally works; under the condition that the test is not affected in the test stage, when the display panel 10 normally works, the test trace 110 has no charge at the end near the exposed portion after passing through the protection circuit 140 and the first active switch, so as to prevent the problems of short circuit at the exposed portion of the test trace 110 and ESD (Electro-Static discharge) and the like.
It should be noted that, the high-level signal traces and the low-level signal traces are connected to the driving circuit of the display panel 10, that is, when the display panel displays, signals provided by the circuit board are transmitted to other circuits, such as the driving circuit on the display panel, along the high-level signal traces and the low-level signal traces. The high-level signal test line and the low-level signal test line are used for providing test signals for the display panel through the high-level signal test line and the low-level signal test line by an external test interface such as a probe in the test process, but the signals are not transmitted through the high-level signal test line and the low-level signal test line any more in the normal display process. Generally, the test trace 110 is connected to the internal circuit, and during normal display, there is a charge on the test trace 110. A core idea of the present application is to turn off all the first active switches 130 when the in-plane low level signal is displayed on the display panel 10, but in the test phase, the low level signal does not turn off the first active switches 130, but turns on the first active switches 130 by the high level signal, so that the test signal can be transmitted to the internal circuit of the display panel 10 through the first active switches 130.
In particular, the high level signal and the low level signal used in the present application are a VGH signal (i.e., a gate-on voltage signal) and a VGL signal (i.e., a gate-off voltage signal), which are generally high and low levels of a scan signal of a display panel, and are themselves used to control the on and off of the active switches of the pixels of the display panel. The display panel 10 includes a gate-on voltage trace 11 and a gate-off voltage trace 12, the plurality of test traces 110 includes a gate-on voltage test line 111, a gate-off voltage test line 112 and at least one test signal line 113, the gate-on voltage trace 11 is connected to the gate-on voltage test line 111, and the gate-off voltage trace 12 is connected to the gate-off voltage test line 112; the plurality of first active switches 130 are arranged in one-to-one correspondence with the test signal line 113, the gate turn-off voltage test line 112, and the gate turn-on voltage test line 111, wherein the gate turn-on voltage trace 11 is connected to the gate turn-on voltage test line 111 through one of the first active switches 130, the gate turn-off voltage trace 12 is connected to the gate turn-off voltage test line 112 through another one of the first active switches 130, and the first active switch 130 controls the turn-on and turn-off of the test signal line 113, the gate turn-off voltage test line 112, and the gate turn-on voltage test line 111; the protection circuit 140 includes a control signal input terminal and a control signal output terminal, the control signal input terminal is respectively connected to the gate-on voltage trace and the gate-off voltage trace, and the control signal output terminal is connected to the control terminal of each of the first active switches 130; when the display panel normally works, the protection circuit 140 receives the low level signal on the low level signal trace and outputs the control signal to control the first active switch to be turned off. The grid opening voltage signal is a grid opening voltage and is a high-level signal; the gate-off voltage is a low level signal, and the first active switch 130 of the present application is turned on by the gate-on voltage signal and remains turned off by the gate-off voltage signal.
It should be noted that the gate-off voltage test line 112 is also connected through a first active switch 130, and in the test phase, the first active switch 130 is controlled to be turned on by the gate-on voltage signal, so as to transmit the gate-off voltage signal and other test data signals to the inside of the display panel 10. The test signal lines 113 include a Start Vertical (STV) test line, a clock signal test line, a reset signal test line, and the like. Of course, only some of the test signals are listed here, and the test signals inputted in different stages of the test function, such as the lighting test, the RGB test, etc., may be different, but all of them are suitable for the test circuit 100 of the present application, and the first active switch 130 can be adjusted according to the number of the actual test signal lines 113, so as to keep each test signal line 113 controllable.
In a test stage, the gate-on voltage signal and the gate-off voltage signal also need to be input by the test wire 110, the input of the gate-off voltage signal is controlled by the first active switch 130, specifically, a position of the test wire 110 corresponding to the exposure is a test input end, and a control end of the first active switch 130 is connected to a test input end of the gate-on voltage test wire 111; when the plurality of first active switches are in a display panel testing stage, receiving a grid starting voltage signal on the grid starting voltage testing line to control the first active switches to be conducted; the protection circuit 140 does not output a control signal to the control terminal of the first active switch during the display panel testing stage.
Specifically, the control end and the input end of the first active switch 130 between the gate-on voltage test line and the gate-on voltage trace are connected, and in the test stage, the test input end of the gate-on voltage test line 111 inputs a gate-on voltage signal and then turns on the first active switch 130, and the gate-on voltage signal is transmitted to the gate-on voltage trace 11. When the display panel 10 normally works, the gate-on voltage trace 11 receives a gate-on voltage signal from the circuit board, and the gate-on voltage signal is isolated by the first active switch 130 at the position and is not transmitted to the test input terminal of the gate-on voltage test line 111, so that the exposed position of the gate-on voltage test line 111 does not carry charges.
Specifically, the protection circuit 140 includes a second active switch 142, and an input end and a control end of the second active switch 142 are connected to the gate-on voltage trace 11; the output end of the second active switch 142 is connected to the test input end of the gate turn-off voltage test line 112; the protection circuit 140 includes a third active switch 151, an input end of the third active switch 151 is connected to the gate off voltage trace 12, a control end of the third active switch 151 is connected to an output end of the second active switch 142, and an output end of the third active switch 151 is connected to a control end of the first active switch 130; during a testing stage of the display panel 10, the gate-off voltage signal on the gate-off voltage testing line 112 controls the third active switch 151 to turn off; when the display panel 10 normally works, the gate-on voltage signal on the gate-on voltage trace 11 controls the third active switch 151 to be turned on, the second control signal is the gate-off voltage signal on the gate-off voltage trace 12, and the third active switch 151 receives the gate-off voltage signal on the gate-off voltage trace 12 to control the first active switch 130 to be turned off.
In the testing stage of the display panel 10, the gate-on voltage signal output by the first active switch 130 on the gate-on voltage testing line controls the second active switch 142 to be turned on, and transmits the gate-on voltage signal to the control terminal of the third active switch 151, and at this time, the control terminal of the third active switch 151 is connected to the testing input terminal of the gate-off voltage testing line 112. Generally, the direct connection between the gate-on voltage signal and the gate-off voltage signal may cause a short circuit, which may result in a circuit being burned out, but at this time, the gate-on voltage signal and the gate-off voltage signal are connected through the second active switch 142, which may not cause a short circuit, and may cause the voltage at the control terminal of the third active switch 151 to be forced to be lowered by the gate-off voltage signal, so that the third active switch 151 is in an off state, and the gate-off voltage signal on the gate-off voltage trace 12 may not be transmitted to the control terminal of the first active switch 130 through the third active switch 151, so that the first active switch 130 is still controlled to be turned on by the gate-on voltage signal input from the test input terminal of the gate-on voltage test line 111. When the display panel 10 normally works, at this time, the test input ends of all the test traces 110 are not inputting the test signal, and the signals required by the display panel 10 are all provided by the circuit board, that is, the gate-on voltage signal on the gate-on voltage trace 11 and the gate-off voltage signal on the gate-off voltage trace 12 are both provided by the circuit board, the gate-on voltage signal on the gate-on voltage trace 11 turns on the second active switch 142 and transmits the gate-on voltage signal to the control end of the third active switch 151, at this time, although the control end of the third active switch 151 is connected to the test input end of the gate-off voltage test line 112, the test input end of the gate-off voltage test line 112 does not provide the gate-off voltage signal any more, so that the third active switch 151 is controlled to be turned on by the gate-on voltage signal, and the third active switch 151 transmits the gate-off voltage signal on the gate-off voltage 12 to the test input end of the first active switch 130 Although the control terminal of the first active switch 130 is further connected to the test input terminal of the gate-on voltage test terminal, the test input terminal of the gate-on voltage test terminal no longer provides the gate-on voltage signal, and therefore, the first active switch 130 is controlled to be turned off by the gate-off voltage signal, so that the test signal line 113 and the gate-off voltage test line 112 are in an off state, and therefore, no charge is present at the test input terminals of the test signal line 113 and the gate-off voltage test line 112.
As shown in fig. 3, the test circuit 100 of the display panel 10 of the second embodiment is a variation of the first embodiment, and discloses a test circuit 100 of the display panel 10, which is different from fig. 2 in that the protection circuit 140 further includes a fourth active switch 152, a control terminal of the fourth active switch 152 is connected to the test input terminal of the gate-on voltage test line 111, a control terminal of the third active switch 151 is connected to the test input terminal of the gate-off voltage test line 112 through the fourth active switch 152, and the structures of other parts are the same as those of the first embodiment and are not repeated here.
The difference between the modified embodiment and the previous embodiment is not great in the test phase, specifically, in the test phase, the control terminal of the fourth active switch 152 receives the gate-on voltage signal on the test input terminal of the gate-on voltage test line 111, and controls the fourth active switch 152 to be turned on, so that the control terminal of the third active switch 151 is connected to the gate-off voltage signal on the gate-off voltage test line 112. The difference is that in the normal operation stage of the display panel 10, since the test input terminal of the gate-on voltage test line 111 does not increase the gate-on voltage signal any more, the fourth active switch 152 is not turned on, so that in the test stage, the output terminal of the second active switch 142 is not connected to the test input terminal of the gate-off voltage test line 112 any more, thereby avoiding the influence of the gate-on voltage signal on the test input terminal on the circuit.
Specifically, the first active switch 130, the second active switch 142, the third active switch 151 and the fourth active switch 152 are N-type thin film transistors, respectively. Of course, the design of the corresponding circuit may also need to be changed for the P-type thin film transistor, and the changed scheme also belongs to the protection scope of the present application.
In another variant embodiment, the test signal lines 113 include a frame scanning start signal test line, a clock signal test line, a reset signal test line, and a gate-on voltage test line 111 and a gate-off voltage test line 112. That is, the first active switches 130 are respectively disposed on the test signal lines 113, and the control terminals of the first active switches 130 are respectively connected to the protection circuit 140. In this embodiment, the high-level signal trace is a VDD trace, the high-level signal test line is a VDD test line, the low-level signal trace is a VSS trace, and the low-level signal test line is a VSS test line. The circuit design is basically the same as that of the above embodiments, and is not described herein, but a resistor may be connected in series to prevent short circuit between the VDD test line and the VSS test line. In the above embodiment, a resistor may be disposed between the output terminal of the second active switch and the gate off voltage test line, and the control terminal of the third active switch is connected to a side of the resistor close to the test input terminal of the gate off voltage test line.
As shown in fig. 4, as a third embodiment of the present application, a display device is disclosed, where the display device 200 includes a conductive tape 201, a display panel 10, and the test circuit 100 of the display panel 10 of the first or second embodiment, where the conductive tape is used to cover the exposed positions of the plurality of test traces 110.
In this embodiment, the conductive tape is usually attached to the side surface of the display panel 10 for conducting the static electricity on the display panel 10 to the back plate or the ground terminal, and the test trace 110 is usually formed on the side surface of the display panel 10 as a result of the design of the motherboard, so that the test trace 110 is exposed. Specifically, in the display industry, the process flow is as follows: mother board processing → box forming → cutting for Q-panel → cutting for single display panel 10 → binding circuit board, etc → module manufacturing. In the current process flow, the last step is module manufacturing, which comprises a backlight assembly, a black conductive adhesive tape covering a circuit board and the like; however, in the process of lighting inspection, the screen is always blacked and cannot be lighted due to unknown reasons; after the Q-panel is cut into a single display panel 10, the test trace 110 used in the original test stage is broken, the plurality of test traces 110 form a "metal point" on the cross section, and the conductive tape playing the light leakage prevention and attachment functions is generally made of aluminum, so that the metal point formed after the test trace 110 is broken and the ground terminal on the circuit board form a short circuit through the black conductive tape, which results in the failure of the manufactured module to be normally lit. However, in this embodiment, the test circuit 100 of the first or second embodiment is designed such that the metal point of the test trace 110 at the exposed end does not have electric charges, and thus there is no short circuit.
It should be noted that the inventive concept of the present application can form many embodiments, but the present application has a limited space and cannot be listed one by one, so that, on the premise of no conflict, any combination between the above-described embodiments or technical features can form a new embodiment, and after the embodiments or technical features are combined, the original technical effect will be enhanced.
The technical solution of the present application can be widely applied to various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels, such as OLED (Organic Light-Emitting Diode) display panel, and the above solution can be applied thereto.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (10)
1. A test circuit of a display panel, the display panel includes a high level signal wire and a low level signal wire, the high level signal wire and the low level signal wire are connected with a driving circuit of the display panel, the test circuit includes:
the test device comprises a plurality of test wires, a plurality of test circuits and a plurality of test circuits, wherein the test wires comprise a high-level signal test wire, a low-level signal test wire and at least one test signal wire;
the first active switches are arranged in a one-to-one correspondence manner with the test wiring and control the conduction and the disconnection of the test signal line, the low-level signal test line and the high-level signal test line; the low level signal routing is connected with the low level signal testing line through the first active switch; the high-level signal routing is connected with the high-level signal testing line through a second active switch; the high-level signal test line is also connected with the control end of each first active switch;
the protection circuit comprises a control signal input end and a control signal output end, the control signal input end is respectively connected with the high-level signal wiring and the low-level signal wiring, and the control signal output end is connected with the control end of each first active switch;
And when the display panel works normally, the protection circuit receives the low level signal output control signal on the low level signal wiring to control the first active switch to be switched off.
2. The test circuit of claim 1, wherein the plurality of test traces are respectively exposed from the side surfaces of the display panel.
3. The test circuit of claim 1, wherein the high-level signal trace is a gate-on voltage trace, the high-level signal test line is a gate-on voltage test line, the low-level signal trace is a gate-off voltage trace, and the low-level signal test line is a gate-off voltage test line.
4. The test circuit of claim 3, wherein the corresponding exposed position of the test trace is a test input terminal, and the control terminals of the first active switches are connected to the test input terminal of the gate-on voltage test line;
when the first active switches are in a display panel testing stage, receiving a grid starting voltage signal on the grid starting voltage testing line to control the first active switches to be conducted; and the protection circuit does not output a control signal to the control end of the first active switch in the display panel testing stage.
5. The test circuit of claim 4, wherein the protection circuit comprises a second active switch and a third active switch, and an input terminal and a control terminal of the second active switch are connected to the gate-on voltage trace; the output end of the second active switch is connected with the test input end of the grid turn-off voltage test line;
the input end of the third active switch is connected with the grid turn-off voltage wiring, the control end of the third active switch is connected with the output end of the second active switch, and the output end of the third active switch is connected with the control end of the first active switch;
when the display panel is in a test stage, the grid cut-off voltage signal on the grid cut-off voltage test line controls the third active switch to be turned off; when the display panel works normally, the grid opening voltage signal on the grid opening voltage wire controls the third active switch to be switched on, and the third active switch receives the grid closing voltage signal on the grid closing voltage wire and controls the first active switch to be switched off.
6. The test circuit of claim 5, wherein the protection circuit further comprises a fourth active switch, a control terminal of the fourth active switch is connected to the test input terminal of the gate-on voltage test line, and a control terminal of the third active switch is connected to the test input terminal of the gate-off voltage test line through the fourth active switch.
7. The test circuit for a display panel according to claim 1, wherein the test signal line includes a frame scanning start signal test line, a clock signal test line, and a reset signal test line.
8. The testing circuit of claim 6, wherein the first active switch, the second active switch, the third active switch and the fourth active switch are N-type thin film transistors respectively.
9. The test circuit of claim 4, wherein during a display panel test phase, the test input terminal of the gate-on voltage test line and the test input terminal of the gate-off voltage test line respectively provide the gate-on voltage signal and the gate-off voltage signal; when the display panel works normally, the test input end of the grid opening voltage test line and the test input end of the grid closing voltage test line do not provide the grid opening voltage signal and the grid closing voltage signal.
10. A display device, comprising a conductive tape and a display panel, wherein the display panel is provided with a test circuit of the display panel according to any one of claims 1 to 9, and the conductive tape is used to cover the exposed positions of a plurality of test traces.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111194931.6A CN113643636B (en) | 2021-10-14 | 2021-10-14 | Test circuit of display panel and display device |
| GB2219817.0A GB2614817B (en) | 2021-10-14 | 2021-12-31 | Test circuit of display panel and display device |
| PCT/CN2021/143537 WO2023060780A1 (en) | 2021-10-14 | 2021-12-31 | Test circuit of display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111194931.6A CN113643636B (en) | 2021-10-14 | 2021-10-14 | Test circuit of display panel and display device |
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| CN113643636A true CN113643636A (en) | 2021-11-12 |
| CN113643636B CN113643636B (en) | 2022-01-07 |
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| CN (1) | CN113643636B (en) |
| WO (1) | WO2023060780A1 (en) |
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| GB2614817A (en) * | 2021-10-14 | 2023-07-19 | Hkc Corp Ltd | Test circuit of display panel and display device |
| WO2023216342A1 (en) * | 2022-05-13 | 2023-11-16 | 武汉华星光电半导体显示技术有限公司 | Display panel motherboard, test method for display panel motherboard, and display panel |
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Also Published As
| Publication number | Publication date |
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| CN113643636B (en) | 2022-01-07 |
| WO2023060780A1 (en) | 2023-04-20 |
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