KR20130054678A - Display device - Google Patents

Abstract

PURPOSE: A display device is provided to reduce manufacturing costs by directly connecting a probe of an automatic probe device to LOG wires without a resistor chip to distribute a load. CONSTITUTION: A data driving circuit supplies a data voltage to data lines of a display panel and successively a gate pulse to gate lines of the display panel. The gate pulse swings between a gate high voltage and a gate low voltage. The gate driving circuit includes a level shifter and a shift register. A bottom substrate of the display panel includes a plurality of electrostatic discharge circuits(34). The electrostatic discharge circuit is connected between LOG(Line On Glass) wires connected to input terminals of the shift register and adjacent LOG wires.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device capable of distributing overcurrent applied to a gate driving circuit.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. Liquid crystal displays can be miniaturized compared to cathode ray tubes (CRTs), which are applied to displays in portable information devices, office equipment, computers, etc., as well as televisions, and are rapidly replacing cathode ray tubes. The liquid crystal display forms a liquid crystal layer having anisotropic dielectric constants of upper and lower transparent substrates, and adjusts the intensity of an electric field formed in the liquid crystal layer according to video data to change the molecular arrangement of the liquid crystal material to display a desired image.

The driving circuit of the liquid crystal display device includes a data driving circuit for supplying a data voltage of video data to data lines of the display panel, and a gate pulse synchronized with the data voltage to the gate lines (or scan lines) of the display panel. It includes a gate driving circuit for supplying. The gate driving circuit may be directly formed on the lower substrate of the liquid crystal display panel at the same time as the TFT array by a gate in panel (GIP) process. The GIP type gate driving circuit includes a shift register formed in the display panel, and a level shifter for supplying driving signals to the shift register. The level shifter is mounted on a printed circuit board (hereinafter, referred to as a "PCB") electrically connected to the display panel.

After the lower substrate and the upper substrate of the liquid crystal display panel are bonded together, an inspection process of applying driving signals required for driving the liquid crystal display panel is performed. In this inspection process, necessary driving signals are supplied to the shift register and the data driving circuit formed on the display panel through an auto probe inspection device. The shift register receives driving signals through line on glass (LOG) lines formed on the lower substrate. In the inspection process, the drive signal voltage supplied to the shift register is a voltage swinging between a gate high voltage VGH of approximately 28V and a gate low voltage of -5V, similar to the normal driving condition. Therefore, a high voltage may be applied through the LOG lines during the inspection of the shift register so that overcurrent may flow through the LOG lines. In this case, as shown in FIG. 1, the insulation between the LOG lines burns, and insulation breakdown occurs, resulting in a defect such as shorting or opening of adjacent LOG lines.

In order to prevent the problem of bad LOG wiring connected to the shift register in the inspection process, a resistor chip for load shunt may be connected to a probe contacting the LOG wiring of an auto probe device. The resistor chip contains a number of resistors that limit the overcurrent in the current path between the probe and the LOG lines, reducing the overcurrent that can be fed into the LOG lines. However, a method of inspecting a liquid crystal display panel by connecting a resistor chip to an auto probe has the following problems.

First, a liquid crystal display panel has a different pitch between LOG lines according to models. For this reason, the load balancing resistor chip must be designed independently according to the resolution and model of the liquid crystal display panel.

Secondly, even when there is no defect in the liquid crystal display panel, if the resistance chip for load distribution is defective, the liquid crystal display panel may be determined as defective in the inspection process.

Third, an additional cost is generated due to the load balancing resistor chip, which increases the manufacturing cost of the liquid crystal display.

The present invention relates to a display device capable of distributing overcurrent supplied to a gate driving circuit.

A display device according to the present invention includes a display panel including a pixel array in which an input image is displayed; A data driving circuit supplying a data voltage to data lines of the display panel; And a gate driving circuit for sequentially supplying a gate pulse swinging between a gate high voltage and a gate low voltage to gate lines of the display panel.

The gate driving circuit may include a level shifter configured to level shift an input signal voltage to the gate high voltage and the gate low voltage to output start pulses and gate shift clocks, and to be formed on a lower substrate of the display panel to be input from the level shifter. And a shift register for sequentially shifting the gate pulse by shifting the start pulse to be in accordance with the gate shift clock.

The lower substrate of the display panel includes LOG lines connected to input terminals of the shift register and a plurality of electrostatic discharge circuits connected between adjacent LOG lines.

The present invention provides an electrostatic discharge circuit between adjacent LOG lines in LOG lines connected to a shift register. The display device of the present invention can distribute the overcurrent to neighboring LOG lines when an overcurrent flows into the LOG lines during the inspection process or during normal driving. As a result, the display device of the present invention can prevent the LOG wires from being shorted or disconnected due to overcurrent. Furthermore, the present invention can directly connect the probe of the auto probe device to the LOG wirings without the load distribution resistor chip, thereby eliminating the load distribution resistor chip.

1 is an image showing an insulating film between the LOG lines due to the overcurrent applied in the inspection process.
2 is a block diagram showing a display device according to an embodiment of the present invention.
3 is a block diagram illustrating a shift register configuration formed on a display panel.
4 is a diagram illustrating an example of an electrostatic discharge circuit formed between LOG lines.
5 is a plan view showing LOG wirings and an electrostatic discharge circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The display device of the present invention may be implemented by any one of a liquid crystal display (LCD) and an organic light emitting diode display (OLED). In the following embodiments, an example of a display device will be described with reference to a liquid crystal display device, but it should be noted that the present invention is not limited to the liquid crystal display device.

The liquid crystal display may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, or a reflective liquid crystal display. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The liquid crystal mode applicable to the present invention is a vertical electric field driving method such as twisted nematic (TN) mode and a vertical alignment (VA) mode, or a horizontal electric field driving such as IPS (In-Plane Switching) mode and FFS (Fringe Field Switching) mode. The method may be applied, and all other liquid crystal modes currently known may be applied.

2 and 3, the display device of the present invention includes a display panel 10, a data driving circuit, a GIP type gate driving circuit, a timing controller 22, and the like.

The display panel 10 includes a pixel array displaying an input image. The pixel array may be divided into a TFT array formed on a lower substrate, a color filter array formed on an upper substrate, and liquid crystal cells Clc. The TFT array includes data lines 11, gate lines (or scan lines 12) crossing the data lines 11, TFTs formed at intersections of the data lines and the gate lines, and pixels connected to the TFTs. An electrode 1, a storage capacitor Cst, and the like. A color filter array including a black matrix and a color filter is formed on the upper substrate of the display panel 10. The common electrode 2 may be formed on the lower substrate or the upper substrate. The liquid crystal cells Clc are driven by an electric field between the pixel electrode 1 supplied with the data voltage and the common electrode 2 supplied with the common voltage Vcom.

A polarizing plate having an optical axis orthogonal to each other is attached to the upper substrate and the lower substrate of the display panel 10, and an alignment layer for setting the pretilt angle of the liquid crystal is formed at an interface in contact with the liquid crystal layer. A spacer is disposed between the upper substrate and the lower substrate of the display panel 10 to maintain a cell gap of the liquid crystal layer.

The data driver circuit includes a plurality of source drive ICs 24 and 24a. The source drive ICs 24 and 24a receive digital video data RGB from the timing controller 22. The source drive ICs 24 and 24a convert the digital video data RGB into positive / negative analog data voltages in response to the source timing control signal from the timing controller 22, and then convert the data voltages into gate pulses. (Or scan pulses) are supplied to the data lines of the display panel 10. The source drive ICs 24 and 24a may be connected to the data lines 11 of the display panel 10 by a chip on glass (COG) process or a tape automated bonding (TAB) process. 2 shows an example in which the source drive ICs 24 and 24a are mounted in a tape carrier package (TCP). In FIG. 2, a printed circuit board 20 is connected to a lower substrate of the display panel 10 via TCP.

The gate driving circuit of the GIP type includes a level shifter 26 mounted on the PCB 20 and a shift register 30 formed on the lower substrate of the display panel 10.

The level shifter 26 receives a signal such as a start pulse ST, gate shift clocks GLCK, and a flicker signal FLK from the timing controller 22, and also receives a gate high voltage VGH and a gate low voltage. A driving voltage such as VGL is supplied. The start pulse ST, the gate shift clocks GCLK1 and the flicker signal FLK are signals swinging between 0V and 3.3V. The gate shift clocks GLCK1 to n are n phase clock signals having a predetermined phase difference. The gate high voltage VGH is a voltage equal to or greater than a threshold voltage of the TFTs formed in the TFT array of the display panel 10 and is about 28 V. The gate low voltage VGL is a voltage of the TFTs formed in the TFT array of the display panel 10. It is a voltage lower than the threshold voltage, and the voltage is about -5V.

The level shifter 26 level-shifts each of the start pulse ST and the gate shift clocks GLCK input from the timing controller 22 to the gate high voltage VGH and the gate low voltage VGL. Accordingly, each of the start pulse VST and the shift clocks CLK output from the level shifter 26 swings between the gate high voltage VGH and the gate low voltage VGL. The level shifter 26 may reduce the flicker by lowering the gate high voltage according to the flicker signal FLK to lower the kickback voltage ΔVp of the liquid crystal cell. The level shifter 26 may be applied to any of the known GIP type level shifters, and thus detailed circuit configurations and operation waveforms thereof will be omitted.

The output signals of the level shifter 26 are wires formed in the TCP of the first source drive IC 24a disposed on the upper left of the display panel 10, and LOG wires formed on the lower substrate of the display panel 10. 32 may be supplied to the shift register 30. The shift register 30 is directly formed on the lower substrate of the display panel 10 by a GIP process.

As shown in FIG. 3, the start register VST and the clock signals CLK1 to n are input to the shift register 30. The shift register 30 includes a plurality of stages ST1 to STn connected in cascade. The clock signals CLK1 to n are clock signals of n phase where the phases are sequentially delayed (n is a natural number of 2 or more). The shift register 30 has a gate swinging between the gate high voltage VGH and the gate low voltage VGL by shifting the start pulse VST input from the level shifter 26 according to the gate shift clocks CLK1 to n. Shift the pulses sequentially. The shift register 30 may be applied to any known GIP type shift register, and thus a detailed description thereof will be omitted.

Since the signals swinging between the gate high voltage VGH and the gate low voltage VGL are supplied to the LOG lines 32, overcurrent may be introduced into the LOG lines 32. In order to prevent short circuits or disconnection of the LOG lines 32 due to such overcurrent, the present invention provides an electrostatic discharge circuit 34 as shown in FIGS. 4 and 5 between the LOG lines connected to the input terminals of the shift register 30. ).

The electrostatic discharge circuit 34 is connected to all LOG wires 32a to 32g as shown in FIGS. 4 and 5, and is connected between neighboring LOG wires. The electrostatic discharge circuit 34 may be implemented by various known electrostatic discharge circuits. For example, the electrostatic discharge circuit 34 may include first to third TFTs T1, T2, and T3 as shown in FIG. 4. The first TFT T1 includes a gate electrode and a source electrode connected to the first LOG wiring 32a, a drain electrode connected to the drain electrode of the second TFT T2, and a gate electrode of the third TFT T3. The first TFT T1 turns on the third TFT T3 when an overcurrent flows in the first LOG wiring 32a. The overcurrent is much higher than the normal driving current flowing by the voltage difference between the gate high voltage VGH and the gate low voltage VGL applied to the LOG lines 32a to 32g during normal driving. When the same voltage is instantaneously applied to the LOG lines 32a to 32g, it means a current flowing through the LOG lines 32a to 32g. The second TFT T2 includes a gate electrode and a source electrode connected to the second LOG wiring 32b, and a drain electrode connected to the drain electrode of the first TFT T1 and the gate electrode of the third TFT T3. The second TFT T2 is turned on when an overcurrent flows in the second LOG wiring 32b to turn on the third TFT T3. The third TFT T3 is a gate electrode connected to the drain electrodes of the first and second TFTs T1 and T2, a source electrode connected to the first LOG wiring 32a, and a drain connected to the second LOG wiring 32b. An electrode. The third TFT T3 is turned on according to a rising gate voltage when at least one of the first and second TFTs T1 and T2 is turned on by overcurrent, so that the first and second LOG wirings ( By connecting the 32a and 32b, the overcurrent is distributed to the adjacent LOG lines 32a and 32b.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 20: PCB
22: Timing Controller 24a, 24: Source Drive IC
26: level shifter 30: shift register
32: LOG wiring 34: Electrostatic discharge circuit

Claims (3)

A display panel including a pixel array on which an input image is displayed;
A data driving circuit supplying a data voltage to data lines of the display panel; And
A gate driving circuit sequentially supplying a gate pulse swinging between a gate high voltage and a gate low voltage to gate lines of the display panel;
The gate driving circuit,
A level shifter for level shifting an input signal voltage to the gate high voltage and the gate low voltage to output start pulses and gate shift clocks;
A shift register formed on a lower substrate of the display panel to shift the gate pulse sequentially by shifting a start pulse input from the level shifter according to the gate shift clock,
And the lower substrate of the display panel includes LOG lines connected to input terminals of the shift register and a plurality of electrostatic discharge circuits connected between adjacent LOG lines. The method of claim 1,
And the electrostatic discharge circuit is connected between adjacent LOG wires in all LOG wires. The method of claim 1,
The electrostatic discharge circuit,
A first TFT connected to a first LOG wiring, a second TFT connected to a second LOG wiring adjacent to the first LOG wiring, and one or more of the first and second TFTs when the first LOG wiring is turned on; A third TFT connecting the second LOG wiring;
The first TFT includes a gate electrode and a source electrode connected to the first LOG wiring, a drain electrode connected to the drain electrode of the second TFT and the gate electrode of the third TFT,
The second TFT includes a gate electrode and a source electrode connected to the second LOG wiring, a drain electrode connected to the drain electrode of the first TFT and the gate electrode of the third TFT,
And the third TFT comprises a gate electrode connected to the drain electrodes of the first and second TFTs, a source electrode connected to the first LOG wiring, and a drain electrode connected to the second LOG wiring.

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