KR20170033934A - Large Area Liquid Crystal Display Having Narrow Bezel Structure - Google Patents

Abstract

The present invention relates to a large-size liquid crystal display device in which left and right bezel regions are minimized by arranging a vertical gate line within an array region. The liquid crystal display device according to the present invention includes horizontal gate lines, data lines, pixel regions, pixel electrodes and thin film transistors. The horizontal gate lines are horizontally disposed on the substrate. The data lines are vertically disposed on the substrate. The pixel regions are arranged in the form of (i, j) matrix due to the intersection structure of the data lines and the horizontal gate lines. The (1,1) thin film transistors are arranged in the (1,1) pixel region and connected to the (1,1) pixel electrode. The (1,2) thin film transistors are arranged in the (1,2) pixel region and connected to the (1,2) pixel electrode. The (2,2) thin film transistors are arranged in the (2,2) pixel region and connected to the (2,1) pixel electrode.

Description

[0001] The present invention relates to a large-sized liquid crystal display having a narrow bezel structure,

The present invention relates to a large-sized liquid crystal display device in which the right and left bezel regions are minimized by arranging the vertical gate lines in the array region. In particular, the present invention relates to a large-sized liquid crystal display device that implements a dot-inversion driving method in a column-type version driving method and minimizes left and right bezel areas.

The field of display devices has rapidly developed into a thin, light and large-area flat panel display (FPD) replacing a bulky cathode ray tube (CRT). The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting diode (OLED) display, and an electrophoretic display EPD). Among them, the liquid crystal display device displays an image by controlling the electric field applied to the liquid crystal molecules in accordance with the data voltage. A liquid crystal display device of an active matrix driving type displays a moving image by using a thin film transistor (hereinafter referred to as "TFT") as a switching element.

A liquid crystal display device includes a liquid crystal display panel, a backlight unit for irradiating light to the liquid crystal display panel, a source drive integrated circuit (IC) for supplying a data voltage to the data lines of the liquid crystal display panel, A gate drive IC for supplying gate pulses (or scan pulses) to the wirings (or scan wirings), a control circuit for controlling the ICs, and a light source driving circuit for driving the light source of the backlight unit.

1 is a schematic view showing the structure of a conventional liquid crystal display device. 1, a conventional liquid crystal display device includes a liquid crystal display panel (DPL), a source driving circuit 12 (or a source drive IC), and a timing controller 11 in which a pixel array 10 is formed . A backlight unit (not shown) for uniformly irradiating light to the liquid crystal display panel DPL may be disposed on the back surface of the liquid crystal display panel DPL.

The liquid crystal display panel DPL includes an upper glass substrate and a lower glass substrate opposed to each other with a liquid crystal layer interposed therebetween. A pixel array 10 is formed in the liquid crystal display panel DPL. The pixel array 10 includes liquid crystal cells Clc arranged in a matrix form by an intersection structure of data lines DL and gate lines GL to display video data. Data lines DL, gate lines GL, thin film transistors T, pixel electrodes of a liquid crystal cell Clc connected to the thin film transistor T, And a storage capacitor (Cst) connected to the pixel electrode of the cell. Each of the liquid crystal cells Clc of the pixel array 10 is driven by a voltage difference between a pixel electrode for charging a data voltage through the thin film transistor T and a common electrode to which a common voltage Vcom is applied, The image of the video data is displayed by adjusting the amount.

The source driver circuits 12 are mounted on a TCP (Tape Carrier Package) 15 and bonded to a lower glass substrate of a liquid crystal display panel by a TAB (Tape Automated Bonding) process. A source PCB (Printed Circuit Board) Respectively. The source driver circuits 12 may be bonded onto a lower glass substrate of a liquid crystal display panel by a COG (Chip On Glass) process. The data output channels of each of the source driving circuits 12 are connected to the data lines DL of the pixel array 10 at a ratio of 1: 1.

Each of the source driver circuits 12 receives digital video data from the timing controller 11. [ In response to the source timing control signal from the timing controller 11, the source driver circuits 12 convert the digital video data into positive / negative analog data voltages and output the data lines of the pixel array 10 through the output channels . The source driver circuits 12 supply data voltages of opposite polarities to neighboring data lines under the control of the timing controller 11 and supply the polarities of the data voltages supplied to the respective data lines to the same .

The gate driving circuits 13 sequentially supply gate pulses to the gate wirings of the pixel array in response to a gate timing control signal transmitted from the timing controller 11. [ The gate driver circuits 13 are mounted on the TCP and bonded to the lower glass substrate of the liquid crystal display panel by a TAB process or directly on the lower glass substrate by the GIP (Gate In Panel) . The gate drive circuits 13 may be disposed on one side of the pixel array 10 or on both sides of the pixel array 10 as shown in FIG.

The timing controller 11 supplies the digital video data input from the external system board to the source driver circuits 12. [ The timing controller 11 generates a source timing control signal for controlling the operation timing of the source driving circuits 12 and a gate timing control signal for controlling the operation timing of the gate driving circuit 13. The timing controller 11 is mounted on the control PCB 16. The control PCB 16 and the source PCB 14 are connected through a flexible circuit board 17 such as a flexible flat cable (FFC) or a flexible printed circuit (FPC).

Manufacturers of liquid crystal display devices have made various attempts to implement a narrow bezel. The coarse bezel technology minimizes the area of the bezel area where the image occupying the edge of the display panel is not displayed in order to relatively enlarge the size of the effective screen displayed on the display panel of the same size. A liquid crystal display device having a narrow bezel structure according to the related art will be described with reference to FIG. 2 is a schematic view showing a liquid crystal display device having a narrow bezel structure according to the related art.

Referring to FIG. 2, a liquid crystal display device having a narrow bezel structure according to the related art has basically the same structure as a general liquid crystal display device as shown in FIG. The difference is that the gate drive circuit 13 directly mounted on the left and / or right of the display panel DPL is not included in Fig.

That is, the liquid crystal display device of the narrow bezel structure includes the drive PCB 22 including both the source drive circuits 12 and the gate drive circuits 13. [ The source driver circuits 12 and the gate driver circuits 13 may be mounted together on a flexible circuit board such as a COF (Chip On Film). The input terminal of the COF is connected to the PCB 22, and the output terminal of the COF is connected to the lower substrate of the display panel DPL.

The display panel DPL includes a data line DL and a vertical gate line VGL extending in the vertical direction and a horizontal gate line GL extending in the horizontal direction. A pixel electrode for driving the thin film transistor T and the liquid crystal cell Clc is disposed in a pixel region defined by an intersection structure of the vertical interconnection and the horizontal interconnection.

The vertical gate wiring VGL is branched at the gate drive circuit 13 and extends to the display panel DPL. One vertical gate line (VGL) is connected one-to-one with one horizontal gate line (GL). 1 except that it further includes a vertical gate wiring VGL extending from a gate drive circuit 13 mounted on a drive PCB 22 disposed in the upper bezel region of the display panel DPL. The device and configuration are the same.

In the narrow-bezel liquid crystal display device according to the related art, since the vertical gate lines VGL are arranged in parallel adjacent to the data lines DL, they can affect neighboring pixels at the contacts connecting to the horizontal gate lines. For this reason, there is a problem that a luminance difference occurs and a streak is generated at a contact portion where the vertical gate wiring VGL and the horizontal gate wiring GL are connected, and the picture quality is deteriorated.

In addition, liquid crystal display devices are becoming increasingly popular. In driving the liquid crystal cell of the large liquid crystal display device, it is preferable to reverse the polarity of the driving voltage in order to prevent deterioration. The inversion method includes a column inversion method and a dot inversion method. In a large-sized liquid crystal display device, a dot-inversion method can not be used because of a problem of high heat generation and high power consumption. Therefore, in a large-sized liquid crystal display device, a version method of a column is inevitable. As the area becomes larger, a voltage difference due to a change in polarity becomes larger, resulting in a bad image quality in the form of a vertical stripe.

As described above, there is an increasing demand for a large-size liquid crystal display device, particularly a large-sized liquid crystal display device having a narrow-bezel structure. However, in order to provide a good display quality, a structural improvement is required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device and a liquid crystal display device which are designed to overcome the above problems by arranging a gate driving unit adjacent to a data driving unit in a vertical bezel area, Device. Another object of the present invention is to provide a narrow-bezel liquid crystal display device in which gate signals are provided using vertical gate lines, thereby minimizing the amount of left and right bezels occupied by the gate driver. It is still another object of the present invention to provide a liquid crystal display device in which data wiring is arranged in every two pixel columns and a vertical gate wiring is arranged in a column in which no data wiring is arranged, And a liquid crystal display device. It is still another object of the present invention to provide a liquid crystal display device which inverts a driving signal in a column-type version mode but is driven in a dot-inversion mode in a liquid crystal panel.

In order to achieve the above object, a liquid crystal display device according to the present invention includes horizontal gate lines, data lines, pixel regions, pixel electrodes, and thin film transistors. The horizontal gate lines proceed horizontally on the substrate. The data lines proceed in a vertical direction on the substrate. The pixel regions are arranged in an (i, j) matrix manner by the intersection structure of the data lines and the horizontal gate lines. Here, i and j are natural numbers. (1,1) pixel electrodes are arranged in the (1,1) pixel region. (1,2) pixel electrodes are arranged in the (1,2) pixel region. (2,1) pixel electrodes are arranged in the (2,1) pixel region. (2,2) pixel electrodes are arranged in the (2,2) pixel region. The (1,1) thin film transistor is disposed in the (1,1) pixel region and connected to the (1,1) pixel electrode. (1,2) thin film transistor is disposed in the (1,2) pixel region and is connected to the (1,2) pixel electrode. (2,1) thin film transistor is disposed in the (2,1) pixel region and is connected to the (2,2) pixel electrode. (2,2) thin film transistor is disposed in the (2,2) pixel region, and is connected to the (2,1) pixel electrode.

For example, the liquid crystal display device according to the present invention further includes a first horizontal connection electrode and a second horizontal connection electrode. The first horizontal connecting electrode extends from the (2,1) thin film transistor to the (2,2) pixel region and is connected to the (2,2) pixel electrode. The second horizontal connection electrode extends from the (2,2) thin film transistor to the (2,1) pixel region and is connected to the (2,1) pixel electrode.

For example, the liquid crystal display device according to the present invention further includes a first horizontal dummy electrode and a second horizontal dummy electrode. The first horizontal dummy electrode extends from the (1,1) thin film transistor to the (1,2) pixel region. The second horizontal dummy electrode extends from the (1,2) thin film transistor to the (1,1) pixel region.

For example, the dummy parasitic capacitance formed between the first horizontal dummy electrode and the second horizontal dummy electrode is substantially equal to the connection parasitic capacitance formed between the first horizontal connection electrode and the second horizontal connection electrode.

In one example, the data lines include a first column data line and a second column data line disposed between the first column pixel column and the second column pixel column.

In one example, the horizontal gate wirings include a first horizontal gate wiring and a second horizontal gate wiring. The liquid crystal display device according to the present invention further includes a first vertical gate wiring and a second vertical gate wiring. The first vertical gate wiring is disposed in the left column of the first column pixel column and connected to the first horizontal gate wiring. The second vertical gate wiring is disposed in the right column of the two column pixel column and connected to the second horizontal gate wiring.

For example, the liquid crystal display device according to the present invention further includes horizontal common wiring and vertical common wiring. The horizontal common wiring is arranged in parallel with the horizontal gate wirings. The vertical common wirings are arranged in parallel to the vertical gate wirings, overlapping with each other, and connected to the horizontal common wirings.

The liquid crystal display according to the present invention has a pixel region of 2x2 matrix as a basic unit, and two pairs of pixel electrodes are connected to a thin film transistor disposed in a pixel region of the pixel region. The remaining two pairs of pixel electrodes, And is connected to the thin film transistor disposed in the pixel region. Due to such a structure, even if a driving method which changes the polarity of the data voltage in the column-type version method is used, the liquid-crystal display panel can obtain the result that the data voltage changes in a dot-inversion manner. As a result, it is possible to solve the problem of image quality in the form of a vertical stripe generated in the version method of the column, and at the same time to overcome the problem of the invention in a large area and the increase in power consumption, which occur in dot- Further, by arranging the two data wirings in one column, the vertical gate wirings can be arranged so as not to be adjacent to the data wirings. Due to such a structure, it is possible to realize a liquid crystal display device with a narrow bezel structure in which image quality imbalance is eliminated even in a large-sized panel.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a structure of a liquid crystal display device according to a related art; FIG.
2 is a schematic view showing a liquid crystal display device having a narrow bezel structure according to the related art.
3 is a plan view showing a pixel array of a large liquid crystal display device having a narrow bezel structure according to the present invention.
4 is a plan enlarged view showing a pixel structure of a large liquid crystal display device having a narrow bezel structure according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, a detailed description of known technologies or configurations related to the present invention will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured. In addition, the component names used in the following description may be selected in consideration of easiness of specification, and may be different from the parts names of actual products.

Hereinafter, a large liquid crystal display device having a narrow bezel structure according to the present invention will be described with reference to FIGS. 3 is a plan view showing a pixel array of a large liquid crystal display device having a narrow bezel structure according to the present invention. 4 is a plan enlarged view showing a pixel structure of a large liquid crystal display device having a narrow bezel structure according to the present invention.

A schematic structure of a liquid crystal display device according to the present invention will be described with reference to FIG. In the liquid crystal display device according to the present invention, pixel regions arranged in a matrix manner on a substrate are defined. For example, it may have an (i, j) matrix array of i rows and j columns. Here, i and j are natural numbers.

The pixel regions are regions formed by crossing a plurality of wirings extending in the horizontal direction and a plurality of wirings extending in the vertical direction. For example, the horizontal wiring lines GL1, GL2, GL3, ..., horizontal common wiring lines CL are included in the wiring extending in the horizontal direction. The horizontal gate lines GL1, GL2, GL3, ... are arranged in the vertical direction at regular intervals. The horizontal common lines CL are arranged in parallel and adjacent to the horizontal gate lines GL1, GL2, GL3, ....

Vertical wiring lines VGL, VGL2, VGL3, ..., data lines DL1, DL2, DL3, DL4, ..., and vertical common wiring lines VCL, . The vertical gate wirings VGL1, VGL2, VGL3, ... are arranged in the horizontal direction, one for each of the two pixel region rows. The vertical common wirings VCL are arranged in parallel to overlap with the vertical gate wirings VGL1, VGL2, VGL3, .... The data lines DL1, DL2, DL3, DL4, ... are arranged in two between adjacent two vertical gate wirings. In particular, two data lines are arranged next to each other between two rows of pixel regions arranged between two adjacent vertical gate wirings.

Referring to FIG. 3, a first vertical gate line VGL1 is disposed on the left side of the first pixel column. In addition, one vertical vertical interconnect VCL is disposed so as to be parallel to the first vertical gate interconnect VGL1 with the insulating film therebetween. A first data line DL1 and a second data line DL2 are arranged in parallel between the first pixel column and the second pixel column. A second vertical gate line VGL2 and a vertical common line VCL are disposed on the right side of the second pixel column. A horizontal gate line GL1 and a horizontal common line CL are arranged at the lower side of the first pixel row. Thus, the pixel region is defined by the intersection structure of the vertical wiring and the horizontal wiring.

In each pixel region, the thin film transistors T11, T12, T21, T22, ... and the pixel electrodes PXL11, PXL12, PXL21, PXL22, ... are arranged one by one. The liquid crystal display according to the present invention has a structure in which pixel matrixes of 2x2 matrix type are repeatedly arranged. Accordingly, pixel regions having four matrix arrays of (1,1), (1,2), (2,1) and (2,2) will be mainly described in the (i, j) matrix method.

(1,1) thin film transistor T11 and (1,1) pixel electrode PXL11 are arranged in the (1,1) pixel region. (1,2) thin film transistor T12 and (1,2) pixel electrode PXL12 are arranged in the (1,2) pixel region. Similarly, (2,1) thin film transistor T21 and (2,1) pixel electrode PXL21 are arranged in the (2,1) pixel region. (2,2) thin film transistor T22 and (2,2) pixel electrode PXL22 are arranged in the (2,2) pixel region. However, the connection structure is different from the liquid crystal display device of the conventional structure.

For example, the (1,1) thin film transistor T11 is connected to the (1,1) pixel electrode PXL11, the (1,2) thin film transistor T12 is connected to the (1,2) Lt; / RTI > That is, the two pixel regions have a structure in which the thin film transistor of the pixel and its pixel electrode are connected to each other. However, the (2,1) thin film transistor T21 is connected to the (2,2) pixel electrode PXL22 and the (2,2) thin film transistor T22 is connected to the (2,1) do. That is, the remaining two pairs of pixel regions have a structure in which neighboring thin film transistors and their pixel electrodes are staggered.

In order to have such a connected structure, a first horizontal connection terminal (2) extending from the drain electrode of the (2,1) thin film transistor T21 to the (2,2) pixel region and connected to the pixel electrode (PXL22) (CT1). And a second horizontal connection terminal CT2 extending from the drain electrode of the (2,2) thin film transistor T22 to the (2,1) pixel region and connected to the (2,1) pixel electrode PXL21 .

In this way, by having a structure in which a 2x2 matrix is used as a basic unit, a pair of thin film transistors are connected to each other, and a pair of adjacent thin film transistors are connected to each other, thereby applying voltages of opposite polarities to neighboring data wires, A data voltage whose polarity is inverted in the vertical direction can be applied. For example, when a (+) polarity data voltage is applied to the first data line DL1 and a (-) polarity data voltage is applied to the second data line DL2, the (1,1) ) Polarity, the voltage of the (1, 2) pixel electrode is the voltage of the negative polarity, the voltage of the (2, 1) pixel electrode is the voltage of the negative polarity, . That is, a data voltage is applied in a version mode, which is an inverted column for each data line, but a liquid crystal display device can be driven in a dot-inversion mode for each pixel.

Thus, in realizing a large-sized liquid crystal display device, polarity bunching does not occur. This does not result in poor image quality with alternating bright and dark vertical lines. Further, in realizing a dot-in version, since a data voltage is applied in a column-type version method in practice, there is no problem of deterioration and power consumption increase in a large-sized liquid crystal display device.

The first vertical gate line VGL1 is connected to the first horizontal gate line GL1. And the second vertical gate wiring VGL2 is connected to the second horizontal gate wiring GL2. The third vertical gate line VGL3 is connected to the third horizontal gate line GL3. That is, the gate signals applied to the horizontal gate lines GL1, GL2, GL3, ... are received from the vertical gate lines VGL1, VGL2, VGL3,. As shown in the figure, these vertical gate wirings (VGL1, VGL2, VGL3, ....) are not disposed outside the substrate, but are arranged inside the display region. As a result, the bezel area around the display area can be minimized.

The vertical gate wirings VGL1, VGL2, VGL3, .... are not arranged for every pixel column but one for every two pixel columns. Also, the data lines DL1, DL2, DL3, DL4, ... are not arranged for every pixel column, but two are arranged for every two pixel columns. In particular, the vertical gate wirings VGL1, VGL2, VGL3, .... have a structure in which the data wirings DL1, DL2, DL3, DL4,. Therefore, in the pixel region where the vertical gate wirings VGL1, VGL2, VGL3, .... are connected to the horizontal gate wirings GL1, GL2, GL3, ..., It does not occur largely. Therefore, the image quality defect in which the connection point portions of the vertical gate wirings VGL1, VGL2, VGL3, .... and the horizontal gate wirings GL1, GL2, GL3, ... are particularly dark does not occur.

Hereinafter, a detailed structure of the liquid crystal display device according to the present invention will be described with reference to FIG. The basic structure is the same as in Fig. In FIG. 4, the structure in which the respective components are connected is shown in more detail.

A first horizontal gate line GL1 and a second horizontal gate line GL2 extending in the horizontal direction are arranged in parallel at regular intervals. On the upper sides of the respective gate wirings, horizontal common wirings (CL) are arranged one by one in parallel.

A first vertical gate line VGL1 extending in the vertical direction is disposed on the left side of the first pixel row. Further, vertical common wirings (VCL) overlapping the first vertical gate wirings (VGL1) with the insulating film therebetween and arranged in parallel are arranged one by one. In addition, the first data line DL1 and the second data line DL2 extending in the vertical direction are arranged in parallel between the first pixel line and the second pixel line.

(1,1) pixel electrode PXL11 is arranged in the (1,1) pixel region. In the horizontal electric field type liquid crystal display device, the pixel electrode PXL11 has a structure in which a plurality of line segments are arranged at regular intervals. Further, a (1,1) thin film transistor T11 is arranged in the (1,1) pixel region. The thin film transistor T11 is spaced apart from the gate electrode G which branches off from the first horizontal gate line GL1 and the source electrode S which branches off from the first data line DL1 and the source electrode S And a drain electrode D disposed thereon.

That is, the (1, 1) thin film transistor T11 connected to the first gate line GL1 and the first data line DL1 is arranged in the (1,1) pixel region and the (1, 1) pixel electrode PXL11. The (1,1) pixel electrode PXL11 is connected to the drain electrode D of the (1,1) thin film transistor T11 through the pixel contact hole PH. Hereinafter, the connection structure of the thin film transistor and the pixel electrode is basically the same, and a detailed description thereof will be omitted.

In addition, the (1, 2) thin film transistor T12 connected to the first gate wiring GL1 and the second data wiring DL2 is arranged in the (1,2) pixel region and the (1, 2) pixel electrode PXL12.

On the other hand, the (2, 1) thin film transistor T21 connected to the second gate wiring GL2 and the first data wiring DL1 is arranged in the (2,1) pixel region. However, it is connected to the (2, 2) pixel electrode PXL22 arranged in the neighboring (2,2) pixel region. For example, the first horizontal connecting electrode CT1 connected to the drain electrode of the (2, 1) thin film transistor T21 through the pixel contact hole PH is connected to the first data line DL1 and the second data line DL2 (2, 2) pixel region, and is connected to the (2, 2) pixel electrode PXL22.

The (2, 2) thin film transistor T22 connected to the second gate wiring GL2 and the second data wiring DL2 is arranged in the (2,2) pixel region. However, it is connected to the (2,1) pixel electrode PXL21 arranged in the neighboring (2,1) pixel region. For example, the second horizontal connection electrode CT2 connected to the drain electrode of the (2, 2) thin film transistor T22 through the pixel contact hole PH is connected to the second data line DL2 and the first data line DL1 (2, 1) pixel region, and is connected to the (2,1) pixel electrode PXL21.

Here, the first connection electrode CT1 and the second connection electrode CT2 are disposed adjacent to each other in parallel, and a parasitic capacitance may be generated therebetween. Therefore, it can be displayed darker than (1, 1) pixel area and (1, 2) pixel area in which parasitic capacitance is not generated. In order to solve this problem, it is preferable to make the same parasitic capacitance in the (1,1) pixel region and the (1,2) pixel region.

For example, a (1, 1) pixel region is divided into (1, 1) pixel electrodes PXL11 and (1,2) pixels It is preferable to dispose a first horizontal dummy electrode DT1 which is extended to the (1, 2) pixel electrode PXL12 and not connected to the pixel electrode PXL12. Further, in the (1,2) pixel region, the (1, 2) pixel electrode PXL12 is divided into (1, 1) pixel regions across the second data line DL2 and the first data line DL1 It is preferable to dispose a second horizontal dummy electrode DT2 which is extended and is not connected to the (1,1) pixel electrode PXL11.

In particular, it is preferable that the first horizontal dummy electrode DT1 and the second horizontal dummy electrode DT2 have the same interval and the same length as the first horizontal connecting electrode CT1 and the second horizontal connecting electrode CT2. The dummy parasitic capacitance formed between the first horizontal dummy electrode DT1 and the second horizontal dummy electrode DT2 is connected to the first horizontal connection electrode CT1 through the connection formed between the first horizontal connection electrode CT1 and the second horizontal connection electrode CT2 And becomes substantially equal to the parasitic capacitance. As a result, since the two pairs of pixel electrodes having an asymmetric connection structure have the same structure, image quality problems due to structural imbalance can be prevented.

It is preferable that the vertical gate wirings VGL1, VGL2, VGL3, ... are formed in the same layer as the data wirings DL1, DL2, DL3, DL4,. Therefore, the vertical gate wirings VGL1, VGL2, VGL3, ... are arranged in different layers with the gate insulating film interposed between the horizontal gate wirings GL1, GL2, GL3, .... In order to connect them, it is preferable to connect them to the gate connection terminal GLT through the gate contact hole GH. In particular, the gate connection terminal GLT can be formed of the same material in the same layer as the vertical common wiring VCL, the pixel electrode PXL, and the common electrode COM.

In the liquid crystal display device according to the present invention, the vertical gate lines VGL1, VGL2, VGL3, ... and the data lines DL1, DL2, DL3, DL4, And spaced apart from each other. Therefore, the connection terminal GLT, to which one vertical gate line is connected to one horizontal gate line, is disposed apart from the data lines DL1, DL2, DL3, DL4, .... Therefore, the voltage drop in the data line does not occur due to the electrical influence by the connection terminal GLT.

The horizontal common wiring CL is formed of the same material in the same layer as the horizontal gate wirings GL1, GL2, GL3, .... The horizontal common wiring CL is preferably connected to the vertical common wiring VCL. For example, the vertical common wiring VCL can be connected to the horizontal common wiring CL through the common contact hole CLH.

In the embodiment of the present invention, the pixel regions of the 2x2 matrix type are described as a basis. The first vertical gate line VGL1 is arranged on the left side of the first pixel column and the second vertical gate line VGL2 is arranged on the right side of the second pixel column. The first data line DL1 and the second data line DL2 are disposed between the first pixel line and the second pixel line. In other words, by arranging two neighboring data lines in one column, it is possible to secure heat where data lines are not arranged every two columns. Place the vertical gate wiring in a column where data wiring is not arranged.

In the liquid crystal display device, the number of pixel columns and the number of pixel rows have a ratio of 4: 3, 16: 9, and 2.33: 1 on the basis of a unit pixel. In addition, one unit pixel includes three or four sub-pixels of at least RGB or RGBW. Therefore, the number of pixel columns and the number of pixel rows are set to 12: 3 (or), 48: 9 (or 64: 9), or 6.99: 1 (or 9.32: 1) Ratio. Therefore, in a structure in which two neighboring data lines are arranged in one column, a lot of vacant heat is generated even when vertical gate lines are arranged. In other words, the vertical gate wiring may be arranged every three columns, every four columns or every fifth column.

In the liquid crystal display according to the present invention, when selecting pixel regions of any 2x2 matrix structure, vertical gate wirings may not be included. For convenience, the detailed description of the present invention describes the case where all the vertical gate wirings are included.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Pixel array 11: Timing controller
12: Source drive IC 13: Gate drive circuit
14: Source PCB 15: Source drive IC
16: control PCB 17: flexible circuit board
VGL: vertical gate wiring GL: horizontal gate wiring
DL: Data wiring
VCL: Vertical common wiring CL: Horizontal common wiring
CT1: first horizontal connecting electrode CT2: second horizontal connecting electrode
DT1: first horizontal dummy electrode DT2: second horizontal dummy electrode

Claims (7)

Horizontal gate wirings running horizontally above the substrate;
Data lines extending in a vertical direction on the substrate;
Pixel regions arranged in an (i, j) matrix manner by an intersection structure of the data lines and the horizontal gate lines, wherein i and j are natural numbers;
(1,1) pixel electrodes arranged in a (1,1) pixel region;
(1,2) pixel electrodes arranged in a (1,2) pixel region;
(2,1) pixel electrodes arranged in a (2,1) pixel region;
(2,2) pixel electrodes arranged in a (2,2) pixel region;
A (1,1) thin film transistor arranged in the (1,1) pixel region and connected to the (1,1) pixel electrode;
A (1,2) thin film transistor arranged in the (1,2) pixel region and connected to the (1,2) pixel electrode;
A (2, 1) thin film transistor arranged in the (2,1) pixel region and connected to the (2,2) pixel electrode;
And a (2,2) thin film transistor arranged in the (2,2) pixel region and connected to the (2,1) pixel electrode.
The method according to claim 1,
A first horizontal connection electrode extending from the (2,1) thin film transistor to the (2,2) pixel region and connected to the (2,2) pixel electrode;
And a second horizontal connection electrode extending from the (2,2) thin film transistor to the (2,1) pixel region and connected to the (2,1) pixel electrode.
3. The method of claim 2,
A first horizontal dummy electrode extending from the (1,1) thin film transistor to the (1,2) pixel region;
And a second horizontal dummy electrode extending from the (1,2) thin film transistor to the (1,1) pixel region.
The method of claim 3,
Wherein a dummy parasitic capacitance formed between the first horizontal dummy electrode and the second horizontal dummy electrode is substantially equal to a connection parasitic capacitance formed between the first horizontal connection electrode and the second horizontal connection electrode.
The method according to claim 1,
The data wirings,
And a first column data line and a second column data line arranged between the first column pixel column and the second column pixel column.
The method according to claim 1,
The horizontal gate wirings,
A first horizontal gate line and a second horizontal gate line,
A first vertical gate line disposed in the left column of the first column pixel column and connected to the first horizontal gate line; And
And a second horizontal gate line and a second vertical gate line arranged in the right column of the two column pixel column.
The method according to claim 6,
A horizontal common wiring arranged parallel to the horizontal gate wirings; And
And a vertical common wiring connected to the horizontal common wiring, the vertical common wiring being disposed in parallel with the vertical gate wiring.

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