KR20150033024A

KR20150033024A - Display device

Info

Publication number: KR20150033024A
Application number: KR20130112472A
Authority: KR
Inventors: 장훈; 이슬
Original assignee: 엘지디스플레이 주식회사
Priority date: 2013-09-23
Filing date: 2013-09-23
Publication date: 2015-04-01
Also published as: KR102045810B1

Abstract

The present invention relates to a display device, and more specifically, to a display device in which two thin film transistors are formed between two data lines, and each thin film transistor is respectively connected to two pixels which are formed on both right and left sides. To this end, the display device comprises: a panel forming a plurality of data line units consisting of adjacent two data lines, and a plurality of gate lines which are vertically formed in the vertical direction to the data lines; and a driver to drive the panel. The panel comprises: pixels formed on both right and left sides of the data line units, and displaying an image; and a switching unit formed between two data lines which form the data line units, supplying data voltages transmitted through the data lines to each pixel formed on both right and left sides.

Description

Display device {DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a liquid crystal display device composed of a panel made of low temperature polysilicon (LTPS).

Flat panel displays (FPDs) are used in various types of electronic products including mobile phones, tablet PCs, and notebook computers. Examples of flat panel display devices include a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) (EPD: ELECTROPHORETIC DISPLAY) are also widely used.

Of the flat panel display devices (hereinafter, simply referred to as 'display devices'), liquid crystal displays are most widely commercialized at present because of their advantages of mass production technology, ease of driving means, and high image quality.

Of the display devices, an organic light emitting display device has been attracting attention as a next generation display device because it has a high response speed of 1 ms or less and low power consumption.

1 is a cross-sectional view of a thin film transistor formed on a panel applied to a conventional liquid crystal display device. 2 is a cross-sectional view of a thin film transistor formed on a panel applied to a conventional liquid crystal display device, and particularly shows a cross section of a thin film transistor formed on a panel made of low temperature polysilicon (LTPS) have.

In a conventional LCD panel, pixels are formed in regions where gate lines and data lines cross each other. Each of the pixels is formed with one thin film transistor for switching.

The thin film transistor includes a gate electrode formed on a substrate, a gate insulating film covering the gate electrode, a semiconductor layer formed on the gate insulating film, and a source electrode and a drain electrode formed on the semiconductor layer. That is, in the conventional general thin film transistor, the gate electrode is formed at the lowermost end of the substrate.

However, recently, as shown in Fig. 1, a thin film transistor in which a semiconductor layer is formed at the bottom of the substrate and a gate electrode is formed at the top of the semiconductor layer is manufactured. This type of thin film transistor is referred to as a top gate type thin film transistor.

That is, the top gate type thin film transistor includes a semiconductor layer 12 formed on a substrate 11, a gate insulating film 13 formed on the semiconductor layer 12, a gate formed on the gate insulating film 13, A source electrode 16 formed on the semiconductor layer 12 and the passivation layer 15 and a passivation layer 15 covering the semiconductor layer 12 and the passivation layer 15, And a drain electrode 17 formed on the substrate.

Here, as the thin film transistor, an amorphous silicon thin film transistor using amorphous silicon and a low temperature polysilicon thin film transistor using low temperature polysilicon (LTPS) are used.

Since the low temperature polysilicon thin film transistor has higher charge mobility than the amorphous silicon thin film transistor, the low temperature polysilicon thin film transistor is suitable for a high resolution display device requiring a fast response speed.

The low temperature polysilicon thin film transistor may be manufactured in the form as shown in FIG. However, in the low temperature polysilicon thin film transistor manufactured in the form as shown in FIG. 1, off-current is likely to occur.

Therefore, in order to reduce the occurrence of off-current, the low-temperature polysilicon thin-film transistor is manufactured using two gate electrodes as shown in Fig.

That is, the low-temperature polysilicon thin film transistor shown in FIG. 2 includes a semiconductor layer 12 formed on a substrate 11, a first gate insulating film 13a formed on the semiconductor layer 12, A first gate electrode 14a formed on the first gate insulating film 13a and a second gate insulating film 13b formed on the second gate insulating film 13b formed on the second gate insulating film 13b, A protective film 15 covering the first gate electrode 14a and the second gate electrode 14b; a source electrode 14b formed on the semiconductor layer 12 and the protective film 15; And a drain electrode 17 formed on the semiconductor layer 12 and the passivation layer 15.

FIG. 3 and FIG. 4 are plan views schematically illustrating the structure of a pixel applied to a conventional liquid crystal display, and show the structure of a pixel composed of thin film transistors using two gate electrodes.

As described above, in the panel using the low-temperature polysilicon thin-film transistor, two gate electrodes are formed in the low-temperature polysilicon thin-film transistor.

In order to form two gate electrodes in the low temperature polysilicon thin film transistor, a conventional pixel may be configured as shown in FIG. 3 or FIG.

First, referring to FIGS. 2 and 3, the semiconductor layer 12 may be formed in a U-shape to manufacture a thin film transistor having the two gate electrodes 13a and 13b.

In this case, the semiconductor layer 12 extending from the source electrode 16 connected to the data line 19 to the drain electrode 17 connected to the pixel electrode 18, And passes through the line 13 twice. Therefore, the semiconductor layer 12 may be formed to overlap with the first gate electrode 13a and the second gate electrode 13b.

However, in the pixel in which the U-shaped semiconductor layer 12 is formed as shown in FIG. 3, since the left-right spacing A of the U-shaped semiconductor layer 12 must be maintained at a constant size, There is a limit in reducing the interval B between the first and second electrodes 19. Therefore, the pixel structure as shown in FIG. 2 is difficult to apply to a liquid crystal display device of a high resolution.

In this case, the upper and lower widths D of the pixel may be the same size as in the related art, and the vertical width C of the pixel electrode 18 formed in the pixel may be the same size as the conventional one .

2 and 4, in order to manufacture a thin film transistor having the two gate electrodes 13a and 13b, the gate line 13 may be formed as two gate lines .

In this case, the semiconductor layer 12 extending from the source electrode 16 connected to the data line 19 to the drain electrode 17 connected to the pixel electrode 18 is formed of two And passes through the gate line 13. Therefore, the semiconductor layer 12 may be formed to overlap with the first gate electrode 13a and the second gate electrode 13b.

However, since the pixel in which the U-shaped semiconductor layer 12 is formed as shown in FIG. 4 has to be divided into two gate lines, one of the gate lines 13 must be branched into two gate lines, The area occupied by the gate line 13 is increased. Therefore, in the pixel structure as shown in FIG. 2, the size of the opening through which light is output to the outside is inevitably reduced.

3, the vertical width C 'of the pixel electrode 18 formed on the pixel may be the same as that of the pixel shown in FIG. 3, Is smaller than the vertical width (C) of the electrode (18).

That is, in the pixel structure as shown in FIG. 2, the aperture ratio is lowered compared with the conventional liquid crystal display device.

As described above, conventional liquid crystal display devices composed of thin film transistors having two gate electrodes have a limitation in reducing the width B of the pixel, and have a problem that the aperture ratio is low.

In addition, the above-described problems may occur in various display devices driven using thin film transistors, such as organic light emitting display devices and electrophoretic display devices, in addition to the liquid crystal display devices.

SUMMARY OF THE INVENTION The present invention has been proposed in order to solve the above-described problems, and has two thin film transistors formed between two data lines, each of the two thin film transistors being formed on both sides of the two data lines The display device being connected to each of the two pixels.

According to an aspect of the present invention, there is provided a display device including a plurality of data line portions formed by two adjacent data lines, a gate line formed in a direction perpendicular to the data lines, A plurality of panels; And a driver for driving the panel, wherein the panel is formed on both left and right sides of the data line portion and includes pixels for displaying an image; And a switching unit which is formed between the two data lines forming the data line unit and supplies data voltages transmitted through the data lines to each of two pixels formed on both sides of the data line unit, .

According to the present invention, since the intervals between the pixel widths can be reduced, it is possible to realize a high-resolution display device.

Further, according to the present invention, since the black matrix does not need to be formed in the direction parallel to the gate lines, the aperture ratio of the display device can be improved.

1 is a cross-sectional view of a thin film transistor formed on a panel applied to a conventional liquid crystal display device.
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device.
3 and 4 are plan views schematically illustrating the structure of a pixel applied to a conventional liquid crystal display device.
5 is a view schematically showing a display device according to the present invention.
FIG. 6 is an exemplary view showing the area A shown in FIG. 5 in detail; FIG.
FIG. 7 is another exemplary view showing the area A shown in FIG. 5 in detail. FIG.
FIG. 8 is an exemplary view showing a comparison between a configuration of pixels applied to a display device according to the present invention and a configuration of pixels applied to a conventional display device. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a view schematically showing a display device according to the present invention.

As shown in FIG. 5, a liquid crystal display according to the present invention includes a plurality of data line portions DP formed of two adjacent data lines DL1 and DL2, and the data lines And a driver 200 for driving the panel 100. The panel 100 includes a plurality of gate lines GL formed in a direction perpendicular to the plurality of gate lines DL1 and DL2.

First, the driver 200 will be described in detail as follows.

The driver 200 outputs a data voltage to the data lines DL1 to DLd formed on the panel 100 and outputs a scan pulse to the gate lines GL1 to GLg, Circuit (IC), and can be mounted in the non-display area of the panel 100. [ The driver 200 may include a data driver, a gate driver, and a timing controller.

First, the data driver converts the digital image data transmitted from the timing controller into a data voltage and supplies the data voltage for one horizontal line to the data lines for every one horizontal period in which a scan pulse is supplied to the gate line do.

That is, the data driver converts the image data into the data voltage using the gamma voltages supplied from the gamma voltage generator (not shown), and outputs the data voltage to the data line. To this end, the data driver includes a shift register unit, a latch unit, a digital-analog converter (DAC), and an output buffer.

The shift register unit outputs a sampling signal using data control signals (SSC, SSP, etc.) received from the timing controller.

The latch unit latches the digital image data (Data) sequentially received from the timing controller, and simultaneously outputs the latched digital image data (Data) to the digital-analog converter (DAC).

The digital-to-analog converter converts the image data transmitted from the latch unit into a data voltage of positive or negative polarity and outputs the same. That is, the digital-to-analog converter converts the image data into a positive polarity signal or a negative polarity signal according to the polarity control signal POL transmitted from the timing controller, using the gamma voltage supplied from the gamma voltage generator (not shown) Polarity data voltage and outputs the data voltage to the data lines. In this case, the gamma voltage generator converts the image data into the data voltage using the input voltage Vdd.

The output buffer outputs a positive or negative polarity data voltage transmitted from the digital-analog converter to data lines (DL1 to DLd) of the panel according to a source output enable signal (SOE) transmitted from the timing controller. .

Next, the timing controller uses the timing signals input from the external system, that is, the vertical synchronization signal (Vsync), the horizontal synchronization signal (Hsync), and the data enable signal (DE) A data control signal DCS for controlling the operation timing of the data driver, and generates image data to be transmitted to the data driver.

The timing controller may include a receiver for receiving input image data and timing signals from the external system, a control signal generator for generating various control signals, a rearrangement unit for rearranging the input image data, A data arrangement unit for outputting the image data, and an output unit for outputting the control signals and the image data.

That is, the timing controller rearranges input image data input from the external system according to the structure and characteristics of the panel 100, and transmits the rearranged image data to the data driver. Such a function can be executed in the data arrangement section.

The timing controller uses the timing signals transmitted from the external system, that is, the vertical synchronization signal (Vsync), the horizontal synchronization signal (Hsync), and the data enable signal (DE) Generates a control signal DCS and a gate control signal (GCS) for controlling the gate driver, and transmits the control signals to the data driver and the gate driver. This function can be executed by the control signal generator 420. [

The gate control signals GCS generated by the control signal generator include a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a gate start signal VST, a gate clock GCLK, .

The data control signals generated by the control signal generator include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

Finally, the gate driver sequentially supplies scan pulses to the gate lines GL1 to GLg using the gate control signals GCS generated by the timing controller.

Here, the scan pulse has a voltage capable of turning on the switching thin film transistors connected to the gate lines. A voltage capable of turning off the switching thin film transistor is referred to as a gate off signal, and the scan pulse and the gate off signal are generically referred to as a scan signal.

When the thin film transistor is of the N type, the scan pulse has a high level voltage and the gate off signal has a low level voltage. When the thin film transistor is of the P type, the scan pulse has a low level voltage and the gate off signal has a high level voltage.

Second, the overall structure of the panel 100 will be described as follows.

The panel 100 includes a first substrate and a second substrate facing each other.

The first substrate includes a display region X formed by pixels defined by the intersection of a plurality of gate lines GL and a plurality of data lines DL, And a non-display area Y provided.

The driver 100 is formed in the non-display area Y. [ Each of the plurality of pixels displays an image in accordance with a scan pulse supplied from an adjacent gate line GL and a data voltage supplied from an adjacent data line DL. The pixel may comprise at least one thin film transistor.

When the panel 100 is a liquid crystal panel, the pixel can display an image by controlling the light transmittance of the liquid crystal according to the data voltage. When the panel 100 is an organic light emitting panel, the pixel can display an image by emitting light in proportion to a current according to the data voltage. In addition to the pixels performing the functions described above, the pixels may be formed in various shapes according to the type of the panel 100. [

Next, the second substrate covers the whole of the first substrate excluding the part of the non-display area (Y). When the panel 100 is a liquid crystal panel, a color filter layer may be formed on the second substrate. When the panel 100 is an organic light emitting panel, the second substrate may serve as an encapsulating substrate for sealing the first substrate. The second substrate may also be formed in various shapes depending on the type of the panel 100.

Next, on the first substrate, pixels P are formed in the regions where the data lines DL1 to DLd and the gate lines GL1 to GLg cross each other, as shown in FIG. In FIG. 5, the areas denoted by P1, P2 and P3 are also pixels and are shown as separate marks for the description of FIGS. 6 and 7. FIG.

Here, two data lines adjacent to each other among the data lines are collectively referred to as a data line unit (DP). 5, the first data line DL1 and the second data line DL2 form a first data line portion DP1, and the third data line DL3 and the fourth data line DL4 form a first data line DL1, 2 data line portion DP2.

Between the two data lines forming the data line portion DP, a switching portion to be described below is formed. The switching unit supplies the data voltages transmitted through the data lines to the two pixels formed on both sides of the data line unit DP.

Finally, the thin film transistor (TFT) formed in each of the pixels is turned on by the scan pulse supplied from the gate line, and the data voltage supplied from the data line is applied to the pixel electrode Or the organic light emitting diode (OLED) formed in the pixel P emits light.

That is, the panel 100 displays an image by the scan pulse supplied through the gate line GL and the data voltage supplied through the data line DL, and may be formed in various forms . In addition, the display device according to the present invention may be a liquid crystal display device, an organic light emitting display device, or an electrophoretic display device (EPD) according to the type of the panel 100. Hereinafter, for convenience of explanation, the present invention will be described by way of an example in which the display device is a liquid crystal display device and the panel 100 is a liquid crystal panel. That is, the present invention will be described below as an example in which the display device shown in Fig. 5 is formed of the liquid crystal panel 100 as shown in Fig. However, as described above, the display device according to the present invention can also be applied to the organic light emitting display device, the electrophoretic display device, and the like.

The detailed configuration of the panel 100 will be described with reference to FIGS. 5 and 6. FIG.

FIG. 6 is an exemplary view showing in detail the area A shown in FIG. 5, in particular, pixels applied to a liquid crystal display device. FIG. 7 is another exemplary view showing in detail the area A shown in FIG. 5, in particular, a black matrix is shown.

The first pixel P1, the second pixel P2 and the third pixel P3 shown in FIG. 5 are formed in the area A, and the first pixel P1 and the second pixel P2, The first data line DL1 and the second data line DL2 pass between the first data line DL1 and the second data line DL2. The first data line DL1 and the second data line DL2 form the first data line portion DP as described above.

5 and 6, the panel 100 includes pixels P1, P2, P3, and P, which are formed on both sides of the data line portion DP, And two data lines DL1 and DL2 forming the data line part DP and two pixels P1 and P2 formed on both the left and right sides of the data line part DP. And a switching unit 400 for supplying data voltages transmitted through the data lines DL1 and DL2, respectively.

First, the pixels P are formed in the intersection region of the data lines and the gate lines as described above. Particularly, in the present invention, the intersections of the data lines DP and the gate lines As shown in FIG. In Fig. 6, the pixels shown as P1, P2 and P3 are subpixels, for example, a subpixel P1 representing red, a subpixel representing green and subpixels representing blue .

The two pixels P1 and P2 supplied with the data voltages from the switching unit 400 are formed on the upper and lower sides of one gate line GL2 connected to the switching unit 400 have.

6, a second gate line is connected to the switching unit 400, and the switching unit 400 includes a first pixel P1 and a second pixel P1 formed on both sides of the switching unit 400, The first pixel P1 and the second pixel P2 are formed on the upper and lower sides with the second gate line GL2 as a boundary.

In this case, the first pixel P1 is formed on the second gate line GL2, and the second pixel P2 is formed on the lower side of the second gate line GL2.

Third, two pixels are formed in a line between the two data line portions.

5, the first data line unit DP1 including the first data line DL1 and the second data line DL2, the third data line DL3 including the third data line DL2, And two pixels are formed in a line between the second data line portion DP2 including the line DL4.

In other words, not only the data lines DP but also the data lines are not formed between the two pixels formed in a line between the two data lines DP.

Fourth, the two pixels P1 and P2, which are supplied with the data voltages from the switching unit 400, are formed on different horizontal lines in the panel 100.

That is, the horizontal line means a line formed in parallel with one gate line, and a plurality of pixels are arranged in a line along the horizontal line.

In general, pixels that are turned on by one gate line and are simultaneously supplied with data voltages from the data lines are formed on one horizontal line. However, in the present invention, as shown in FIG. 6, the two pixels P1 and P2 supplied with the data voltages from the switching unit 400 are arranged above and below the second gate line GL2 Respectively. That is, the two pixels P1 and P2 are formed on different horizontal lines.

The two pixels P1 and P2 that are supplied with the data voltages from the switching unit 400 are connected to the first data line unit DP1 and the second gate line DP2, Are arranged diagonally with respect to each other when the reference line GL2 is used as a reference.

Fifth, the switching unit DP includes a first thin film transistor T1 and a second thin film transistor T2 for supplying the data voltages to the two pixels P1 and P2, respectively.

That is, the switching unit DP includes the first thin film transistor T1 and the second thin film transistor T2, and the first thin film transistor T1 includes the first thin film transistor T1 and the second thin film transistor T2, And the second thin film transistor T2 supplies the data voltage to the second pixel P2 formed in the left diagonal direction.

In this case, the first thin film transistor T1 and the second thin film transistor T2 each share two gate electrodes.

That is, in FIG. 6, the first gate electrode 413a constituting the first thin film transistor T1 is the same electrode as the first gate electrode 423a constituting the second thin film transistor T2.

6, the second gate electrode 413b constituting the first thin film transistor T1 is the same electrode as the second gate electrode 423b constituting the second thin film transistor T2.

Accordingly, the first thin film transistor T1 and the second thin film transistor T2 each share two gate electrodes.

Sixth, the two gate electrodes are branched from one gate line. That is, the first gate electrode and the second gate electrodes constituting the first thin film transistor T1 or the second thin film transistor T2 are branched from the second gate line GL2.

In other words, the gate line formed by one line is formed by branching into two lines in the data line portion DP. Here, the two lines branched from the one gate line may be the first gate electrode 413a and the second gate electrode 413b forming the first thin film transistor T1, The first gate electrode 423a and the second gate electrode 423b forming the second thin film transistor T2.

Seventh, the two pixels P1 and P2 are formed at the upper and lower ends of one gate line GL2 connected to the two gate electrodes, respectively. Here, the two gate electrodes may be gate electrodes indicated by 413a and 413b, or may be gate electrodes indicated by 423a and 423b. In this case, the gate electrodes labeled 413a and 423a are the same gate electrode, and the gate electrodes labeled 413b and 423b are the same gate electrode.

That is, the two pixels are disposed at positions opposite to each other with respect to the gate line forming the gate electrodes.

Eighth, as described above, the switching unit 400 includes the first thin film transistor T1 and the second thin film transistor T2 for supplying the data voltages to the two pixels P1 and P2, respectively. The first thin film transistor T1 and the second thin film transistor T2 are turned on by a scan pulse transmitted from one gate line G2 and the first thin film transistor T1 is turned on A first data voltage supplied from a first data line DL1 of the two data lines DL1 and DL2 is supplied to a first pixel P1 of the two pixels, Supplies the second data voltage supplied from the second data line DL2 of the two data lines DL1 and DL2 to the second pixel P2 of the two pixels.

That is, the two thin film transistors T1 and T2 are turned on by a scan pulse transmitted from one gate line GL2, and the data voltages transmitted from the different data lines DL1 and DL2 To the first pixel (P1) and the second pixel (P2) arranged diagonally to each other with respect to the gate line (GL2).

Ninth, the configuration of the switching unit 400 will be described in detail.

The switching unit 400 includes two gate electrodes 413a and 413b or 423a and 423b branched from the gate line GL2 and two gate electrodes 413a and 413b formed to cross the two gate electrodes, A first semiconductor layer 412 formed to intersect the first semiconductor layer 412 and a second semiconductor layer 412 formed on the first semiconductor layer 412 and connected to a first data line DL1 of the two data lines, A first source electrode 411 formed to overlap with the first pixel 412 and a second drain electrode 411 electrically connected to the first pixel P1 of the two pixels on the other side of the first semiconductor layer 412, A second semiconductor layer 422 formed so as to intersect the two gate electrodes, an electrode 414, a second semiconductor layer 422 connected to a second data line DL2 of the two data lines, 422 and the second semiconductor layer 422, And a second drain electrode 424 which is electrically connected to the second pixel P2 of the two pixels at one side of the second semiconductor layer 422 do.

Here, the two gate electrodes 413a and 413b, the first semiconductor layer 412, the first source electrode 411, and the first drain electrode 414 form the first thin film transistor T1 do.

In addition, the two gate electrodes 423a and 423b, the second semiconductor layer 422, the second source electrode 421, and the second drain electrode 424 form the second thin film transistor T2 do.

The functions of the first thin film transistor and the second thin film transistor are as described above.

A cross section of the switching unit 400 is as follows.

First, the first semiconductor layer 412 and the second semiconductor layer 422 are formed in parallel on a substrate.

Next, a gate insulating film is formed on the tops of the first semiconductor layer 412 and the second semiconductor layer 422.

Next, the two gate electrodes are formed in a portion of the top of the gate insulating film that overlaps the first semiconductor layer 412 and the second semiconductor layer 422.

Next, a protective film covering the two gate electrodes is formed on the top of the two gate electrodes.

Finally, the first source electrode 411 and the first drain electrode 414 are formed on the first semiconductor layer 412 and the top of the passivation layer, and the second semiconductor layer 422 and the top of the passivation layer The second source electrode 421, and the second drain electrode 424 are formed.

7, black matrices BM are formed in regions corresponding to the data line portions DP, and black matrixes BM are formed in regions corresponding to the gate lines GL, Is not formed.

That is, the data line portions DP are non-openings and are covered by the black matrix BM to prevent light from leaking.

However, the gate lines GL are formed on the panel in the form of a single line, except for the gate electrodes formed on the data line portion DP.

In this case, since the line width of each of the gate lines GL is considerably smaller than the width of the pixels and the data line portion DP, a black matrix is formed at the top of the gate lines GL You do not have to.

That is, according to the present invention, since the black matrix may not be formed at the top of the gate lines GL, the area of the opening of the pixel may be increased.

8A and 8B are diagrams for comparing the configuration of pixels applied to a display device according to the present invention and the configuration of pixels applied to a conventional display device, wherein FIG. 8A shows a configuration of pixels applied to a conventional display device , (b) show the configuration of pixels applied to a display device according to the present invention.

Referring to FIG. 8A, pixels applied to a conventional display device are formed with openings and non-openings (thin film transistors TFT) along a data line DL formed on the panel .

That is, in the conventional display device, an opening portion in which an image is displayed and a non-opening portion in which a thin film transistor is formed are formed in a row along the data line.

However, referring to FIG. 8 (b), the pixels used in the display device according to the present invention are arranged such that the opening portion in which an image is displayed and the non-opening portion in which the thin film transistor TFT is formed are formed along the gate line GL Respectively.

That is, in the panel applied to the display device according to the present invention, the thin film transistor and the opening are formed along the gate line.

In this case, the thin film transistors (TFTs) driving the pixels adjacent to each other are adjacent to each other in the gate line direction.

Therefore, the opening portion in which the image is displayed in any one of the pixels is arranged in the shape adjacent to the opening portion in which the image is displayed in another pixel.

In the display device according to the present invention configured as described above, since the black matrix can be formed only in the data line portion DP in which the thin film transistors are formed, the aperture ratio of the display device can be improved.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: panel 200:
DP: Data line section

Claims

A plurality of data line portions formed by two adjacent data lines and a plurality of gate lines formed in a direction perpendicular to the data lines; And a driver for driving the panel,
Wherein:
Pixels formed on both sides of the data line portion for displaying an image; And
And a switching unit formed between the two data lines forming the data line unit and supplying data voltages transmitted through the data lines to each of two pixels formed on both sides of the data line unit / RTI >

The method according to claim 1,
Wherein the two pixels supplied with the data voltages from the switching unit are formed on both upper and lower sides of one gate line connected to the switching unit.

The method according to claim 1,
And two pixels are formed in a line between the two data line portions.

The method according to claim 1,
Wherein black matrixes are formed in regions corresponding to the data line portions, and black matrixes are not formed in regions corresponding to the gate lines.

The method according to claim 1,
Wherein the two pixels supplied with the data voltages from the switching unit are formed on different horizontal lines in the panel.

The method according to claim 1,
The switching unit includes:
A first thin film transistor and a second thin film transistor for supplying the data voltages to each of the two pixels,
Wherein each of the first thin film transistor and the second thin film transistor includes two gate electrodes.

The method according to claim 6,
And the two gate electrodes are branched from one gate line.

The method according to claim 6,
Wherein the two pixels are formed at the upper and lower ends of one gate line connected to the two gate electrodes, respectively.

The method according to claim 1,
Wherein the switching unit includes a first thin film transistor and a second thin film transistor for supplying the data voltages to the two pixels,
Wherein the first thin film transistor and the second thin film transistor are turned on by a scan pulse transmitted from one gate line,
Wherein the first thin film transistor supplies a first one of the two pixels with a first data voltage supplied from a first one of the two data lines,
And the second thin film transistor supplies a second data voltage supplied from a second data line of the two data lines to a second pixel of the two pixels.

The method according to claim 1,
The switching unit includes:
Two gate electrodes branched from the gate line;
A first semiconductor layer formed to cross the two gate electrodes;
A first source electrode connected to a first data line of the two data lines, the first source electrode overlapping the first semiconductor layer at one side of the first semiconductor layer;
A first drain electrode electrically connected to a first pixel of the two pixels, on the other side of the first semiconductor layer;
A second semiconductor layer formed to cross the two gate electrodes;
A second source electrode connected to a second data line of the two data lines and formed on the other side of the second semiconductor layer so as to overlap with the second semiconductor layer; And
And a second drain electrode electrically connected to a second pixel of the two pixels, at one side of the second semiconductor layer.