KR20180003703A - Display panel and display device using the same - Google Patents

Abstract

The present invention relates to a display panel capable of reducing a bezel area and degradation of an aperture ratio of pixels, and a display apparatus using the same. The display panel comprises: a pixel array in which data lines and gate lines are crossed and pixels having pixel TFTs and pixel electrodes are arranged in a matrix form; and a shift register distributed in the pixel array. The pixel array includes clock wirings supplying a shift clock to the shift register.

Description

DISPLAY PANEL AND DISPLAY DEVICE USING THE SAME [0002]

The present invention relates to a display panel on which a shift register of a gate driving circuit can be arranged in a pixel array and a display using the same.

Various flat panel display devices such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display, and a field emission display (FED) are commercially available.

The liquid crystal display controls an electric field applied to the liquid crystal layer to modulate light incident from the backlight unit to display an image. In an active matrix type liquid crystal display device, a thin film transistor (hereinafter referred to as "TFT") is arranged for each pixel and pixels are driven using the TFT. Such a liquid crystal display device is rapidly evolving into a large-sized and high-resolution image due to development of process technology and achievement of research and development.

A display panel of a liquid crystal display device includes an upper plate and a lower plate joined with a liquid crystal layer interposed therebetween. An alignment film is formed on the surface of the substrate in contact with the liquid crystal layer in each of the upper plate and the lower plate. The alignment film sets the pre-tilt angle of the liquid crystal molecules. In order to maintain the cell gap of the liquid crystal layer, a spacer is disposed between the upper plate and the lower plate. The lower plate may comprise a TFT array formed on a lower glass substrate. The top plate may include a color filter array formed on the top glass substrate. A polarizing plate is bonded to each of the upper plate and the lower plate.

The manufacturing process of the liquid crystal display device includes a substrate cleaning process, a substrate patterning process, an orientation film forming / rubbing process, a substrate adhering process and a liquid crystal dropping process, a drive circuit mounting process, an inspection process, a repair process, and a module assembling process.

The substrate cleaning process removes contaminants from the upper glass substrate and the lower glass substrate of the display panel with a cleaning liquid. The substrate patterning process forms signal lines, TFTs, pixel electrodes, common electrodes, etc., including data lines and gate lines, on the lower glass substrate. The substrate patterning process forms a black matrix, a color filter, and the like on the upper glass substrate. In the alignment film forming / rubbing process, an alignment film is applied on glass substrates and the alignment film is rubbed with a rubbing film or optically aligned. Through this series of processes, the lower glass substrate is provided with data lines to which video data voltages are supplied, gate lines that intersect with the data lines and are supplied with scan signals, that is, gate pulses sequentially, intersections of data lines and gate lines TFTs formed on the TFTs, pixel electrodes connected to the TFTs, storage capacitors, and the like are formed. The common electrode is formed on the upper glass substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode or a VA (Vertical Alignment) mode, and is formed in a horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode in the driving method. A polarizing plate is bonded to each of the upper glass substrate and the lower glass substrate.

In the process of adhering a substrate and dropping a liquid crystal, a liquid crystal region is defined by drawing a sealant on either the upper or lower glass substrate of the display panel, liquid crystal is dropped on the liquid crystal region, The glass substrate is bonded with a sealant.

The drive circuit mounting process uses a chip on glass (COG) process or a TAB (Tape Automated Bonding) process to display a drive IC (Integrated Circuit) integrated with a data drive circuit by an anisotropic conductive film (ACF) To the data pads of the panel. The gate drive circuit is formed directly on the lower glass substrate by a GIP (Gate In Panel) process, or integrated into an IC, and is subjected to a TAB (Tape Automated Bonding) process in a drive circuit mounting process to form gate pads As shown in Fig. The driving circuit mounting process connects the ICs and the printed circuit board (PCB) to a flexible circuit board such as an FPC (Flexible Printed Circuit board) or an FFC (Flexible Flat Cable).

The inspecting process includes an inspection for a driver circuit, a wire inspecting of a data line and a gate line formed on a TFT array substrate, an inspecting after a pixel electrode is formed, an electrical inspecting after a liquid crystal dropping process, do. The repair process repairs the defects found by the inspection process.

When the display panel is completed through the above-described series of steps, the module assembly process is performed. In the module assembling process, the backlight unit is aligned below the display panel, and the display panel and the backlight unit are assembled using a tool such as a guide / case member.

The driving circuit of the flat panel display device includes a data driving circuit for supplying a data voltage to the data lines of the display panel, a gate driving circuit for supplying gate pulses (or scan pulses) to the gate lines (or scan lines) of the display panel Or a scan driving circuit), a timing controller (TCON) for controlling all operations of these driving circuits, and the like.

The IC chip on which the data driving circuit is integrated may be mounted on a flexible circuit board, for example, a COF (Chip on Film), and the COF may be adhered to the display panel with an ACF.

Recently, a technique of directly mounting a gate driving circuit on a substrate of a display panel together with a pixel array by using a GIP process centered on a liquid crystal display (LCD) and an organic light emitting diode (OLED) display has been applied. Hereinafter, the shift register of the gate driving circuit mounted directly on the substrate of the display panel will be referred to as a " GIP circuit ".

Since the timing control signals such as the start pulse and the shift clock and the driving voltages are required for the GIP circuit to operate normally, many wires are connected to the GIP circuit. Since the GIP circuit is disposed on the substrate of the display panel outside the pixel array, the GIP circuit increases the size of the bezel which is a non-display region.

The present invention provides a display panel capable of reducing a bezel area and a decrease in aperture ratio of pixels, and a display device using the same.

A display panel according to an embodiment of the present invention includes a pixel array in which pixels having pixel TFTs and pixel electrodes are arranged in a matrix form, in which data lines and gate lines are crossed; And a shift register distributed within the pixel array. The pixel array includes clock wirings for supplying a shift clock to the shift register.

A shift register of a display device according to an embodiment of the present invention is dispersed in the pixel array on a display panel or disposed in a bezel area outside the pixel array. The shift register comprising: a first TFT for charging a Q node in response to a start pulse or an output signal of a previous stage; A second TFT for discharging the Q node in response to a Nth (N is a positive integer) clock signal; A third TFT which charges the voltage of the output terminal in response to the Q node voltage to raise the voltage of the gate pulse; And a fourth TFT for discharging the voltage of the output terminal to the clock wiring supplied with the N-th clock signal in response to an (N-2) -th clock signal generated in an opposite phase to the N-th clock signal.

A shift register of a display device according to another embodiment of the present invention is distributed on the display panel in the pixel array. The shift register comprising: a first TFT for charging a first Q node in response to a start pulse or an output signal of a previous stage; A second TFT for discharging the first Q node in response to a voltage of a second gate line; And a third TFT that charges the Q2 node in response to the voltage of the first gate line in response to the Q1 node voltage. A first clock signal is applied to the first gate line, and a second clock signal is applied to the second gate line.

The present invention can reduce the aperture ratio of pixels even if the GIP circuit is disposed in the pixel array by reducing the bezel area by dispersing the GIP circuit having the minimum circuit configuration in the pixel array or by arranging the GIP circuit in the bezel area.

1 is a plan view schematically showing a display device according to an embodiment of the present invention.
2 is a view schematically showing a part of the shift register configuration of the GIP circuit.
3 is a diagram illustrating a GIP circuit according to the first embodiment of the present invention.
4 is a waveform diagram showing the input / output waveform of the circuit shown in Fig.
5 is a diagram illustrating a GIP circuit according to a second embodiment of the present invention.
6 is a waveform diagram showing an input / output waveform of the circuit shown in FIG.
7 is a waveform diagram showing the voltage and output voltage of the Q node in the N stage circuit shown in FIG.
8A to 8C are views showing a first embodiment in which a GIP circuit is incorporated in a panel array.
FIG. 9 is a circuit diagram showing an enlarged view of the GIP circuit A shown in FIG. 8A.
10A to 10C are views showing a second embodiment in which a GIP circuit is embedded in a panel array.
11 is a circuit diagram showing an enlarged view of the GIP circuit B shown in Fig. 10A.
12A to 12C are views showing a third embodiment in which a GIP circuit is incorporated in a panel array.
13 is a circuit diagram showing an enlarged view of the GIP circuit C shown in Fig. 12A.
14 is a view showing a fourth embodiment in which a GIP circuit is incorporated in a panel array.
15 is a circuit diagram showing an enlarged view of the GIP circuit D shown in Fig.
16 is a waveform diagram showing an input / output waveform of the GIP circuit shown in FIG.
17 and 18 are diagrams illustrating clock wirings in a bezel region outside the pixel array.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The display device of the present invention can be implemented as a flat panel display device such as a liquid crystal display (LCD), an organic light emitting display (OLED) display, or the like. In the following embodiments, a liquid crystal display device will be described as an example of a flat panel display device, but the present invention is not limited thereto.

The GIP circuit of the present invention can be implemented by transistors of an n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. Although n-type transistors are exemplified in the following embodiments, it should be noted that the present invention is not limited thereto. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the transistor, the carriers begin to flow from the source. The drain is an electrode from which the carrier exits from the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, the direction of current flows from drain to source because electrons flow from source to drain. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, the current flows from the source to the drain because the holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed depending on the applied voltage. In the following embodiments, the transistors constituting the GIP are described as n-type MOSFETs, but are not limited thereto. Therefore, in the following description, the invention should not be limited by the source and drain of the transistor.

Referring to FIG. 1, a display device according to an embodiment of the present invention includes a display panel PNL and a driving circuit for writing data of an input image on the display panel PNL.

The driving circuit includes a data driving circuit for supplying a data voltage of an input image to the data lines of the display panel PNL and a gate driving circuit for applying a gate pulse (or a scanning pulse) synchronized with the data voltage to the gate lines GL And a timing controller (TCON) for controlling the operation timing of the data driving circuit and the GIP circuit, and the like. The gate drive circuit includes a GIP circuit distributed in a pixel array or disposed in a bezel region outside the pixel array (AA). In Fig. 1, the data driving circuit is connected to the data lines DL of the display panel PNL in a form integrated in the source drive IC (SIC).

The GIP circuit of the present invention is distributed within the pixel array AA or within a bezel region outside the pixel array. The present invention reduces circuit area by reducing the number of switch elements, clock wiring, and power supply wiring in a GIP circuit. As a result, the aperture ratio degradation of the pixels can be minimized when the GIP circuit is disposed in the pixel array AA. Since the circuit area of the GIP circuit shown in FIG. 5 or 15 is very small, it is not only optimized as a circuit disposed in the pixel array AA, but also can greatly reduce the size of the bezel region when the circuit is disposed in the bezel region. Fig. 1 shows an example in which the GIP circuit is dispersed in the pixel array AA.

The GIP circuit of the present invention is formed directly on the lower substrate SUBS1 of the display panel PNL together with the pixel array AA and connected to the gate lines GL. The GIP circuit includes a shift register that receives a timing control signal such as a start pulse and a shift clock, and sequentially shifts the output in synchronization with the clock timing.

The display panel (PNL) includes an upper plate and a lower plate bonded with a liquid crystal layer interposed therebetween. The substrates may be glass substrates, but are not limited thereto. The display panel PNL includes pixels in which the data lines DL and the gate lines GL are arranged in a matrix form by an intersection structure. The pixels include a pixel TFT formed at the intersection of the data line GL and the gate line GL, a liquid crystal cell Clc connected to the pixel TFT, and a storage capacitor Cst. The pixel TFT supplies the data voltage input through the data line DL to the pixel electrode PXL in response to the gate pulse from the gate line GL. The liquid crystal cell Clc adjusts the refractive index of the incident light according to the data voltage by using liquid crystal molecules driven according to the electric field between the pixel electrode PXL and the common electrode COM.

The lower plate of the display panel (PNL) includes a TFT array formed on the lower substrate. The TFT array includes data lines DL, gate lines GL, TFTs, a pixel electrode PXL connected to the TFT, a common electrode COM, a storage capacitor Cst, and a GIP circuit. GIP circuits are distributed in the TFT array, and clock wirings connected to the GIP circuit are arranged. At least some of the clock wires may be connected to the gate lines. In this case, the gate lines also serve as a clock wiring.

The top plate of the display panel (PNL) includes a color filter array formed on the top substrate. The color filter array includes a black matrix, a color filter, and the like. In the case of the COT (Color Filter on TFT) or the TOC (TFT on Color Filter) model, a color filter may be further formed on the TFT array of the lower plate.

The common electrode COM is formed on the upper substrate in the vertical electric field driving system and on the lower substrate together with the pixel electrode PXL in the horizontal electric field driving system. On the upper substrate and the lower substrate of the display panel (PNL), a polarizing plate orthogonal to the optical axis is attached, and an alignment film for setting the pretilt angle of liquid crystal on the inner surface in contact with the liquid crystal is formed.

A touch screen using an in-cell touch sensor may be implemented on the display panel PNL. The in-line touch sensor is embedded in the pixel array AA of the display panel (PNL). The insole touch sensor can be realized as a capacitive type touch sensor that senses a touch based on a change in capacitance before and after touch. The touch sensors may be disposed on the display panel in an on-cell type or an add-on type.

The timing controller TCON receives data of an input image from an external host system and transmits it to the source drive IC (SIC). The timing controller TCON receives timing signals such as a vertical / horizontal synchronizing signal, a data enable signal, and a main clock signal to generate timing control signals for controlling operation timings of the source drive IC (SIC), the GIP circuit, and the touch sensor do. The host system may be any one of a TV system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

The source driver IC (SIC) converts the digital video data of the input image to the analog positive / negative gamma compensation voltage under the control of the timing controller (TCON) to generate the positive / negative analog data voltage, And outputs them to the lines DL. The source drive IC (SIC) can be mounted on a flexible circuit board, e.g., a COF, that can be bent.

The COFs are bonded to the lower substrate SUBS1 and the source PCB SPCB of the display panel PNL through an anisotropic conductive film (ACF). The input pins of the COFs are electrically connected to the output terminals of the source PCB (SPCB). The output pins of the source COFs (COFs) are electrically connected to data pads formed on the lower substrate of the display panel (PNL) through the ACF.

The GIP circuit outputs a gate pulse synchronized with the data voltage to the gate lines GL under the control of the timing controller TCON. The GIP circuit includes a shift register that starts driving in response to a start pulse (VST) and shifts the output in accordance with a shift clock (CLK1 to CLKn).

The shift register includes a plurality of stages S (N-1) to S (N + 1) which are connected as shown in FIG. The GIP circuit sequentially shifts the gate pulse to the shift clock timing from the timing controller (TCON) using the shift register, thereby sequentially selecting the pixels to which data is written in the display panel (PNL) line by line.

The gate timing control signals such as the start pulse VST and the shift clocks CLK1 to CLK generated from the timing controller TCON are input to the shift register. The level shifter LS shifts the voltage level of the gate timing control signal to generate a signal that swings the gate timing control signal between the gate high voltage VGH and the gate low voltage VGL And transfers it to the shift register. The gate high voltage VGH is set to a voltage higher than the threshold voltage of the pixel TFT. The gate-low voltage VGL is set to a voltage lower than the threshold voltage of the pixel TFT. Thus, the pixel TFT is turned on in response to the gate high voltage VGH of the gate pulse applied to its gate through the gate line GL, while the pixel TFT is turned on in response to the gate low voltage VGL And is turned off.

The timing controller TCON and the level shifter LS may be disposed on the control board CPCB. The control board (CPCB) can be connected to the source PCB (SPCB) through a flexible flat cable (FFC). The gate timing control signal, that is, the start pulse, the shift clock, and the like necessary for driving the shift register is supplied to the dummy channel wiring formed on the COF film and the LOG Line On Glass) wires to the GIP circuit.

2 is a view schematically showing a part of the shift register configuration of the GIP circuit. In Fig. 2, power supply wiring and reset signal wiring are omitted.

Referring to FIG. 2, the GIP circuit includes a shift register that sequentially shifts gate pulses under the control of a timing controller (TCON). The transistors constituting the shift register include at least one of a TFT including amorphous silicon (a-Si), an oxide TFT including an oxide semiconductor, and a TFT including a low temperature polysilicon (LTPS) . The TFT can be implemented with transistors of MOSFET structure. Since the GIP circuit of the present invention is disposed in a pixel array, a circuit having a small number of clock wirings or a small number of driving voltage wires and requiring a small number of TFTs is desirable in order to minimize a drop in aperture ratio of pixels.

Each of the stages S (N-1) to S (N + 1) of the shift register includes a pull-up transistor, a pull-down transistor, a Q node for controlling a pull- A QB node for controlling the transistor, and a control unit for controlling charging and discharging of the Q node and the QB node. Each of the stages S (N-1) to S (N + 1) The Q node is pre-charged in response to a start pulse or a carry signal received from a previous stage. When the shift clocks (CLK1 to CLKn) are input while the Q node is precharged, The Q node is bootstrapped through the parasitic capacitance of the pull-up transistor so that the voltage of the Q node connected to the gate of the pull-up transistor is further raised. When the voltage of the Q node is bootstrapped, Voltage (V GH) to start outputting a gate pulse. The gate pulse swings between the gate high voltage (VGH) and the gate low voltage (VGL).

The carry signal may be an output voltage of the front stage or a separate carry signal generated simultaneously with the output signal as shown in FIG. In FIG. 2, Vout (N-1), Vout (N), and Vout (N + 1) are the output signals of the n-1th to (n + 1) th stages, that is, the voltages of the gate pulses.

The shift clocks CLK1 to CLKn may be four-phase or eight-phase clocks in which the clocks are sequentially shifted, but are not limited thereto. The positions of the carry signal and the stage where the reset signal is generated are not limited to those shown in Fig.

3 and 4 are views showing a GIP circuit according to the first embodiment of the present invention and input / output waveforms thereof.

3 and 4, the start pulse VST, the shift clocks CLK (N), CLK (N-1), and CLK (N) are added to the Nth (N is a positive integer) -2), Vout (N-2), Vout (N + 2), VSS voltage, and the like. The VSS voltage may be generated as a gate-low voltage (VGL). In the shift clock, the phases are shifted in the order of CLK (N-2), CLK (N-1), and CLK (N). Vout (N-2) is a carry signal which is sub-output to the (N-2) th stage. The output signal Vout (N-2) of the (N-2) th stage is supplied to the (N-2) th gate line as a gate pulse and to the VST wiring of the Nth stage S (N) as a carry signal. Also, the output signal Vout (N-2) of the (N-2) th stage is supplied as a reset signal to the clock wiring or other gate line of the (N-4) th stage. And Vout (N + 2) is a reset signal which is sub-output to the (N + 2) th stage. The output signal Vout (N + 2) of the (N + 2) th stage is supplied to the (N + 2) th gate line as a gate pulse and to the VST wiring of the (N + 4) th stage as a carry signal. The output signal Vout (N + 2) of the (N + 2) -th stage is supplied to the clock wiring of the N-th stage or another gate line as a reset signal.

The Nth stage S (N) includes first to fifth TFTs T1 to T5.

The first TFT T1 pre-charges the Q node in response to the start pulse VST or the carry signal Vout (N-2) received from the previous stage. The gate and the drain of the first TFT (T1) are connected to the VST wiring and operate as a diode. The VST wiring is supplied with the start pulse VST or the carry signal Vout (N-2) received from the previous stage. The source of the first TFT (T1) is connected to the Q node (Q).

The second TFT T2 discharges the Q node Q in response to a reset signal received from the next stage. The gate of the second TFT T2 is connected to the clock wiring or other gate line to which the reset signal received from the next stage is supplied. The drain of the second TFT (T2) is connected to the Q node (Q). The source of the second TFT (T2) is connected to the VSS terminal. VSS voltage is supplied to the VSS terminal.

The third TFT T3 is a pull-up transistor that increases the voltage Vout (N) at the output terminal by supplying CLK (N) to the output terminal in response to the Q-node voltage. When CLK (N) is input when the voltage of the Q node Q is precharged and charged to VGH, the Q node is bootstrapped through the parasitic capacitance between the gate and the drain of the third TFT T3 to form 2VGH . As a result, the third TFT T3 charges the gate pulse Vout (N) by charging the voltage of the output terminal to the voltage of CLK (N) when CLK (N) is input. The gate pulse Vout (N) is supplied to the Nth gate line and simultaneously supplied to the VST wiring of the (N + 2) -th stage as a carry signal and supplied to the clock wiring of the (N-2) do. The gate of the third TFT (T3) is connected to the Q node. The drain of the third TFT T3 is connected to the first clock wiring through which CLK (N) is received, and the source of the third TFT T3 is connected to the output terminal.

The fourth TFT T4 is a pull-down transistor for discharging the voltage at the output terminal before the gate pulse is turned on. The fourth TFT T4 discharges the voltage at the output terminal in response to CLK (N-2). The gate of the fourth TFT T4 is connected to a second clock wiring through which CLK (N-2) is received. The drain of the fourth TFT T4 is connected to the output terminal, and the source of the fourth TFT T4 is connected to the VSS terminal.

The fifth TFT T5 discharges the Q node in response to CLK (N-1). The gate of the fifth TFT (T5) is connected to a third clock wiring through which CLK (N-1) is received. The drain of the fifth TFT (T5) is connected to the Q node, and the source of the fifth TFT (T5) is connected to the VSS terminal.

When the start pulse VST or the carry signal from the previous stage is applied to the Nth stage S (N), the voltage of the Q node Q is precharged by VGH by the voltage supplied through the first TFT T1 do. When the CLK (N) is received, the Q-node voltage rises by 2VGH due to the bootstrap, and consequently the third TFT T3 is turned on so that the voltage of CLK (N) charges the output terminal, Vout (N)) is increased. When the carry signal Vout (N + 2) is received from the next stage at the gate of the second TFT T2, the second TFT T2 is turned on to discharge the Q node.

5 and 6, the number of TFTs, the number of clock wirings, and the number of power supply wirings are further reduced in the GIP according to the second embodiment of the present invention. Therefore, the GIP circuit shown in Fig. 5 in comparison with the first embodiment described above is more effective in reducing the aperture ratio drop of the pixels.

5 and 6 are views showing a GIP circuit and its input / output waveform according to a second embodiment of the present invention. 7 shows the voltage (Q-node) and the output voltage Vout (N) of the Q node in the Nth stage circuit shown in FIG.

5 to 7, the start pulse VST, the shift clocks CLK (N) and CLK (N-2), Vout (N-1), Vout N-2)) and the like are supplied. The start pulse VST is omitted from the drawing.

At the shift clock, CLK (N-2) and CLK (N) are generated in opposite phases to each other. Vout (N-2) is a carry signal which is sub-output to the (N-2) th stage. The output signal Vout (N-2) of the (N-2) th stage is supplied to the (N-2) th gate line as a gate pulse and to the VST wiring of the Nth stage S (N) as a carry signal. Also, the output signal Vout (N-2) of the (N-2) th stage is supplied as a reset signal to the clock wiring or other gate line of the (N-4) th stage. Vout (N-1) is a reset signal that is output to the (N-1) th stage. The output signal Vout (N-2) of the (N-1) th stage is supplied to the (N-1) th gate line as a gate pulse and to the VST wiring of the (N + 1) th stage as a carry signal. Also, the output signal Vout (N-1) of the (N-1) th stage is supplied as a reset signal to the clock wiring of the N-th stage or another gate line. Thus, the gate signal output from any stage is applied to the other stages as a carry signal and a reset signal.

The Nth stage S (N) includes the first to fourth TFTs T11 to T14.

The first TFT T11 charges the Q node in response to the start pulse VST or the carry signal Vout (N-2) received from the previous stage. The gate and the drain of the first TFT (T11) are connected to the VST wiring and operate as a diode. The VST wiring is supplied with the start pulse VST or the carry signal Vout (N-2) received from the previous stage. The source of the first TFT (T11) is connected to the Q node (Q).

The second TFT T12 discharges the Q node in response to CLK (N-2). The gate of the second TFT (T12) is connected to the first clock wiring through which CLK (N-2) is received. The drain of the second TFT T12 is connected to the Q node and the source of the second TFT T12 is connected to the clock wiring or other gate line. The output signal of the previous stage, that is, the reset signal Vout (N-1), is received on the clock wiring or other gate line.

The third TFT T13 is a pull-up transistor for raising the voltage of the output terminal in response to the Q-node voltage. The third TFT T13 charges the gate pulse Vout (N) by charging the voltage of the output terminal to the voltage of CLK (N) when CLK (N) is input. The gate pulse Vout (N) is supplied to the Nth gate line and supplied to the VST wiring of the (N + 2) -th stage as a carry signal and supplied to the clock wiring of the (N + 1) do. The gate of the third TFT (T13) is connected to the Q node. The drain of the third TFT (T13) is connected to the second clock wiring through which CLK (N) is received, and the source of the third TFT (T13) is connected to the output terminal.

The fourth TFT T14 is a pull-down transistor responsive to CLK (N-2) for discharging the voltage of the output terminal to the clock wiring via the second clock wiring. The gate of the fourth TFT (T14) is connected to a first clock wiring through which CLK (N-2) is received. The drain of the fourth TFT (T4) is connected to the output terminal, and the source of the fourth TFT (T14) is connected to the second clock wiring.

When the start pulse VST or the carry signal from the previous stage is applied to the Nth stage S (N), the voltage of the Q node Q is precharged by VGH by the voltage supplied through the first TFT T11 do. When the CLK (N) is received, the Q-node voltage rises by 2VGH due to the bootstrap, so that the third TFT T13 is turned on so that the voltage of CLK (N) charges the output terminal, Vout (N)) is increased. The second TFT T12 is turned on to discharge the Q node when CLK (N + 2) is received in the Nth stage S (N).

The GIP circuit of the present invention can be distributedly arranged in the pixel array (AA) of the display panel (PNL) in various forms as in the following embodiments.

8A to 8C are views showing a first embodiment in which a GIP circuit is incorporated in a panel array. 8A to 8C, D1 to D24 are the numbers of the data lines DL. G1 to G8 are the numbers of the gate lines GL. CLK1 to CLK4 are shift clocks applied to the GIP circuit through the clock wirings CL1 and CL2. 8A to 8C show the GIP circuit as shown in Fig. FIG. 9 is a circuit diagram showing an enlarged view of the GIP circuit A shown in FIG. 8A.

8A to 9, the pixel array AA includes pixels arranged in a matrix form by the intersection structure of the data lines D1 to D24 and the gate lines G1 to G8. Each of the pixels includes a pixel electrode (PXL) and a pixel TFT. Also, the pixel array AA is distributedly arranged with the GIP circuits as indicated by dotted lines. The GIP circuit shown in Figs. 8A to 9 exemplifies the circuit shown in Fig. 5, but the present invention is not limited to this. For example, the GIP circuit may be the circuit shown in Figs. 3, 5, and 15. Fig.

The pixel array AA is arranged with clock wirings CL1 and CL2 for transmitting the shift clocks CLK1 to CLK4 to the GIP circuit.

The clock wirings CL1 and CL2 may be arranged in various forms. 8A to 9, the pair of clock wirings CL1 and CL2 are elongated along the vertical direction (the Y-axis direction in FIG. 1) across the space between the right and left neighboring pixels. These clock wirings CL1 and CL2 are parallel to the data lines DL. The data line is not arranged in the space between the pixels where the pair of clock wirings CL1 and CL2 are arranged. This is because when the clock lines CL1 and CL2 are disposed close to the data line DL, the interval between the left and right pixels can be widened and the coupling between the data line DL and the clock lines CL1 and CL2 Coupling can cause mutual electrical adverse effects.

In order to secure a space in which a pair of clock wirings CL1 and CL2 are disposed, the structure of pixels is designed in a symmetrical structure with a pair of clock wirings CL1 and CL2 therebetween, It is possible to secure a space in which there is no data line between neighboring pixels. 8A to 8C, the pair of clock wirings CL1 and CL2 is composed of CLK1-CLK3 between D3 and D4, CLK2-CLK4 between D9 and D10, CLK3-CLK1 between D15 and D16, D21 and D22 CLK4-CLK2 < / RTI > When the clock wirings CL1 and CL2 and the GIP circuit are arranged in the pixel array AA, the clock wiring and the GIP circuit are removed from the left and right bezel regions of the display panel PNL, thereby minimizing the bezel area.

If pixels are designed to be horizontally symmetrical with a pair of clock wirings CL1 and CL2 interposed therebetween, a pair of data lines may be disposed between the left and right neighboring pixels. 8A-8C, the pair of data lines are D6-D7 between D5 and D8, D12-D13 between D11 and D14, D18-D19 between D17 and D20, and so on.

Another method of arranging the pair of clock wirings CL1 and CL2 between the left and right pixels without the data line DL is to apply the pixel array AA of the double rate driving type. In the DRD type pixel array, the number of data lines is reduced to 1/2 because the subpixels neighboring in the right and left (in the X-axis direction in Fig. 1) share one data line, thereby reducing the number of source driver ICs . Due to the reduction of the data lines, a space free of data lines is ensured between the left and right neighboring sub-pixels. A pair of clock wirings CL1 and CL2 may be arranged in this space.

The start pulse VST is applied to the first gate line G1 through the VST wiring line or to the first gate line G1 through a dummy stage not shown. The gate lines G1 to G8 are respectively connected to the output terminals of the shift register and are supplied with gate pulses through their output terminals. In addition, the gate lines supply a carry signal or a reset signal to the other stages. Since the gate lines, carry signal lines, and reset lines are not separated, the number of wires can be reduced, which further reduces the aperture ratio of the pixels.

10A to 10C are views showing a second embodiment in which a GIP circuit is embedded in a panel array. 11 is a circuit diagram showing an enlarged view of the GIP circuit B shown in Fig. 10A. 10A to 10C, D1 to D24 are the numbers of the data lines DL. G1 to G8 are the numbers of the gate lines GL. CLK1 to CLK4 are shift clocks applied to the GIP circuit through clock wirings (CLV, CLH). 10A to 10C show the GIP circuit as shown in Fig. 11 is a circuit diagram showing an enlarged view of the GIP circuit B shown in Fig. 10A.

10A to 11, the pixel array AA includes pixels arranged in a matrix form by an intersection structure of the data lines D1 to D24 and the gate lines G1 to G8. Each of the pixels includes a pixel electrode (PXL) and a pixel TFT. Also, the pixel array AA is distributedly arranged with the GIP circuits as indicated by dotted lines. The GIP circuit shown in Figs. 10A to 11 exemplifies the circuit shown in Fig. 5, but the present invention is not limited thereto. For example, the GIP circuit may be the circuit shown in Figs. 3, 5, and 15. Fig.

The pixel array AA is arranged with clock wirings CLV and CLH for transmitting the shift clocks CLK1 to CLK4 to the GIP circuit. The clock wirings CLV and CLH are connected to the first clock wiring CLV parallel to the data lines DL and the second clock wiring CLH crossing the first clock wiring CLV and the gate lines GL. ). The first clock wiring (CLV) and the second clock wiring (CLH) are intersected with each other with an insulating layer interposed therebetween. The first and second clock wirings (CLV, CLH) to which the same shift clock is applied are connected to each other through a contact hole passing through the insulating layer at the intersection. The pixel array AA in which the clock wirings CLV and CLH are disposed can reduce the number of clock wirings in the vertical direction as compared with the pixel array AA shown in Figs. 8A to 8C, do.

The first clock wiring (CLV) is formed long along the vertical direction across the space between the left and right neighboring pixels. The stage circuit of the GIP circuit may be arranged long in the vertical direction along the first clock wiring (CLV). The data line is not disposed in the portion where the first clock wiring (CLV) and the GIP circuit are arranged. This is because when the clock line CLV and the GIP circuit together with the data line DL are arranged, the interval between the left and right pixels can be widened and the coupling between the data line DL and the clock wiring CLV can be electrically This can adversely affect.

In order to secure a space in which the first clock wiring (CLV) is disposed, the structures of the pixels are designed in a bilaterally symmetrical manner with the first clock wirings (CLV) therebetween so that there is no space between the left and right neighboring pixels . 10A to 10C, the first clock wiring (CLV) and the GIP circuit are arranged between CLK1 between D3 and D4, CLK2 between D9 and D10, CLK3 between D15 and D16, CLK4 between D21 and D22 and the like .

If pixels are designed to be horizontally symmetrical with a pair of clock wirings CL1 and CL2 interposed therebetween, a pair of data lines may be disposed between the left and right neighboring pixels. 10A-10C, the pair of data lines are D6-D7 between D5 and D8, D12-D13 between D11 and D14, D18-D19 between D17 and D20, and so on.

Another method of arranging the pair of clock wirings CL1 and CL2 between the left and right pixels without the data line DL is to apply the pixel array AA of the double rate driving type. In the DRD type pixel array, the number of data lines is reduced to 1/2 because the subpixels neighboring in the right and left (in the X-axis direction in Fig. 1) share one data line, thereby reducing the number of source driver ICs . Due to the reduction of the data lines, a space free of data lines is ensured between the left and right neighboring sub-pixels. A pair of clock wirings CL1 and CL2 may be arranged in this space.

The start pulse VST is applied to the first gate line G1 through the VST wiring line or to the first gate line G1 through a dummy stage not shown. The gate lines G1 to G8 are respectively connected to the output terminals of the shift register and are supplied with gate pulses through their output terminals. In addition, the gate lines supply a carry signal or a reset signal to the other stages. Since the gate lines, carry signal lines, and reset lines are not separated, the number of wires can be reduced, which further reduces the aperture ratio of the pixels.

12A to 12C are views showing a third embodiment in which a GIP circuit is incorporated in a panel array. 13 is a circuit diagram showing an enlarged view of the GIP circuit C shown in Fig. 12A. 12A to 12C, D1 to D24 are the numbers of the data lines DL. G1 to G8 are the numbers of the gate lines GL. CLK1 to CLK4 are shift clocks applied to the GIP circuit through clock wirings (CLV, CLH). 12A to 12C show the GIP circuit as shown in Fig. 13 is a circuit diagram showing an enlarged view of the GIP circuit C shown in Fig. 12A.

12A to 13, the pixel array AA includes pixels arranged in a matrix form by an intersection structure of the data lines D1 to D24 and the gate lines G1 to G8. Each of the pixels includes a pixel electrode (PXL) and a pixel TFT. Also, the pixel array AA is distributedly arranged with the GIP circuits as indicated by dotted lines. The GIP circuit shown in FIGS. 12A to 13 exemplifies the circuit shown in FIG. 5, but the present invention is not limited to this. For example, the GIP circuit may be the circuit shown in Figs. 3, 5, and 15. Fig.

The pixel array AA is arranged with clock wirings CLV and CLH for transmitting the shift clocks CLK1 to CLK4 to the GIP circuit. The clock wirings CLV and CLH are connected to the first clock wiring CLV parallel to the data lines DL and the second clock wiring CLH crossing the first clock wiring CLV and the gate lines GL. ). The first clock wiring (CLV) and the second clock wiring (CLH) are intersected with each other with an insulating layer interposed therebetween. The first and second clock wirings (CLV, CLH) to which the same shift clock is applied are connected to each other through a contact hole passing through the insulating layer at the intersection. This embodiment is entirely similar to the second embodiment described above except that the portion unnecessary for driving in the second clock wiring CLH is removed.

14 is a view showing a fourth embodiment in which a GIP circuit is incorporated in a panel array. 15 is a circuit diagram showing an enlarged view of the GIP circuit D shown in Fig. This embodiment further reduces the number of wirings and the number of transistors necessary for driving the GIP by connecting the GIP circuit to the pixel TFT and the gate line as the horizontal clock wiring.

14 and 15, the vertical clock wirings are arranged in parallel with the data lines. The gate lines also serve as a horizontal clock wiring. Thus, this embodiment has no separate horizontal clock wiring. The vertical clock wirings and gate lines are crossed with an insulating layer interposed therebetween. The vertical clock wirings and the gate lines to which the same shift clock is applied are connected to each other through the contact holes passing through the insulating layer at the intersections.

In the GIP circuit, three TFTs (T21 to T23) are connected to the first pixel TFT (TFT1) and the first pixel electrode arranged in the Nth (N is a positive integer) line of the display panel (PNL). The first TFT T21 precharges the Q1 node in response to the start pulse VST or the carry signal received from the previous stage. The gate and the drain of the first TFT (T21) are connected to the VST line parallel to the gate line and operate as a diode. The VST wiring is supplied with the start pulse VST or the carry signal Vout (N-2) received from the previous stage. The source of the first TFT (T21) is connected to the Q node (Q).

The second TFT T22 discharges the node Q1 in response to the voltage of the second gate line G2. The gate of the second TFT T22 is connected to the second gate line G2. CLK2 is applied to the second gate line G2 and a second gate pulse is applied through the third TFT T23 of the (N + 1) -th line. Since the VST wiring maintains the low level voltage when CLK2 is applied to the gate line G2, the voltage of the node Q1 is discharged to the VST wiring potential when the second TFT T22 is turned on. The drain of the second TFT (TT22) is connected to the node Q1, and the source of the second TFT (T22) is connected to the second gate line G2.

The third TFT T23 pre-charges the Q2 node of the (N + 1) th line in response to the voltage of the first gate line G1 in response to the Q1 node voltage. CLK1 is applied to the first gate line G1. Since the third TFT (T23) is turned on only when the node Q1 is charged, the node Q2 is charged only when the node Q1 is charged and the node CLK1 is applied to the first gate line G1. The gate of the third TFT (T23) is connected to the node Q1. The drain of the third TFT T23 is connected to the first gate line G1 for receiving CLK1 and the source of the third TFT T23 is connected to the node Q2.

A fourth TFT (T24) is disposed between the first pixel TFT (TFT1) and the first pixel electrode (PXL1). The fourth TFT (T24) is turned on when the node Q1 is charged to connect the first pixel TFT (TFT1) to the first pixel electrode (PXL1). Due to the fourth TFT (T24), the data voltage is supplied to the first pixel electrode (PXL1) only when the first pixel TFT (TFT1) is turned on and the node Q1 is charged. The gate of the fourth TFT (T24) is connected to the node Q1. The drain of the fourth TFT T24 is connected to the source of the first pixel TFT (TFT1), and the source of the fourth TFT T24 is connected to the first pixel electrode PXL1.

The first pixel TFT (TFT1) is turned on in response to the first gate pulse from the first gate line G1 to supply the data voltage from the data line DL to the fourth TFT (T24). The first gate pulse is raised to the CLK1 voltage. The gate of the first pixel TFT (TFT1) is connected to the first gate line. The drain of the first pixel TFT (TFT1) is connected to the data line (DL), and the source of the first pixel TFT (TFT1) is connected to the drain of the fourth TFT (T24).

In the GIP circuit, two TFTs T22 and T23 are connected to the second pixel TFT (TFT2) and the second pixel electrode PXL disposed in the (N + 1) th line of the display panel PNL. Since the operation of these switches is similar to that described above, a description thereof will be omitted. CLK2 is applied to the second gate line G2 through the vertical clock line.

17 and 18 are diagrams illustrating clock wirings in a bezel region outside the pixel array.

17 and 18, clock wirings and VST wiring may be disposed in a bezel area BA outside the pixel array AA. The source drive IC may be adhered to the bezel area BA or the COF on which the source drive IC is mounted may be adhered.

17, the bezel area BA includes clock wirings in the horizontal direction. The " CLK Link " is the portion where the horizontal clock wirings arranged in the bezel area BA are connected to the vertical clock wirings of the pixel array AA. The " Data Link " is the portion to which the output terminals of the source drive IC or COF and the data lines DL are connected.

18 shows an example in which there are no horizontal clock wirings in the bezel area BA. In Fig. 18, " CLK Link " is an example in which the vertical clock wirings in the bezel area BA are extended as they are to the pixel array AA.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

PNL: Display panel SIC: Source drive IC
104: Gate driver TCON: Timing controller
AD: GIP circuit DL (D1 to D24): Data line
GL (G1 to G8): Gate line CL, CL1, CL2, CLV, CLH: Clock wiring
TFT: Pixel TFTs T1 to T5, T11 to T14, T21 to T24: transistors of a GIP circuit

Claims (8)

A pixel array in which data lines and gate lines are crossed, pixels having pixel TFTs and pixel electrodes are arranged in a matrix form; And
And a shift register distributed within the pixel array,
Wherein the pixel array includes clock wirings for supplying a shift clock to the shift register.
The method according to claim 1,
The shift register includes:
A first TFT which charges the Q node in response to a start pulse or an output signal of a previous stage;
A second TFT for discharging the Q node in response to an output signal of a next stage;
A third TFT for charging the output terminal in response to the Q-node voltage when the N-th (N is a positive integer) clock signal is input to raise the voltage of the gate pulse;
A fourth TFT for discharging a voltage of the output terminal in response to an (N-2) -th clock signal;
And a fifth TFT for discharging the Q node in response to the (N-1) -th clock signal.
The method according to claim 1,
The shift register
A first TFT which charges the Q node in response to a start pulse or an output signal of a previous stage;
A second TFT for discharging the Q node in response to a Nth (N is a positive integer) clock signal;
A third TFT which charges the voltage of the output terminal in response to the Q node voltage to raise the voltage of the gate pulse; And
And a fourth TFT for discharging a voltage of the output terminal to a clock wiring supplied with the Nth clock signal in response to an (N-2) th clock signal generated in an opposite phase to the Nth clock signal.
The method according to claim 1,
The shift register
A first TFT for charging a first Q node in response to a start pulse or an output signal of a previous stage;
A second TFT for discharging the first Q node in response to a voltage of a second gate line; And
And a third TFT responsive to the Q1 node voltage for charging the Q2 node in response to the voltage of the first gate line,
Wherein a first clock signal is applied to the first gate line and a second clock signal is applied to the second gate line.
5. The method of claim 4,
The pixel connected to the shift register,
And a fourth TFT connected between the pixel TFT and the pixel electrode to turn on when the node Q1 is charged to connect the pixel TFT to the pixel electrode.
A display panel including a pixel array in which pixels having a pixel TFT and a pixel electrode are arranged in a matrix and in which data lines and gate lines are crossed and a gate drive circuit for supplying gate pulses to the gate lines using a shift register A display device comprising:
Wherein the shift register is distributed on the display panel in the pixel array or in a bezel area outside the pixel array,
The shift register
A first TFT which charges the Q node in response to a start pulse or an output signal of a previous stage;
A second TFT for discharging the Q node in response to a Nth (N is a positive integer) clock signal;
A third TFT which charges the voltage of the output terminal in response to the Q node voltage to raise the voltage of the gate pulse; And
And a fourth TFT for discharging a voltage of the output terminal to a clock wiring supplied with the Nth clock signal in response to an (N-2) -th clock signal generated in an opposite phase to the Nth clock signal.
A display panel including a pixel array in which pixels having a pixel TFT and a pixel electrode are arranged in a matrix and data lines and gate lines are crossed and a gate drive circuit for supplying a gate pulse to the gate lines using a shift register In the display device,
Wherein the shift register is distributed on the display panel in the pixel array,
The shift register
A first TFT for charging a first Q node in response to a start pulse or an output signal of a previous stage;
A second TFT for discharging the first Q node in response to a voltage of a second gate line; And
And a third TFT responsive to the Q1 node voltage for charging the Q2 node in response to the voltage of the first gate line,
Wherein a first clock signal is applied to the first gate line and a second clock signal is applied to the second gate line.
8. The method of claim 7,
The pixel connected to the shift register,
And a fourth TFT connected between the pixel TFT and the pixel electrode to turn on when the Q1 node is charged to connect the pixel TFT to the pixel electrode.

Images