KR102411379B1 - Display panel and display device using the same - Google Patents

Abstract

The present invention relates to a display panel and a display device using the same, and the display panel includes wirings for supplying timing control signals and driving voltages necessary for driving a gate driving circuit. The wirings include a first wiring divided into a 1a wiring and a 1b wiring, a second wiring longer than each of the 1a wiring and the 1b wiring and connected to a first flexible circuit board, and the 1a wiring and the first wiring and a third wiring longer than each of the 1b wirings and connected to the second flexible circuit board. The present invention can reduce the size of the bezel area and increase the yield of the COF bonding process by using such a wiring structure.

Description

DISPLAY PANEL AND DISPLAY DEVICE USING THE SAME

The present invention relates to a display panel in which a pixel array and a gate driving circuit are mounted together on the same substrate, and a display device using the same.

Electroluminescence Display (ELD) such as Liquid Crystal Display (LCD), Organic Light Emitting Diode Display (OLED Display), Field Emission Display (FED) , Plasma Display Panel (PDP), electrophoresis display (Electrophoresis Display, EPD), such as various flat panel display devices are commercially available.

A liquid crystal display displays an image by controlling an electric field applied to a liquid crystal layer to modulate light incident from a backlight unit. In an active matrix type liquid crystal display device, a thin film transistor (hereinafter, referred to as “TFT”) is disposed in each pixel, and the TFTs are used to drive pixels. Such liquid crystal display devices are rapidly developing toward larger sizes and higher resolutions as a result of advances in process technology and R&D.

A display panel of a liquid crystal display includes an upper plate and a lower plate bonded to each other with a liquid crystal layer interposed therebetween. An alignment layer is formed on the surface of the substrate in contact with the liquid crystal layer on each of the upper and lower plates. The alignment layer sets a pre-tilt angle of the liquid crystal molecules. In order to maintain a cell gap of the liquid crystal layer, a spacer is disposed between the upper plate and the lower plate. The lower plate may include a TFT array formed on the lower glass substrate. The upper plate may include a color filter array formed on the upper glass substrate. A polarizing plate is attached to each of the upper and lower plates.

The manufacturing process of the liquid crystal display device includes substrate cleaning, substrate patterning process, alignment layer forming/rubbing process, substrate bonding and liquid crystal dropping process, driving circuit mounting process, inspection process, repair process, module assembly process, and the like.

In the substrate cleaning process, foreign substances contaminated on the surfaces of the upper and lower glass substrates of the display panel are removed with a cleaning solution. In the substrate patterning process, a signal wiring including a data line and a gate line, a TFT, a pixel electrode, a common electrode, and the like are formed on a lower glass substrate. In the substrate patterning process, a black matrix, a color filter, and the like are formed on the upper glass substrate. In the alignment film formation/rubbing process, an alignment film is applied on glass substrates and the alignment film is rubbed with a rubbing cloth or subjected to photo-alignment treatment. Through this series of processes, the data lines to which the video data voltage is supplied to the lower glass substrate, the gate lines intersected with the data lines and sequentially supplied with a scan signal, that is, a gate pulse, and the intersection of the data lines and the gate lines A TFT array including TFTs formed in the portion, pixel electrodes connected to the TFTs, a storage capacitor, and the like is formed. The common electrode is formed on the upper glass substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, etc., and horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode It is formed on the lower glass substrate together with the pixel electrode in the driving method. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate.

In the substrate bonding and liquid crystal dropping process, liquid crystal is dropped by drawing a sealant on one of the upper and lower glass substrates of the display panel, and then the upper glass substrate and the lower glass substrate are bonded with the sealant. The liquid crystal layer is defined as the liquid crystal region defined by the sealant.

The drive circuit mounting process uses the COG (Chip On Glass) process or the TAB (Tape Automated Bonding) process to display the drive IC (Integrated Circuit, IC) in which the data driving circuit is integrated with an anisotropic conductive film (ACF). Adhesive to the data pads of the panel. The gate driving circuit is formed directly on the lower glass substrate by the GIP (Gate In Panel) process, or is integrated into an IC and is used as an ACF in the TAB (Tape Automated Bonding) process in the driving circuit mounting process. Gate pads of the display panel can be attached to The driving circuit mounting process connects ICs and a printed circuit board (PCB) with a flexible circuit board such as a flexible printed circuit board (FPC) and a flexible flat cable (FFC).

The inspection process includes inspection of the driving circuit, wiring inspection of data lines and gate lines formed on the TFT array substrate, inspection performed after pixel electrodes are formed, electrical inspection conducted after substrate bonding and liquid crystal dropping process, lighting inspection, etc. do. The repair process repairs defects found by the inspection process.

When the display panel is completed through the above-described series of processes, a module assembly process is performed. In the module assembly process, the backlight unit is aligned under the display panel, and the display panel and the backlight unit are assembled by using a guide/case member or the like.

The driving circuit of the flat panel display includes a data driving circuit that supplies a data voltage to data lines of a display panel, a gate driving circuit that supplies a gate pulse (or scan pulse) to gate lines (or scan lines) of the display panel; and a timing controller (TCON), etc., that controls overall operations of these driving circuits.

The IC chip on which the data driving circuit is integrated is mounted on a flexible circuit board, for example, a Chip on Film (COF), and the COF may be attached to the display panel with an ACF.

Recently, a technique of directly mounting a gate driving circuit together with a pixel array on a substrate of a display panel using a GIP process is being applied, centering on a liquid crystal display (LCD) and an organic light emitting diode display (OLED). Hereinafter, the gate driving circuit directly mounted on the substrate of the display panel will be referred to as a “GIP circuit”.

In order for the GIP circuit to operate normally, timing control signals such as a start pulse and a shift clock and driving voltages such as a gate high voltage VGH and a gate low voltage VGL are required. Timing control signals and driving voltages of the GIP circuit are supplied to the GIP circuit through dummy channel lines of the COF and line on glass (LOG) lines formed on the substrate of the display panel.

As the demand for ultra-high-resolution products continues to increase according to changes in the display market environment, GIP circuit technology suitable for ultra-high-resolution and high-speed driving display devices is required. As an example of an ultra-high-resolution, high-speed driving display device, a 98” display device driven with a resolution of 8K (7680 X 4320) and a frame rate of 240 Hz is being developed. As the resolution of the display device increases and the driving frequency increases, the timing control signal of the GIP circuit may increase and the driving voltage may increase. In this case, the pitch or pin pitch between the pins of the COF becomes narrow because the number of wirings of the COF and the pins connected to the wirings increases. In the ground COF bonding process, the frequency of occurrence of defects such as a short pitch between the COF and the wirings of the display panel increases, resulting in a reduction in yield.

The present invention provides a display panel capable of reducing a COF bonding process defect and reducing a bezel width in an ultra-high-resolution, high-speed driving display device and a display device using the same.

In the display panel of the present invention, a substrate is connected to data lines and gate lines, a pixel array is disposed, the data lines are separated into upper data lines and lower data lines, and on the substrate, in a bezel area outside the pixel array. a gate driving circuit disposed on the substrate to supply a gate pulse to the gate lines, and wirings disposed in a bezel area outside the pixel array on the substrate to supply timing control signals and driving voltages necessary for driving the gate driving circuit do.

The wirings include a first wiring divided into a 1a wiring and a 1b wiring, a second wiring longer than each of the 1a wiring and the 1b wiring and connected to a first flexible circuit board, and the 1a wiring and the first wiring and a third wiring longer than each of the 1b wirings and connected to the second flexible circuit board.

In the display device of the present invention, a substrate is connected to data lines and gate lines, a pixel array is disposed, the data lines are separated into upper data lines and lower data lines, and a data voltage is supplied to the upper data lines. a first flexible circuit board on which a data driving circuit is mounted and disposed on an upper end of the substrate; a second flexible circuit board on which a data driving circuit for supplying data voltages to the lower data lines is mounted and disposed at a lower end of the substrate; a gate driving circuit arranged in a bezel region outside the pixel array to supply a gate pulse to the gate lines, and a wiring arranged in a bezel region outside the pixel array to supply timing control signals and driving voltages necessary for the gate driving circuit include those

The wirings include a first wiring divided into a 1a wiring connected to the first flexible circuit board, a 1b wiring connected to the second flexible circuit board, and a length longer than each of the 1a wiring and the 1b wiring. a second wiring connected to the first flexible circuit board, and a third wiring longer than each of the 1a wiring and the 1b wiring and connected to the second flexible circuit board.

Among the signals necessary for driving the gate driving circuit, the present invention supplies a high-frequency signal that greatly affects the panel load to the gate driving circuit through divided LOG wirings connected to upper and lower COFs, while a low frequency signal and a driving voltage is supplied to the gate drive circuit through long LOG wires connecting either of the upper and lower COFs. As a result, the present invention uses a structure that asymmetrically connects the LOG wires connected to the gate driving circuit to the upper COFs and the lower COFs in an ultra-high-resolution, high-speed driving display device to reduce the number of pins of the COFs, thereby improving the yield of the COF bonding process. can increase

1 is a plan view schematically showing a display device according to an embodiment of the present invention.
FIG. 2 is an enlarged plan view of a part of the display panel shown in FIG. 1 .
3 is an enlarged plan view of the LOG wiring in FIG. 2 .
4 is a diagram illustrating dummy channels of a COF.
5 is a diagram schematically showing a part of the shift register configuration of the GIP circuit.
6 and 7 are diagrams illustrating an example in which a large-screen high-resolution display panel is driven in 4 divisions.
8 is a plan view illustrating an embodiment of LOG wires connected to a GIP circuit.
9A to 9E are plan views illustrating various embodiments of LOG wirings connected to a GIP circuit.
10 is a circuit diagram illustrating an example of a GIP circuit.
11 is a waveform diagram illustrating a gate timing control signal applied to the GIP circuit shown in FIG. 10 .
12 is a waveform diagram illustrating a Q node voltage, a QB node voltage, a carry signal voltage, and an output voltage of the GIP circuit shown in FIG. 10 .

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

The display device of the present invention may be implemented as any display device to which a GIP circuit is applicable, such as a flat panel display device such as a liquid crystal display (LCD) or an organic light emitting diode display (OLED Display). . In the following embodiments, a liquid crystal display will be mainly described as an example of a flat panel display device, but the present invention is not limited thereto. For example, the display device of the present invention may be any display device to which the in-cell touch sensor technology is applicable.

1 to 3 , a display device according to an exemplary embodiment of the present invention includes a display panel PNL and a driving circuit for writing input image data to the display panel PNL.

The driving circuit includes a data driving circuit that supplies a data voltage of an input image to data lines of the display panel PNL, and a gate pulse (or scan pulse) synchronized with the data voltage to the gate lines GL of the display panel PNL. ), and a timing controller TCON for controlling operation timings of the data driving circuit and the gate driving circuit. In FIG. 1 , the data driving circuit is connected to the data lines DL of the display panel PNL in an integrated form in the source driver IC SIC. The gate driving circuit is implemented as a GIP circuit and is directly formed on the lower substrate SUBS1 of the display panel PNL together with the pixel array AA and connected to the gate lines GL. The GIP circuit includes a shift register that receives a start pulse and a shift clock as inputs and sequentially outputs them in synchronization with clock timing.

The display panel PNL includes an upper plate and a lower plate bonded to each other with a liquid crystal layer interposed therebetween. The substrates may be glass substrates, but are not limited thereto. The display panel PNL includes pixels in which the data lines DL and the gate lines GL are arranged in a matrix form by a cross structure. The pixels include a TFT formed at the intersection of the data line GL and the gate line GL, a liquid crystal cell Clc connected to the TFT, and a storage capacitor Cst. The TFT supplies a data voltage input through the data line DL to the pixel electrode PXL in response to a gate pulse from the gate line GL. The liquid crystal cell Clc adjusts the refractive index of incident light according to the data voltage using liquid crystal molecules driven according to the electric field between the pixel electrode PXL and the common electrode COM.

A lower panel of the display panel PNL includes a TFT array formed on a lower substrate. The TFT array includes data lines DL, gate lines GL, TFTs, a pixel electrode PXL connected to the TFT, a common electrode COM, and a storage capacitor Cst. The upper plate of the display panel PNL includes a color filter array formed on an upper substrate. The color filter array includes a black matrix, a color filter, and the like. In the case of the COT (Color Filter on TFT) model, a color filter may be further formed on the TFT array of the lower plate.

The common electrode COM is formed on the upper substrate in the vertical electric field driving method, and is formed on the lower substrate together with the pixel electrode PXL in the horizontal electric field driving method. A polarizing plate having optical axes orthogonal to each other is attached on the upper substrate and the lower substrate of the display panel PNL, and an alignment layer for setting a pretilt angle of the liquid crystal is formed on the inner surface in contact with the liquid crystal.

A touch screen using an in-cell touch sensor may be implemented in the display panel PNL. The in-cell touch sensor is embedded in the pixel array AA of the display panel PNL. The in-cell touch sensor may be implemented as a capacitive-type touch sensor that senses a touch based on a change in capacitance before and after the touch.

The timing controller (TCON) receives input image data from an external host system and transmits it to the source drive IC (SIC). The timing controller TCON receives timing signals such as vertical/horizontal synchronization signals, data enable signals, and main clock signals, and generates timing control signals for controlling operation timings of the source drive IC (SIC) and the GIP circuit. The host system may be any one of a television (Television) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

Source drive IC (SIC) converts digital video data of input image into analog positive/negative gamma compensation voltage under the control of timing controller (TCON) to generate positive/negative analog data voltage and converts the data voltage to data output to the lines DL. The source drive IC (SIC) may be mounted on a bendable flexible circuit board, for example, a COF.

The source PCB (Printed Circuit Board, SPCB) may be divided into two. The COFs are dividedly connected to two source PCBs (SPCB). The COFs are adhered to the lower substrate SUBS1 and the source PCB SPCB of the display panel PNL through an anisotropic conductive film (ACF). The input pins of the COFs ( FIGS. 4 and 82 ) are electrically connected to the output terminals of the source PCB (SPCB). Output pins ( FIGS. 8 and 84 ) of the source COFs COF are electrically connected to data pads formed on the lower substrate SUBS1 of the display panel PNL through the ACF.

The GIP circuit is formed in the bezel area BZ of the display panel PNL together with the LOG lines. The GIP circuit outputs a gate pulse synchronized with the data voltage to the gate lines GL under the control of the timing controller TCON. The GIP circuit includes a shift register that starts driving in response to the start pulse VST and shifts the output according to the timing of the shift clock GCLK. A shift register includes a number of stages that are cascadedly connected. The GIP circuit sequentially selects pixels to be written data line by line by shifting the gate pulse according to the shift clock timing from the timing controller TCON using the shift register.

A gate timing control signal such as a start pulse and a shift clock generated from the timing controller TCON is input to the shift register. A level shifter (LS) shifts the voltage level of the gate timing control signal to swing the gate timing control signal between a gate high voltage (VGH) and a gate low voltage (VGL). converted to and transferred to the shift register. The gate high voltage VGH is set to a voltage higher than the threshold voltage of the TFTs constituting the pixel and the GIP circuit (shift register). The gate low voltage VGL is set to a voltage lower than the threshold voltage of the TFTs constituting the pixel and the GIP circuit (shift register).

The timing controller TCON and the level shifter LS may be disposed on the control board CPCB. The control board (CPCB) may be connected to the source PCB (SPCB) through a flexible flat cable (FFC). A gate timing control signal necessary for driving the shift register, that is, a start pulse and a shift clock, as well as a gate high voltage (VGH), a gate low voltage (VGL), and the like are dummy channel wirings formed on the COF film. (80 of FIG. 8 ) and the LOG wirings formed on the lower substrate of the display panel PNL may be supplied to the GIP circuit.

The COF includes source channels SOUT connected to the source drive IC SIC and dummy channels DUM as shown in FIG. 4 . Each of the source channels SOUT and the dummy channels DUM includes an input pin 82 , an output pin 84 , and wires connecting the pins 82 and 84 . In FIG. 4 , reference numeral 80 denotes dummy channel wirings disposed in the dummy channels DUM. The input pin 82 is connected to the output pad of the source PCB SPCB through the ACF, and the output pin 84 is connected to the pads of the lower substrate SUBS1 of the display panel PNL through the ACF.

Among the COFs, the COFs disposed at a corner portion of the display panel close to the GIP circuit are used to supply gate timing control signals and driving voltages of the GIP circuit to the GIP circuit. Gate timing control signals and driving voltages of the GIP circuit are transmitted to the GIP circuit via the LOG lines through the dummy channels DUM of the COFs.

5 is a diagram schematically showing a part of the shift register configuration of the GIP circuit.

Referring to FIG. 5 , the GIP circuit may be disposed on one edge of the display panel PNL or dividedly disposed on both edges of the display panel PNL. The GIP circuit includes a shift register that sequentially shifts gate pulses under the control of a timing controller (TCON). The transistors constituting the shift register are made of one or more of a TFT including amorphous silicon (a-Si), an oxide TFT (TFT) including an oxide semiconductor, and a TFT (LTPS TFT) including a low temperature poly silicon (LTPS). may include The GIP circuit may be implemented with any known circuit.

The pin pitch of the COF and the pitch of the pad portion of the display panel PNL to which the COF is bonded become narrower as the resolution and driving frequency of the display device increase. As the resolution of the display panel increases, resistance and capacitance of the display panel increase, thereby increasing the panel load. This increase in panel load and driving frequency causes non-uniformity in charging of pixels and deterioration in charging. In order to solve this problem, there is a method of increasing the number of shift clocks supplied to the GIP circuit and lengthening the overlapping width of the shift clocks to lengthen the gate pulse width supplied to the pixels.

According to the present invention, the display panel can be divided into two vertically or quadrupled as shown in FIGS. 6 and 7 in a large-screen, high-resolution, high-speed driving display device. Here, it does not mean that the display panel PNL is physically divided. The pixel array AA is formed on a single substrate and is dividedly driven into a plurality of pixel array blocks. The display panel PNL is driven in four divisions along the virtual horizontal boundary line HL and the virtual vertical boundary line VL. The horizontal boundary line HL divides the central portion of the pixel array AA into vertical halves along the horizontal direction X in the pixel array AA. The vertical boundary line VL bisects the central portion of the pixel array AA in the vertical direction Y to the left and right. Accordingly, the virtual horizontal boundary line HL and the virtual vertical boundary line VL intersect at the central portion of the pixel array.

At least some of the data lines DL and the LOG lines may be separated on the horizontal boundary line HL. The gate lines GL may be separated on a vertical boundary line VL. The gate lines GL may be separated on a vertical boundary line VL.

The pixel array AA includes a first pixel array block A1 driven by a first driving circuit, a second pixel array block A2 driven by a second driving circuit, and a second pixel array block A2 driven by a third driving circuit It is divided into three pixel array blocks A3 and a fourth pixel array block A4 driven by a fourth driving circuit. Each of the first to fourth driving circuits is independently implemented with the circuit configuration shown in FIG. 1 and operates in synchronization with each other.

According to the present invention, the upper and lower halves of the display panel PNL are simultaneously driven by dividing the high-resolution and high-speed driving display device by dividing the data lines vertically as shown in FIGS. As a result, according to the present invention, the timing of one horizontal period can be sufficiently secured, and the panel load including resistance and capacitance can be reduced due to the division of data lines and gate lines.

In the high-resolution high-speed driving display device, the number of gate timing control signals and the number of driving voltages may increase. This may cause an increase in the size of the bezel region BZ of the display panel and decrease the fin pitch of the COF and the pad pitch of the display panel, thereby reducing the yield in the COF bonding process. The bezel area BZ of the display panel is a non-display area at the edge of the display panel outside the pixel array.

In order to reduce the number of gate timing control signals and driving voltages without reducing the number of driving voltages, the COF bonding process has an asymmetric structure on a substrate by LOG wirings supplied with low-frequency gate timing signals and driving voltages that are hardly affected by panel load. to form with The asymmetric LOG wiring structure reduces the number of dummy channels of the COFs of the display panel PNL and increases the pin pitch of the COF and the pad pitch of the display panel, thereby reducing the COF bonding defect.

8 is a plan view illustrating an embodiment of LOG wires connected to a GIP circuit. 9A to 9E are plan views illustrating various embodiments of LOG wirings connected to a GIP circuit.

8 to 9E , the display panel PNL of the present invention includes a plurality of LOG wires LOG1u, LOG1d, LOG2, and LOG3 that supply gate timing control signals and driving voltages to the GIP circuit. According to the present invention, the display panel PNL of FIGS. 6 and 7 can be dividedly driven by connecting the upper COF (COFu) and the lower COF (COFd) to the display panel.

The first LOG wirings LOG1u and LOG1d are separated on a horizontal boundary line HL crossing the central portion of the pixel array AA and divided into 1a LOG wirings LOG1u and 1b LOG wirings LOG1d. lose The 1a LOG wirings LOG1u and the 1b LOG wirings LOG1d are formed so that the number of pins connected to the first LOG wirings LOG1u and LOG1d in the upper COF (COFu) and the lower COF (COFd) is the same. is the same number. The COFs COFu and COFd can be shared only when the upper COF (COFu) and the lower COF (COFd) have the same number of pins.

The upper COF COFu is connected to the 1a LOG lines LOG1u at the upper end of the display panel PNL. The lower COF COFd is connected to the 1b LOG lines LOG1d at the lower end of the display panel PNL. The upper COF (COFu) and the lower COF (COFd) simultaneously supply high-frequency gate timing signals to the first LOG lines LOG1u and LOG1d. For example, the upper COF(COFu) supplies the first shift clock GCLK1 to the upper wiring of the first clock among the 1a LOG wirings LOG1u, and the lower COF(COFd) transmits the first shift clock GCLK1 ) is supplied to the lower wiring of the first clock among the 1b LOG wirings LOG1d.

The first LOG wirings LOG1u and LOG1d have a short wiring length. When the wiring length is short, the RC delay of the signal supplied through the wiring becomes small because the resistance and capacitance of the wiring are small. When a high-frequency gate timing control signal, for example, a shift clock, has a large panel load, a rising time and a falling time of the clock are delayed due to the RC delay, which may lead to a decrease in charging of the pixel. Accordingly, it is preferable that the gate timing control signals having such a high frequency are supplied through the first LOG wirings LOG1u and LOG1d having a short wiring length.

Each of the second LOG lines LOG2 is not separated and formed to be elongated along the bezel area BZ of the display panel PNL. The upper COF (COFu) is connected to the second LOG lines LOG2 at the upper end of the display panel PNL. Each of the third LOG lines LOG3 is not separated and formed to be elongated along the bezel area BZ of the display panel PNL. The lower COF COFd is connected to the third LOG lines LOG3 at the lower end of the display panel PNL. The second LOG wires ( LOG2) and the third LOG wirings LOG3 have the same number. The upper COF (COFu) and the lower COF (COFd) must have the same number of pins to share the COFs COFu and COFd.

The upper COF (COFu) supplies a low frequency gate timing signal and a driving voltage to the second LOG lines LOG2 . The lower COF (COFd) supplies a low frequency gate timing signal and a driving voltage to the third LOG lines LOG3 . The gate timing signal and the driving voltage supplied through the second LOG lines LOG2 may be set differently from the gate timing signal and the driving voltage supplied through the third LOG lines LOG3 . For example, the upper COF(COFu) supplies the first gate high voltage VGH_O to the first VGH line among the second LOG lines LOG2, and the lower COF(COFd) provides the second gate high voltage VGH_E. is supplied to the second VGH wiring among the second LOG wirings LOG2. The first and second gate high voltages VGH_E and VGH_O are alternately applied to the first and second QB nodes of the GIP circuit to relieve DC gate bias stress of the pull-down transistors.

Since the second and third LOG wirings LOG2 and LOG2 have long wiring lengths, if the frequency of the signal supplied through the second and third LOG wirings LOG2 and LOG2 is high, the panel load RC delay becomes large. The low-frequency gate timing signal or driving voltage is hardly affected by the panel load because of its short frequency.

A signal having a relatively high frequency among the gate timing signals, for example, a shift clock is supplied to the GIP circuit through the first LOG wirings LOG1u and LOG1d. Among the gate timing signals, signals having a relatively low frequency, for example, signals such as VST and VNEXT and driving voltages VGH and VSS, are GIP through the second LOG wiring LOG2 and the third LOG wiring LOG3. supplied to the circuit. In other words, according to the present invention, a gate timing control signal and a driving voltage having a relatively low frequency are supplied to the second and third LOG lines LOG2 and LOG3 . As a result, according to the present invention, the yield of the COF bonding process can be increased by reducing the number of fins of the upper COF (COFu) and the lower COF (COFd) to increase the fin pitch of the COF and the pad pitch of the display panel PNL.

The low-frequency gate timing control signal supplied through the second and third LOG lines LOG2 and LOG3 includes one or more of the following VST, VNEXT, and RST signals. The driving voltages supplied through the second and third LOG lines LOG2 and LOG3 include VGH, VGH_E, VGH_O, VGL(VSS1, VSS2), and a ground voltage GND as follows.

VGH_E, VGH_O: 25Hz

VGH, VSS1, VSS2, GND: 0Hz

VST, VNEXT2, VNEXT2, VNEXT3, RST: 240Hz

The second and third LOG wires LOG2 and LOG3 may be disposed in various shapes as shown in FIGS. 8 to 9E .

10 is a circuit diagram illustrating an example of a GIP circuit. 11 is a waveform diagram illustrating a gate timing control signal applied to the GIP circuit shown in FIG. 10 . 12 is a waveform diagram illustrating a Q node voltage, a QB node voltage, a carry signal voltage, and an output voltage of the GIP circuit shown in FIG. 10 . It should be noted that the GIP circuit of the present invention is not limited to Figs.

10 and 12, the GIP circuit of the present invention includes an n-th (n is a positive integer) stage (S(n)) and an n+1-th stage (S(n+1)) that are dependently connected. include The nth stage S(n) and the n+1th stage S(n+1) start to be driven in response to a start pulse VST or a carry signal from a previous stage, and shift clock GCLK timing In synchronization with , the output voltages Vout(n), Vout(n+1) and the carry signals Carry(n), Carry(n+1) are output. The output voltages Vout(n) and Vout(n+1) are sequentially supplied to the gate lines GL of the display panel PNL. The carry signals Carry(n) and Carry(n+1) are input to the VST terminal of the next stage (S(n+4), S(n+5)), and the stages S(n+4), S(n+5)) The upper dummy stage (not shown) outputs a carry signal for precharging the Q nodes of the first to third stages disposed on the upper end of the display panel PNL. The stage is not connected to the gate lines and is connected to the VST terminal of the first to third stages In general, the VNEXT signal is the previous stage in the next stage or the lower dummy stage to induce the Q node discharge of the previous stage. V When the display panel PNL is driven vertically as shown in FIGS. 6 and 7 , a separate VNEXT signal is generated from the timing controller 106 because a dummy stage cannot be added near the boundary line.

The circuit configuration of the stages S(n) and S(n+1) is substantially the same, and the GIP circuit configuration will be described by taking the n-th stage S(n) as an example.

The n-th stage S(n) is a pull-up transistor T6C, T6, a pull-down transistor T7C, T7, a Q node controlling the pull-up transistor T6C, T6, a pull-down transistor (T6C, T6) a QB (or Q Bar) node and a control unit for controlling charging and discharging of the Q node and the QB node according to an input signal, the control unit including a plurality of transistors T1, T3R, T3N, T3, T4A, T4, T4Q; T5Q, T5, T5QI). Transistors of the GIP circuit are implemented as TFTs of an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure in the embodiment, but are not limited thereto. Hereinafter, transistors will be described with reference numerals without separate names.

The n-th stages S(n) precharge the Q node in response to a start pulse VST received through the VST terminal or a carry signal Carry(n-3) received from a previous stage and perform a shift clock CLK) When this is input, the voltage of the output terminal is increased to the gate high voltage VGH to generate the output voltage Vout(n) as the gate high voltage VGH.

T1 supplies the gate high voltage VGH to the Q node Q1_node in response to the start pulse VST or the carry signal Carry(n-3) received from the n-3 stage to make the Q node Q1_node Pre-charging. The gate of T1 is connected to the VST terminal. The start pulse VST or the carry signal Carry(n-3) received from the previous stage is supplied to the VST terminal. The drain of T1 is connected to the VGH terminal to which the gate high voltage VGH is supplied. The source of T1 is connected to the Q node (Q1_node).

T3R initializes the Q node Q1_node by discharging the Q node Q1_node to the VSS1 potential in response to the reset pulse RST. The gate low voltage VGL is divided into VSS1 and VSS2. VSS1 may be set to a lower voltage than VSS2. The gate of T3R is connected to the RST terminal. The drain of T3R is connected to the Q node (Q1_node), and the source of T3R is connected to the VSS1 terminal.

T3N discharges the Q node (Q1_node) to the potential of VSS1 in response to the carry signal (Carry(n+4)) or the VNEXT signal received from the next stage. The gate of T3R is connected to the VNEXT terminal. The carry signal (Carry(n+4)) or VNEXT signal received from the next stage is supplied to the VNEXT terminal. The drain of T3N is connected to the Q node (Q1_node), and the source of T3N is connected to the VSS1 terminal.

T3 discharges the Q node Q1_node in response to the voltage of the QB node Q_ODD. The QB node may be divided into two to relieve DC gate bias stress of the pull-down transistors T7 and T7C by alternately charging and discharging the gate voltages of the pull-down transistors T7 and T7C. In this case, T3 is split in two. The gate of the first T3 is connected to the first QB node QB_ODD. The drain of the first T3 is connected to the Q node Q1_node, and the source of the first T3 is connected to the VSS1 terminal. The gate of the second T3 is connected to the second QB node QB_EVEN. The drain of the first T3 is connected to the Q node Q1_node, and the source of the first T3 is connected to the VSS1 terminal.

VGH_O and VGH_E are alternating signals generated by VGH alternately. The first QB node QB_ODD is charged with VGH_O, and the second QB node QB_EVEN is charged with VGH_E input through the next stage. T4A supplies VGH_O to T4. The gate of T4A is connected to the gate of T4 and the drain of T4Q. The drain of T4A is connected to the VGH_O terminal, and the source of T4A is connected to the first QB node QB_ODD. When T4A is turned on while T4Q is off, T4 operates as a diode to supply VGH_O to the first QB node QB_ODD to charge the first QB node QB_ODD. The gate of T4 is connected to the source of T4A and the drain of T4Q. The drain of T4 is connected to the VGH_O terminal, and the source of T4 is connected to the first QB node QB_ODD. T4Q is turned on in response to the voltage of the Q node Q1_node to prevent the pull-up transistors T6C and T6 and the pull-down transistors T7 and T7C from being turned on at the same time. Discharge the gate voltage of T4. The gate of T4Q is connected to the Q node (Q1_node). The drain of T4Q is connected to the drain of T4A and the gate of T4, and the source of T4Q is connected to the VSS1 terminal.

T5Q discharges the first QB node QB_ODD in response to the voltage of the Q node Q1_node. The gate of T5Q is connected to the Q node (Q1_node). The drain of T5Q is connected to the first QB node QB_ODD, and the source of T5Q is connected to the VSS1 terminal.

T5 discharges the first QB node QB_ODD in response to the start pulse VST or the carry signal Carry(n-3) received from the n-3 th stage. The gate of T5Q is connected to the VST terminal. The start pulse VST or the carry signal Carry(n-3) received from the previous stage is supplied to the VST terminal. The drain of T5 is connected to the first QB node QB_ODD, and the source of T5 is connected to the VSS1 terminal.

T5QI connects the drain and source of T4Q in response to the voltage of the Q node (Q2_node) of the next stage (S(n+)). The gate of T5QI is connected to the Q node Q2_node of the next stage S(n+). The drain of T5QI is connected to the drain of T4Q, and the source of T5QI is connected to the source of T4Q.

T6C is a pull-up transistor that rises the carry signal Carry(n) when the shift clock GCLK1 is input while the Q node Q1_node is precharged. The gate of T6C is connected to the Q node (Q1_node). The drain of T6C is connected to the GCLK terminal, and the source of T6C is connected to the first output terminal and the drain of T7C. A gate shift clock GCLK1 is supplied to the GCLK terminal.

T6 is a pull-up transistor that increases the output voltage Vout(n) when the shift clock GCLK1 is input while the Q node Q1_node is precharged. The gate of T6 is connected to the Q node (Q1_node). The drain of T6 is connected to the GCLK terminal, and the source of T6C is connected to the second output terminal and the drain of T7.

T7 and T7C are pull-down transistors that poll the carry signal Carry(n) and the output voltage Vout(n) in response to the voltage of the QB node and discharge the voltages of the first and second output terminals. When the QB node is divided into the first and second QB nodes QB_ODD and QB_EVEN, T7 and T7C are divided into two. The gate of the first T7C is connected to the first QB node QB_ODD. The drain of the first T7C is connected to the first output terminal, and the source of the first T7C is connected to the VSS1 terminal. The gate of the second T7C is connected to the second QB node QB_EVEN. The drain of the second T7C is connected to the first output terminal, and the source of the first T7C is connected to the VSS1 terminal. The gate of the first T7 is connected to the first QB node QB_ODD. The drain of the first T7 is connected to the second output terminal, and the source of the first T7 is connected to the VSS2 terminal. The gate of the second T7 is connected to the second QB node QB_EVEN. The drain of the second T7 is connected to the second output terminal, and the source of the second T7 is connected to the VSS2 terminal.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

PNL : Display panel AA, A1~A4 : Pixel array
GIP: Gate driving circuit SPCB: Soso PCB
CPCB: Control board LOG, LOG1d, LOG1u, LOG1, LOG2, LOG3: LOG wiring
T1~T7 : Transistor

Claims (8)

a substrate connected to the data lines and the gate lines, on which a pixel array is disposed, the data lines being separated into upper data lines and lower data lines;
a gate driving circuit disposed in a bezel region outside the pixel array on the substrate to supply a gate pulse to the gate lines; and
and wirings disposed in a bezel area outside the pixel array on the substrate to supply timing control signals and driving voltages necessary for driving the gate driving circuit;
The wires are
a first wiring divided into a 1a wiring and a 1b wiring;
a second wiring longer than each of the 1a wiring and the 1b wiring and connected to the first flexible circuit board; and
and a third wiring that is longer than each of the first and first wirings and is connected to a second flexible circuit board. The method of claim 1,
a display panel in which the data lines and the first wiring are vertically divided along an imaginary horizontal boundary line that crosses a central portion of the pixel array and bisects the pixel array. The method of claim 1,
The number of the 1a wirings is the same as the number of the 1b wirings,
A display panel in which the number of the second wires is the same as the number of the third wires. The method of claim 1,
a signal having a relatively high frequency among the timing control signals is supplied to the gate driving circuit through the first wiring;
A display panel in which a signal having a relatively low frequency among the timing control signals and driving voltages are supplied to a gate driving circuit through the second and third wirings. 5. The method of claim 4,
The gate driving circuit is
a shift register that starts driving in response to a start pulse and shifts an output according to a shift clock timing;
wherein the shift register comprises a plurality of stages connected cascadingly;
The relatively high frequency signal includes the shift clock,
The relatively low frequency signal includes at least one of the start pulse, a signal for discharging the Q node of the previous stage, and a reset pulse for simultaneously initializing the stages,
The driving voltage includes a gate high voltage equal to or greater than a threshold voltage of transistors constituting the gate driving circuit, a gate low voltage lower than the threshold voltage of the transistors, and a ground voltage. a substrate connected to the data lines and the gate lines, on which a pixel array is disposed, the data lines being separated into upper data lines and lower data lines;
a first flexible circuit board on which a data driving circuit for supplying a data voltage to the upper data lines is mounted and disposed on the upper side of the board;
a second flexible circuit board on which a data driving circuit for supplying a data voltage to the lower data lines is mounted and disposed at a lower end of the board;
a gate driving circuit disposed in a bezel region outside the pixel array to supply a gate pulse to the gate lines; and
and wirings disposed in a bezel area outside the pixel array to supply timing control signals and driving voltages necessary for the gate driving circuit;
The wires are
a first wiring divided into a 1a wiring connected to the first flexible circuit board and a 1b wiring connected to the second flexible circuit board;
a second wiring longer than each of the 1a wiring and the 1b wiring and connected to the first flexible circuit board; and
and a third wire connected to the second flexible circuit board, which is longer than the length of each of the first and second wires 1a and 1b. 7. The method of claim 6,
a signal having a relatively high frequency among the timing control signals is supplied to the gate driving circuit through the first wiring;
A display device in which a signal having a relatively low frequency among the timing control signals and driving voltages are supplied to the gate driving circuit through the second and third wirings. 8. The method of claim 7,
The gate driving circuit is
a shift register that starts driving in response to a start pulse and shifts an output according to a shift clock timing;
wherein the shift register comprises a plurality of stages connected cascadingly;
The relatively high frequency signal includes the shift clock,
The relatively low frequency signal includes at least one of the start pulse, a signal for discharging the Q node of the previous stage, and a reset pulse for simultaneously initializing the stages,
The driving voltage includes a gate high voltage equal to or greater than a threshold voltage of transistors constituting the gate driving circuit, a gate low voltage lower than the threshold voltage of the transistors, and a ground voltage.

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