KR102489512B1 - Liquid crystal display device having common voltage compensatiing circuit - Google Patents

Abstract

The present invention relates to a liquid crystal display device capable of preventing image quality degradation due to a reduction in wiring width of a common voltage supply line or reducing a bezel width, and includes a display panel, a data driving circuit, a gate driving circuit, and a common voltage compensating circuit. . The display panel displays an input image and includes a pixel array including a pixel electrode to which a data voltage is supplied and a common electrode to which a common voltage is supplied. A data driving circuit supplies data voltages to data lines of the display panel. The gate driving circuit includes a level shifter and a shift register. The level shifter outputs shift clocks and a start pulse. The shift register receives a gate low voltage and a gate high voltage, shifts the start pulse according to the shift clock, sequentially shifts the gate pulse, and supplies it to gate lines. The common voltage compensating circuit receives a gate sensing voltage obtained by sensing the gate lines through a gate low voltage supply line to which the gate low voltage is supplied, extracts a ripple component included in the gate sensing voltage, and inverts the ripple component. The amplified common voltage compensation voltage is supplied to the common electrode.

Description

Liquid crystal display device having a common voltage compensation circuit

The present invention relates to a liquid crystal display capable of compensating for a common voltage supplied to a common electrode of a display panel.

A liquid crystal display includes a display panel in which liquid crystal molecules in an intermediate state between liquid and solid are positioned between two substrates. A liquid crystal display reproduces an image of an input image by adjusting the amount of light passing through the display panel according to the gradation value of the video data by changing the arrangement of liquid crystal molecules according to the video data of the input image.

An active matrix driving type liquid crystal display uses a thin film transistor as a switching element to display moving images. The display panel of this liquid crystal display includes data lines, gate lines (or scan lines) crossing the data lines, and pixels formed in matrix-type pixel areas defined by the data lines and the gate lines. do.

Pixels of the liquid crystal display device include a thin film transistor positioned adjacent to a data line and a gate line crossing each other. The thin film transistor supplies a data voltage supplied through a data line to a pixel electrode of a liquid crystal cell in response to a gate pulse from a gate line. The liquid crystal cell rotates by an electric field generated according to a voltage difference between the voltage of the pixel electrode and the common voltage applied to the common electrode to adjust the amount of light passing through the polarizing plate. The storage capacitor is connected to the pixel electrode of the liquid crystal cell to maintain the voltage of the liquid crystal cell.

The common voltage applied to the common electrode causes a ripple phenomenon due to electrical coupling with the pixel electrode. The ripple phenomenon of the common voltage is proportional to the variation of the data voltage over time. Therefore, in the inversion method in which the polarity of the data voltage is varied, the ripple phenomenon of the common voltage becomes severe at the moment when the polarity of the data voltage is changed because the variation range of the data voltage is large. As such, the ripple phenomenon of the common voltage induces a line-dim phenomenon along the horizontal direction, thereby deteriorating display quality.

Therefore, in order to prevent such a line-dim phenomenon, various common voltage compensation circuits have been developed that receive feedback of the common voltage supplied to the common electrode and supply a compensating common voltage capable of canceling the ripple voltage.

However, in order to apply the common voltage compensation circuit to a GIP (Gate In Panel) model in which a gate driving circuit is formed on a display panel, a common voltage supply line, a common voltage feedback line, a GIP circuit, and the like must be formed in a limited bezel area. In particular, in order to sense the common voltage of the common electrode, the wiring width of the common voltage feedback line must be secured to some extent, but in order to stably secure the wiring width of the common voltage feedback line in the same bezel area, the bezel area must be increased, There was a problem in that the wiring width of the common voltage supply line had to be reduced.

An object of the present invention is to prevent image quality deterioration due to a reduction in wiring width of a common voltage supply line or to reduce a bezel width by compensating for a common voltage supplied to a common electrode by sensing a change in gate voltage supplied to gate lines of a display panel. It is to provide a liquid crystal display device that can be reduced.

A liquid crystal display device according to the present invention for achieving the above object includes a display panel, a data driving circuit, a gate driving circuit, and a common voltage compensation circuit. The display panel displays an input image and includes a pixel array including a pixel electrode to which a data voltage is supplied and a common electrode to which a common voltage is supplied. A data driving circuit supplies data voltages to data lines of the display panel. The gate driving circuit includes a level shifter and a shift register. The level shifter outputs shift clocks and a start pulse. The shift register receives the gate low voltage and the gate high voltage, shifts the start pulse according to the shift clock, sequentially shifts the gate pulse swinging between the gate high voltage and the gate low voltage, and supplies it to the gate lines do. The common voltage compensating circuit receives a gate sensing voltage obtained by sensing the gate lines through a gate low voltage supply line to which the gate low voltage is supplied, extracts a ripple component included in the gate sensing voltage, and inverts the ripple component. The amplified common voltage compensation voltage is supplied to the common electrode.

In the above configuration, the shift register is composed of a plurality of stages each connected to the gate lines. Each stage includes a logic unit that controls charging and discharging operations of a Q node and a QB node that are charged and discharged in opposite directions in response to the start pulse, the gate high voltage, and the gate low voltage, and the Q node is charged to an active level. and a first pull-up transistor outputting a scan pulse at a turn-on level when the QB node is charged to an active level, and a first pull-down transistor outputting a scan pulse at a turn-off level when the QB node is charged to an active level. A gate sensing voltage is supplied to the common voltage compensation circuit through the first pull-down transistor and the gate low voltage supply line.

Also, the first pull-up transistor includes a gate electrode connected to the Q node, a source electrode receiving the shift clock, and a drain electrode connected to the first output node. A first pull-down transistor includes a gate electrode connected to the QB node, a source electrode connected to the gate low voltage supply line, and a drain electrode connected to the first output node. The scan pulse supplied through the first output node is supplied to a gate line connected to a stage of a current stage and a stage of a next stage.

In addition, the common voltage compensation circuit includes an operational amplifier including a non-inverting input terminal to which the common voltage is supplied, an inverting input terminal, and an output terminal connected to a common voltage supply line, the inverting input terminal and the gate low voltage supply It includes a buffer, a capacitor, and a first resistor connected in series between lines, and a second resistor connected in parallel between the inverting input terminal and the output terminal.

In addition, the liquid crystal display according to the present invention may further include a third resistor disposed between an output terminal to which the gate low voltage is supplied and a buffer of the common voltage compensation circuit.

In addition, the gate low voltage supply line includes a first gate low voltage supply line for supplying a first gate low voltage and a second gate low voltage supply for supplying a second gate low voltage having a level different from that of the first gate low voltage. line can be included. The shift register includes a plurality of stages each connected to the gate lines. Each stage includes a logic unit controlling charging and discharging operations of a Q node and a QB node that are charged and discharged in opposite directions in response to the start pulse, the gate high voltage, and the first and second gate low voltages; A first pull-up transistor and a second pull-up transistor outputting a scan pulse to a turn-on level when the Q node is charged to an activation level, and a first pull-down transistor to output a scan pulse to a turn-off level when the QB node is charged to an activation level transistor and a second pull-down transistor. A gate sensing voltage is supplied to the common voltage compensation circuit through the first pull-down transistor and the first gate low voltage supply line.

Also, the first pull-up transistor includes a gate electrode connected to the Q node, a source electrode receiving the shift clock, and a drain electrode connected to the first output node. The second pull-up transistor includes a gate electrode connected to the Q node, a source electrode receiving the clock signal, and a drain electrode connected to the second output node. A first pull-down transistor includes a gate electrode connected to the QB node, a source electrode connected to the first gate low voltage supply line, and a drain electrode connected to the first output node. The second pull-down transistor includes a gate electrode connected to the QB node, a source electrode connected to the second gate low voltage supply line, and a drain electrode connected to the second output node. The scan pulses supplied through the first output node are supplied to the gate line connected to the stage of the current stage, and the scan pulses supplied through the second output node are supplied to the next stage.

Further, the common voltage compensation circuit includes an operational amplifier including a non-inverting input terminal to which the common voltage is supplied, an inverting input terminal, and an output terminal connected to a common voltage supply line, the inverting input terminal and the first gate low voltage It includes a buffer, a capacitor and a first resistor connected in series between supply lines, and a second resistor connected in parallel between the inverting input terminal and the output terminal.

In addition, the liquid crystal display according to the present invention may further include a third resistor disposed between an output terminal to which the first gate low voltage is supplied and a buffer of the common voltage compensation circuit.

According to the display device with a built-in touch sensor according to the present invention, it is possible to supply a compensating common voltage for removing a ripple component included in the feedback common voltage by sensing a change in the gate line, thereby preventing image degradation due to parasitic capacitance. In addition, since the common voltage feedback line can be removed, an effect of reducing the bezel area can be obtained.

1 is a block diagram schematically showing a liquid crystal display device according to an embodiment of the present invention;
2 schematically shows a partial area of a liquid crystal display device according to an embodiment of the present invention;
3 is a plan view schematically showing wires of a liquid crystal display device according to an embodiment of the present invention;
4 is a circuit diagram showing an example of each stage of the shift register shown in FIG. 2;
5 is a circuit diagram showing another example of each stage of the shift register shown in FIG. 2;
6 is a circuit diagram showing a common voltage compensator for compensating for a common voltage by sensing a gate low voltage in a liquid crystal display according to an embodiment of the present invention;
7 is a diagram for explaining the principle of the common voltage compensator shown in FIG. 6 removing a DC component and amplifying an AC component and outputting the amplified AC component;
8 is a waveform diagram showing a ripple voltage generated by sensing a gate line corresponding to a display pattern of a region in which grayscale changes in a liquid crystal display device according to an embodiment of the present invention;
9 is a plan view schematically showing effects obtained by a liquid crystal display according to an embodiment of the present invention with respect to a conventional liquid crystal display having a feedback common voltage supply line;

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numbers throughout the specification indicate substantially the same elements. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

First, a liquid crystal display device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 3 .

1 is a schematic block diagram of a liquid crystal display device according to an embodiment of the present invention. 2 is a diagram schematically illustrating a partial area of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 3 is a plan view schematically illustrating wires of the liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display device according to an embodiment of the present invention includes a display panel 10, a data driving circuit, a GIP (Gate In Panel) type gate driving circuit, a common voltage compensation circuit (CVC) and a timing controller ( TC), etc.

The display panel 10 includes an active area AA and a bezel area BA. The active area AA is an area where an input image is displayed and a pixel array is disposed. The bezel area BA is an area where the shift register of the gate driving circuit, various signal wires, and a common voltage supply line are disposed.

The pixel array may include a thin film transistor (TFT) array formed on the first substrate, a color filter array formed on the second substrate, and liquid crystal cells Clc.

The TFT array is formed at each intersection of the data lines DL, the gate lines (or scan lines) GL crossing the data lines DL, and the intersections of the data lines DL and the gate lines GL. It includes a thin film transistor (TFT), a pixel electrode 1 connected to the thin film transistor (TFT), and a storage capacitor (Cst). A color filter array including a black matrix and color filters is formed on the second substrate of the display panel 10 . The common electrode 2 may be formed on the first substrate or the second substrate. The liquid crystal cells Clc are driven by an electric field between the pixel electrode 1 supplied with the data voltage and the common electrode 2 supplied with the common voltage Va.

The common voltage Va may be supplied from a separate power source (not shown) and is supplied to the common electrode 2 through the common line CL. As shown in FIG. 3 , the common line CL is disposed in the bezel area BA and is branched off from the first common line CLa arranged in parallel with the data line and the first common line CLa to form gate lines. A plurality of second common lines CLb arranged in parallel with GL, and second common lines extending in a vertical direction from the second common lines CLb and arranged in parallel with data lines DL and adjacent to each other and a plurality of third common lines CLc connecting the lines CLb. In this case, the common line CL is formed in a matrix type in the active area AA by the second common lines CLb and the third common lines CLc.

In the embodiment of the present invention, an example in which the common line is composed of first to third common lines has been described, but in the case of a small liquid crystal display device, the first common line is directly connected to the common electrode, and the second common lines or the third Common lines may be omitted or both the second and third common lines may be omitted.

Also, unlike the exemplary embodiment of FIG. 3 , the common line CL is disposed in the bezel area BA and is branched off from the first common line arranged in parallel with the gate line to form the data lines DL and A plurality of second common lines arranged in parallel, and a plurality of third common lines extending in a horizontal direction from the second common lines, arranged in parallel with the gate lines GL, and connecting adjacent second common lines. It may be configured to include In this case, the common line CL is formed in a matrix type in the active area AA by the second common lines and the third common lines. Even in this modified embodiment, in the case of a small liquid crystal display device, the first common line may be directly connected to the common electrode, the second common lines or the third common lines may be omitted, or both the second and third common lines may be omitted. .

Also, the display panel 10 may be formed in a color filter on transistor (COT) method in which the color filter array is not formed on the second substrate and color filters are provided on the TFT array.

Polarizers having optical axes orthogonal to each other are attached to the first substrate and the second substrate of the display panel 10 , and an alignment layer for setting a pretilt angle of the liquid crystal is formed at an interface in contact with the liquid crystal layer. A spacer may be disposed between the first substrate and the second substrate of the display panel 10 to maintain a cell gap of the liquid crystal layer.

The data driving circuit includes a plurality of source drive ICs (IDTegrated Circuits) (SDa, SD) each connected to a group of data lines (DL). The source drive ICs SDa and SD receive digital video data RGB from the timing controller TC. The source drive ICs (SDa, SD) convert digital video data (RGB) into positive/negative analog data voltages in response to the source timing control signal from the timing controller (TC), and then convert the data voltages to gates. It is supplied to the data lines DL of the display panel 10 in synchronization with the pulse (or scan pulse). The source drive ICs SDa and SD may be connected to the data lines DL of the display panel 10 through a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process. The source drive ICs SDa and SD shown in FIG. 1 show an example of being mounted on a Tape Carrier Package (TCP). In addition, the printed circuit board (PCB) 20 is connected to the first substrate of the display panel 10 via TCP.

The GIP type gate driving circuit includes a level shifter LS mounted on the PCB 20 and a shift register SR formed on the first substrate of the display panel 10 .

The level shifter LS receives signals such as a start pulse ST, gate shift clocks GLCK, and a flicker signal FLK from the timing controller TC, and also generates a gate high voltage VGH and a gate low voltage. (VGL) and the like are supplied. The start pulse ST, the gate shift clocks GCLK and the flicker signal FLK are signals that swing between 0V and 3.3V. The gate shift clocks GLCK1 to n are n-phase clock signals having a predetermined phase difference. The gate high voltage (VGH) is a voltage higher than or equal to the threshold voltage of the thin film transistor (TFT) formed in the thin film transistor array of the display panel 10 and is a voltage of about 28V, and the gate low voltage (VGL) is the voltage of the thin film transistor (TFT) of the display panel 10 It is a voltage lower than the threshold voltage of the thin film transistor (TFT) formed in the transistor array and is approximately -5V.

The level shifter LS is a shift clock signal obtained by level-shifting the start pulse ST and the gate shift clocks GLCK input from the timing controller TC to a gate high voltage VGH and a gate low voltage VGL, respectively. outputs (CLK). Accordingly, each of the start pulse VST and shift clock signals CLK output from the level shifter LS swings between the gate high voltage VGH and the gate low voltage VGL. The level shifter LS may reduce the flicker by lowering the kickback voltage ΔVp of the liquid crystal cell by lowering the gate high voltage according to the flicker signal FLK.

As shown in FIG. 1 , the output signals of the level shifter LS are connected to wires formed in the TCP of the first source drive IC SDa disposed at the top left of the display panel 10 and the It may be supplied to the shift register SR through Line On Glass (LOG) lines LW formed on the first substrate. The shift register SR is directly formed on the first substrate of the display panel 10 by a GIP process.

As shown in FIG. 2 , a start pulse VST, clock signals CLK1 to CLKn, a gate low voltage VGL and a gate high voltage VGH are input to the shift register SR. The shift register SR includes a plurality of stages ST1 to STn that are cascadedly connected. The clock signals CLK1 to n are n (n is a natural number greater than or equal to 2) phase clock signals whose phases are sequentially delayed. The clock signals CLK1 to CLKn are supplied to the respective stages ST1 to STn through the clock signal supply lines SL1 to SLn.

The shift register SR shifts the start pulse VST input from the level shifter LS according to the gate shift clock signals CLK1 to CLKn, thereby swinging between the gate high voltage VGH and the gate low voltage VGL. sequentially shifts the gate pulses. Gate pulses output from the shift register SR are sequentially supplied to the gate lines GL.

Next, with reference to FIGS. 4 and 5 , a shift register SR of a liquid crystal display according to an embodiment of the present invention will be described in more detail.

FIG. 4 is a circuit diagram showing one example of each stage of the shift register shown in FIG. 2, and FIG. 5 is a circuit diagram showing another example of each stage of the shift register shown in FIG.

Referring to FIG. 4 , each of the stages ST1 to STn of the shift register SR generates a voltage of a Q node and a QB node in response to a gate start signal VST, a gate high voltage VGH, and a gate low voltage VGL. A logic unit (LO) that controls charge and discharge operations, a pull-up transistor (TU) that outputs a scan pulse to a turn-on level when the Q node is charged to an activation level, and a scan pulse when the QB node is charged to an activation level. It includes a pull-down transistor (TD) outputting at a turn-off level.

The pull-up transistor TU includes a gate electrode connected to the Q node, a source electrode receiving the clock signal GCLK, and a drain electrode connected to the output node N1.

The pull-down transistor TD includes a gate electrode connected to the QB node, a source electrode connected to the gate low voltage VGL supply line, and a drain electrode connected to the output node N1.

The Q node and QB node are charged and discharged opposite to each other. That is, when the Q node is charged to the active level, the QB node is discharged to the inactive level, and conversely, when the Q node is discharged to the inactive level, the QB node is charged to the active level.

When the Q node is activated, the pull-down transistor TD is turned off, and the pull-up transistor TU outputs one of the gate shift clock signals GCLK1 to GCLKn as a turn-on level scan pulse. This scan pulse becomes a gate voltage (Gout) output to the corresponding gate line and is used as a carry signal (Cout) supplied to the next stage.

On the other hand, when the QB node is activated, the pull-up transistor TU is turned off and the pull-down transistor TD is turned on, so that the gate voltage of the corresponding gate line is sensed and supplied to the gate low voltage VGL supply line. In general, since the gate lines GL have an intersection with the data lines DL, the gate sensing voltage obtained by sensing the gate line GL when the QB node is activated is the gate line ( GL) and the noise component generated by the coupling of the data line DL are included.

As such, the gate sensing voltage of each gate line GL including the noise component is supplied to the common voltage compensation circuit CVC (see FIGS. 2 and 4).

Referring to FIG. 5 , each of the stages ST1 to STn of the shift register SR has a gate start signal VST, a gate high voltage VGH, and first and second gate low voltages VGL1 and VGL2. A logic unit (LO) that controls charging and discharging operations of the Q node and the QB node in response, and first and second pull-up transistors (TUa, TUb) that output scan pulses to turn-on levels when the Q1 node is charged to an active level. ), and first and second pull-down transistors TDa and TDb outputting scan pulses to a turn-off level when the QB node is charged to an active level.

The first pull-up transistor TUa includes a gate electrode connected to the Q node, a source electrode receiving the clock signal GCLK, and a drain electrode connected to the first output node N1. The second pull-up transistor TUb includes a gate electrode connected to the Q node, a source electrode receiving the clock signal GCLK, and a drain electrode connected to the second output node N2.

The first pull-down transistor TD includes a gate electrode connected to the QB node, a source electrode connected to the first gate low voltage VGL1 supply line, and a drain electrode connected to the first output node N1. The second pull-down transistor TDb includes a gate electrode connected to the QB node, a source electrode connected to the second gate low voltage VGL2 supply line, and a drain electrode connected to the second output node N2. Levels of the first gate low voltage VGL1 and the second gate low voltage VGL2 are different, and the first gate low voltage VGL1 may be set higher than the second gate low voltage VGL2.

The first node N1 to which the first pull-up transistor TUa and the first pull-down transistor TDa are connected functions as a gate voltage output terminal supplying a gate voltage to the gate line, and the second pull-up transistor TUb and the second pull-down transistor The second node N2 to which the transistor TDb is connected functions as a carry stage for supplying a carry signal to a stage in the next stage. Accordingly, signals output to the first and second output terminals N1 and N2 are the same.

As a result, the stages ST1 to STn of the shift register SR of FIG. 5 are obtained by dividing the gate voltage output terminal and the carry signal output terminal into two, and the stages ST1 to STn of the shift register SR of FIG. Their functions and operations are the same. Therefore, further description is omitted to avoid redundant description.

In the embodiment of FIG. 5 , the gate sensing voltage of each gate line including the noise component is supplied to the common voltage compensating circuit.

8 is a waveform diagram showing a ripple voltage generated by sensing a gate line corresponding to a display pattern of a region in which grayscale changes in a liquid crystal display device according to an embodiment of the present invention, and a display pattern changing from 64 to 255 grayscale. The ripple component obtained by sensing the gate line corresponding to is shown.

From the stages ST1 to STn of the shift register SR according to the embodiments of FIGS. 4 and 5, the gate sensing voltage of each gate line including the noise component is supplied through the gate low voltage (VGL, VGL1) supply line. It is supplied to the common voltage compensation circuit (CVC).

Next, referring to FIG. 6, a common voltage compensation circuit (CVC) of a liquid crystal display according to an embodiment of the present invention will be described.

The common voltage compensation circuit CVC has an input terminal connected to gate low voltage supply lines VGL and VGL1 to which the gate low voltage VGL is supplied, and an output terminal connected to the common line CL.

The common voltage compensation circuit (CVC) is an operational amplifier including a non-inverting input terminal (+) to which the common voltage Va is supplied, an inverting input terminal (-), and an output terminal connected to the common voltage supply line (CL). (OP), a buffer (BUF) connected in series between the inverting input terminal (-) and the gate low voltage (VGL) supply line, a capacitor (C) and a first resistor (R1), an inverting input terminal (-) and an output A second resistor (R2) connected in parallel between the terminals is included.

The buffer BUF of the common voltage compensation circuit CVC buffers the gate sensing voltage supplied from each stage of the shift register. As shown in FIG. 7, the capacitor C is connected to the common voltage Va input to the non-inverting input terminal (+). At the rear end of the buffer BUF so that the DC level difference (B) of the gate sensing voltages VGL and VGL1 obtained by sensing the gate lines is not amplified and the ripple component (AC component) (A) of the gate sensing voltage can be extracted. is placed on

The first resistor R1 and the second resistor R2 and the operational amplifier OP invert and amplify the ripple component of the gate sensing voltage at the ratio of R2/R1 to the common voltage compensation voltage Vb to the common line CL. print out

As described above, the common voltage compensating circuit of the liquid crystal display device according to an embodiment of the present invention is generated by coupling the gate line GL and the data line DL through the gate low voltage VGL supply wiring. The ripple of the common voltage is obtained by obtaining a gate sensing voltage including noise components, extracting a ripple component (noise component) included in the gate sensing voltage, inverting and amplifying the noise component, and supplying the amplified voltage of the opposite phase to the common electrode. is compensating for

Accordingly, a feedback common line for sensing the common voltage is unnecessary in order to compensate for a ripple component, which is a noise component included in the common voltage.

9 is a plan view schematically showing effects obtained by a liquid crystal display according to an embodiment of the present invention with respect to a conventional liquid crystal display having a feedback common voltage supply line.

9(a) is an example of a case in which a feedback common line FB for sensing a common line CLa is formed in a bezel area of a conventional liquid crystal display.

9(b) shows a common line for supplying a common voltage in a liquid crystal display according to an embodiment of the present invention (eg, a first common line (CLa in FIG. 3) shown in the embodiment of the present invention). When the common line is formed as shown in FIG. Therefore, the effect of improving the display quality can be obtained.

9(c) shows a common line CL for supplying a common voltage in a liquid crystal display according to an embodiment of the present invention (eg, a first common line shown in the embodiment of the present invention (Fig. 3). When forming a common line as shown in (c) of FIG. 9, the feedback common line FB formed in (a) of FIG. 9 can be removed. Therefore, the effect of reducing the bezel area can be obtained.

Through the above description, those skilled in the art will understand that various changes and modifications are possible without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

10: display panel 20: PCB
CVC: common voltage compensation circuit LS: level shifter
SDa, SD: Source Drive IC SR: Shift Register
ST1~STn: stage TC: timing controller

Claims (9)

a display panel displaying an input image and having a pixel array including a pixel electrode to which a data voltage is supplied and a common electrode to which a common voltage is supplied;
a data driving circuit supplying data voltages to data lines of the display panel;
Shift clocks, a level shifter outputting a start pulse, a gate low voltage and a gate high voltage are input, and a gate swinging between the gate high voltage and the gate low voltage by shifting the start pulse according to the shift clock a gate driving circuit including a shift register for sequentially shifting pulses and supplying them to gate lines; and
A common voltage compensation obtained by receiving a gate sensing voltage obtained by sensing the gate lines through a gate low voltage supply line to which the gate low voltage is supplied, extracting a ripple component included in the gate sensing voltage, and inverting and amplifying the ripple component A liquid crystal display device comprising a common voltage compensation circuit supplying a voltage to the common electrode. According to claim 1,
The shift register includes a plurality of stages each connected to the gate lines,
each stage,
a logic unit controlling charging and discharging operations of a Q node and a QB node, which are charged and discharged opposite to each other, in response to the start pulse, the gate high voltage, and the gate low voltage;
a first pull-up transistor outputting a scan pulse to a turn-on level when the Q node is charged to an active level; and
A first pull-down transistor outputting a scan pulse to a turn-off level when the QB node is charged to an active level;
The gate sensing voltage is supplied to the common voltage compensation circuit through the first pull-down transistor and the gate low voltage supply line. According to claim 2,
The first pull-up transistor includes a gate electrode connected to the Q node, a source electrode receiving the shift clock, and a drain electrode connected to a first output node;
The first pull-down transistor includes a gate electrode connected to the QB node, a source electrode connected to the gate low voltage supply line, and a drain electrode connected to the first output node;
The scan pulse supplied through the first output node is supplied to a gate line connected to a stage of a current stage and to a stage of a next stage. According to any one of claims 1 to 3,
The common voltage compensation circuit,
an operational amplifier including a non-inverting input terminal to which the common voltage is supplied, an inverting input terminal, and an output terminal connected to a common voltage supply line;
a buffer, a capacitor and a first resistor connected in series between the inverting input terminal and the gate low voltage supply line;
A liquid crystal display device comprising a second resistor connected in parallel between the inverting input terminal and the output terminal. According to claim 4,
and a third resistor disposed between an output terminal to which the gate low voltage is supplied and a buffer of the common voltage compensation circuit. According to claim 1,
The gate low voltage supply line includes a first gate low voltage supply line supplying a first gate low voltage and a second gate low voltage supply line supplying a second gate low voltage having a level different from that of the first gate low voltage. Including,
The shift register includes a plurality of stages each connected to the gate lines,
each stage,
a logic unit controlling charging and discharging operations of a Q node and a QB node, which are charged and discharged opposite to each other, in response to the start pulse, the gate high voltage, and the first and second gate low voltages;
a first pull-up transistor and a second pull-up transistor outputting a scan pulse to a turn-on level when the Q node is charged to an active level; and
A first pull-down transistor and a second pull-down transistor outputting a scan pulse to a turn-off level when the QB node is charged to an active level,
The gate sensing voltage is supplied to the common voltage compensation circuit through the first pull-down transistor and the first gate low voltage supply line. According to claim 6,
The first pull-up transistor includes a gate electrode connected to the Q node, a source electrode receiving the shift clock, and a drain electrode connected to a first output node;
The second pull-up transistor includes a gate electrode connected to the Q node, a source electrode receiving the shift clock, and a drain electrode connected to a second output node;
The first pull-down transistor includes a gate electrode connected to the QB node, a source electrode connected to the first gate low voltage supply line, and a drain electrode connected to the first output node;
the second pull-down transistor includes a gate electrode connected to the QB node, a source electrode connected to the second gate low voltage supply line, and a drain electrode connected to the second output node;
The scan pulse supplied through the first output node is supplied to a gate line connected to a stage of a current stage, and the scan pulse supplied through the second output node is supplied to a stage of a next stage. The method of any one of claims 6 and 7,
The common voltage compensation circuit,
an operational amplifier including a non-inverting input terminal to which the common voltage is supplied, an inverting input terminal, and an output terminal connected to a common voltage supply line;
a buffer, a capacitor and a first resistor connected in series between the inverting input terminal and the first gate low voltage supply line;
A liquid crystal display device comprising a second resistor connected in parallel between the inverting input terminal and the output terminal. According to claim 8,
and a third resistor disposed between an output terminal to which the first gate low voltage is supplied and a buffer of the common voltage compensation circuit.

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