KR102496175B1 - Display device and driving method thereof - Google Patents

Abstract

The present invention relates to a gate in panel (GIP) display device, and more particularly, to a panel including a display area and a non-display area, and a GIP formed in the non-display area and including a plurality of shift register logics. (gate in panel) circuit part, a plurality of signal transmission wires formed in the non-display area and transmitting signals involved in driving the GIP (gate in panel) circuit part, electrically connected to a plurality of signal transmission wires in the non-display area, It is formed in multiple layers in the vertical direction and includes a plurality of multi-layer wires for transmitting signals to each of the plurality of shift register logics, and a plurality of connection wires for connecting each of the plurality of signal transmission wires and each of the plurality of multi-layer wires to each other.

Description

Display device and its driving method {DISPLAY DEVICE AND DRIVING METHOD THEREOF}

The present invention relates to a display device and a method for driving the same, and more particularly, to a display device using a gate-in-panel (GIP) method in which a gate drive integrated circuit is directly formed on a display panel and a method for driving the same.

As the information society develops, demands for display devices for displaying images are increasing in various forms. Accordingly, recently, various flat panel displays (FPDs) capable of reducing the weight and volume, which are disadvantages of cathode ray tubes, have been developed and marketed. For example, various flat panel displays such as Liquid Crystal Display (LCD), Plasma Display Panel (PDP), and Organic Light Emitting Diode (OLED) are being utilized. .

A display device displays an image using a gate driving circuit supplying scan signals to gate lines of a display panel and a data driving circuit supplying data voltages to data lines. The gate driving circuit may be formed using a Tape Automated Bonding (TAB) method in which a printed circuit board on which a plurality of gate drive integrated circuits are mounted is attached to a display panel, or an integrated gate drive circuit is directly formed on the display panel. It may be formed in a GIP (Gate-in-panel) method. Compared to the TAB method, the GIP method can make the display device slimmer, so not only can the external aesthetics be improved, but also cost can be reduced. There is an advantage in that the display panel maker can directly design scan signals of . Therefore, gate driving circuits are recently formed using the GIP method rather than the TAB method.

In a panel of a general flat panel display (hereinafter simply referred to as a 'display device'), a gate driving circuit is formed on the panel in a GIP method. Therefore, for example, when the source driver IC is in the non-display area of the upper part, the gate driving circuit and gate transmission lines for transmitting driving signals to the gate driving circuit are formed in the non-display area of the panel. This gate driving circuit includes a gate shift register that sequentially supplies scan pulses to a plurality of gate lines.

Meanwhile, recent display devices tend to add additional functions such as a high resolution trend, a narrow bezel trend, and an in-cell touch. Therefore, efforts to reduce the size of the gate driving circuit and the gate on time of the driving circuit are continuously required.

1 is an exemplary diagram illustrating a waveform of a signal input to a gate driving circuit of a conventional display device.

As shown in FIG. 1, the clock signal input to the gate driving circuit is the rising time required to reach the high gate voltage (VGH) from the low gate voltage (VGL) and the low gate voltage (VGH). There is a falling time required to reach the gate voltage VGL. When the width of the clock signal, that is, the Gate on Time is reduced, the load increases at the Rising Time and Falling Time of the input driving signals, which is caused by the gate driving circuit. A deviation occurs between the scan pulses output from the furnace to the panel, that is, the gate voltages. To improve this, it is necessary to reduce the load deviation by adding a large buffer to the gate driving circuit, but this increases the size of the gate driving circuit. Therefore, it is necessary to improve the deviation occurring in the load of the input clock signal.

Accordingly, the inventors of the present invention invented a new structure and manufacturing method of a display device for improving a load deviation of a clock signal input from a GIP type gate driving circuit.

In addition, the inventors of the present invention invented a new structure and manufacturing method capable of reducing the size of the GIP type gate driving circuit.

The problem to be solved by the present invention is a long lifespan narrow gate driving circuit that can reduce the load deviation caused by the input clock signals by changing the structure of the clock signal transmission wiring of the gate in panel (GIP). and a display device using the same.

In addition to the technical problems of the present invention mentioned above, other features and advantages of the present invention will be described below, or will be clearly understood by those skilled in the art from such description and description.

In order to solve the above problems, a display device according to an embodiment of the present invention is formed in a panel including a display area and a non-display area, and a plurality of shift register logics formed in the non-display area. GIP (gate in panel) circuit part, a plurality of signal transmission wires formed in the non-display area and transmitting signals involved in driving the GIP (gate in panel) circuit part, electrically connected to a plurality of signal transmission wires in the non-display area, , A plurality of multi-layer wirings formed in multiple layers in the vertical direction to transmit signals to each of a plurality of shift register logics, and a plurality of connection wires connecting each of the plurality of signal transmission wires and each of the plurality of multi-layer wirings to each other. .

The plurality of shift register logics may be a plurality of stages that receive a plurality of clock signals and sequentially output gate voltages to gate lines of the panel.

The display device may further include a clock signal sharing wire branching from a multi-layer wiring electrically connected to a K-th stage among the plurality of stages and transmitting a clock signal to the K-th stage.

The clock signal sharing wire may be electrically connected to a control switch terminal for discharging a gate voltage output from the Kth stage.

The clock signal sharing wire may be located in the non-display area and formed in a structure that does not intersect with a plurality of signal transmission wires, thereby minimizing generation of parasitic capacitance that causes a deviation in clock signal transmission.

The clock signal sharing wire is positioned apart from the plurality of signal transmission wires and may be formed of the same material as the plurality of signal transmission wires.

The display device may further include a gate line, a data line, a common electrode, and a pixel electrode in the display area of the panel.

The plurality of signal transmission lines may be formed of the same material as the gate line in the non-display area.

The display device may further include an organic insulating layer having a specific thickness to minimize parasitic capacitance between layers of the multilayer wiring.

The thickness of the organic insulating film may be 2.5 μm to 3.5 μm.

In order to minimize the resistance of the multi-layer wiring, two layers of the multi-layer wiring may be in direct contact with each other to form a double wiring.

The double wiring may include a common electrode pattern formed of the same material as the common electrode of the display area and a dummy metal pattern formed on the common electrode pattern.

The multilayer wiring may have a structure in which a gate line, a gate insulating layer, a data line, an organic insulating layer, a common electrode pattern, and a dummy metal pattern are sequentially formed.

The connection line may be a pixel electrode pattern formed of the same material as the pixel electrode in the non-display area.

The pixel electrode pattern may electrically connect the gate line, the data line, the common electrode pattern, and the dummy metal pattern to each other.

In order to solve the above problems, a liquid crystal display device according to an exemplary embodiment of the present invention provides data lines, gate lines crossing the data lines, and thin film transistors (TFTs) formed at each intersection of the data lines and the gate lines. ), liquid crystal cells connected to the TFT and driven by an electric field between the pixel electrode and the common electrode, and a TFT array including a storage capacitor, a panel including a display area and a non-display area, the panel A gate in panel (GIP) gate including a driving unit including a timing controller and a data driving circuit for driving, and a shift register formed in the non-display area to supply a gate voltage involved in panel driving to a gate line. It transmits the gate voltage generation signals transmitted from the driver circuit and the driver to the shift register, and is composed of multi-layers including an insulating layer between layers, so that the load deviation of the gate voltage generation signals Including multi-layer wiring that minimizes

The shift register includes a plurality of stages that receive a plurality of gate shift clock signals and sequentially output scan pulses, and is branched from a multi-layer wiring that inputs a signal to the K-2th stage among the plurality of stages to the Kth stage. A clock signal transmission wire for transmitting a clock signal may be included.

The clock signal transmission wiring does not intersect with the multi-layer wiring, so parasitic capacitance generation can be minimized.

The clock signal transmission line may be positioned between the plurality of stages and formed of the same material as the gate lines of the display area.

The multilayer wiring may further include sequentially formed gate lines, insulating layers, data lines, organic insulating layers, common electrode patterns, and dummy metal patterns.

An organic insulating film and a dummy metal pattern can minimize resistance and capacitance of multi-layer wiring.

The liquid crystal display device may further include a contact hole formed in a partial area of the multi-layer wiring.

The liquid crystal display may further include connection wires electrically connecting the gate line, the data line, the common electrode pattern, and the additional metal pattern through the contact hole.

In order to solve the above problems, a method of manufacturing a liquid crystal display device according to an embodiment of the present invention includes forming a gate line in a non-display area of a substrate, forming a gate insulating layer on the gate line, and forming a gate line. Forming a data line on the insulating layer and contacting the data line and the gate line, forming an organic insulating film on the data line, forming a common electrode pattern on a portion of the organic insulating film, forming a common electrode pattern on the common electrode pattern forming a dummy metal pattern, forming a passivation layer to cover the organic insulating layer and the dummy metal pattern, etching a portion of the passivation layer to form a contact hole; and forming a connection wire connecting the data line, the common electrode pattern, and the dummy metal pattern.

In order to solve the above problems, a gate driving circuit according to an embodiment of the present invention is a first clock of a dual structure in which a gate metal and a source/drain metal are overlapped in parallel along a predetermined length direction and section at different interlayer positions above and below. A first input terminal and a source/drain metal to which signal lines are connected, an organic insulating film having a sufficient thickness to minimize generation of parasitic capacitance, a common electrode pattern (Vcom), and a dummy metal pattern (3rd metal) in direct contact with the common electrode pattern and a second input terminal to which second clock signal wires composed of pixel electrodes connected to are connected, and a load applied due to the structure of the second clock signal wires is reduced compared to a case where the second clock signal wires are not structured. It is relatively reduced and the overall circuit width can be designed to be relatively narrow.

At least one of resistance and capacitance of the second clock signal wires may be reduced.

By changing the structure of the clock signal transmission wiring of the GIP (gate in panel) type gate driving circuit according to an embodiment of the present invention, load deviation caused by input clock signals can be reduced.

The display device of the GIP method according to at least one embodiment of the present invention minimizes resistance and parasitic capacitance by using a signal transmission line for transmitting clock signals to a gate driving circuit in a multi-layer wiring structure, thereby minimizing the load of clock signals. There is an effect of reducing the deviation and reducing the size of the gate driving circuit.

1 is an exemplary diagram illustrating a waveform of a signal input to a gate driving circuit of a conventional display device;
2A is a block diagram showing a plurality of signal transmission lines for transmitting signals to shift registers of a gate driving circuit according to an embodiment of the present invention;
2B is an exemplary diagram illustrating various waveforms of shift register logic according to an embodiment of the present invention;
3A is an exemplary view showing a transmission wiring for transmitting a clock signal to a gate driving circuit according to an embodiment of the present invention;
3B is a schematic cross-sectional view showing the structure of a transmission line for transmitting a clock signal to a gate driving circuit according to an embodiment of the present invention.
4 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention;

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Hereinafter, for convenience of description, a liquid crystal display device will be described as an example of the present invention, but the present invention is not limited thereto. That is, the present invention can be applied to various display devices capable of displaying an image by supplying a scan signal to a gate line.

FIG. 2A is a block diagram showing a shift register of a gate driving circuit and a plurality of signal transmission lines for transmitting signals to the shift register according to an embodiment of the present invention. Referring to FIG. 2A , the shift register 110 of the gate driving circuit 100 according to an embodiment of the present invention includes a plurality of stages 111 (stage(1) to stage(n), n are cascadedly connected). the number of stages as a natural number). In FIG. 2A, only the first to fourth stages (stage(1) to stage(4)) are illustrated for convenience of description. In this specification, the stage may also be referred to as shift register logic.

In the following description, "front stage" refers to the one located above the standard stage. For example, based on the kth stage (1<k<n, where k is a natural number equal to or greater than 2) (stage(k)), the front stage is the first stage (stage(1)) to the k−1th stage (stage(k) Indicates one of -1)). "Later stage" refers to a stage positioned below a standard stage. For example, based on the kth stage (stage(k)), the next stage indicates any one of the k+1th stage (stage(k+1)) to the nth stage (stage(n)).

For reference, the above-described TFT in the embodiment may be configured as a P-type or N-type, but hereinafter, the TFT will be configured as an N-type. Accordingly, in the embodiment, the gate-on voltage is the gate high voltage (VGH), and the gate-off voltage is the gate low voltage (VGL).

The non-display area of the display panel includes a plurality of signal transmission wires 120 for transmitting driving signals and a shift register 110 of the gate driving circuit 100 in the GIP method. The gate driving circuit 100 is composed of a level shifter and a shift register 110 .

The shift register 110 is directly formed on a lower substrate of a display panel (not shown) in a Gate Driver-IC In Panel (GIP) method. The shift register 110 sequentially outputs gate pulses to gate lines of the display panel. In this specification, a gate line may also be referred to as a gate metal.

The shift register 110 includes a plurality of control switches (T(1) to T(4)) for receiving clock signals and outputting scan pulses, that is, gate voltages, to gate lines located in the display area of the display panel. It is composed of a plurality of stages. A plurality of stages are electrically connected to gate lines. In this specification, a switch may also be referred to as a switch terminal or a terminal.

The signal transmission lines 120 positioned in the non-display area of the display panel are formed on the same layer as the gate lines in the display area. That is, the signal transmission line 120 may be simultaneously formed of the same material as the gate line. The signal transmission lines 120 include an initialization signal line Vstable for transmitting an initialization clock signal to each stage of the shift register 110 . In addition, the signal transmission wires 120 include a start signal line Vstart for transmitting the start clock signal Vst to the first stage (Stage(1)) and the second stage (Stage(2)) of the shift register. .

The signal transmission lines 120 include a first clock signal line CLK1 for transmitting a first clock signal to a first stage, a third clock signal line CLK3 for transmitting a third clock signal to a second stage, and a fifth clock signal line CLK1 for transmitting a third clock signal to a first stage. A fifth clock signal line CLK5 for transmitting a signal to the third stage and a seventh clock signal line CLK7 for transmitting a seventh clock signal to the fourth stage are further included.

The non-display area of the display panel includes a plurality of branch wires branching from each of the signal transmission wires 120 and sequentially inputting a clock signal to each stage of the shift register 110 . Unlike the signal transmission wires 120, the branch wires are multilayer wires 130 including an insulating layer in the vertical direction. The multi-layer wiring 130 has lower resistance and parasitic capacitance than the signal transmission wires 120, so that load deviation of a clock signal supplied to each stage can be minimized. The structure of the multilayer wiring 130 will be described in detail later.

An output voltage output to a gate line corresponding to a clock signal is applied to an output terminal of each stage. The output voltage needs to be discharged before the output voltage is output to the gate line in the next stage. Accordingly, the output voltage of the Kth stage may be discharged using the clock signal used to generate the output voltage of the K−2th stage. A clock signal sharing wire 140 for this is located between the previous stage and the current stage. Also, the clock signal sharing wire 140 is formed on the same layer as the gate line. That is, the clock signal sharing wiring 140 may be simultaneously formed of the same material as the gate line. Also, since the clock signal sharing wiring 140 does not branch from the signal transmission wirings 120, it does not cross the signal transmission wirings 120. Accordingly, the clock signal sharing wire 140 has little parasitic capacitance, and thus, clock load can be minimized.

2B is an exemplary diagram illustrating various waveforms of shift register logic according to an embodiment of the present invention. Specifically, FIG. 2B shows input and output signals of the kth stage (stage(k)). The operation of the kth stage (stage(k)) will be described step by step with reference to FIGS. 2A and 2B.

Each of the stages (stage(1) to stage(4)) includes a switch (T4) involved in initialization, a switch (T1) involved in starting each stage, and a switch (T2) involved in discharging the output voltage of each stage. , the switch involved in the output voltage of each stage, the Q-node (Q_node) connected to the gate terminal that controls the turn-on and turn-off of the output voltage switch of each stage, and the voltage applied to the Q-node (Q_node) is raised bootstrapping capacitance and a switch (T3) involved in discharging the Q-node (Q_node). In each of the stages (stage(1) to stage(4)), the Q_node is initialized in response to the clock input to the initialization switch T4. In addition, each of the stages (stage(1) to stage(4)) generates a voltage at the Q-node (Q_node) in response to the start signal (VST) input to the switch (T1) involved in starting or the carry signal of the previous stage. to charge The voltage of the Q_node is further increased by bootstrapping in response to a clock signal input to a switch involved in the output voltage of each stage (stage(1) to stage(4)). Accordingly, the gate voltage transmitted to the gate line of the panel is output through the output terminal by the voltage of the Q_node. That is, each of the stages (stage(1) to stage(4)) outputs a scan pulse having the same pulse as the clock input to the switch through the output terminal G_OUT.

Subsequently, one of the multi-layer wirings 130 is connected to a switch related to an output voltage to which a clock signal related to outputting a gate voltage of each stage is input. In addition, between the stages (stage(1) to stage(4)), a switch T2 to which a clock signal for discharging the output voltage of each stage is input and one of the multi-layer wirings 130 are electrically connected. It is connected. This wiring is a clock signal sharing wiring 140 that shares a clock signal. The output voltage of the output terminal (G_OUT) is discharged by the clock signal input through the clock signal sharing line 140 and the first low level voltage (VGL) input to each stage (stage(1) to stage(4)). will do Also, the Q_node is discharged by the previous output voltage input from the previous stage output terminal G_OUT and the input second low level voltage VSS.

As described above, the structure and position of each signal wire connected to a switch involved in a clock signal input to each stage (stage 1 to stage) is different in the embodiment. Therefore, the load deviation of the clock signal applied to the wirings can be minimized according to the characteristics of these signal wires.

3A is an exemplary diagram illustrating a transmission wiring for transmitting a clock signal to a gate driving circuit according to an embodiment of the present invention. 3B is a schematic cross-sectional view showing the structure of a transmission line for transmitting a clock signal to a gate driving circuit according to an embodiment of the present invention. Referring to FIGS. 3A and 3B , a stacked structure of multilayer wirings 130 shown in FIG. 2A among signal wirings for transmitting a clock signal to each stage of a shift register according to an embodiment of the present invention is shown. In FIG. 3B, only one multi-layer wiring for transmitting a clock signal to a stage is illustrated for convenience of description.

The multilayer wiring is electrically connected to a plurality of signal transmission wires in the non-display area of the panel to transmit a clock signal to each stage of the shift register. Also, the multi-layer wiring is formed in a multi-layer structure in the vertical direction. Specifically, the multilayer wiring includes a first electrode 310, a gate insulating layer 320, a second electrode 330, an organic insulating film 340, a common electrode pattern 350 (Vcom), and a dummy metal pattern 360; 3 ^rd metal) is a structure formed sequentially. Multi-layer wiring is formed in the following sequence. In this specification, the data line may be formed of the same material as the material forming the source electrode and the drain electrode, and accordingly, the data line may be referred to as a source/drain metal.

First, the first electrode 310 of the multilayer wiring is formed of the same material in the non-display area of the panel at the same time as the gate line located in the display area of the panel is formed. A gate insulating layer 320 is formed on the display panel. Next, the second electrode 330 of the multilayer wiring is formed of the same material in the non-display area at the same time as the data line is formed on the gate insulating layer in the display area. The first electrode 310 and the second electrode 330 are electrically connected to each other in a portion of the non-display area. In addition, an organic insulating film 340 is formed on the second electrode 330 . The organic insulating layer 340 is formed to a thickness of about 2.5 μm to about 3.5 μm. The organic insulating layer 340 may play two roles of photo resist (PR) and passivation. Specifically, the organic insulating film 340 is made of photo resist and may serve as a mask to form a conductive pattern under the organic insulating film 340, for example, the second electrode 330. In addition, the organic insulating film 340 may serve as a protective film to reduce signal transmission distortion of a magnetic field generated from data lines and pixel electrodes. And, it plays a role of minimizing parasitic capacitance generated in multilayer wiring. Then, when the common electrode is formed on the organic insulating film 340 in the display area, the multi-layer wiring common electrode pattern 350 is also formed in the non-display area at the same time. A dummy metal pattern 360 is formed on the common electrode pattern 350 in the non-display area of the panel. This results in a double wiring pattern structure in which any one layer of the multi-layer wiring directly contacts each other. The dummy metal pattern 360 is directly connected to the common electrode pattern 350 to lower the resistance of the multilayer wiring. That is, two layers of the multi-layer wiring, for example, the dummy metal pattern 360 and the common electrode pattern 350 may directly contact each other to minimize resistance of the multi-layer wiring. Next, a passivation layer 370 for protecting the multilayer wiring is positioned on the dummy metal pattern 360 . An inorganic insulating film is used as the passivation layer 370 , and silicon nitride (SiNx) and silicon oxide (SiO ₂ ) may be used as the passivation layer 370 . A contact hole is formed by simultaneously etching the passivation layer 370 and the organic insulating layer 350 in a partial region of the multi-layer wiring without the common electrode pattern 350 and the dummy metal pattern 360 . Thereafter, in the non-display area, the pixel electrode pattern 380 connects the first electrode 310, the second electrode 330, the common electrode pattern 350, and the dummy metal pattern 360 of the multilayer wiring through the contact hole. It is formed by connecting wires that connect electrically. Therefore, the multi-layer wiring includes the first electrode 310, the gate insulating layer 320, the second electrode 330, the organic insulating film 340, the common electrode pattern 350, the dummy metal pattern 360, the passivation layer ( 370) and the pixel electrode pattern 380 are sequentially formed in the non-display area to transmit a clock signal to each stage. This structure of multi-layered wires can minimize distortion during transmission of a clock signal.

4 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention. Referring to FIG. 4 , a display device according to an exemplary embodiment includes a display panel 15 , a data driving circuit, a gate driving circuit, and a timing controller 16 .

A display device according to an embodiment of the present invention may include any display device that sequentially supplies gate pulses (or scan pulses) to gate lines (or scan lines) to write digital video data into pixels through line-sequential scanning. can For example, the display device according to the exemplary embodiment of the present invention includes a liquid crystal display (LCD), an organic light emitting diode (OLED) display, and a field emission display (FED). , Electrophoresis (EPD). Although the present invention is mainly exemplified by the display device implemented as a liquid crystal display in the following embodiments, it should be noted that the display device of the present invention is not limited to the liquid crystal display. The liquid crystal display may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, and a reflective liquid crystal display.

In the display panel 15, a liquid crystal layer is formed between two substrates. The lower substrate of the display panel 15 is connected to data lines, gate lines intersecting the data lines, TFTs formed at each intersection of the data lines and gate lines, and a TFT connected to an electric field between the pixel electrode and the common electrode. A TFT array including driven liquid crystal cells, a storage capacitor, and the like is formed. A color filter array including a black matrix and color filters is formed on the upper substrate of the display panel 15 . The liquid crystal display according to an embodiment of the present invention may also be implemented in a liquid crystal mode such as a twisted nematic (TN) mode, a vertical alignment (VA) mode, an in plane switching (IPS) mode, and a fringe field switching (FFS) mode. The common electrode may be formed on the upper substrate in vertical electric field driving methods such as TN mode and VA mode, and may be formed on the lower substrate together with the pixel electrode in horizontal electric field driving methods such as IPS mode and FFS mode. Polarizers having optical axes orthogonal to each other are attached to the upper substrate and the lower substrate of the display panel 15, and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed at an interface in contact with the liquid crystal layer.

The data driving circuit includes a plurality of source drive ICs 12 . The source drive ICs 12 receive digital video data DATA from the timing controller 16 . Each of the source drive ICs 12 generates a data voltage by converting digital video data DATA into a gamma compensation voltage in response to a source timing control signal from the timing controller 16, and synchronizes the data voltage to a gate pulse. supplied to the data lines of the display panel 15 as much as possible. The source drive ICs 12 may be connected to the data lines of the display panel 15 through a Chip On Glass (COG) process or a Tape Automated Bonding (TAB) process.

The gate driving circuit 100 includes a level shifter 13 and a shift register 10 . The level shifter 13 level-shifts the transistor-transistor-logic (TTL) logic level voltage of the clocks CLKs input from the timing controller 16 into a gate high voltage VGH and a gate low voltage VGL. The level-shifted clocks CLKs are input to the shift register 10. The shift register 10 is connected to gate lines of the display panel 15 to sequentially output gate pulses to the gate lines. The shift register 10 is directly formed on the lower substrate of the display panel 15 in a GIP (Gate Driver-IC In Panel) method. In the GIP method, the level shifter 13 is mounted on a printed circuit board 14.

The timing controller 16 receives digital video data (RGB) from an external host system through an interface such as a low voltage differential signaling (LVDS) interface or a transition minimized differential signaling (TMDS) interface. The timing controller 16 transmits digital video data (DATA) input from the host system to the source drive ICs 12. In addition, the timing controller 16 receives timing signals such as a vertical sync signal, a horizontal sync signal, a data enable signal, and a main clock from a host system through an LVDS or TMDS interface receiving circuit. The timing controller 16 generates timing control signals for controlling operation timings of the data driving circuit and the gate driving circuit based on the timing signal from the host system. The timing control signals include a gate timing control signal for controlling the operation timing of the gate driving circuit and a data timing control signal (DCS) for controlling the operation timing of the source drive ICs 12 and the polarity of the data voltage.

The gate timing control signal includes clocks CLKs sequentially generated on the start voltage VST and i (i is a natural number greater than or equal to 3). The start voltage VST is input to the shift register 10 to control shift start timing of the shift register 10 . The clocks CLKs are input to the level shifter 13, level shifted, and then input to the shift register 10, and are used as clock signals for shifting the start voltage VST.

The data timing control signal (DCS) includes a source start pulse (SSP), a source sampling clock, a polarity control signal, a source output enable signal, and the like. . The source start pulse controls the shift start timing of the source drive ICs 12. The source sampling clock is a clock signal that controls data sampling timing in the source drive ICs 12 based on a rising or falling edge. The polarity control signal controls the polarity of data voltages output from the source drive ICs 12 . If the data transmission interface between the timing controller 16 and the source drive ICs 12 is a mini LVDS interface, the source start pulse (SSP) and the source sampling clock (SSC) may be omitted.

Those skilled in the art to which the present invention pertains will understand that the present invention may be embodied in other specific forms without changing its technical spirit or essential features. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not limiting. The scope of the present invention is indicated by the claims to be described later rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and equivalent concepts should be construed as being included in the scope of the present invention. .

15: panel 16: timing controller
12: source drive IC 100: gate driving circuit
10,110: shift register 13: level shifter
14: printed circuit board
111: stage 120: signal transmission wiring
130 multilayer wiring 140 clock signal sharing wiring
310: first electrode 320: gate insulating layer
330: second electrode 340: organic insulating film
350: common electrode pattern 360: dummy metal pattern
370: passivation layer 380: pixel electrode pattern

Claims (26)

a panel including a display area and a non-display area;
a data line disposed in the display area and a gate line crossing the data line;
a gate in panel (GIP) circuit unit formed in the non-display area and including a plurality of shift register logic;
a plurality of signal transmission lines formed in the non-display area and transmitting signals involved in driving the gate in panel (GIP) circuit;
A plurality of multi-layers disposed in the non-display area, electrically connected to the plurality of signal transmission lines in the non-display area, and formed as a multi-layer in a vertical direction to transmit the signal to each of the plurality of shift register logics. Wiring; and
Including a plurality of connection wires connecting each of the plurality of signal transmission wires and each of the plurality of multi-layer wires to each other,
The plurality of multi-layer wirings
a first electrode formed of the same material on the same layer as the gate line of the display area; and
a second electrode formed of the same material on the same layer as the data line of the display area;
The second electrode overlaps the first electrode and is electrically connected to a portion of the non-display area. According to claim 1,
The plurality of shift register logics are a plurality of stages that receive a plurality of clock signals and sequentially output gate voltages to gate lines of the panel. According to claim 2,
and a clock signal sharing wiring branched off from the multi-layer wiring electrically connected to a K-2th stage among the plurality of stages and transmitting the clock signal to a K-th stage. According to claim 3,
The clock signal sharing wire is electrically connected to a control switch terminal for discharging a gate voltage output from the Kth stage. According to claim 3,
Wherein the clock signal sharing wire is located in the non-display area and is formed in a structure that does not cross the plurality of signal transmission wires, thereby minimizing generation of parasitic capacitance that causes a deviation in transmission of the clock signal. According to claim 3,
The clock signal sharing wire is positioned apart from the plurality of signal transmission wires and is formed of the same material as the plurality of signal transmission wires. According to claim 1,
further comprising a common electrode and a pixel electrode in the display area of the panel;
The plurality of signal transmission lines are formed of the same material as the gate line in the non-display area. delete According to claim 1,
and an organic insulating film having a specific thickness to minimize parasitic capacitance between layers of the multi-layer wiring. delete According to claim 1,
wherein two layers of the multi-layer wiring are in direct contact with each other to form a double wiring so as to minimize resistance of the multi-layer wiring. According to claim 11,
The double wiring includes a common electrode pattern formed of the same material as a common electrode of the display area and a dummy metal pattern formed on the common electrode pattern. According to claim 12,
The multi-layer wiring has a structure in which the first electrode, the gate insulating layer, the second electrode, the organic insulating film, the common electrode pattern, and the dummy metal pattern are sequentially formed. According to claim 1,
The connection wiring is a pixel electrode pattern formed of the same material as a pixel electrode in the non-display area;
The pixel electrode pattern electrically connects the first electrode, the second electrode, the common electrode pattern, and the dummy metal pattern to each other. delete Data lines, gate lines crossing the data lines, thin film transistors (TFTs) formed at each intersection of the data lines and gate lines, and liquid crystal cells connected to the TFTs and driven by an electric field between the pixel electrode and the common electrode. , and a panel including a display area and a non-display area in which a TFT array including a storage capacitor is formed;
a driving unit including a timing controller and a data driving circuit for driving the panel;
a gate in panel (GIP) gate driving circuit including a shift register formed in the non-display area and supplying a gate voltage involved in panel driving to the gate line; and
It is disposed in the non-display area and transmits gate voltage generation signals transmitted from the driver to the shift register, and is composed of multi-layers including an insulating layer between layers to generate the gate voltage. Including multi-layer wiring that minimizes load deviation of signals,
The multilayer wiring is
a first electrode formed of the same material on the same layer as the gate lines of the display area; and
a second electrode formed of the same material on the same layer as the data lines of the display area;
The second electrode overlaps the first electrode and is electrically connected to a portion of the non-display area. 17. The method of claim 16,
The shift register includes a plurality of stages receiving a plurality of gate shift clock signals and sequentially outputting scan pulses, and is branched off from the multi-layer wiring that inputs a signal to a K-2th stage among the plurality of stages. and a clock signal sharing wiring for transmitting the clock signal to K stages. 18. The method of claim 17,
Wherein the clock signal sharing wiring does not intersect with the multi-layer wiring to minimize parasitic capacitance generation. 18. The method of claim 17,
wherein the clock signal sharing wiring is positioned between the plurality of stages and is formed of the same material as gate lines of the display area. 17. The method of claim 16,
The multi-layer wiring further includes the first electrode, the insulating layer, the second electrode, the organic insulating film, the common electrode pattern, and the dummy metal pattern sequentially formed, so that the organic insulating film and the dummy metal pattern form the multi-layer wiring. A liquid crystal display that minimizes resistance and capacitance. delete 21. The method of claim 20,
The liquid crystal display device further comprises a contact hole formed in a partial region of the multi-layer wiring. 23. The method of claim 22,
and a connection wire electrically connecting the first electrode, the second electrode, the common electrode pattern, and the dummy metal pattern through the contact hole. delete delete delete

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