KR20110000469A - A shift register - Google Patents

Abstract

PURPOSE: A shift register is provided to stabilize each pull-up switch element by discharging the enable node of at each stage periodically. CONSTITUTION: A plurality of stages(ST1~STn) provides at least one clock pulse. A plurality of clock pulses have different phase difference. Each stage comprises the pull-up switching element and a stabilizing switch element. The pull-up switching element outputs at least clock pulse as an output signal. The stabilizing switch element supplies a start pulse or the output signal of a front stage to the enable node.

Description

Shift register {A SHIFT REGISTER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register of a liquid crystal display, and more particularly, to a shift register capable of stabilizing switching elements included in each stage of a shift register to prevent display defects of an image and to improve reliability thereof.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix and driving circuits for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and data lines are arranged to cross each other, and a pixel region is positioned in an area defined by vertical crossings of the gate lines and the data lines. The driving circuit includes a gate driver for driving the gate lines of the liquid crystal panel, a data driver for driving the data lines, and a timing controller for controlling the gate driver and the data driver. Here, the gate driver or the data driver is provided with shift registers for sequentially outputting at least one output pulse.

In particular, the shift register included in the conventional gate driver is composed of a plurality of stages connected dependently to each other. Each of these stages outputs one output pulse sequentially, and these output pulses are sequentially supplied to gate lines of the liquid crystal panel, thereby sequentially scanning the gate lines.

Looking at the same conventional stage configuration in more detail with reference to Figure 1, each conventional stage is a node control unit 10 for controlling the charging and discharging state of the enable node (Q) and the disable node (QB) ), The pull-up switching device Trup for outputting the output pulse Vout according to the signal state of the enable node Q and the discharge voltage source VSS for outputting the signal state of the disable node QB. And a pull-down switching element Trpd.

The enable node Q and the disable node QB of each stage configured as described above are alternately charged and discharged. When the enable node Q is in a charged state, the disable node QB is charged. ) Maintains a discharge state, and when the disable node QB is charged, the enable node Q maintains a discharge state. Here, the output pulse Vout from the pull-up switching device Trup is output to the corresponding gate line when the enable node Q is in a charged state, and the pull-down switching device when the disable node QB is in a charged state. The discharge voltage source VSS from Trpd is output to the corresponding gate line.

The gate terminal of the pull-up switching device Trpu is connected to the enable node Q, the drain terminal is connected to the clock transmission line to which the clock pulse CLK is applied, and the source terminal is connected to the gate line. Here, the clock pulse CLK has a high state and a low state periodically and is supplied to the drain terminal of the pull-up switching device Trpu. At this time, the pull-up switching device Trpu has a high clock pulse CLK, which is input at the time when the enable node Q is charged, among the clock pulses CLK which are periodically input to its drain terminal. Will be output as output pulse (Vout). After the output of the output pulse Vout, the enable node Q is maintained in the discharge state until the next frame period starts, so that the pull-up switching device Trpu outputs one output pulse Vout per frame. Only print out.

However, since the clock pulse CLK is supplied multiple times in one frame period, even when the pull-up switching device Trpu is turned off, that is, even when the enable node Q is discharged, the pull-up switching device Trpu is discharged. Is continuously supplied to the drain terminal.

Accordingly, a coupling phenomenon occurs between the enable node Q to which the gate terminal of the pull-up switching device Trpu is connected and the drain terminal of the pull-up switching device Trpu. Then, the enable node Q is continuously charged with the predetermined voltage according to the clock pulse CLK due to the coupling phenomenon, so that the enable node Q can be maintained in a charged state at an unwanted timing. In this case, the enable node Q may be charged more than once in one frame period, and the pull-up switching device Trpu may also be turned on more than once in one frame period.

As a result, the coupling phenomenon causes a problem that at least one stage outputs two or more output pulses Vout during one frame period. As such, when one stage outputs two or more output pulses Vout during one frame period, the reliability of the image is reduced along with the quality of the image displayed on the liquid crystal panel.

The present invention is to solve the above problems, by periodically discharging the enable node of each stage, to stabilize the respective pull-up switching elements to prevent the display of the image and improve the reliability The purpose is to provide a shift register.

The shift register according to an embodiment of the present invention for achieving the above object includes a plurality of stages that are sequentially outputted by receiving at least one clock pulse of a plurality of clock pulses having a different phase difference, Each of the stages comprises: a pull-up switching element configured to output at least one clock pulse among the plurality of clock pulses as the output signal according to a signal state of an enable node; And a start pulse from an external device or an output signal from a previous stage in response to at least one reset clock of a plurality of reset clocks having a low voltage level lower than the low level voltages of the respective clock pulses. It characterized by comprising a stabilizing switching element for supplying to.

Each of the plurality of clock pulses is generated to maintain an active state simultaneously with each other for a predetermined period between clock pulses generated adjacent to each other, and is supplied to corresponding stages so as to be circulated with each other, and the plurality of reset clocks are each provided with the plurality of reset clocks. It is characterized in that it is generated to correspond to each of the clock pulses having a width smaller than the pulse width of the clock pulses.

The plurality of reset clocks are generated in four phases corresponding to the clock pulses of the four phases, and the first reset clock is supplied to the stabilization switching element provided in the fourth k + 1 stage (k is a natural number including 0), and the second reset is performed. The clock is supplied to the stabilization switching device provided in the 4k + 2 stage, the third reset clock is supplied to the stabilization switching device provided in the 4k + 3 stage, and the fourth reset clock is provided to the 4k + 4 stage. It is characterized in that the supply to the stabilization switching device.

The first reset clock is low in a period between a time point when a fourth clock pulse changes from a low state to a high state among the clock pulses generated in four phases and a time point when the first clock pulse changes from a low state to a high state. State is changed from the high state to the high state and changes from the high state to the low state in the period between the time when the first clock pulse changes from the low state to the high state and the time when the fourth clock pulse changes from the high state to the low state. The second reset clock changes from a low state to a high state in a period between a time point when the first clock pulse changes from a low state to a high state and a time point when the second clock pulse changes from a low state to a high state. At a time when the second clock pulse changes from a low state to a high state and at a time when the first clock pulse changes from a high state to a low state It characterized in that the change from a high state to a low state in the period.

In a blank time during which output of the output signals is stopped, the plurality of clock pulses are maintained at a low voltage level and supplied to the stages, and the plurality of reset clock levels are supplied at a low voltage level of each clock pulse. The lower voltage level is maintained and supplied to the stabilization switch of each stage.

Wherein each stage further comprises a node controller for controlling the signal state of the enable node and at least one pull-down switching element for discharging the output terminal of the pull-up switching element in response to an output signal from a next stage. It features.

The node controller is configured to charge the node for enabling the current stage with a charging voltage source in response to an output pulse from a front stage or a start pulse from the outside, and the current in response to an output pulse from a next stage. And a second switching element for discharging the enable node of the stage to a discharge voltage source.

The at least one pull-down switching device discharges the output terminal of the pull-up switching device to the discharge voltage source in response to the clock pulse of at least one of the first to fourth clock pulses or the first to fourth reset clocks. And a fourth switching element for connecting between the drain terminal and the source terminal of the pull-up switching element in response to an output signal from the third switching element and the pull-up switching element.

The third switching device has a low voltage having the output terminal of the pull-up switching device in response to at least one clock pulse of the first to fourth clock pulses or the first to fourth reset clocks. It is characterized by discharging at a level.

Each of the stages may further include a reset switching device configured to discharge the respective enable node to the discharge voltage source according to the start pulse.

The shift register of the present invention having the above characteristics periodically discharges the enable node of each stage by using reset clocks supplied with a low voltage having a lower level than a low voltage of an externally supplied clock pulse. Accordingly, by preventing and further stabilizing the pull-up switching element connected to the enable node, it is possible to prevent the display failure of the image and further improve its reliability.

Hereinafter, the shift register according to an embodiment of the present invention having the above characteristics will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a shift register according to an exemplary embodiment of the present invention. 3 is a waveform diagram illustrating a signal supplied to the shift register of FIG. 2 and a signal output from the shift register.

The shift register shown in FIG. 2 is composed of n stages ST1 to STn and one dummy stage STn + 1 connected to each other. Here, each of the stages ST1 to STn outputs one output pulse Vout1 to Voutn + 1 for one frame period, and sequentially outputs from the first stage ST1 to the dummy stage STn + 1. Output a pulse.

Accordingly, output pulses Vout1 to Voutn output from the stages ST1 to STn except the dummy stage STn + 1 are sequentially supplied to gate lines of the liquid crystal panel (not shown). Each gate line of the liquid crystal panel is sequentially scanned.

Specifically, when the first stage ST1 outputs the first output pulse Vout1, the second stage ST2 then outputs the second output pulse Vout2, and the third stage ST3 next generates the first output pulse Vout1. The output pulse Vout3 is output, and the n-th stage STn outputs the n-th output pulse Voutn. On the other hand, after the nth stage STn outputs the nth output pulse Voutn, the dummy stage STn + 1 outputs the n + 1th output pulse Voutn + 1, wherein the dummy stage STn + The n + 1th output pulse Voutn + 1 outputted from 1) is not supplied to the gate line but is supplied only to the nth stage STn. The shift register of the present invention is incorporated in the non-display portion of the liquid crystal panel.

The stages ST1 to STn + 1 of the shift register may include at least one of the charging voltage source VDD and the discharge voltage source VSS, and the first to fourth clock pulses CLK1 to CLK4 having sequential phase differences with each other. In addition to the clock pulse, at least one reset clock of the plurality of reset clocks RC1 to RC4 supplied to stabilize each stage ST1 to STn + 1 is applied. The plurality of reset clocks RC1 to RC4 are supplied to be circulated with a sequential phase difference from each other. For the plurality of reset clocks, for example, the first to fourth reset clocks RC1 to RC4 are attached later. It will be described in more detail with reference to. Here, the number of clock pulses and reset clocks supplied to each of the stages ST1 to STn + 1 may vary according to the circuit configuration of each of the stages ST1 to STn + 1.

The charging voltage source VDD and the discharge voltage source VSS are voltage sources having different sizes, and the charging voltage source VDD has a larger voltage size than the discharge voltage source VSS. In general, the charging voltage source VDD exhibits a positive polarity, and the discharge voltage source VSS exhibits a negative polarity. In addition, the discharge voltage source VSS may be a ground voltage.

The first stage ST1 positioned at the top of each of the stages ST1 to STn + 1 includes the charging voltage source VDD, the discharge voltage source VSS, and the first to fourth clock pulses CLK1 to CLK4. A start pulse Vst is further supplied along with at least one reset clock of the first to fourth reset clocks RC1 to RC4 together with at least one clock pulse. The remaining stages ST2 to STn + 1 except for the first stage ST1 are the remaining signals except for the start pulse Vst, that is, the charging voltage source VDD, the discharge voltage source VSS, and the first to fifth signals. At least one clock pulse among the four clock pulses CLK1 to CLK4 and at least one reset clock among the first to fourth reset clocks RC1 to RC4 are supplied. Here, the remaining stages ST2 to STn + 1 except for the first stage ST1 are started when the stages ST2 to STn + 1 are initialized using, for example, the start pulse Vst as necessary. The pulse Vst may be further supplied.

As shown in FIG. 3, the first to fourth clock pulses CLK1 to CLK4 are generated to maintain a high period simultaneously for a predetermined period between clock pulses generated adjacent to each other, and are supplied to the shift register. . In more detail, in the case of the second clock pulse CLK2, the phase delay is generated by a 2/3 pulse width than the first clock pulse CLK1, and the third clock pulse CLK3 is generated by the second clock pulse CLK2. Phase delayed by 2/3 pulse width is generated than CLK2, and fourth clock pulse CLK4 is generated by phase delayed by 2/3 pulse width than third clock pulse CLK3. Each of these clock pulses CLK1 to CLK4 has the same pulse width and duty ratio. The first clock pulse CLK1 is delayed in phase by 2/3 pulse width and output from the fourth clock pulse CLK4.

Accordingly, the clock pulses output in the adjacent periods are kept high at the same time for a predetermined period. For example, the pulse width (pulse width in the high state) of the first clock pulse CLK1 and the pulse width (pulse width in the high state) of the second clock pulse CLK2 are the same, and the first clock pulse CLK1 is the same. The latter half of the overlaps with the first half of the second clock pulse CLK2. At this time, an overlapping section between the pulse width of the first clock pulse CLK1 and the pulse width of the second clock pulse CLK2 corresponds to about 1/3 pulse width section.

The fourth clock pulse CLK4 and the start pulse Vst may be generated and output to be synchronized with each other. Accordingly, the second half of the start pulse Vst overlaps the first half of the first clock pulse CLK1. In this case, the fourth clock pulse CLK4 is first generated and output among the first to fourth clock pulses CLK1 to CLK4. However, each clock pulse CLK1 to CLK4 is output several times during one frame period, but the start pulse Vst is output only once during one frame period. In other words, each clock pulse CLK1 to CLK4 shows several active states (high states) periodically during one frame period, while the start pulse Vst shows only one active state during one frame period.

Meanwhile, the shift register according to the present invention may use two clock pulses (two phase clock pulses) having different phase differences, or three clock pulses (three phase clock pulses). In addition, the shift register according to the present invention may use five or more clock pulses having different phases.

At least one clock pulse is supplied to each stage ST1 to STn + 1 provided in the shift register according to an exemplary embodiment of the present invention. In the case where two clock pulses are supplied, one clock pulse is applied to each stage. (ST1 to STn + 1) are clock pulses necessary for outputting the output pulses Vout1 to Voutn, and another clock pulse lowers the output pulse (Vout1 to Voutn) output stage of each stage ST1 to STn + 1. It can be a clock pulse to stabilize to a voltage level.

Meanwhile, the plurality of reset clocks RC1 to RC4 according to the present invention are supplied to stabilize each of the stages ST1 to STn + 1, and the plurality of reset clocks RC1 to RC4 are also supplied with the clock pulse ( It may be a clock pulse of at least two phases so as to correspond to the CLK1 to CLK4).

Specifically, the pulse widths of the plurality of reset clocks, for example, the first to fourth reset clocks RC1 to RC4, are set smaller than the pulse widths of the first to fourth clock pulses CLK1 to CLK4. In other words, the plurality of reset clocks RC1 to RC4 preferably decrease the pulse width in order to prevent the threshold voltage of the stabilization switching devices provided in the stages ST1 to STn + 1 from rising. Therefore, the pulse widths of the first to fourth reset clocks RC1 to RC4 are preferably set smaller than the pulse widths of the first to fourth clock pulses CLK1 to CLK4.

In addition, the low voltage level rcl of the first to fourth reset clocks RC1 to RC4 may be set lower than the low voltage level vgl of the first to fourth clock pulses CLK1 to CLK4. For example, the high voltage level vgh of the first to fourth clock pulses CLK1 to CLK4 may be generated at 15 V, and the low voltage level vgl may be generated at −5 V. have. In this case, the high voltage level rch of the first to fourth reset clocks RC1 to RC4 may be generated at 15 V in the same manner as the high voltage level vgh of the first to fourth clock pulses CLK1 to CLK4. have. However, the low voltage level rcl of the first to fourth reset clocks RC1 to RC4 is -10 V, which is lower than -5 V, which is the low voltage level vgl of the first to fourth clock pulses CLK1 to CLK4. Is generated. That is, when the low voltage level vgl of the first to fourth clock pulses CLK1 to CLK4 is generated at 0 V, the low voltage level rcl of the first to fourth reset clocks RC1 to RC4 is generated at −5 V. When the low voltage level vgl of the first to fourth clock pulses CLK1 to CLK4 is generated at −10 V, the low voltage level rcl of the first to fourth reset clocks RC1 to RC4 is −15 V. To be generated.

As such, when the low voltage level rcl of the first to fourth reset clocks RC1 to RC4 is set lower than the low voltage level vgl of the first to fourth clock pulses CLK1 to CLK4, each stage ( It is possible to stabilize the deterioration of the stabilization switching element provided in ST1 to STn + 1, that is, the threshold voltage of the stabilization switching element.

The reset clocks RC1 to RC4 in the present invention overlap each other with the clock pulses CLK1 to CLK4 such that the clock pulses CLK1 to CLK4 overlap each other. RC1 to RC4) remain high between the rising time of the clock pulse outputted previously to the high state and the rising time of the clock pulse outputted thereafter to the high state, and remain low again within a predetermined period.

More specifically, the first reset clock RC1 may have a time t4 when the fourth clock pulse CLK4 changes from a low state to a high state and a first clock pulse CLK1 from a low state to a high state. In the period tr1 between the changing time points t1, the state changes from the low state to the high state. The first reset clock RC1 includes a time t1 when the first clock pulse CLK1 changes from a low state to a high state and a time t3 when the fourth clock pulse CLK4 changes from a high state to a low state. Change from the high state to the low state during the period tr2. That is, the first reset clock RC1 changes from a high state to a low state in the overlapping period t3 where the fourth clock pulse CLK4 and the first clock pulse CLK1 overlap.

In the case of the second reset clock RC1, a time t1 when the first clock pulse CLK1 changes from a low state to a high state and a time t5 when the second clock pulse CLK2 changes from a low state to a high state In the period tr3 between), it changes from the low state to the high state. The second reset clock RC2 includes a time t5 when the second clock pulse CLK2 changes from a low state to a high state and a time point when the first clock pulse CLK1 changes from a high state to a low state ( It changes from the high state to the low state in the period tr4 between t6). That is, the second reset clock RC2 changes from a high state to a low state in the overlapping period t6 where the first clock pulse CLK1 and the second clock pulse CLK2 overlap.

Meanwhile, the reset clocks RC1 to RC4 output in adjacent periods may overlap each other for a predetermined period, but may not overlap each other. The shift register of the present invention may use two reset clocks (two phase reset clocks) having different phases, or three reset clocks (three phase reset clocks) having different phases. In addition, the shift register of the present invention may use five or more reset clocks having different phases. However, hereinafter, only the case of using four reset clocks, that is, the first to fourth reset clocks RC1 to RC4 will be described as an example.

The first reset clock RC1 described above is supplied to the stabilization switching device provided in the 4k + 1 stage, and the second reset clock RC2 is supplied to the stabilization switching device provided in the 4k + 2 stage. The third reset clock RC3 is supplied to the stabilization switching device provided in the 4k + 3 stage, and the fourth reset clock RC4 is supplied to the stabilization switching device provided in the 4k + 4 stage. Where k is a natural number including zero.

On the other hand, as shown in FIG. 3, a blank time period during which no image signal is supplied to each data line of the liquid crystal panel, for example, a period between every frame period during which the image signal is supplied to each data line. The supply of image signals or scan pulses to the data lines and gate lines is stopped. At this time, the shift register of the present invention is supplied with the first to fourth clock pulses CLK1 to CLK4 maintained at a low voltage level vgl, and the first to fourth reset clocks RC1 to RC4 are provided. The low voltage level rcl lower than the low voltage level vgl of the first to fourth clock pulses CLK1 to CLK4 is maintained and supplied. Accordingly, the respective stages ST1 to STn + 1 can be stabilized even in a blank period in which supply of image signals or scan pulses is stopped.

Next, the configuration of each stage ST1 to STn + 1 provided in the shift register according to an embodiment of the present invention will be described in more detail.

4 is a diagram illustrating a circuit configuration of the second stage illustrated in FIG. 2.

Each stage ST1 to STn + 1 shown in FIG. 4 has an output pulse according to the signal state of the node control unit NC and the enable node Q for controlling the signal state of the enable node Q. A pull-up switching device Trup for outputting Vout), at least one pull-down switching device Tr3 and Tr4 for discharging the output terminal of the pull-up switching device Trup in response to an output pulse from a next stage, and the enable Stabilization switching device (RTr) for periodically discharging the node (Q).

In order for the stages ST1 to STn + 1 configured as described above to output the output pulses Vout1 to Voutn, the enable operation in which the enable node Q of each stage ST1 to STn + 1 is first charged is performed. To this end, each stage ST1 to STn + 1 receives the output pulses from the stage located at the front end from the stage, and makes its enable node Q charged. That is, the k-th stage charges the enabling node Q of the k-th stage with the charging voltage source VDD in response to the output pulse from the k-th stage.

Since the stage does not exist in front of the first stage ST1 positioned first, the first stage ST1 receives the start pulse Vst from the timing controller or the level shifter to receive its enable node Q. Charge with a charging voltage source (VDD).

Further, each stage ST1 to STn + 1 discharges its enable node Q in response to an output pulse from the next stage. That is, the k-th stage discharges the enabling node Q of the k-th stage to the discharge voltage source VSS in response to the output pulse from the k + 1th stage.

The node controller NC includes first and second switching devices Tr1 and Tr2.

The first switching device Tr1 provided in the node controller NC of the kth stage supplies the enabling node Q of the kth stage to the charging voltage source VDD in response to an output pulse from the k-1st stage. Charge with.

To this end, the gate terminal of the first switching device (Tr1) provided in the node control unit (NC) of each stage is connected to the output terminal or the start pulse (Vst) input terminal of the preceding stage, the drain terminal is the charging voltage source ( VDD) is connected to the power supply line. The source terminal is connected to the enable node Q.

For example, the first switching device Tr1 included in the second stage ST2 of FIG. 4 may be configured to respond to the first output pulse Vout1 from the first stage ST1 and may be used to control the second stage ST2. The enable node Q is charged with the charging voltage source VDD. However, since the stage does not exist in front of the first stage ST1, the first switching element Tr1 included in the first stage ST1 responds to the start pulse Vst from the timing controller, thereby providing the first stage. The enable node Q of ST1 is charged with the charging voltage source VDD.

The second switching element Tr2 provided in the node controller NC of the kth stage prevents the enable node Q of the kth stage in response to an output pulse from the k + 1 stage, that is, the next stage. Discharge to a dedicated voltage source (VSS). To this end, the gate terminal of the second switching element Tr2 provided in the node controller NC of the kth stage is connected to the output terminal of the k + 1th stage, and the drain terminal of the enable node Q of the kth stage. ), And the source terminal is connected to a power supply line for transmitting the discharge voltage source (VSS). For example, the second switching device Tr2 provided in the second stage ST2 of FIG. 4 is connected to the second stage ST2 in response to the third output pulse Vout3 from the third stage ST3. The enable node Q is discharged to the discharge voltage source VSS.

Since the clock pulses supplied to the shift register of the present invention are four-phase clock pulses, the following clock pulses are supplied to the drain terminals of the respective pull-up switching devices Trup included in each of the stages ST1 to STn + 1.

That is, the pull-up switching device Trup provided in the 4k + 1 stage receives the first clock pulse CLK1, and the pull-up switching device Trup provided in the 4k + 2 stage receives the second clock pulse CLK2. Is supplied, the pull-up switching device Trup provided in the 4k + 3 stage is supplied with the third clock pulse CLK3, and the pull-up switching device Trup provided in the 4k + 4 stage is the fourth clock. The pulse CLK4 is supplied. Accordingly, the pull-up switching device Trup provided in the second stage ST2 of FIG. 4 receives the second clock pulse CLK2.

At least one pull-down switching element provided in each of the stages ST1 to STn + 1, for example, the third switching element Tr3 of the third and fourth switching elements Tr3 and Tr4 may be the first to fourth portions. In response to one of the clock signals of at least one of the clock pulses CLK1 to CLK4, the enable node Q of the k-th stage is discharged to the discharge voltage source VSS. Here, the third switching device Tr3 receives the clock of any one of four or more reset clocks RC1 to RC4 in addition to the first to fourth clock pulses CLK1 to CLK4, thereby enabling the node of the k-th stage. (Q) may be discharged to the discharge voltage source VSS.

To this end, the gate terminal of the third switching device Tr3 provided in the k-th stage is at least one of the first to fourth clock pulses CLK1 to CLK4 or the first to fourth reset clocks RC1 to RC4. It is connected to the supply line, the drain terminal is connected to the enabling node Q of the k-th stage, and the source terminal is connected to the power supply line for transmitting the discharge voltage source (VSS).

The fourth switching device Tr4 provided in the k-th stage connects the drain terminal and the source terminal of the pull-up switching device Trup in response to the output from the pull-up switching device Trup. To this end, the gate terminal and the drain terminal of the fourth switching device Tr4 provided in the k-th stage are connected to the source terminal of the pull-up switching device Trup, and the source terminal is connected to the drain terminal of the pull-up switching device Trup. do. It is possible to prevent the fourth switching device Tr4 from being degraded by the connection structure of the fourth switching device Tr4.

The gate terminal of the stabilization switching element RTr is connected to at least one clock input line of the plurality of reset clocks RC1 to RC4, the drain terminal is connected to the output pulse of the front stage, and the source terminal is enabled. It is connected to node Q.

Referring to FIG. 3, since the reset clocks RC1 to RC4 supplied to the stabilization switching elements RTr of the stages ST1 to STn + 1 are supplied in four phases, they are provided in each of the stages ST1 to STn + 1. The following clock pulses are supplied to each stabilized switching element (RTr) gate terminal.

That is, the stabilization switching device RTr provided in the 4k + 1 stage receives the first reset clock RC1, and the stabilization switching device RTr included in the 4k + 2 stage receives the second reset clock RC2. Is supplied, and the stabilization switching element RTr provided in the 4k + 3 stage is supplied with the third reset clock RC3, and the stabilization switching element RTr provided in the 4k + 4 stage is the fourth reset clock ( RC4). Accordingly, the stabilization switching device RTr included in the second stage ST2 of FIG. 4 receives the second reset clock RC2. In this way, the reset clock supplied to the gate terminal of each stabilization switching element RTr has a phase ahead of the clock pulse supplied to the drain terminal of the pull-up switching element Trup.

Output pulses from the preceding stage are supplied to the drain terminals of the stabilization switching elements RTr provided in each of the stages ST1 to STn + 1. In other words, the output terminal from the front stage, that is, the k-th stage, is supplied to the drain terminal of the stabilization switching element RTr included in the k-th stage.

The output pulses output from each of the stages ST1 to STn + 1 and the reset clock supplied to the stabilization switching element RTr provided in the next stage have a high state simultaneously for a period equal to the pulse width of the reset clock. That is, the k-th output pulse output from the pull-up switching device Trup included in the k-th stage is an output based on a clock pulse supplied to the drain terminal of the pull-up switching device Trup. The k-th output pulse is k + 1. The reset clock supplied to the gate terminal of the stabilization switching element RTr provided in the stage is simultaneously in the high state for one period, that is, as long as the pulse width of the reset clock.

Here, each of the output pulses Vout1 to Voutn represents a high state for one period in one frame period and a low state for the remaining period in one frame period. The clock pulses corresponding to the output pulses Vout1 to Voutn exhibit a plurality of high states periodically during one frame period. That is, the high state of the output pulses Vout1 to Voutn is any one of a plurality of high states of the clock pulses CLK1 to CLK4.

The stabilization switching element RTr is controlled by the first to fourth reset clocks RC1 to RC4 as described above, and supplies an output pulse output from the front stage to the enable node Q of the stage to which it belongs. do. Since any one of the reset clocks RC1 to RC4 supplied to the gate terminal of each stabilization switching element RTr has several high states during one frame period as described above, each stabilization switching element RTr is one frame. It is turned on several times during the period.

At this time, between any one of the reset clocks RC1 to RC4 supplied to each of the stabilization switching elements RTr and the charger in which the output pulses are simultaneously in the high state, each of the stabilized switching elements RTr turned on is output in the high state. The pulse is supplied to the enable node Q of the stage to which it belongs. Accordingly, the enable node Q is charged.

Then, in the discharge period in which each output pulse and the reset clock have different states, that is, in the period in which the output pulse indicates the low state and the reset clock indicates the high state, the turned-on stabilization switching element RTr is in the low state. The output pulse of is supplied to the enable node (Q) of the stage to which it belongs. Accordingly, the enable node Q of the stage to which it belongs is discharged. At this time, since the reset clocks RC1 to RC4 periodically exhibit a high state, the enable node Q is applied to an output pulse in a low state every time the stabilization switching element RTr is turned on during this discharge period. Discharged periodically.

As described above, the shift register of the present invention can prevent the unwanted voltage from accumulating on the enable node Q by the conventional coupling phenomenon. In addition, in the present invention, the low voltage level rcl of the first to fourth reset clocks RC1 to RC4 is set to be lower than the low voltage level vgl of the first to fourth clock pulses CLK1 to CLK4. Therefore, a greater effect can be obtained in preventing deterioration of the stabilization switching elements provided in each stage ST1 to STn + 1 of the shift register.

Referring to the operation of the shift register according to an embodiment of the present invention configured as described above in detail.

First, the enable operation will be described with reference to the enable node Q charging waveforms of the first and second stages ST1 and ST2 illustrated in FIG. 3, that is, the Q (ST1) and Q (ST2) waveforms. Is the same as

In the enable period of the enable node Q provided in the first stage ST1, as shown in FIG. 3, the start pulse Vst and the fourth clock pulse output from the level shifter controlled by the timing controller. Only CLK4 remains high, and the remaining clock pulses CLK1, CLK2 and CLK3 represent a low state.

At this time, the start pulse Vst is input to the gate terminal of the first switching element Tr1 and the source terminal of the stabilization switching element RTr provided in the first stage ST1. Then, the first switching device Tr1 of the first stage ST1 is turned on, and the charging voltage source VDD is turned on through the turned-on first switching device Tr1. This is supplied to the enabling node Q of the first stage ST1. In addition, during the enable period, the first reset clock RC1 is supplied to the gate terminal of the stabilization switching element RTr. Then, the stabilization switching element RTr is turned on, and at this time, the start pulse Vst is supplied to the enable node Q of the first stage ST1 through the turned-on stabilization switching element RTr. Accordingly, the enable node Q of the first stage ST1 is charged by the charging voltage source VDD and the start pulse Vst in the high state, and the gate terminal of the charged enable node Q is charged. The pull-up switching device Trup to which the is connected is turned on.

On the other hand, since there is no output pulse from the second stage STn + 1 in the enable period, the second switching element Tr2 provided in the first stage ST1 is turned off.

Next, the operation during the output pulse Vout1 output period of the first stage ST1 will be described.

During the output pulse Vout output period, as shown in FIG. 3, only the first clock pulse CLK1 remains high, and the start pulse Vst and the remaining clock pulses CLK2, CLK3, and CLK4 are low. Maintain state. Therefore, the first switching device Tr1 of the first stage ST1 is turned off in response to the start pulse Vst in the low state. At this time, the enabling node Q of the first stage ST1 is maintained in a floating state.

As the enable node Q of the first stage ST1 is kept charged by the charging voltage source VDD applied during the enable period, the gate terminal is connected to the enable node Q. The pull-up switching device Trup remains turned on. At this time, the first clock pulse CLK1 is supplied to the drain terminal of the turned-on pull-up switching device Trup. Then, as shown in FIG. 3, the charging voltage source VDD charged in the enabling node Q of the first stage ST1 is amplified (bootstrapping). This amplification occurs because the enable node Q is in a floating state.

Therefore, the first clock pulse CLK1 supplied to the drain terminal of the pull-up switching device Trup included in the first stage ST1 is stably output through the source terminal of the pull-up switching device Trup. Here, the first clock pulse CLK1 output from the pull-up switching device Trup may be the first output pulse Vout1.

The output first output pulse Vout1 is supplied to the first gate line to serve as a scan pulse for driving the first gate line, and is supplied to the second stage ST2 to supply the second stage ST2. It acts as a start pulse Vst for charging the enabling node Q.

That is, the first output pulse Vout1 output from the first stage ST1 during the output pulse output period is the gate terminal and the second stage ST2 of the first switching element Tr1 provided in the second stage ST2. It is supplied to the drain terminal of the stabilization switching element (RTr) provided in.

Then, the first switching device Tr1 of the second stage ST2 is turned on. In addition, since the second reset clock RC2 in a high state is supplied to the gate terminal of the stabilization switching element RTr included in the second stage ST2, the stabilization switching element RTr of the second stage ST2 is turned on. -ON state.

That is, in the output pulse output period of the first stage ST1, the first switching element Tr1 and the stabilization switching element RTr included in the second stage ST2 are turned on together. The charging voltage source VDD is supplied to the enabling node Q of the second stage ST2 through the turned-on first switching element Tr1. In addition, the first output pulse Vout1 is supplied to the enabling node Q of the second stage ST2 through the turned-on stabilization switching element RTr. Accordingly, the enable node Q of the second stage ST2 is charged by the charging voltage source VDD and the first output pulse Vout1 in the high state, and charged to the charged enable node Q. The pull-up switching device Trup connected to the gate terminal is turned on. At this time, since there is no output pulse from the third stage ST3 which is the next stage, the second switching device Tr2 provided in the second stage ST2 is turned off.

Next, the operation during the output pulse output period of the second stage ST2 will be described.

During the output pulse output period of the second stage ST2, only the second clock pulse CLK2 is maintained high as shown in FIG. On the other hand, the start pulse Vst, the remaining clock pulses CLK1, CLK3, and CLK4 and the first output pulse Vout1 remain low.

Therefore, the first switching device Tr1 of the second stage ST2 is turned off in response to the first output pulse Vout1 in the low state. At this time, as the enable node Q of the second stage ST2 remains in a floating state, the pull-up switching device Trup having a gate terminal connected to the enable node Q maintains a turn-on state. do. In addition, the second clock pulse CLK2 is applied to the drain terminal of the turned-on pull-up switching device Trup. Then, as illustrated in FIG. 3, the voltage source charged in the enabling node Q of the second stage ST2 is amplified (bootstrapping). Therefore, the second clock pulse CLK2 supplied to the drain terminal of the pull-up switching device Trup included in the second stage ST2 is stably output through the source terminal of the pull-up switching device Trup. The second clock pulse CLK2 output from the pull-up switching device Trup is the second output pulse Vout2.

The output second output pulse Vout2 acts as a scan pulse supplied to the second gate line to drive the second gate line, and supplied to the third stage ST3 to supply the third stage ST3. It acts as a start pulse Vst for charging the node Q for the enable. That is, the second output pulse Vout2 output from the second stage ST2 during the output pulse output period is the gate terminal of the first switching element Tr1 and the stabilization switching element RTr provided in the third stage ST3. Is supplied to the drain terminal. Then, as described above, the enable node Q of the third stage ST3 is charged. That is, the third stage ST3 is enabled.

Meanwhile, the second output pulse Vout2 output from the second stage ST2 is supplied to the first stage ST1 to discharge the enable node Q of the first stage ST1. That is, the first stage ST1 is disabled in response to the second output pulse Vout2 from the second stage ST2. If this is explained in more detail as follows.

The second output pulse Vout2 output from the second stage ST2 is supplied to the gate terminal of the second switching element Tr2 provided in the first stage ST1. Then, the second switching device Tr2 is turned on, and the discharge voltage source VSS is turned on to the enabling node Q of the first stage ST1 through the turned-on second switching device Tr2. Supplied. Then, the pull-up switching device Trup connected to the enabling node Q of the discharged first stage ST1 is turned off. The fourth switching device Tr4 of the first stage ST1, which receives the second clock pulse CLK2, is turned on to supply the discharge voltage source VSS to the first gate line. As a result, the first gate line is discharged.

In this manner, the respective output pulses Vout3 to Voutn are output in the enable period and the output pulse output period of each subsequent stage ST3 to STn + 1.

On the other hand, the stabilization switching elements RTr included in each of the stages ST1 to STn + 1 periodically enable the node Q for the low stage voltage after outputting the output voltage of each stage of the front stage, that is, the output pulse. By supplying to, the enable node Q is stabilized.

FIG. 5 is a diagram illustrating another circuit configuration of the second stage shown in FIG. 2.

Each of the stages ST1 to STn + 1 shown in FIG. 5 has an output pulse according to the signal state of the node control unit NC and the enable node Q for controlling the signal state of the enable node Q. The configuration of the stabilization switching device RTr for periodically discharging the pull-up switching device Trup for outputting Vout) and the enabling node Q is the same as the stage configuration of FIG. 4. Therefore, the description thereof will be omitted and only the third and fourth switching devices Tr3 and Tr4 that discharge the output terminal of the pull-up switching device Trup will be described. .

The third switching device Tr3 provided in each of the stages ST1 to STn responds to a clock signal of any one of at least one clock pulse among the first to fourth clock pulses CLK1 to CLK4. The output terminal of (Trup) is discharged with a low level clock pulse. Here, the third switching device Tr3 receives the clock of any one of four or more reset clocks RC1 to RC4 in addition to the first to fourth clock pulses CLK1 to CLK4 and outputs the output terminal of the pull-up switching device Trup. Can be discharged to a low level clock pulse or reset clock.

To this end, the gate terminal of the third switching device Tr3 provided in the k-th stage is at least one of the first to fourth clock pulses CLK1 to CLK4 or the first to fourth reset clocks RC1 to RC4. The drain terminal is connected to the output terminal of the pull-up switching element Trup, and the source terminal is connected to the source terminal of the fourth switching element Tr4.

On the other hand, in each stage (ST1 to STn) of the present invention, as shown in Figure 5, the reset for discharging the enable node (Q) to the discharge voltage source (VSS) in accordance with the start pulse (Vst) input from the outside The switching element STr may be further provided.

As described above, the shift register of the present invention can prevent the unwanted voltage from accumulating on the enable node Q by the conventional coupling phenomenon. In addition, in the present invention, the low voltage level rcl of the first to fourth reset clocks RC1 to RC4 is set to be lower than the low voltage level vgl of the first to fourth clock pulses CLK1 to CLK4. Therefore, a greater effect can be obtained in preventing deterioration of the stabilization switching elements provided in each stage ST1 to STn + 1 of the shift register.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a view showing a circuit configuration provided in a conventional stage.

2 is a block diagram illustrating a shift register according to an exemplary embodiment of the present invention.

3 is a waveform diagram illustrating a signal supplied to the shift register of FIG. 2 and a signal output from the shift register;

4 is a diagram showing the circuit configuration of the second stage shown in FIG.

FIG. 5 shows another circuit configuration of the second stage shown in FIG. 2; FIG.

* Brief description of symbols for the main parts of the drawings.

Tr: switching element RTr: stabilization switching element

ST2: second stage Vout2: second output pulse

VDD: Voltage source for charging VSS: Voltage source for discharge

Q: Enable node Trup: Pull-up switching device

Trpd: Pull-down switching device NC: Node control

Vout1: First output pulse CLK: Clock pulse

Vout3: third output pulse STr: reset switching element

Claims (10)

It includes a plurality of stages to receive at least one clock pulse of a plurality of clock pulses having a different phase difference and to sequentially output the output signal, Each stage A pull-up switching element configured to output at least one clock pulse among the plurality of clock pulses as the output signal according to a signal state of an enable node; And In response to at least one reset clock of a plurality of reset clocks supplied with a low voltage level lower than the low level voltages of the respective clock pulses, an external start pulse or an output signal from a previous stage is supplied to the enable node. A shift register comprising a stabilizing switching element for supplying. The method of claim 1, Each of the plurality of clock pulses The clock pulses generated adjacent to each other are generated to maintain an active state simultaneously with each other for a predetermined period of time, and are supplied to corresponding stages so as to circulate with each other. The plurality of reset clocks are each And a width smaller than a pulse width of the plurality of clock pulses so as to correspond to each of the clock pulses. The method of claim 2, The plurality of reset clocks It is generated in 4 phases corresponding to 4 phase clock pulses. The first reset clock is supplied to the stabilization switching device provided in the 4k + 1 stage (k is a natural number including 0), the second reset clock is supplied to the stabilization switching device provided in the 4k + 2 stage, and the third The reset clock is supplied to the stabilization switching device provided in the 4k + 3 stage, and the fourth reset clock is supplied to the stabilization switching device provided in the 4k + 4 stage. The method of claim 3, wherein The first reset clock is Among the clock pulses generated in four phases, the state changes from the low state to the high state in the period between when the fourth clock pulse changes from the low state to the high state and when the first clock pulse changes from the low state to the high state. Change from a high state to a low state in a period between a time point when the first clock pulse changes from a low state to a high state and a time point when the fourth clock pulse changes from a high state to a low state, The second reset clock is The period between the time when the first clock pulse changes from the low state to the high state and the time when the second clock pulse changes from the low state to the high state changes from the low state to the high state, and the second clock pulse is low. And a shift register from a high state to a low state in a period between a time point when the state changes from the high state and the time point when the first clock pulse changes from the high state to the low state. The method of claim 4, wherein In the blank time during which the output of the output signals is stopped, The plurality of clock pulses are maintained at a low voltage level to be supplied to each stage, and the plurality of reset clock levels are maintained at a low voltage level lower than the low voltage level of each clock pulse to stabilize the switch. And a shift register. The method of claim 5, Each stage A node controller for controlling a signal state of the enable node; And at least one pull-down switching element for discharging the output terminal of the pull-up switching element in response to an output signal from a next stage. The method of claim 6, The node control unit A first switching element for charging the enable node of the current stage with a charging voltage source in response to an output pulse from a front stage or a start pulse from outside; and And a second switching element for discharging the enable node of the current stage to a discharge voltage source in response to an output pulse from a next stage. The method of claim 7, wherein The at least one pull-down switching device A third switching device for discharging the output terminal of the pull-up switching device to the discharge voltage source in response to a clock pulse of at least one of the first to fourth clock pulses or the first to fourth reset clocks; And a fourth switching element for connecting between the drain terminal and the source terminal of the pull-up switching element in response to an output signal from the pull-up switching element. The method of claim 8, The third switching device is And discharging the output terminal of the pull-up switching device to a low voltage level of the at least one clock pulse in response to at least one of the first to fourth clock pulses or the first to fourth reset clocks. Shift register. The method of claim 7, wherein In each stage And a reset switching device for discharging each of the enable nodes to the discharge voltage source in response to the start pulse.

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