KR20180012077A - Gate driving circuit and display device using the same - Google Patents

Abstract

The present invention relates to a gate driving circuit and a display device using the same which can improve output signal properties and reliability of a GIP circuit. The display device comprises: a first transistor charging an output terminal with a high-level voltage of a first clock while a Q node is charged; a second transistor for discharging the Q node in response to a second clock; and a third transistor for discharging the output terminal in response to a third clock. A low-level voltage of at least any one of the second and third clocks is lower than a low-level voltage of the first clock.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate driving circuit,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driving circuit and a display device using the same.

The display device includes a data driving circuit for supplying a data signal to the data lines of the pixel array, a gate for sequentially supplying a gate pulse (or a scan pulse) synchronized with the data signal to the gate lines (or scan lines) A driving circuit (or a scan driving circuit), a timing controller for controlling the data driving circuit and the gate driving circuit, and the like.

Each of the pixels may include a thin film transistor (TFT) that supplies a voltage of the data line to the pixel electrode in response to the gate pulse. The gate pulse swings between the gate high voltage (VGH) and the gate low voltage (VGL). The gate high voltage VGH is set to a voltage higher than the threshold voltage of the pixel TFT and the gate low voltage VGH is set to a voltage lower than the threshold voltage of the pixel TFT.

Recently, a technique of embedding a gate drive circuit in a display panel together with a pixel array has been applied. Hereinafter, the gate drive circuit incorporated in the display panel will be referred to as a " GIP (Gate In Panel) circuit ". The GIP circuit includes a shift register. The shift register includes a plurality of stages connected in a dependent manner. The stages generate an output in response to the start pulse and shift the output according to the shift clock.

Each of the stages of the shift register includes a Q node that charges the gate line, a QB node that discharges the gate line, and a switch circuit that is connected to the Q node and the QB node. The switch circuit charges the Q node in response to the start pulse or the output of the previous stage and discharges the Q node in response to the output of the next stage or the reset pulse.

The switch circuit includes transistors of a metal oxide semiconductor field effect transistor (MOSFET) structure. These transistors degrade device characteristics due to DC gate bias stress. The DC gate bias stress increases as the DC voltage applied to the gate of the transistor is higher and the application time is longer. The transistors are shifted in the threshold voltage by DC gate bias stress in FIG. 1, and the on current is reduced. In particular, the threshold voltage shift due to the DC gate bias stress at a high temperature becomes larger than the room temperature, which further adversely affects the reliability of the product in a high temperature environment. Here, the high temperature environment may be defined differently depending on the application field because the use temperature varies depending on the application field of the product.

1 is a diagram showing an example in which a threshold voltage of a transistor is positively shifted due to a DC gate bias stress of the transistor. In Fig. 1, Vgs (V) is the gate-source voltage of the MOSFET. Ids (A) is the drain-source current of the MOSFET.

In the GIP circuit, the transistors switching the discharge path of the Q node receive a large amount of DC gate bias stress. When the transistors of the GIP circuit are implemented as NMOS transistors, the threshold voltage of the transistors shifts in the positive direction as the driving bias is repeatedly applied to the gate-source of the transistors. As a result, the low level voltage of the Q node and the low level voltage of the gate lines become unstable, so that one or more abnormal output voltages from the GIP circuit can be applied to the gate lines. As a result, the output signal characteristic of the GIP circuit becomes unstable and the reliability of the GIP circuit becomes low. Due to the abnormal output voltage of the GIP circuit, the leakage current flows through the TFTs of the pixel array so that the voltage of the pixels can be discharged.

The present invention provides a gate driver circuit and a display device using the same that can improve the output signal characteristics and reliability of a GIP circuit.

A gate drive circuit of the present invention includes a first transistor for charging an output terminal with a high level voltage of a first clock in a state where a Q node is charged, a second transistor for discharging the Q node in response to a second clock, And a third transistor for discharging the output terminal in response to the third clock. And the low level voltage of at least any one of the second and third clocks is lower than the low level voltage of the first clock. The high level voltage of each of the second and third clocks is equal to the high level voltage of the first clock.

The phase of the second clock is faster than the first clock and slower than the third clock. The third clock is generated as a reverse phase clock with respect to the first clock. The first clock swings between a high level voltage and a first low level voltage, and each of the second and third clocks swings between the high level voltage and the second low level voltage. And the second low level voltage is lower than the first low level voltage.

The present invention can improve the reliability of the GIP circuit by compensating for the DC gate bias stress of the transistor by applying a bias voltage of the opposite polarity. Therefore, the present invention can secure the operation margin of the GIP circuit, and can stably drive the GIP circuit during long-time driving or in a high-temperature environment.

The present invention can improve the polling time of the clock and improve the output signal characteristic of the GIP circuit. Further, since the present invention can be widely applied to a transistor including amorphous silicon (a-Si) or a transistor-based display including an oxide semiconductor by securing the reliability of the GIP driving circuit, the application model can be expanded.

1 is a diagram showing an example in which the threshold voltage of a transistor is positively shifted due to a DC gate bias stress of the transistor.
2 is a block diagram schematically showing a display device according to an embodiment of the present invention.
3 is a diagram showing one frame period of the display device.
4 is a block diagram showing the GIP circuit of the present invention.
5 is a detailed circuit diagram of a GIP circuit according to the first embodiment of the present invention.
FIGS. 6 and 7 are waveform diagrams showing input / output signals and Q node waveforms showing the operation of the GIP circuit shown in FIG.
Figures 8A-8H show the gate-source voltages of each of the transistors in a GIP circuit operating as in Figures 5-7.
9 is a diagram showing a GIP circuit according to the second embodiment of the present invention and input / output signals thereof.
10 is a diagram showing a GIP circuit according to the third embodiment of the present invention and input / output signals thereof.
11 is a view showing a GIP circuit according to a fourth embodiment of the present invention and input / output signals thereof.
12 shows a GIP circuit according to the fifth embodiment of the present invention and input / output signals thereof.
13 shows a GIP circuit according to the sixth embodiment of the present invention and input / output signals thereof.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The display device of the present invention can be implemented as a flat panel display device such as a liquid crystal display (LCD), an organic light emitting display (OLED) display, or the like. In the following embodiments, the liquid crystal display device will be described as an example of the flat panel display device, but the present invention is not limited thereto. For example, the display device of the present invention may be any display device requiring a gate drive circuit.

In the gate driving circuit of the present invention, the switching elements may be implemented as n-type or p-type metal oxide semiconductor field effect transistor (MOSFET) transistors. Although n-type transistors are exemplified in the following embodiments, it should be noted that the present invention is not limited thereto. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the transistor, the carriers begin to flow from the source. The drain is an electrode from which the carrier exits from the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, the direction of current flows from drain to source because electrons flow from source to drain. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, the current flows from the source to the drain because the holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed depending on the applied voltage. In the following description of the embodiment, the source and the drain of the transistor will be referred to as first and second electrodes. It should be noted that the invention is not limited by the source and drain of the transistor in the following description.

The transistors constituting the gate drive circuit of the present invention may be implemented with at least one of a transistor including an amorphous silicon (a-Si), a transistor including an oxide semiconductor, and a transistor including a low temperature polysilicon (LTPS) .

The gate driving circuit of the present invention includes a first transistor for charging an output terminal with a voltage of a first clock when a first clock is inputted in a state where a Q node is charged, a second transistor for discharging a Q node in response to a second clock, And a third transistor for discharging the output terminal in response to the third clock. The low level voltage of at least one of the second and third clocks is lower than the low level voltage of the first clock. The high level voltage of each of the second and third clocks is equal to the high level voltage of the first clock. The first clock is CLK (N) in the embodiment, the second clock is CLK (N-1) or CLK (N-1) 'in the embodiment and the third clock is / CLK (N) CLK (N) ', respectively. The first transistor is described as T6 or T6_C in the embodiment, the second transistor as T3C in the embodiment, and the third transistor as T7C in the embodiment, respectively.

2 and 3, a display device according to an embodiment of the present invention includes a display panel PNL, a display panel driving circuit for writing data of an input image to a pixel array of the display panel PNL, Respectively.

The display panel PNL is formed in the form of a matrix defined by the data lines 12, the gate lines 14 orthogonal to the data lines 12, and the data lines 12 and gate lines 14 And a pixel array in which pixels are arranged. The input image is displayed on the pixel array.

The pixels of the pixel array may include red (R), green (G), and blue (B) subpixels for color implementation. The pixels may further include white (W, W) subpixels in addition to RGB subpixels. The pixels may further include one or more of blue, cyan, magenta, yellow, and yellow subpixels.

The pixel array of the display panel (PNL) includes a TFT array and a color filter array. A TFT array may be formed on the lower plate of the display panel (PNL). The TFT array includes TFTs (Thin Film Transistors) formed at intersections of the data lines 12 and the gate lines 14, pixel electrodes for charging data voltages, storage capacitors Storage Capacitor, Cst), and the like.

The top plate of the display panel (PNL) may include a color filter array formed on the top substrate. The color filter array includes a black matrix, a color filter, and the like. In the case of a color filter on TFT (COT) or a TFT on color filter (TOC) model, a color filter and a black matrix may be arranged in a TFT array.

A touch screen using an in-cell touch sensor may be implemented on the display panel PNL. The touch sensor of Incell Time is embedded in the pixel array of the display panel (PNL). The touch sensors may be disposed on the display panel PNL in an on-cell type or an add-on type. The touch sensor may be implemented by a capacitive type touch sensor, for example, a mutual capacitance sensor or a self capacitance sensor.

The display panel driving circuit includes a data driver 16, gate drivers 18 and 22, and a timing controller (TCON) 20 to write data of the input image to the pixels of the display panel 100.

The data driver 16 includes one or more source drive ICs (SIC). The data driver 16 converts digital video data of an input image received from the timing controller 20 into a gamma compensation voltage to output a data voltage. The data voltages output from the data driver 16 are supplied to the data lines 12. A multiplexer (not shown) may be disposed between the data driver 16 and the data lines 12. [ The multiplexer distributes the data voltages input from the data driver 16 to the data lines 12 under the control of the timing controller 20. [ In the case of the 1: 2 multiplexer, the multiplexer time-divides the data voltages input through one output channel of the data driver 16 and supplies the data voltages to the two data lines in a time division manner. Therefore, when the 1: 2 multiplexer is used, the number of channels of the source drive IC (SIC) can be reduced to 1/2.

The gate drivers 18 and 22 include a GIP circuit 18 directly mounted on the TFT array substrate in the display panel PNL and a level shifter 18 disposed between the timing controller 20 and the GIP circuit 18, LS) < / RTI >

The GIP circuit 18 includes a shift register. The GIP circuit 18 may be formed on one side edge of the display panel PNL outside the pixel array or on both side edges thereof. The level shifter 22 increases the swing width of the gate timing control signal voltage to the gate high voltage (VGH) and the gate low voltage (VGL) and outputs it to the GIP circuit (18).

The GIP circuit 18 shifts the gate pulse in accordance with the shift clock timing and sequentially supplies gate pulses to the gate lines 14. [ The gate pulse swings between the gate high voltage (VGH) and the gate low voltage (VGL). The gate high voltage (VGH) is higher than the threshold voltage of the TFTs disposed in the pixel array. The gate-low voltage VGL is lower than the threshold voltage of the TFTs disposed in the pixel array. The TFTs of the pixel array are turned on in response to the gate high voltage VGH of the gate pulse to supply the data voltage from the data lines 12 to the pixel electrodes.

The shift register of the GIP circuit 18 includes stages that are cascade connected to shift the output to the clock timing. Each of the stages outputs a gate pulse to the gate lines 14 in response to the voltage of the Q node, and carries the carry signal to another stage. The gate pulse and the carry signal may be the same signal or separated. The Q node is charged according to the start pulse or the carry signal from the previous stage to pre-charge the gate of the pull-up transistor. The Q node is bootstrapped through the parasitic capacitance between the gate and the drain of the pull-up transistor when the shift clock is input in the precharged state. When the voltage of the Q node is raised by bootstrapping, the pull-up transistor is turned on so that the voltage of the output terminal rises to the gate high voltage VGH and the gate pulse starts to be output. The gate pulse is supplied to the gate lines 14 to simultaneously turn on the TFTs of the line in which the data voltage is written.

The timing controller 20 transmits the digital video data of the input image received from the host system (not shown) to the data driver 16. The timing controller 20 inputs a timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a main clock MCLK received in synchronization with the input video data And outputs a data timing control signal for controlling the operation timing of the data driver 16 and a gate timing control signal for controlling the operation timing of the operation timing of the GIP circuit 18. [

The gate timing control signal includes a start pulse VST, a shift clock CLK, an output enable signal GOE, and the like. The output enable signal (GOE) may be omitted. The start pulse VST is input to the VST terminal of the first stage in the shift register to control the output timing of the first gate pulse that occurs first in one frame period. The shift clock (CLK) is generated sequentially during the display period to control the output timing of the gate pulse in each of the stages to control the shift timing of the gate pulse.

The host system may be implemented in any one of a television system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system. The host system includes a system on chip (SoC) with a built-in scaler to convert the digital video data of the input image into a format suitable for display on the display panel 100. The host system transmits timing signals (Vsync, Hsync, DE, MCLK) to the timing controller 20 together with the digital video data of the input video. The host system executes the application program associated with the coordinate information of the touch input received from the touch sensing unit 110. [

3 is a diagram showing one frame period of the display device.

Referring to FIG. 3, the vertical synchronization signal Vsync defines one frame period. The horizontal synchronization signal (Hsync) defines one horizontal period. The data enable signal DE defines an effective data interval. The data enable signal DE is synchronized with the valid data to be displayed on the pixel array of the display panel P100. One pulse period of the data enable signal DE is one horizontal period, and a high logic period of the data enable signal DE indicates one line data input timing. One horizontal period is a time required to write data to pixels of one line in the display panel 100. [

One frame period is divided into one vertical active period (AT) and one vertical blank period (VB). The data enable signal DE and the valid data of the input image are input during the vertical active period AT and are not input to the vertical blank period VB. The vertical active period (AT) is a time period for writing one frame of data to all the pixels of the pixel array in which the image is displayed in the display panel 100.

As can be seen from the data enable signal DE, no input data is received on the display device during the vertical blank period. The vertical blank period VB includes a vertical sync time VS, a vertical front porch FP, and a vertical back porch BP. The vertical sync time (VS) is the time from the falling edge of the Vsync to the rising edge, and indicates the start (or end) timing of one screen. The vertical front porch FP is the time from the falling edge of the last DE pulse indicative of the last line data timing of one frame data to the start of the vertical blank period VB. The vertical back porch BP is the time from the end of the vertical blank period VB to the rising edge of the first DE pulse indicative of the first line data timing of one frame of data.

4 is a block diagram illustrating the GIP circuit 18 of the present invention.

Referring to FIG. 4, the GIP circuit 18 of the present invention includes a shift register. The shift register includes the stages S (N-1) to S (N + 1) that are connected in a dependent manner. The stages S (N-1) to S (N + 1) start outputting the gate pulse in response to the start pulse Vst and shift the output in response to the shift clock Output CLK (Control CLK) . Output signals sequentially output from the stages S (N-1) to S (N + 1) are supplied to the gate lines 14 as gate pulses. The output of each of the stages S (N-1) to S (N + 1) is transferred to the next stage as a carry signal. The carry signal is input to the VST terminal of the next stage. A signal input to the VST terminal (hereinafter referred to as " VST signal ") is a signal for precharging the Q node. The carry signal is input to the VNEXT terminal of the front stage. The signal input to the VNEXT terminal discharges the Q node.

The shift clock of the GIP circuit 18 is divided into an output clock (Output CLK) and a control clock (Control CLK). The output clock Ouput CLK is a clock CLK1 to CLK4 swinging between the gate high voltage VGH and the first gate low voltage VGL1 as shown in FIG. The control clock (Control CLK) is a clock CLK1 'to CLK4' that swings between the gate high voltage VGH and the second gate low voltage (hereinafter referred to as "VGL2") as shown in FIG. VGL2 is a voltage lower than VGL1. The reason why the VGL potential of the control clock (Control CLK) is lower than the VGL potential of the output clock (Output CLK) is to cancel the stress applied to the transistors of the GIP circuit by the opposite polarity stress to restore the threshold voltage shift. In the prior art, only the output clock (Output CLK) is input to the shift register.

Each of the stages S (N-2) to S (N + 2) includes input / output terminals such as a VST terminal, a VDD terminal, a VSS terminal, a VNEXT terminal, a VRST terminal, a VBLK terminal and an output terminal. The VST terminal receives a start pulse (VST) or a carry signal from the preceding stage. The start pulse VST is input to the VST terminal of the first stage and the carry signal Vgout (N-2) from the preceding stage is received at the other stages. The output terminal is connected to the gate line 14.

The power supply voltage applied to the VDD terminal is maintained at VGH during the vertical active period (AT) and lowered to VGL2 during the vertical blank period (VB). As a sufficient negative bias voltage is applied to the gate-source of the transistors during the vertical blank period VB, VGL2 lower than VGL1 is applied to the VDD terminal.

The gate-low voltage (hereinafter referred to as " VGL ") may be divided into VGL1 and VGL2. VGL1 is applied to the VSS1 terminal as shown in Fig. A voltage at which VGL is varied is applied to the VSS2 terminal. VGL2 is applied to the VSS2 terminal during the vertical active period (AT), and VGL2 lower than VGL1 is applied as a sufficient negative bias voltage is applied to the gate-source of the transistors during the vertical blank period (VB).

The reset signal VRST is applied to the VRST terminal. The reset signal VRST is generated immediately after the power supply of the display device is turned on, and is generated in the vertical blank period every frame period. The reset signal VRST is commonly input to the VST terminals of all the stages to simultaneously discharge the Q nodes to initialize the shift register.

The blank signal VBLK is generated at VGL2 so that a negative bias voltage can be sufficiently applied to the gate-source of the transistors during the vertical active period AT every frame period. And the blank signal VBLK is generated with the VGH voltage to turn on the transistors T3R and T7B in the vertical blank period VB. When the fifth transistor T3R is turned on, the voltage of the Q node is lowered to VGL2. When the eighth transistor T7B is turned on, the voltage of the output terminal is lowered to VGL1. The blank signal VBLK is commonly input to the VBLK terminals of all the stages to simultaneously discharge the Q nodes to initialize the shift register. The blank signal VBLK is longer in pulse width than the reset signal VRST. For example, the blank signal VBLK may be generated with a pulse width of 2/1 or more of the vertical blank period VB and a maximum vertical blank period VB.

5 is a detailed circuit diagram of a GIP circuit according to the first embodiment of the present invention. Fig. 5 illustrates the circuit of the N-th stage shown in Fig. Each of the stages constituting the shift register is substantially the same as the N stage shown in Fig. 6 is a waveform diagram showing an input / output signal and a waveform of a Q node showing the operation of the GIP circuit shown in FIG. 7 is a circuit diagram showing the configuration of the output clocks CLK (N-1) and CLK (N), the control clocks CLK (N-1) 'and CLK And a gate pulse Vgout (N)

Referring to FIGS. 5 to 7, the N-th stage S (N) includes a VGH of a first clock CLK (N) when a first clock CLK (N) A second transistor T3C for discharging the Q node in response to the second clock CLK (N-1) ', and a second transistor T3C for discharging the third clock CLK (N-1) And a third transistor T7C for discharging the output terminal.

The first transistor T6 outputs a voltage VGH of the first clock CLK (N) when the first clock CLK (N) is input through the first CLK terminal in a state where the Q node voltage is charged. Up transistor for charging the terminal. When the output terminal is charged by the first transistor T6, the gate pulse Vgout (N) starts to be supplied to the gate line 14. [ The gate pulse Vgout (N) is supplied as a carry signal to the VST terminal of the next stage and the VNEXT terminal of the previous stage. The first transistor T6 includes a gate coupled to the Q node, a first electrode coupled to the output CLK terminal, and a second electrode coupled to the output terminal.

The second transistor T3C responds to CLK (N-1) 'inputted through the second CLK terminal and outputs the Q node to the output terminal Vgout (N-1) of the (N-1) th stage S ). When Vgout (N-1) is VGH when CLK (N-1) 'is VGH, the Q node is charged. When Vgout (N-1) is VGL1 when CLK (N-1) 'is VGH, the Q node is discharged. The second transistor T3C includes a gate connected to the second CLK terminal, a first electrode connected to the Q node, and a second electrode at the output terminal of the (N-1) th stage S (N-1).

The third transistor T7C is a pull-down transistor that discharges the output terminal to VGL2 in response to the third clock / CLK (N) 'input via the third CLK terminal. The third clock CLK (N) 'is generated in the reverse phase of the output clock CLK (N) and is phase-shifted faster than the first control clock CLK (N-1)' by one horizontal period. When the output terminal is discharged by the third transistor T7C, since the gate line 14 is discharged to VGL2 lower than VGL1, the falling time of the gate pulse is shortened and the polling timing is improved. The third transistor T7C includes a gate connected to the third CLK terminal, a first electrode connected to the output terminal, and a second electrode connected to the VSS2 terminal.

The low level voltage VGL2 of the second and third clocks CLK (N-1) 'and / CLK (N)' is lower than the low level voltage VGL1 of the first clock CLK (N). The high level voltage VGH of each of the second and third clocks CLK (N-1) 'and / CLK (N)' is equal to the high level voltage VGH of the first clock CLK (N).

The phase of the second clock CLK (N-1) 'is faster than the first clock CLK (N) and slower than the third clock (/ CLK (N)'). The third clock (/ CLK (N ')) is generated with a reverse phase clock with respect to the first clock (CLK (N)). The first clock CLK (N) swings between VGH and VGL1 and each of the second and third clocks CLK (N-1) 'and CLK (N)' swings between VGH and VGL2. VGL2 is lower than VGL1.

The N-th stage S (N) includes a VST terminal to which a start signal VST for precharging the Q node is applied, a VGH generated during the vertical active period AT and a VGL2 generated during the vertical blank period VB A VDD terminal to which VDD is applied, a VSS1 terminal to which VSS1 generated at VGL1 is applied during a vertical active period (AT) and a vertical blank period (VB), a VSS1 terminal generated at VGL1 during a vertical active period (AT) A VNEXT terminal to which the output signal Vgout (N + 2) of the next stage S (N + 2) is applied and a VNEXT terminal to which the VSS2 terminal generated by VGL2 are applied, and VGL1 during the vertical active period AT And a VBLK terminal to which a blank signal VBLK generated at VGL is applied during the vertical blank period VB.

The Nth stage S (N) includes a fourth transistor T1 for precharging the Q node to VGH in response to the start signal VST, a fifth transistor T1 for discharging the Q node to VGL2 in response to the blank signal VBLK, A sixth transistor T3N for discharging the Q node to the second low level voltage in response to the output signal Vgout (N + 2) of the transistor T3R and the next stage S (N + 2) A seventh transistor T7D having a first electrode to which a first signal CLK (N) is applied, a second electrode connected to the output terminal and a gate, and a seventh transistor T7D for discharging the voltage of the output terminal to VGL1 in response to the blank signal VBLK 8 transistor T7B.

The fourth transistor T1 applies VGH to the Q node in response to the VST signal to pre-charge the Q node. The voltage of the Q node is boosted by charging the voltage applied through the fourth transistor T1. The fourth transistor T1 includes a gate connected to the VST terminal, a first electrode connected to the VDD terminal, and a second electrode connected to the Q node.

The fifth transistor T3R connects the Q node to the VSS2 terminal in response to the vertical blank signal VBLK input through the VBLK terminal to discharge the Q node to VGL2 during the vertical blank period VB. The fifth transistor T3R includes a gate connected to the VBLK terminal, a first electrode connected to the Q node, and a second electrode connected to the VSS2 terminal.

The sixth transistor T3N connects the Q node to the VSS2 terminal in response to the signal input through the VNEXT terminal, thereby discharging the Q node. The sixth transistor T3N includes a gate connected to the VNEXT terminal, a first electrode connected to the Q node, and a second electrode connected to the VSS2 terminal.

The seventh transistor T7D is turned on when the voltage of the output terminal rises above its threshold voltage, while it remains off when the voltage of the output terminal is VGL1 or VGL2. The seventh transistor T7D operates as a diode. When the voltage of the output CLK is VGL1 and a ripple higher than VGL1 is generated in the gate line 14, the seventh transistor T7D is turned on so that the ripple voltage of the gate line 14 becomes the seventh transistor T7D ) And the first CLK terminal. Thus, the gate line 14 keeps the VGL stable during the remaining frame period except for the gate pulse. The gate and the second electrode of the seventh transistor T7D are connected to the output terminal. The first electrode of the seventh transistor T7D is connected to the first CLK terminal.

The eighth transistor T7B discharges the output terminal to VGL1 in response to the blank signal VBLK input through the VBLK terminal. The eighth transistor T7B includes a gate connected to the VBLK terminal, a first electrode connected to the output terminal, and a second electrode connected to the VSS1 terminal.

The transistors T1, T3N, T3R, T3C, T6, T7C, T7D, and T7B are illustrated as NMOS transistors, but are not limited thereto. The transistors T1, T3N, T3R, T3C, T6, T7C, T7D, and T7B may be PMOS transistors.

5 and 6, when a start signal such as a start pulse VST or a carry signal Vgout (N-2) from the preceding stage stage is applied through the VST terminal, the Q node Precharged and boosted. The first transistor T6 is turned on and a gate pulse is output through the output terminal when the first clock CLK (N) is generated at the VGH voltage in the state where the Q node is boosted. When one gate pulse is outputted, the Q node is discharged to VGL2 by the VNEXT signal (Vgout (N + 2)), and the gate pulse is not outputted until the signal is inputted again to the VST terminal. The Q node is discharged for every second clock CLK (N-1) 'through the second transistor T3C so that the first transistor T6 stably maintains the OFF state. The eighth transistor T7B stably maintains the voltage of the gate lines 14 to VGL1 during the vertical blank period VB.

The first clock CLK (N) belongs to the output clock (Output CLK) in Fig. The second and third clocks CLK (N-1) 'and / CLK (N)' belong to the control clock (Control CLK) in FIG.

The output clock (Output CLK) includes clocks (CLK1 to CLK4) swinging between VGH and VGL1 and sequentially shifted by one horizontal period (1H). The control clock (Control CLK) includes clocks CLK1 'to CLK4' that swing between VGH and VGL2 and are sequentially shifted by one horizontal period (1H). VGH may be set to a DC voltage of 28 V or higher, but is not limited thereto. VGL2 is a voltage lower than VGL1. VGL1 is -5 V and VGL2 is -15 V, but is not limited thereto.

 The output clock (Output CLK) and the control clock (Control CLK) are generated by a 4-phase clock, but are not limited thereto. For example, the clock may be generated with an 8-phase clock. Each of the output clock (Output CLK) and the control clock (Control CLK) may be generated with a pulse width of two horizontal periods (2H), but is not limited thereto.

5, the first clock signal CLK (N) and the third clock signal / CLK (N) 'are in opposite phase to each other and have different voltages. For example, when CLK (N) = CLK3 / CLK (N) 'is CLK1'. The voltage of the first clock CLK (N) swings between VGH and VGL1. On the other hand, the voltage of the second and third clocks CLK (N-1) ', / CLK (N) swings between VGH and VGL2. VGL2 is a voltage lower than VGL1. Therefore, the swing width of the second and third clocks CLK (N-1) 'and / CLK (N)' is larger than that of the first clock CLK (N).

The second clock CLK (N-1) 'has a phase faster than the first clock CLK (N) and is slower in phase than the third clock (/ CLK (N)'). The second clock CLK (N-1) 'has a phase faster than the start signal input through the VST terminal. CLK (N-1) 'is CLK2' and / CLK (N) 'is CLK1' when CLK (N) = CLK3.

According to the prior art, when the transistors of the GIP circuit are implemented as NMOS transistors, the threshold voltages of the transistors are shifted in the positive direction due to the gate bias strains whose positive bias voltage is larger than the negative bias voltage. The present invention compensates for the gate bias stress of these transistors with a bias voltage of opposite polarity, thereby reducing the gate bias stress of the transistors constituting the GIP circuit. For example, in a GIP circuit, a negative bias voltage as much as a positive bias applied to T3C and T7C, which is most vulnerable to gate bias stress, can be prevented to prevent a threshold voltage shift of the transistors, thereby improving the reliability and lifetime of the GIP circuit.

The present invention separates a shift clock signal applied to the GIP circuit into an output clock (Output CLK) and a control clock (Control CLK). As a result, the present invention can stably apply the negative bias voltage to the transistors without adding additional transistors without affecting the normal operation of the GIP circuit by isolating the clock signal.

On the other hand, if a separate transistor is added to apply a negative bias voltage to the transistor, the gate bias stress of the added transistor must be compensated, which complicates the GIP circuit.

Figures 8A-8H show the gate-source voltage (Vgs) of each of the transistors in a GIP circuit operating as in Figures 5-7.

Referring to Fig. 8A, the voltage of the VDD terminal is generated at VGH during the vertical active period (AT) and lowered to VGL2 during the vertical blank period (VB). The voltage VQ (N) of the Q node is precharged to the VGH during the 2 horizontal periods 2H by the VST signal so that the Q node is boosted and the first clock CLK (N) is generated in the VGH When it is increased by 2VGH. At this time (NB section), the source of the fourth transistor T1 is the first electrode connected to the VDD terminal since it is an electrode having a lower voltage than the drain. In the NB period, Vgs of the fourth transistor T1 is Vgs = VGL1 - VGH. Therefore, in the NB period, Vgs of the fourth transistor T1 is a negative bias voltage (Vgs < 0).

During the vertical blank period VB, the voltage at the VDD terminal is lowered to VGL2. At this time, the source of the fourth transistor T1 is the first electrode connected to VDD. During the vertical blank VB, Vgs of the fourth transistor T1 is Vgs = VGL1 - VGL2. Therefore, during the vertical blank VB, Vgs of the fourth transistor T1 is a positive bias voltage (Vgs > 0).

The fourth transistor T1 is turned on because a positive bias Vgs > 0 is applied to the fourth transistor T1 during the vertical blank period VB. The drain and the source of the fourth transistor T1 can be shorted when the Q node voltage is higher than the voltage of the VDD terminal during the vertical blank period VB in the state where the fourth transistor T1 is turned on. To prevent such a phenomenon, the voltage of the VDD terminal should be lowered to VGL2 during the vertical blank period VB and the voltage of the Q node should be lowered to VGL2 by using the fifth transistor T3R so as not to affect the GIP driving.

Referring to FIG. 8B, the second transistor T3C is most vulnerable to gate bias stress because it receives a positive bias whenever the second clock CLK (N-1) 'is applied to the gate.

The output signal Vgout (N-1) of the front stage stage S (N-1) is applied so that the second transistor T3C does not affect the boost operation of the Q node. (N-1) 'is applied during the PB period in which the voltage of the second clock CLK (N-1)' is VGH, and the second clock CLK (Vgs = VGH-VGL1, Vgs > 0) is applied to the second transistor T3C during each of the PB periods to turn on the second transistor T3C The voltage of the Q node becomes VGL1 every time the second transistor T3C is turned on. In FIG. 8B, CLK2 'is the second clock CLK (N-1)'.

The second electrode to which the voltage Vgout (N-1) is applied for the second clock CLK (N-1) 'during the VGL2 section is the source of the second transistor T3C, and the second transistor T3C (Vgs = VGL2 - VGL, Vgs < 0) is applied to the second transistor T3C and the second transistor T3C is turned off. The present invention reduces the low level voltage of the first control clock CLK (N-1) 'to VGL2 and applies a negative bias to the second transistor T3C by the positive bias period PB, The threshold voltage shift of the second transistor T3C is prevented by balancing the positive bias and the negative bias of the second transistor T3C. During the vertical blank period VG, vgs = 0 because Vgs = VGL2 - VGL2 of T3C.

Referring to Fig. 8C, the low potential voltage applied to the VSS2 terminal is generated at VGL1 = -5V during the vertical active period (AT) and lowered to VGL2 = -15V during the vertical blank period (VB).

During the VGH period of the VNEXT signal, a positive bias (Vgs = VGH-VGL1, Vgs> 0) is applied to the sixth transistor T3N to turn on the sixth transistor T3N. Every time the sixth transistor T3N is turned on. The Q node is discharged and the voltage of the Q node becomes VGL1.

In order to apply a negative bias to the sixth transistor T3N, the Q node is discharged to VGL2 during the vertical blank period VB through the fifth transistor T3R. During the vertical blank period VB, since the VNEXT signal applied to the gate of the sixth transistor T3N is VGL1 and the Q node connected to the source of the sixth transistor T3N is VGL2, The transistor T3N is turned on. The voltage of the VSS2 terminal should be VGL2 so that the drain and the source of the sixth transistor T3N are not short-circuited during the vertical blank period VB.

Referring to FIG. 8D, the VBLK signal is generated as VGL2 to apply a negative bias to the fifth transistor T3R during the vertical active period (AT) every frame period. And the VBLK signal is generated at the VGH voltage during the vertical blank period VB. The fifth transistor T3R is turned on by the positive bias (Vgs = VGH-VGL2, Vgs > 0) during the vertical blank period VB. When the fifth transistor T3R is turned on, the Q node is discharged to VGL2. During the vertical active period AT other than the vertical blank period VB, since the VBLK signal is VGL1, the fifth transistor T3R receives a negative bias (Vgs = VGL2-VGL1, Vgs <0). During this vertical active period AT, the source of the fifth transistor T3R is the second electrode to which VGL1 is applied through the VSS2 terminal.

8E, the first transistor T6 receives a positive bias voltage (Vgs = VQ (N) - VGL1, Vgs> 0) during two horizontal periods (2H) in which the Q node is precharged, The first transistor T6 receives a positive bias voltage Vgs = VQ (N) - VGH, Vgs > 0 in two horizontal periods in which the first transistor T6 is bootstrapped by the clock signal CLK (N). Therefore, a positive bias voltage is applied to the first transistor T6 during the PB period of the 4 horizontal periods 4H. 8E, CLK3 is CLK (N).

Since the gate of the first transistor T6 is connected to the node Q and the second transistor T3C is connected to the node Q, it is difficult to apply the negative bias voltage to the first transistor T6 while the GIP circuit is driven. The present invention applies the negative bias voltage (Vgs = VGL2-VGL1, Vgs <0) to the first transistor T6 by discharging the Q node to VGL2 through the fifth transistor T3R during the vertical blank period VB.

Since the first transistor T6 is a pull-up transistor, when the first transistor T6 is turned on, VGH of the first clock CLK (N) is output as the gate pulse Vgout (N). Unlike the second and third clocks CLK (N-1) 'and / CLK (N)', the first clock CLK (N) has a low level voltage VGL1. This is because the voltage of CLK (N) must be higher than VGL2 of the Q node in order to apply the negative bias voltage to the first transistor T6 during the vertical blank period VB. Therefore, the present invention applies a negative bias to the first transistor T6 by the positive bias applied to the first transistor T6 to prevent the threshold voltage shift of the first transistor T6. If the low level voltage of the first clock CLK (N) is the same as the low level voltage of the second and third clocks CLK (N-1) 'and / CLK (N)') The negative bias voltage for recovering the characteristics of the first transistor T6 can not be applied to the first transistor T6.

Referring to FIG. 8F, the third transistor T7C operates similarly to the second transistor T3C. The second electrode of the third transistor T7C becomes the source and the positive bias voltage Vgs = VGH-VGL1, Vgs (Vgs) is applied to the third transistor T7C during the PB period in which the third clock / CLK (N) 'is VGH, > 0) is applied. The source of the third transistor T7C is the second electrode even when the voltage of the third clock / CLK (N) 'is VGL2. Since the voltage of the VSS2 terminal is VGL1 during the vertical active period AT, the negative bias voltages Vgs = VGL2-VGL1 and Vgs <VGL2 are applied to the third transistor T7C when the voltage of the second control clock CLK (N) 'is VGL2, 0).

The voltage of the VSS2 terminal must be VGL1 in order to apply a negative bias voltage to the third transistor T7C during a period (AT) other than the vertical blank period VB. FIG. 8F shows an example (Vgs = 0) in which no bias voltage is applied to the third transistor T7C during the vertical blank period VB. As another example, the present invention may apply a negative bias voltage to the third transistor T7C by applying VGL1 instead of VGL2 to the VSS2 terminal during the vertical blank period (VG).

As shown in FIG. 8G, the seventh transistor T7D does not have a bias voltage biased by any one polarity since Vgs = 0 during one frame period.

The output terminal of the Nth stage S (N) becomes a floating state and the voltage of the gate line becomes unstable because the third transistor T7C is in the turn-off state during the vertical blank period VB. In order to solve such a problem, the first embodiment of the present invention adds an eighth transistor T7B to the GIP circuit and increases the voltage of the blank signal VBLK to VGH during the vertical blank period VB as shown in Fig. 8H The voltage of the gate line 14 is lowered to VGL1 by turning on the eighth transistor T7B. During the PB period in which the gate pulse Vgou (N) is output, VGL2 of the blank signal is applied to the gate of the eighth transistor T7B, and VGL1 is applied to the VSS1 terminal. Thus, during the vertical active period AT, the eighth transistor T7B receives a negative bias voltage (Vgs = VGL2-VGL1, Vgs <0). During the vertical blank period VB, the gate voltage of the eighth transistor T7B is VGH and the source voltage of the eighth transistor T7B is VGL1. Therefore, the eighth transistor T7B receives the positive bias voltage (Vgs = VGH = VGL1, Vgs> 0) during the vertical blank period VB. The eighth transistor T7B may be omitted depending on the driving characteristics and the model of the display device, as shown in FIGS.

It should be noted that the GIP circuit of the present invention can be variously modified as shown in Figs. 9 to 13, and thus is not limited to Fig. 5 and Fig. 9 to 13, the detailed description of the substantially same constitution as that of the above embodiment will be omitted.

9 is a diagram showing a GIP circuit according to the second embodiment of the present invention and input / output signals thereof.

Referring to FIG. 9, the N-th stage S (N) of the GIP circuit according to the second embodiment of the present invention includes a first NAND stage S (N) A first transistor T6 for charging the output terminal with a high level voltage VGH of one clock CLK (N) and a second transistor T6 for discharging the Q node in response to the second clock CLK (N-1) A transistor T3C, and a third transistor T7C for discharging the output terminal in response to the third clock / CLK (N) '. The third transistor T7C includes a gate connected to the third CLK terminal, a first electrode connected to the output terminal, and a second electrode connected to the VSS terminal.

The low level voltage VGL2 of the second and third clocks CLK (N-1) 'and / CLK (N)' is lower than the low level voltage VGL1 of the first clock CLK (N). The high level voltage VGH of each of the second and third clocks CLK (N-1) 'and / CLK (N)' is equal to the high level voltage VGH of the first clock CLK (N).

The N-th stage S (N) includes a VST terminal to which a start signal VST for precharging the Q node is applied, a low potential power supply voltage VGL1 generated in VGL1 during the vertical active period AT and the vertical blank period VB, A VNEXT terminal to which the output signal Vgout (N + 2) of the next stage S (N + 2) is applied, a vertical blank period VB generated at VGL1 during the vertical active period AT, A fourth transistor T1 for precharging a Q node to VGH in response to a start signal, a Q-node VGL1 responsive to a reset signal VRST in response to a reset signal VRST, A sixth transistor T3N for discharging the Q node to VGL1 in response to the output signal Vgout (N + 2) of the next stage, and a fifth transistor T3R for discharging the first clock CLK (N) A second electrode connected to the output terminal, and a seventh transistor T 7D.

The gate and the first electrode of the fourth transistor T1 are connected to the VST terminal. A Q node is connected to the second electrode of the fourth transistor T1. The fifth transistor T3R includes a gate coupled to the VRST terminal, a first electrode coupled to the Q node, and a second electrode coupled to the Vss terminal. The sixth transistor T3N includes a gate connected to the VNEXT terminal, a first electrode connected to the Q node, and a second electrode connected to the VSS terminal.

The second embodiment of the present invention alternately applies the positive bias voltage and the negative bias voltage to the transistors T3C and T7C only in the transistors T3C and T7C which are most vulnerable to gate bias stress in the GIP circuit. In contrast to the first embodiment described above, the GIP circuit of the second embodiment does not require the VDD terminal, the VSS2 terminal, the transistor T7B, and the like. VGL1 is applied to the VSS terminal. And a reset signal VRST is applied to the VRST terminal. The reset signal VRST is generated with the VGH voltage of the same pulse width as the clock during the initial two horizontal periods 2H of the vertical blank period VB.

10 is a diagram showing a GIP circuit according to the third embodiment of the present invention and input / output signals thereof.

Referring to FIG. 10, in the GIP circuit according to the third embodiment of the present invention, the N-th stage S (N) A first transistor T6 for charging the output terminal with VGH of one clock CLK (N), a second transistor T3C for discharging the Q node in response to the second clock CLK (N-1) ', And a third transistor T7C for discharging the output terminal in response to the third clock / CLK (N). The low level voltage VGL2 of the second clock CLK (N-1) 'is lower than the low level voltage VGL1 of the first and third clocks CLK (N) and / CLK (N)'.

The N-th stage S (N) is connected to a VST terminal to which a start signal for precharging the Q node is applied, a low potential power supply voltage generated in VGL1 during a vertical active period (AT) and a vertical blank period VB A VSS terminal to which a VSS terminal is applied, a VNEXT terminal to which the output signal Vgout (N + 2) of the next stage S (N + 2) is applied, a VGH terminal that is generated at VGL1 during a vertical active period AT, A fourth transistor T1 for precharging the Q node to VGH in response to the start signal VST and a fourth transistor T1 for precharging the Q node to VGL1 in response to the reset signal VRST in response to the start signal VST. A sixth transistor T3R for discharging the Q node to VGL1 in response to the output signal Vgout (N + 2) of the next stage, and a sixth transistor T3N for discharging the first node CLK (N) A second electrode connected to the output terminal, and a seventh transistor T7 D).

The third embodiment of the present invention alternately applies the positive bias voltage and the negative bias voltage to the transistor T3C only in the transistor T3C which is vulnerable to gate bias stress in the GIP circuit. In contrast to the first embodiment described above, the GIP circuit of the third embodiment does not require the VDD terminal, the VSS2 terminal, and the transistor T7B. VGL1 is applied to the VSS terminal. The reset signal VRST is applied to the VRST terminal at the beginning of the vertical blank period VB.

In the third embodiment, the shift clock applied to the gate of the third transistor T7C is different from that of the first embodiment. In the third embodiment, an output clock (/ CLK (N)) having a higher low-level voltage than the control clock (/ CLK (N) ') is applied to the gate of the third transistor T7C. / CLK (N) is an inverse phase clock signal to CLK (N) and swings with the same swing width. When CLK (N) is CLK3, / CLK (N) is CLK1, which is phase earlier than CLK3 by two horizontal periods (2H). The high level voltage of / CLK (N) and CLK (N) is VGH and the low level voltage is VGL1.

T1, T3R, T3N, T3C, T6 and T7D in the third embodiment are substantially the same as those in the second embodiment.

11 is a view showing a GIP circuit according to a fourth embodiment of the present invention and input / output signals thereof.

Referring to FIG. 11, the N-th stage S (N) of the GIP circuit according to the fourth embodiment of the present invention is configured such that when the first clock CLK (N) A first transistor T6 for charging the output terminal with the VGH of the clock CLK (N), a second transistor T3C for discharging the Q node in response to the second clock CLK (N-1) And a third transistor T7C for discharging the output terminal in response to the third clock / CLK (N) '. The low level voltage VGL2 of the third clock / CLK (N) Is lower than the low level voltage VGL1 of the second clocks CLK (N) and CLK (N-1).

The N-th stage S (N) includes a VST terminal to which a start signal VST for precharging the Q node is applied, a low potential power supply voltage VGL1 generated in VGL1 during the vertical active period AT and the vertical blank period VB, A VNEXT terminal to which the output signal Vgout (N + 2) of the next stage S (N + 2) is applied, an initial stage of the vertical blank period VB generated at VGL1 during the vertical active period AT, A fourth transistor T1 for precharging the Q node to VGH in response to the start signal VST and a fourth transistor T1 responsive to the reset signal VRST in response to the start signal VST. A fifth transistor T3R for discharging up to VGL1 and a sixth transistor T3N for discharging the Q node to VGL1 in response to the output signal Vgout (N + 2) of the next stage, ), A second electrode connected to the output terminal, and a seventh transistor For (T7D) further includes.

The fourth embodiment of the present invention alternately applies the positive bias voltage and the negative bias voltage to the transistor T7C only in the transistor T7C which is vulnerable to gate bias stress in the GIP circuit. In contrast to the first embodiment described above, the GIP circuit of the third embodiment does not require the VDD terminal, the VSS2 terminal, and the transistor T7B.

The shift clock applied to the gate of the second transistor T3C in the fourth embodiment is different from that in the first embodiment. In the fourth embodiment, the output clock (/ CLK (N-1)) having a higher low level than the control clock (/ CLK (N-1) ') is applied to the gate of the second transistor T3C.

T1, T3R, T3N, T6, T7C and T7D in the fourth embodiment are substantially the same as those in the second embodiment.

12 shows a GIP circuit according to the fifth embodiment of the present invention and input / output signals thereof.

Referring to FIG. 12, the N-th stage S (N) of the GIP circuit according to the fifth embodiment of the present invention includes a first node CL1 (N) A first transistor T6 for charging the first output terminal with VGH of the clock CLK (N), a second transistor T3C for discharging the Q node in response to the second clock CLK (N-1) ', And a third transistor T7C for discharging the first output terminal in response to the third clock CLK (N) '. The second and third clocks CLK (N-1)', / CLK N) 'of the first clock CLK (N) is lower than the low level voltage VGL1 of the first clock CLK (N).

The Nth stage S (N) includes a VST terminal to which a start signal for precharging the Q node is applied, a first low potential power supply voltage generated in VGL1 during the vertical active period (AT) and the vertical blank period (VB) A VSS2 terminal to which a second low potential power supply voltage generated in VGL2 during a vertical active period (AT) and a vertical blank period (VB) is applied, and an output signal Vgout (V) of a next stage S (N + A VRST terminal to which a reset signal VRST generated at VGH at the beginning of the vertical blank period VB is applied is applied to the VLST terminal generated at VGL1 during the vertical active period AT, A fifth transistor T3R for discharging the Q node to VGL2 in response to the reset signal VRST and a fourth transistor T3R for precharging the Q node to VGH in response to the output signal Vgout N + 2)) to discharge the Q node to VGL2 A seventh transistor T7D having a gate, a first electrode to which the first clock CLK (N) is applied, a second electrode connected to the output terminal, and a gate; And an eighth transistor T6_C for charging the second output terminal with the VGH of the first clock CLK (N) when the first clock CLK (N) And a ninth transistor (T7C_C) for discharging the second output terminal.

A fifth embodiment of the present invention separates the gate pulse Vgout (N) and the carry signal Carry (N). The Nth stage S (N) outputs the gate pulse Vgout (N) through the first output terminal and the carry signal Carry (N) through the second output terminal.

The first transistor T6 includes a gate coupled to the Q node, a first electrode coupled to the output CLK terminal, and a second electrode coupled to the first output terminal. The third transistor T7C includes a gate connected to the third CLK terminal, a first electrode connected to the first output terminal, and a second electrode connected to the VSS1 terminal.

The gate and the first electrode of the fourth transistor T1 are connected to the VST terminal. A Q node is connected to the second electrode of the fourth transistor T1. The fifth transistor T3R includes a gate connected to the VRST terminal, a first electrode connected to the Q node, and a second electrode connected to the VSS2 terminal.

The eighth transistor T6_C includes a gate coupled to the Q node, a first electrode coupled to the first CLK terminal, and a second electrode coupled to the second output terminal. The ninth transistor T7C_C includes a gate connected to the third CLK terminal, a first electrode connected to the second output terminal, and a second electrode connected to the VSS2 terminal.

T3N, T3C, and T7D are substantially the same as those in the first embodiment, and therefore, detailed description thereof will be omitted.

13 shows a GIP circuit according to the sixth embodiment of the present invention and input / output signals thereof.

Referring to FIG. 13, the N-th stage S (N) of the GIP circuit according to the sixth embodiment of the present invention includes a first NAND circuit S (N) A first transistor T6 for charging the output terminal with VGH of one clock CLK (N), a second transistor T3C for discharging the Q node in response to the second clock CLK (N-1) ', And a third transistor T7C for discharging the output terminal in response to the third clock CLK (N) '.

The N-th stage S (N) includes a VST terminal to which a start signal VST for precharging the Q node is applied, a VGH generated during the vertical active period AT and a VGL2 generated during the vertical blank period VB A VDD terminal to which a high potential power supply voltage is applied, a VSS terminal which is generated at VGL1 during a vertical active period AT and is applied with a low potential power supply voltage generated at VGL2 during a vertical blank period VB, VBLK to which a blank signal VBLK generated at VGL2 during a vertical active period (AT) and applied at VGH during a vertical blank period (VB) is applied, a VNKT terminal to which the output signal Vgout (N + 2) A fourth transistor T1 for precharging the Q node to VGH in response to the start signal VST, a fifth transistor T3R for discharging the Q node to VGL2 in response to the blank signal VBLK, In response to the output signal Vgout (N + 2) A sixth transistor T3N for discharging up to GL1 and a seventh transistor T7D having a first electrode to which the first clock CLK (N) is applied, a second electrode connected to the output terminal, and a gate.

The sixth embodiment of the present invention generates the VSS voltage in alternating current and controls the first and third transistors T6 and T7C to be off during the vertical blank period VB. Since the first and third transistors T6 and T7C are off during the vertical blank period VB, the output terminal is floating. The voltage of the output terminal is maintained at VGL before the vertical blank period VB so that it can maintain the VGL during the vertical blank period VB.

Since the seventh transistor T7D operates as a diode, the voltage of the output terminal does not operate while maintaining the voltage VGL. The seventh transistor T7D is turned on when the voltage of the output terminal is higher than the voltage VGL, and VGL is applied to the output terminal through the seventh transistor T7D.

The third transistor T7C includes a gate connected to the second control CLK terminal, a first electrode connected to the output terminal, and a second electrode connected to the VSS terminal. The fifth transistor T3R includes a gate coupled to the VRST terminal, a first electrode coupled to the Q node, and a second electrode coupled to the Vss terminal. The sixth transistor T3N includes a gate connected to the VNEXT terminal, a first electrode connected to the Q node, and a second electrode connected to the VSS terminal.

The sixth embodiment can eliminate the VSS1 terminal and the wiring connected thereto in comparison with the first embodiment. T1, T3C, T6, and T7D are substantially the same as those in the second embodiment, and thus a detailed description thereof will be omitted.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

12: Data line 14: Gate line
16, SIC: data driving circuit 18, GIP: gate driving circuit (GIP circuit)
20, TCON: Timing controller PNL: Display panel
LS: Level shifter
T1, T3R, T3N, T3C, T6, T7B, T7C, T7D, T6_C,

Claims (20)

A first transistor for charging an output terminal with a high level voltage of a first clock in a state where a Q node is charged;
A second transistor for discharging the Q node in response to a second clock; And
And a third transistor for discharging the output terminal in response to a third clock,
The low level voltage of at least any one of the second and third clocks is lower than the low level voltage of the first clock,
And a high level voltage of each of the second and third clocks is equal to a high level voltage of the first clock. The method according to claim 1,
The phase of the second clock is faster than the first clock, slower than the third clock,
The third clock is generated as a reverse phase clock with respect to the first clock,
The first clock swings between a high level voltage and a first low level voltage and each of the second and third clocks swings between the high level voltage and the second low level voltage,
And the second low level voltage is lower than the first low level voltage. 3. The method of claim 2,
A VST terminal to which a start signal for precharging the Q node is applied;
A VDD terminal which is generated by the high level voltage during a vertical active period and is applied with a high potential power supply voltage generated by the second low level voltage during a vertical blank period;
A VSS1 terminal to which a first low potential power supply voltage generated at the first low level voltage during the vertical active period and the vertical blank period is applied;
A VSS2 terminal generated by the first low level voltage during the vertical active period and being supplied with a second low potential power supply voltage generated by the second low level voltage during the vertical blank period;
A VNEXT terminal to which the output signal of the next stage is applied;
A VBLK terminal which is generated by the first low level voltage during the vertical active period and to which a blank signal generated by the high level voltage during the vertical blank period is applied;
A fourth transistor for precharging the Q node to the high level voltage in response to the start signal;
A fifth transistor for discharging the Q node to the second low level voltage in response to the blank signal;
A sixth transistor for discharging the Q node to the second low level voltage in response to an output signal of the next stage;
A seventh transistor having a first electrode to which the first clock is applied, a second electrode connected to the output terminal, and a gate; And
And an eighth transistor for discharging the voltage of the output terminal to the first low level voltage in response to the blank signal. 3. The method of claim 2,
A VST terminal to which a start signal for precharging the Q node is applied;
A VSS terminal to which a low potential power supply voltage generated by the first low level voltage is applied during a vertical active period and a vertical blank period;
A VNEXT terminal to which the output signal of the next stage is applied;
A VRST terminal which is generated by the first low level voltage during the vertical active period and is applied with a reset signal generated at the high level voltage at the beginning of the vertical blank period;
A fourth transistor for precharging the Q node to the high level voltage in response to the start signal;
A fifth transistor for discharging the Q node to the first low level voltage in response to the reset signal;
A sixth transistor for discharging the Q node to the first low level voltage in response to an output signal of the next stage; And
A first electrode to which the first clock is applied, and a seventh transistor having a second electrode connected to the output terminal and a gate. The method according to claim 1,
The low level voltage of the second clock is lower than the low level voltage of each of the first and third clocks,
The phase of the second clock is faster than the first clock, slower than the third clock,
The third clock is generated as a reverse phase clock with respect to the first clock,
The first and third clocks swing between a high level voltage and a first low level voltage and the second clock swings between the high level voltage and the second low level voltage,
And the second low level voltage is lower than the first low level voltage. 6. The method of claim 5,
A VST terminal to which a start signal for precharging the Q node is applied;
A VSS terminal to which a low potential power supply voltage generated by the first low level voltage is applied during a vertical active period and a vertical blank period;
A VNEXT terminal to which the output signal of the next stage is applied;
A VRST terminal that is generated by the first low level voltage during the vertical active period and is applied with a reset signal generated at the high level voltage at the beginning of the vertical blank period;
A fourth transistor for precharging the Q node to the high level voltage in response to the start signal;
A fifth transistor for discharging the Q node to the first low level voltage in response to the reset signal;
A sixth transistor for discharging the Q node to the first low level voltage in response to an output signal of the next stage; And
A first electrode to which the first clock is applied, and a seventh transistor having a second electrode connected to the output terminal and a gate. The method according to claim 1,
The low-level voltage of the third clock is lower than the low-level voltage of each of the first and second clocks,
The phase of the second clock is faster than the first clock, slower than the third clock,
The third clock is generated as a reverse phase clock with respect to the first clock,
The first and second clocks swing between a high level voltage and a first low level voltage and the third clock swings between the high level voltage and the second low level voltage,
And the second low level voltage is lower than the first low level voltage. 8. The method of claim 7,
A VST terminal to which a start signal for precharging the Q node is applied;
A VSS terminal to which a low potential power supply voltage generated by the first low level voltage is applied during a vertical active period and a vertical blank period;
A VNEXT terminal to which the output signal of the next stage is applied;
A VRST terminal that is generated by the first low level voltage during the vertical active period and is applied with a reset signal generated at the high level voltage at the beginning of the vertical blank period;
A fourth transistor for precharging the Q node to the high level voltage in response to the start signal;
A fifth transistor for discharging the Q node to the first low level voltage in response to the reset signal;
A sixth transistor for discharging the Q node to the first low level voltage in response to an output signal of the next stage; And
A first electrode to which the first clock is applied, and a seventh transistor having a second electrode connected to the output terminal and a gate. 3. The method of claim 2,
A VST terminal to which a start signal for precharging the Q node is applied;
A VSS1 terminal to which a first low potential power supply voltage generated by the first low level voltage is applied during a vertical active period and a vertical blank period;
A VSS2 terminal to which a second low potential power supply voltage generated by the second low level voltage during the vertical active period and the vertical blank period is applied;
A VNEXT terminal to which the output signal of the next stage is applied;
A VRST terminal that is generated by the first low level voltage during the vertical active period and is applied with a reset signal generated at the high level voltage at the beginning of the vertical blank period;
A fourth transistor for precharging the Q node to the high level voltage in response to the start signal;
A fifth transistor for discharging the Q node to the second low level voltage in response to the reset signal;
A sixth transistor for discharging the Q node to the second low level voltage in response to an output signal of the next stage;
A seventh transistor having a first electrode to which the first clock is applied, a second electrode connected to the output terminal, and a gate;
An eighth transistor for charging the second output terminal with a high level voltage of the first clock when the first clock is inputted in a state where the Q node is charged; And
And a ninth transistor for discharging the second output terminal in response to the third clock. 3. The method of claim 2,
A VST terminal to which a start signal for precharging the Q node is applied;
A VDD terminal which is generated by the high level voltage during a vertical active period and is applied with a high potential power supply voltage generated by the second low level voltage during a vertical blank period;
A VSS terminal which is generated by the first low level voltage during the vertical active period and is applied with a low potential power supply voltage generated by the second low level voltage during the vertical blank period;
A VNEXT terminal to which the output signal of the next stage is applied;
A VBLK terminal which is generated by the second low level voltage during the vertical active period and to which a blank signal generated by the high level voltage during the vertical blank period is applied;
A fourth transistor for precharging the Q node to the high level voltage in response to the start signal;
A fifth transistor for discharging the Q node to the second low level voltage in response to the blank signal;
A sixth transistor for discharging the Q node to the first low level voltage in response to an output signal of the next stage; And
A first electrode to which the first clock is applied, and a seventh transistor having a second electrode connected to the output terminal and a gate. A display panel including a data line and a gate line; And
And a gate driving circuit for supplying a gate pulse to the gate line through an output terminal,
The gate drive circuit includes:
A first transistor for charging the output terminal with a high level voltage of a first clock in a state where a Q node is charged;
A second transistor for discharging the Q node in response to a second clock; And
And a third transistor for discharging the output terminal in response to a third clock,
The low level voltage of at least any one of the second and third clocks is lower than the low level voltage of the first clock,
And a high level voltage of each of the second and third clocks is a high level voltage of the first clock. 12. The method of claim 11,
The phase of the second clock is faster than the first clock, slower than the third clock,
The third clock is generated as a reverse phase clock with respect to the first clock,
The first clock swings between a high level voltage and a first low level voltage and each of the second and third clocks swings between the high level voltage and the second low level voltage,
And the second low level voltage is lower than the first low level voltage. 13. The method of claim 12,
The gate drive circuit includes:
A VST terminal to which a start signal for precharging the Q node is applied;
A VDD terminal which is generated by the high level voltage during a vertical active period and is applied with a high potential power supply voltage generated by the second low level voltage during a vertical blank period;
A VSS1 terminal to which a first low potential power supply voltage generated at the first low level voltage during the vertical active period and the vertical blank period is applied;
A VSS2 terminal generated by the first low level voltage during the vertical active period and being supplied with a second low potential power supply voltage generated by the second low level voltage during the vertical blank period;
A VNEXT terminal to which the output signal of the next stage is applied;
A VBLK terminal which is generated by the first low level voltage during the vertical active period and to which a blank signal generated by the high level voltage during the vertical blank period is applied;
A fourth transistor for precharging the Q node to the high level voltage in response to the start signal;
A fifth transistor for discharging the Q node to the second low level voltage in response to the blank signal;
A sixth transistor for discharging the Q node to the second low level voltage in response to an output signal of the next stage;
A seventh transistor having a first electrode to which the first clock is applied, a second electrode connected to the output terminal, and a gate; And
And an eighth transistor for discharging the voltage of the output terminal to the first low level voltage in response to the blank signal. 13. The method of claim 12,
The gate drive circuit includes:
A VST terminal to which a start signal for precharging the Q node is applied;
A VSS terminal to which a low potential power supply voltage generated by the first low level voltage is applied during a vertical active period and a vertical blank period;
A VNEXT terminal to which the output signal of the next stage is applied;
A VRST terminal that is generated by the first low level voltage during the vertical active period and is applied with a reset signal generated at the high level voltage at the beginning of the vertical blank period;
A fourth transistor for precharging the Q node to the high level voltage in response to the start signal;
A fifth transistor for discharging the Q node to the first low level voltage in response to the reset signal;
A sixth transistor for discharging the Q node to the first low level voltage in response to an output signal of the next stage; And
A first electrode to which the first clock is applied, and a seventh transistor having a second electrode connected to the output terminal and a gate. 12. The method of claim 11,
The low level voltage of the second clock is lower than the low level voltage of each of the first and third clocks,
The phase of the second clock is faster than the first clock, slower than the third clock,
The third clock is generated as a reverse phase clock with respect to the first clock,
The first and third clocks swing between a high level voltage and a first low level voltage and the second clock swings between the high level voltage and the second low level voltage,
And the second low level voltage is lower than the first low level voltage. 16. The method of claim 15,
The gate drive circuit includes:
A VST terminal to which a start signal for precharging the Q node is applied;
A VSS terminal to which a low potential power supply voltage generated by the first low level voltage is applied during a vertical active period and a vertical blank period;
A VNEXT terminal to which the output signal of the next stage is applied;
A VRST terminal that is generated by the first low level voltage during the vertical active period and is applied with a reset signal generated at the high level voltage at the beginning of the vertical blank period;
A fourth transistor for precharging the Q node to the high level voltage in response to the start signal;
A fifth transistor for discharging the Q node to the first low level voltage in response to the reset signal;
A sixth transistor for discharging the Q node to the first low level voltage in response to an output signal of the next stage; And
A first electrode to which the first clock is applied, and a seventh transistor having a second electrode connected to the output terminal and a gate. 12. The method of claim 11,
The low-level voltage of the third clock is lower than the low-level voltage of each of the first and second clocks,
The phase of the second clock is faster than the first clock, slower than the third clock,
The third clock is generated as a reverse phase clock with respect to the first clock,
The first and second clocks swing between a high level voltage and a first low level voltage and the third clock swings between the high level voltage and the second low level voltage,
And the second low level voltage is lower than the first low level voltage. 18. The method of claim 17,
The gate drive circuit includes:
A VST terminal to which a start signal for precharging the Q node is applied;
A VSS terminal to which a low potential power supply voltage generated by the first low level voltage is applied during a vertical active period and a vertical blank period;
A VNEXT terminal to which the output signal of the next stage is applied;
A VRST terminal that is generated by the first low level voltage during the vertical active period and is applied with a reset signal generated at the high level voltage at the beginning of the vertical blank period;
A fourth transistor for precharging the Q node to the high level voltage in response to the start signal;
A fifth transistor for discharging the Q node to the first low level voltage in response to the reset signal;
A sixth transistor for discharging the Q node to the first low level voltage in response to an output signal of the next stage; And
A first electrode to which the first clock is applied, and a seventh transistor having a second electrode connected to the output terminal and a gate. 13. The method of claim 12,
The gate drive circuit includes:
A VST terminal to which a start signal for precharging the Q node is applied;
A VSS1 terminal to which a first low potential power supply voltage generated by the first low level voltage is applied during a vertical active period and a vertical blank period;
A VSS2 terminal to which a second low potential power supply voltage generated by the second low level voltage during the vertical active period and the vertical blank period is applied;
A VNEXT terminal to which the output signal of the next stage is applied;
A VRST terminal that is generated by the first low level voltage during the vertical active period and is applied with a reset signal generated at the high level voltage at the beginning of the vertical blank period;
A fourth transistor for precharging the Q node to the high level voltage in response to the start signal;
A fifth transistor for discharging the Q node to the second low level voltage in response to the reset signal;
A sixth transistor for discharging the Q node to the second low level voltage in response to an output signal of the next stage;
A seventh transistor having a first electrode to which the first clock is applied, a second electrode connected to the output terminal, and a gate;
An eighth transistor for charging the second output terminal with a high level voltage of the first clock when the first clock is inputted in a state where the Q node is charged; And
And a ninth transistor for discharging the second output terminal in response to the third clock. 13. The method of claim 12,
The gate drive circuit includes:
A VST terminal to which a start signal for precharging the Q node is applied;
A VDD terminal which is generated by the high level voltage during a vertical active period and is applied with a high potential power supply voltage generated by the second low level voltage during a vertical blank period;
A VSS terminal which is generated by the first low level voltage during the vertical active period and is applied with a low potential power supply voltage generated by the second low level voltage during the vertical blank period;
A VNEXT terminal to which the output signal of the next stage is applied;
A VBLK terminal which is generated by the second low level voltage during the vertical active period and to which a blank signal generated by the high level voltage during the vertical blank period is applied;
A fourth transistor for precharging the Q node to the high level voltage in response to the start signal;
A fifth transistor for discharging the Q node to the second low level voltage in response to the blank signal;
A sixth transistor for discharging the Q node to the first low level voltage in response to an output signal of the next stage; And
A first electrode to which the first clock is applied, and a seventh transistor having a second electrode connected to the output terminal and a gate.

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