KR102555058B1 - Gate driving circuit and display device using the same - Google Patents

Abstract

The present invention relates to a display device, and relates to a gate driving circuit and a display device using the same, wherein the gate driving circuit includes a first transistor for charging an output terminal with a high level voltage of a first clock while a Q node is charged. , a second transistor discharging the Q node in response to a second clock, and a third transistor discharging the output terminal in response to a third clock. A low level voltage of at least one of the second and third clocks is lower than that of the first clock.

Description

Gate driving circuit and display device using the same {GATE DRIVING CIRCUIT AND DISPLAY DEVICE USING THE SAME}

The present invention relates to a gate driving circuit capable of increasing reliability and a display device using the gate driving circuit.

A display device includes a data driving circuit that supplies data signals to data lines of a pixel array, and a gate that sequentially supplies gate pulses (or scan pulses) synchronized with the data signals to gate lines (or scan lines) of the pixel array. It includes a driving circuit (or scan driving circuit), a timing controller controlling the data driving circuit and the gate driving circuit.

Each of the pixels may include a thin film transistor (TFT) for supplying a voltage of a data line to a pixel electrode in response to a gate pulse. The gate pulse swings between the Gate High Voltage (VGH) and the Gate Low Voltage (VGL). The gate high voltage (VGH) is set to a voltage higher than the threshold voltage of the pixel TFT, and the gate low voltage (VGH) is set to a voltage lower than the threshold voltage of the pixel TFT.

Recently, a technique of embedding a gate driving circuit together with a pixel array in a display panel has been applied. Hereinafter, the gate driving circuit embedded in the display panel will be referred to as a “Gate In Panel (GIP) circuit”. The GIP circuit includes a shift register. A shift register includes a number of cascadingly connected stages. The stages generate an output in response to a start pulse and shift that output according to the shift clock.

Each of the stages of the shift register includes a Q node for charging the gate line, a QB node for discharging the gate line, and a switch circuit connected to the Q node and the QB node. The switch circuit charges the Q node in response to the start pulse or output of the previous stage, and discharges the Q node in response to the output of the next stage or reset pulse.

The switch circuit includes transistors having a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structure. Device characteristics of these transistors are deteriorated due to DC gate bias stress. DC gate bias stress increases as the DC voltage applied to the gate of the transistor increases and the application time increases. In FIG. 1 , the threshold voltage of the transistors is shifted by DC gate bias stress, so that the on current is reduced. In particular, the threshold voltage shift due to DC gate bias stress at high temperature is greater than at room temperature, thereby adversely affecting product reliability in a high temperature environment. Here, since the use temperature of the high-temperature environment is different depending on the application field of the product, the temperature of the high-temperature environment may be differently defined according to the application field.

1 is a diagram illustrating an example in which a threshold voltage of a transistor is positively shifted due to DC gate bias stress of the transistor. In Figure 1, Vgs (V) is the gate-to-source voltage of the MOSFET. Ids(A) is the drain-to-source current of the MOSFET.

Transistors switching the discharge path of the Q node in the GIP circuit receive a lot of DC gate bias stress. If the transistors of the GIP circuit are implemented as NMOS transistors, a positive bias voltage is repeatedly applied to the gate-source of the transistors, so that the threshold voltage of the transistors shifts in a + direction as the driving time increases. Due to this, the low level voltage of the Q node and the low level voltage of the gate lines become unstable, so that one or more abnormal output voltages from the GIP circuit may be applied to the gate lines. As a result, the output signal characteristic of the GIP circuit is unstable and the reliability of the GIP circuit is lowered. Due to the abnormal output voltage of the GIP circuit, leakage current flows through the TFTs of the pixel array and the voltage of the pixels may be discharged.

The present invention provides a gate driving circuit capable of improving output signal characteristics and reliability of a GIP circuit and a display device using the same.

The gate driving circuit of the present invention includes a first transistor charging the output terminal with a high level voltage of a first clock while the Q node is charged, a second transistor discharging the Q node in response to a second clock, and a second transistor. 3 includes a third transistor for discharging the output terminal in response to a clock. A low level voltage of at least one of the second and third clocks is lower than that of the first clock. A high level voltage of each of the second and third clocks is equal to a high level voltage of the first clock.

A phase of the second clock is faster than that of the first clock and slower than that of the third clock. The third clock is generated as an anti-phase clock with respect to the first clock. The first clock swings between a high level voltage and a first low level voltage, and each of the second and third clocks swings between the high level voltage and a second low level voltage. The second low level voltage is lower than the first low level voltage.

According to the present invention, reliability of a GIP circuit can be improved by compensating DC gate bias stress of a transistor by applying a bias voltage of opposite polarity. Therefore, the present invention can secure the operating margin of the GIP circuit and stably drive the GIP circuit during long-time driving or in a high-temperature environment.

The present invention can improve output signal characteristics of the GIP circuit, such as improving the polling time of a clock. In addition, since the present invention secures the reliability of the GIP driving circuit and can be widely applied to a display panel manufactured based on a transistor including amorphous silicon (a-Si) or a transistor including an oxide semiconductor, application models can be expanded.

1 is a diagram showing an example in which the threshold voltage of a transistor is positively shifted due to DC gate bias stress of the transistor.
2 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention.
3 is a diagram showing one frame period of a display device.
4 is a block diagram showing the GIP circuit of the present invention.
5 is a circuit diagram showing in detail the GIP circuit according to the first embodiment of the present invention.
6 and 7 are waveform diagrams showing input/output signals showing the operation of the GIP circuit shown in FIG. 5 and waveforms of Q nodes.
8A to 8H show the gate-source voltage of each transistor in the GIP circuit operating as shown in FIGS. 5 to 7 .
9 is a diagram showing a GIP circuit and its input/output signals according to a second embodiment of the present invention.
10 is a diagram showing a GIP circuit and its input/output signals according to a third embodiment of the present invention.
11 is a diagram showing a GIP circuit and its input/output signals according to a fourth embodiment of the present invention.
12 is a diagram showing a GIP circuit and its input/output signals according to a fifth embodiment of the present invention.
13 is a diagram showing a GIP circuit and its input/output signals according to a sixth embodiment of the present invention.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numbers throughout the specification indicate substantially the same elements. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

The display device of the present invention may be implemented as a flat panel display device such as a Liquid Crystal Display (LCD) or an Organic Light Emitting Display (OLED Display). In the following embodiments, a liquid crystal display will be mainly described as an example of a flat panel display, but the present invention is not limited thereto. For example, the display device of the present invention may be any display device requiring a gate driving circuit.

Switch elements in the gate driving circuit of the present invention may be implemented as n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structured transistors. Although n-type transistors are illustrated in the following embodiments, it should be noted that the present invention is not limited thereto. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within a transistor, carriers start flowing from the source. The drain is an electrode through which carriers exit the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since carriers are electrons, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. Since electrons flow from the source to the drain in an n-type MOSFET, the direction of the current flows from the drain to the source. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a MOSFET are not fixed. For example, the source and drain of a MOSFET can be changed depending on the applied voltage. In the following description of the embodiment, the source and drain of the transistor will be referred to as first and second electrodes. It should be noted that the invention is not limited by the source and drain of the transistor in the following description.

The transistors constituting the gate driving circuit of the present invention may be implemented as one or more of a transistor including amorphous silicon (a-Si), a transistor including an oxide semiconductor, and a transistor including low temperature poly silicon (LTPS). .

The gate driving circuit of the present invention includes a first transistor charging the output terminal with the voltage of the first clock when the first clock is input while the Q node is charged, and a second transistor discharging the Q node in response to the second clock. and a third transistor for discharging an output terminal in response to a transistor and a third clock. A low level voltage of at least one of the second and third clocks is lower than the low level voltage of the first clock. The high level voltage of each of the second and third clocks is equal to the high level voltage of the first clock. The first clock is CLK(N) in the embodiment, the second clock is CLK(N-1) or CLK(N-1)' in the embodiment, and the third clock is /CLK(N) or / in the embodiment. CLK(N)', respectively. The first transistor is described as T6 or T6_C in the embodiment, the second transistor as T3C in the embodiment, and the third transistor as T7C in the embodiment.

Referring to FIGS. 2 and 3 , a display device according to an exemplary embodiment of the present invention includes a display panel PNL and a display panel driving circuit for writing input image data into a pixel array of the display panel PNL. furnish a row

The display panel PNL has data lines 12 , gate lines 14 orthogonal to the data lines 12 , and a matrix defined by the data lines 12 and the gate lines 14 . It includes a pixel array in which pixels are disposed. The input image is displayed on a pixel array.

The pixels of the pixel array may include red (R), green (G), and blue (B) sub-pixels for color implementation. The pixels may further include a white (W) sub-pixel in addition to the RGB sub-pixels. The pixels may further include one or more of Cyan (C), Magenta (M), and Yellow (Y) subpixels.

The pixel array of the display panel PNL includes a TFT array and a color filter array. A TFT array may be formed on a lower plate of the display panel PNL. The TFT array includes thin film transistors (TFTs) formed at intersections of the data lines 12 and the gate lines 14, a pixel electrode that charges the data voltage, and a storage capacitor that is connected to the pixel electrode and maintains the data voltage ( Displays the input image including Storage Capacitor, Cst), etc.

The upper plate of the display panel PNL may include a color filter array formed on the upper substrate. The color filter array includes a black matrix, color filters, and the like. In the case of a COT (Color Filter on TFT) or TOC (TFT on Color Filter) model, a color filter and a black matrix may be disposed in a TFT array.

A touch screen using an in-cell touch sensor may be implemented in the display panel PNL. The in-cell time touch sensor is embedded in the pixel array of the display panel PNL. The touch sensors may be disposed on the display panel PNL in an on-cell type or an add-on type. The touch sensor may be implemented as a capacitive type touch sensor, for example, a mutual capacitance sensor or a self capacitance sensor.

The display panel driving circuit includes a data driving unit 16 , gate driving units 18 and 22 , and a timing controller (TCON) 20 to write data of an input image into pixels of the display panel 100 .

The data driver 16 includes one or more source drive ICs (SICs). The data driver 16 converts digital video data of an input image received from the timing controller 20 into a gamma compensation voltage and outputs a data voltage. The data voltage output from the data driver 16 is supplied to the data lines 12 . A multiplexer (not shown) may be disposed between the data driver 16 and the data lines 12 . The multiplexer distributes the data voltage input from the data driver 16 to the data lines 12 under the control of the timing controller 20 . In the case of the 1:2 multiplexer, the multiplexer time-divides the data voltage input through one output channel of the data driver 16 and supplies the time-divided data to two data lines. Therefore, if a 1:2 multiplexer is used, the number of channels of the source drive IC (SIC) can be reduced by half.

The gate drivers 18 and 22 include a GIP circuit 18 directly mounted on a TFT array substrate in the display panel PNL and a level shifter disposed between the timing controller 20 and the GIP circuit 18. LS) (22).

The GIP circuit 18 includes a shift register. The GIP circuit 18 may be formed on one edge or both edges of the display panel PNL outside the pixel array. The level shifter 22 increases the swing width of the gate timing control signal voltage to a gate high voltage (VGH) and a gate low voltage (VGL) and outputs it to the GIP circuit 18.

The GIP circuit 18 shifts the gate pulse according to the shift clock timing and sequentially supplies the gate pulse to the gate lines 14 . The gate pulse swings between a gate high voltage (VGH) and a gate low voltage (VGL). The gate high voltage (VGH) is a voltage higher than the threshold voltage of TFTs disposed in the pixel array. The gate low voltage VGL is a voltage lower than the threshold voltage of TFTs disposed in the pixel array. The TFTs of the pixel array are turned on in response to the gate high voltage (VGH) of the gate pulse to supply data voltages from the data lines 12 to the pixel electrodes.

The shift register of GIP circuit 18 includes stages that are cascade connected to shift the output at clock timing. Each of the stages outputs a gate pulse to the gate lines 14 in response to the voltage of the Q node and transfers a carry signal to another stage. The gate pulse and carry signal can be the same signal or separate. The Q node is charged according to a start pulse or a carry signal from a previous stage to pre-charge the gate of a pull-up transistor. When the shift clock is input in a pre-charged state, the Q node is bootstrapped through parasitic capacitance between the gate and drain of the pull-up transistor. When the voltage of the Q node is increased by bootstrapping, the pull-up transistor is turned on, and the voltage of the output terminal is raised to the gate high voltage (VGH), and the gate pulse is started to be output. A gate pulse is supplied to the gate lines 14 to simultaneously turn on the TFTs of the line to which the data voltage is written.

The timing controller 20 transmits digital video data of an input image received from a host system (not shown) to the data driver 16 . The timing controller 20 inputs timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a main clock (MCLK) received in synchronization with input image data. and outputs a data timing control signal for controlling the operation timing of the data driver 16 and a gate timing control signal for controlling the operation timing of the GIP circuit 18.

The gate timing control signal includes a start pulse (VST), a gate shift clock (CLK), a gate output enable signal (GOE), and the like. The output enable signal (Gate Output Enable, GOE) may be omitted. The start pulse VST is input to the VST terminal of the first stage in the shift register to control the output timing of the first gate pulse that occurs first in one frame period. The shift clock CLK is sequentially generated during the display period to control the output timing of gate pulses in each of the stages, thereby controlling the shift timing of gate pulses.

The host system may be implemented as any one of a television system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system. The host system includes a System on Chip (SoC) with a built-in scaler to convert digital video data of an input image into a format suitable for display on the display panel 100 . The host system transmits timing signals (Vsync, Hsync, DE, MCLK) together with digital video data of the input image to the timing controller 20. The host system executes an application associated with the coordinate information of the touch input received from the touch sensing unit 110 .

3 is a diagram showing one frame period of a display device.

Referring to FIG. 3, the vertical synchronization signal Vsync defines one frame period. The horizontal synchronization signal (Hsync) defines one horizontal period (Horizontal time). The data enable signal DE defines a valid data period. The data enable signal DE is synchronized with valid data to be displayed on the pixel array of the display panel P100. One pulse period of the data enable signal DE corresponds to one horizontal period, and a high logic period of the data enable signal DE indicates one-line data input timing. One horizontal period is a time required to write data to pixels of one line in the display panel 100 .

One frame period is divided into one vertical active period (AT) and one vertical blank period (VB). The data enable signal DE and valid data of the input image are input during the vertical active period AT, and are not input during the vertical blank period VB. The vertical active period (AT) is a time when one frame of data is written to all pixels of a pixel array on which an image is displayed on the display panel 100 .

As can be seen from the data enable signal DE, input data is not received by the display device during the vertical blank period. The vertical blank period VB includes a vertical sync time (VS), a vertical front porch (FP), and a vertical back porch (BP). The vertical sync time (VS) is a time from a falling edge to a rising edge of Vsync, and represents the start (or end) timing of one screen. The vertical front porch (FP) is the time from the falling edge of the last DE pulse indicating the timing of the last line data of 1 frame data to the start of the vertical blank period (VB). The vertical back porch (BP) is the time from the end of the vertical blank period (VB) to the rising edge of the first DE pulse representing the first line data timing of one frame data.

4 is a block diagram showing the GIP circuit 18 of the present invention.

Referring to Fig. 4, the GIP circuit 18 of the present invention includes a shift register. The shift register includes cascadingly connected stages S(N-1) to S(N+1). The stages S(N-1) to S(N+1) start outputting gate pulses in response to the start pulse Vst and shift outputs in response to shift clocks (Output CLK, Control CLK). . Output signals sequentially output from the stages S(N−1) to S(N+1) are supplied to the gate lines 14 as gate pulses. The output of each of the stages S(N−1) to S(N+1) is transferred to the next stage as a carry signal. The carry signal is input to the VST terminal of the next stage. A signal input to the VST terminal (hereinafter referred to as “VST signal”) is a signal for pre-charging the Q node. The carry signal is input to the VNEXT terminal of the previous stage. A signal input to the VNEXT terminal discharges the Q node.

The shift clock of the GIP circuit 18 is divided into an output clock (Output CLK) and a control clock (Control CLK). As shown in FIG. 6 , the output clock Output CLK is clocks CLK1 to CLK4 swinging between a gate high voltage VGH and a first gate low voltage (hereinafter referred to as “VGL1”). As shown in FIG. 6 , the control clock Control CLK is clocks CLK1' to CLK4' swinging between the gate high voltage VGH and the second gate low voltage (hereinafter referred to as "VGL2"). VGL2 is a lower voltage than VGL1. The reason why the VGL potential of the control clock (Control CLK) is lower than the VGL potential of the output clock (Output CLK) is to recover the threshold voltage shift by canceling the stress applied to the transistors of the GIP circuit with the stress of the opposite polarity. In the prior art, only the output clock (Output CLK) is input to the shift register.

Each of the stages S(N−2) to S(N+2) includes input/output terminals such as a VST terminal, a VDD terminal, a VSS terminal, a VNEXT terminal, a VRST terminal, a VBLK terminal, and an output terminal. The VST terminal receives a start pulse (VST) or a carry signal from the previous stage. The start pulse VST is input to the VST terminal of the first stage, and the carry signal Vgout(N-2) from the previous stage is received by the other stages. The output terminal is connected to the gate line 14.

The power supply voltage applied to the VDD terminal is maintained at VGH during the vertical active period (AT) and lowered to VGL2 during the vertical blank period (VB). During the vertical blank period VB, VGL2 lower than VGL1 is applied to the VDD terminal as a sufficient negative bias voltage is applied to the gate-source of the transistors.

The gate low voltage (hereinafter referred to as “VGL”) may be divided into VGL1 and VGL2. VGL1 is applied to the VSS1 terminal as shown in FIG. 6 . A voltage for varying VGL is applied to the VSS2 terminal. VGL1 is applied to the VSS2 terminal during the vertical active period (AT), and VGL2 lower than VGL1 is applied as a sufficient negative bias voltage is applied to the gates and sources of the transistors during the vertical blank period (VB).

A reset signal VRST is applied to the VRST terminal. The reset signal VRST is generated immediately after the power of the display device is turned on, and is generated during a vertical blank period in every frame period. The reset signal VRST is commonly input to the VST terminal of all stages to simultaneously discharge the Q nodes to initialize the shift register.

The blank signal VBLK is generated as VGL2 so that a negative bias voltage can be sufficiently applied to the gates and sources of transistors during the vertical active period AT of every frame period. Also, the blank signal VBLK is generated as a VGH voltage to turn on the transistors T3R and T7B in the vertical blank period VB. When the fifth transistor T3R is turned on, the voltage of the Q node is lowered to VGL2. When the eighth transistor T7B is turned on, the voltage of the output terminal is lowered to VGL1. The blank signal VBLK is commonly input to the VBLK terminal of all stages to simultaneously discharge the Q nodes to initialize the shift register. The blank signal VBLK has a longer pulse width than the reset signal VRST. For example, the blank signal VBLK may be generated with a pulse width equal to or greater than 2/1 of the vertical blank period VB and the maximum vertical blank period VB.

5 is a circuit diagram showing in detail the GIP circuit according to the first embodiment of the present invention. FIG. 5 illustrates a circuit of the Nth stage shown in FIG. 4 . Each of the stages constituting the shift register is substantially the same as the Nth stage shown in FIG. 5 . 6 is a waveform diagram showing input/output signals and Q node waveforms showing the operation of the GIP circuit shown in FIG. 5; 7 shows output clocks (CLK(N-1), CLK(N)), control clocks (CLK(N-1)', CLK(N)'), Q node voltages (VQ(N)), and output terminals. It is a waveform diagram showing the gate pulse (Vgout(N)) output through

Referring to FIGS. 5 to 7 , the Nth stage (S(N)) is VGH of the first clock (CLK(N)) when the first clock (CLK(N) is input in a state where the Q node is charged). The first transistor T6 charges the output terminal with the second transistor T3C, the second transistor T3C discharges the Q node in response to the second clock CLK(N-1)', and the third clock (/CLK(N) ') is provided with a third transistor (T7C) for discharging the output terminal.

The first transistor T6 outputs up to the voltage VGH of the first clock CLK(N) when the first clock CLK(N) is input through the first CLK terminal in a state where the Q node voltage is charged. It is a pull-up transistor that charges the terminal. When the output terminal is charged by the first transistor T6, the gate pulse Vgout(N) starts to be supplied to the gate line 14. The gate pulse Vgout(N) is supplied as a carry signal to the VST terminal of the next stage and the VNEXT terminal of the preceding stage. The first transistor T6 includes a gate connected to the Q node, a first electrode connected to the output CLK terminal, and a second electrode connected to the output terminal.

The second transistor T3C connects the Q node to the output terminal Vgout(N-1) of the N-1th stage S(N-1) in response to CLK(N-1)' input through the second CLK terminal. )) to the When CLK(N-1)' is VGH If Vgout(N-1) is VGH, the Q node is charged. When CLK(N-1)' is VGH, if Vgout(N-1) is VGL1, the Q node is discharged. The second transistor T3C includes a gate connected to the second CLK terminal, a first electrode connected to the Q node, and a second electrode connected to the output terminal of the N−1th stage S(N−1).

The third transistor T7C is a pull-down transistor that discharges the output terminal to VGL2 in response to a third clock (/CLK(N)') input through the third CLK terminal. The third clock (/CLK(N)') is generated in the opposite phase of the output clock (CLK(N)), and is earlier in phase than the first control clock (CLK(N-1)') by one horizontal period. When the output terminal is discharged by the third transistor T7C, the gate line 14 is discharged to VGL2 lower than VGL1, so the falling time of the gate pulse is shortened and the falling time is improved. The third transistor T7C includes a gate connected to the third CLK terminal, a first electrode connected to the output terminal, and a second electrode connected to the VSS2 terminal.

The low level voltage VGL2 of the second and third clocks CLK(N−1)′ and /CLK(N)′ is lower than the low level voltage VGL1 of the first clock CLK(N). The high level voltage VGH of each of the second and third clocks CLK(N−1)′ and /CLK(N)′ is equal to the high level voltage VGH of the first clock CLK(N).

The phase of the second clock (CLK(N-1)') is faster than that of the first clock (CLK(N)) and slower than that of the third clock (/CLK(N)'). The third clock (/CLK(N')) is generated as an anti-phase clock with respect to the first clock (CLK(N)). The first clock CLK(N) swings between VGH and VGL1, and each of the second and third clocks CLK(N-1)' and CLK(N)' swings between VGH and VGL2. VGL2 is lower than VGL1.

The Nth stage (S(N)) is a VST terminal to which a start signal (VST) for precharging the Q node is applied, VGH is generated during the vertical active period (AT) and VGL2 is generated during the vertical blank period (VB). VDD terminal to which VDD is applied, VSS1 terminal to which VSS1 generated by VGL1 is applied during the vertical active period (AT) and vertical blank period (VB), and generated by VGL1 during the vertical active period (AT) and during the vertical blank period (VB) VSS2 terminal to which the VSS2 voltage generated by VGL2 is applied, VNEXT terminal to which the output signal (Vgout(N+2)) of the next stage (S(N+2)) is applied, and VGL1 generated during the vertical active period (AT) and a VBLK terminal to which the blank signal VBLK generated by VGL is applied during the vertical blank period VB.

The Nth stage S(N) includes a fourth transistor T1 precharging the Q node to VGH in response to the start signal VST and a fifth transistor T1 discharging the Q node to VGL2 in response to the blank signal VBLK. Transistor T3R, a sixth transistor T3N for discharging the Q node to a second low level voltage in response to the output signal Vgout(N+2) of the next stage S(N+2), and a first clock A seventh transistor T7D having a first electrode to which (CLK(N)) is applied, a second electrode connected to an output terminal, and a gate, and a seventh transistor T7D that discharges the voltage of the output terminal to VGL1 in response to the blank signal VBLK. 8 transistors T7B are further provided.

The fourth transistor T1 precharges the Q node by applying VGH to the Q node in response to the VST signal. The voltage of the Q node is boosted by charging the voltage applied through the fourth transistor T1. The fourth transistor T1 includes a gate connected to the VST terminal, a first electrode connected to the VDD terminal, and a second electrode connected to the Q node.

The fifth transistor T3R connects the Q node to the VSS2 terminal in response to the vertical blank signal VBLK input through the VBLK terminal, and discharges the Q node to VGL2 during the vertical blank period VB. The fifth transistor T3R includes a gate connected to the VBLK terminal, a first electrode connected to the Q node, and a second electrode connected to the VSS2 terminal.

The sixth transistor T3N discharges the Q node by connecting the Q node to the VSS2 terminal in response to a signal input through the VNEXT terminal. The sixth transistor T3N includes a gate connected to the VNEXT terminal, a first electrode connected to the Q node, and a second electrode connected to the VSS2 terminal.

The seventh transistor T7D is turned on when the voltage of the output terminal rises above its threshold voltage, but remains off when the voltage of the output terminal is VGL1 or VGL2. The seventh transistor T7D operates as a diode. When the voltage of the output CLK is VGL1 and a ripple higher than VGL1 is generated on the gate line 14, the seventh transistor T7D is turned on and the ripple voltage of the gate line 14 is reduced to the seventh transistor T7D. ) and discharged through the first CLK terminal. Accordingly, the gate line 14 keeps VGL stable during the rest of the frame period except for the gate pulse. The gate and the second electrode of the seventh transistor T7D are connected to the output terminal. A first electrode of the seventh transistor T7D is connected to the first CLK terminal.

The eighth transistor T7B discharges the output terminal to VGL1 in response to the blank signal VBLK input through the VBLK terminal. The eighth transistor T7B includes a gate connected to the VBLK terminal, a first electrode connected to the output terminal, and a second electrode connected to the VSS1 terminal.

The transistors T1, T3N, T3R, T3C, T6, T7C, T7D, and T7B are illustrated as NMOS transistors, but are not limited thereto. The transistors T1, T3N, T3R, T3C, T6, T7C, T7D, and T7B may be PMOS transistors.

Looking at the operation of the GIP circuit, when a start signal such as a start pulse (VST) or a carry signal (Vgout(N-2)) from a previous stage is applied through the VST terminal as shown in FIGS. 5 and 6, the Q node It is pre-charged and boosted. When the first clock CLK(N) is generated at the VGH voltage while the Q node is boosted, the first transistor T6 is turned on and a gate pulse is output through the output terminal. When one gate pulse is output, the Q node is discharged to VGL2 by the VNEXT signal (Vgout(N+2)), and the gate pulse is not output until the signal is input to the VST terminal again. The Q node is discharged every second clock signal CLK(N−1)′ through the second transistor T3C so that the first transistor T6 is stably maintained in an off state. The eighth transistor T7B stably maintains the voltage of the gate lines 14 at VGL1 during the vertical blank period VB.

The first clock CLK(N) belongs to the output clock Output CLK in FIG. 6 . The second and third clocks CLK(N−1)′ and /CLK(N)′ belong to the control clock Control CLK in FIG. 6 .

The output clock (Output CLK) swings between VGH and VGL1 and includes clocks (CLK1 to CLK4) sequentially shifted by one horizontal period (1H). The control clock Control CLK swings between VGH and VGL2 and includes clocks CLK1' to CLK4' sequentially shifted by one horizontal period (1H). VGH may be set to a DC voltage of 28V or higher, but is not limited thereto. VGL2 is a lower voltage than VGL1. VGL1 is exemplified as -5V and VGL2 as -15V, but is not limited thereto.

The output clock (Output CLK) and the control clock (Control CLK) are generated as 4-phase clocks, but are not limited thereto. For example, the clock may be generated as an 8-phase clock. Each of the output clock (Output CLK) and the control clock (Control CLK) may be generated with a pulse width of 2 horizontal periods (2H), but is not limited thereto.

In FIG. 5 , the first clock CLK(N) and the third clock /CLK(N)′ are out of phase with each other and have different voltages. For example, when CLK(N) = CLK3, /CLK(N)' is CLK1'. The voltage of the first clock (CLK(N)) swings between VGH and VGL1. In contrast, the voltages of the second and third clocks CLK(N-1)′, /CLK(N) swing between VGH and VGL2. VGL2 is a lower voltage than VGL1. Accordingly, swing widths of the second and third clocks CLK(N−1)′ and /CLK(N)′ are larger than those of the first clock CLK(N).

The phase of the second clock CLK(N-1)' is earlier than that of the first clock CLK(N), and the phase is slower than that of the third clock /CLK(N)'. The phase of the second clock (CLK(N-1)') is earlier than the start signal input through the VST terminal. When CLK(N)) = CLK3, CLK(N-1)' is CLK2' and /CLK(N)' is CLK1'.

According to the prior art, when the transistors of the GIP circuit are implemented as NMOS transistors, the threshold voltage of the transistors is shifted in the + direction due to a gate bias voltage having a positive bias voltage greater than a negative bias voltage. The present invention reduces the gate bias stress of the transistors constituting the GIP circuit by compensating for the gate bias stress of these transistors with a bias voltage of opposite polarity. For example, the reliability and lifetime of the GIP circuit can be improved by applying a negative bias voltage equal to the positive bias applied to T3C and T7C, which are most vulnerable to gate bias stress in the GIP circuit, to prevent shifting of the threshold voltage of the transistors.

In the present invention, the shift clock signal applied to the GIP circuit is separated into an output clock (Output CLK) and a control clock (Control CLK). As a result, the present invention can stably apply a negative bias voltage to the transistors without adding a separate transistor without affecting the normal operation of the GIP circuit by separating the clock signal.

Meanwhile, if a separate transistor is added to apply a negative bias voltage to the transistor, the GIP circuit becomes complicated because the gate bias stress of the added transistor must also be compensated.

8A to 8H show the gate-source voltage (Vgs) of each of the transistors in the GIP circuit operating as shown in FIGS. 5 to 7 .

Referring to FIG. 8A , the voltage of the VDD terminal is generated as VGH during the vertical active period (AT) and lowered to VGL2 during the vertical blank period (VB). The voltage of the Q node (VQ(N)) is precharged to VGH for 2 horizontal periods (2H) by the VST signal, and after the Q node is boosted, the first clock (CLK(N)) is generated with VGH. rises by 2VGH when At this time (NB period), since the source of the fourth transistor T1 is an electrode having a lower voltage than the drain, it is the first electrode connected to the VDD terminal. In the NB period, Vgs of the fourth transistor T1 is Vgs = VGL1 - VGH. Therefore, in the NB period, Vgs of the fourth transistor T1 is a negative bias voltage (Vgs < 0).

During the vertical blank period (VB), the voltage of the VDD terminal is lowered to VGL2. At this time (VB), the source of the fourth transistor T1 is the first electrode connected to VDD. During the vertical blank VB period, Vgs of the fourth transistor T1 is Vgs = VGL1 - VGL2. Therefore, Vgs of the fourth transistor T1 is a positive bias voltage (Vgs > 0) during the vertical blank VB period.

Since a positive bias (Vgs > 0) is applied to the fourth transistor T1 during the vertical blank period VB, the fourth transistor T1 is turned on. When the fourth transistor T1 is turned on and the Q node voltage is higher than the voltage of the VDD terminal during the vertical blank period VB, the drain and source of the fourth transistor T1 may be shorted. In order to prevent this phenomenon from affecting GIP driving, the voltage of the VDD terminal should be lowered to VGL2 during the vertical blank period (VB), and the voltage of the Q node should be lowered to VGL2 by using the fifth transistor (T3R).

Referring to FIG. 8B , the second transistor T3C is most vulnerable to gate bias stress because it receives a positive bias whenever the second clock CLK(N−1)′ is applied to its gate.

The output signal Vgout(N-1) of the previous stage S(N-1) is applied to the second transistor T3C so as not to affect the boost operation of the Q node. The second clock CLK(N-1)' is applied to the gate of the second transistor to which Vgout(N-1) is applied during the PB period when the voltage of the second clock CLK(N-1)' is VGH. The second electrode of (T3C) serves as a source, and a positive bias (Vgs = VGH - VGL1, Vgs > 0) is applied to the second transistor T3C for each PB period, and the second transistor T3C is turned on. Whenever the second transistor T3C is turned on, the Q node is discharged and the voltage of the Q node becomes VGL1 In FIG. 8B, CLK2' is the second clock CLK(N-1)'.

During the period when the voltage of the second clock CLK(N-1)' is VGL2, the second electrode to which Vgout(N-1) is applied becomes the source of the second transistor T3C, and during this period, the second transistor T3C ) is applied with a negative bias voltage (Vgs = VGL2 - VGL, Vgs < 0), and the second transistor T3C is turned off. The present invention lowers the low-level voltage of the first control clock (CLK(N-1)') to VGL2 so that a negative bias is applied to the second transistor T3C as much as the positive bias period PB, thereby reducing the second transistor T3C. A shift in the threshold voltage of the second transistor T3C is prevented by balancing the positive bias and the negative bias of . During the vertical blank period (VG), vgs = 0 because Vgs of T3C = VGL2 - VGL2.

Referring to FIG. 8C , the low potential voltage applied to the VSS2 terminal is generated as VGL1 = -5V during the vertical active period (AT) and lowers to VGL2 = -15V during the vertical blank period (VB).

During the VGH period of the VNEXT signal, a positive bias (Vgs = VGH - VGL1, Vgs > 0) is applied to the sixth transistor T3N, so that the sixth transistor T3N is turned on. Whenever the sixth transistor T3N is turned on. The Q node is discharged and the voltage at the Q node becomes VGL1.

In order to apply a negative bias to the sixth transistor T3N, the Q node is discharged to VGL2 during the vertical blank period VB through the fifth transistor T3R. During the vertical blank period VB, since the VNEXT signal applied to the gate of the sixth transistor T3N is VGL1 and the Q node connected to the source of the sixth transistor T3N is VGL2, during the vertical blank period VB, the sixth Transistor T3N is turned on. During the vertical blank period VB, the voltage of the VSS2 terminal must be VGL2 so that the drain and source of the sixth transistor T3N are not shorted.

Referring to FIG. 8D , the VBLK signal is generated as VGL2 to apply a negative bias to the fifth transistor T3R during the vertical active period AT of every frame period. And, the VBLK signal is generated as the VGH voltage during the vertical blank period (VB). The fifth transistor T3R is turned on by a positive bias (Vgs = VGH - VGL2, Vgs > 0) during the vertical blank period VB. When the fifth transistor T3R is turned on, the Q node is discharged to VGL2. During the vertical active period AT other than the vertical blank period VB, since the VBLK signal is VGL1, the fifth transistor T3R receives a negative bias (Vgs = VGL2 - VGL1, Vgs < 0). During this vertical active period AT, the source of the fifth transistor T3R is the second electrode to which VGL1 is applied through the VSS2 terminal.

Referring to FIG. 8E, during the two horizontal periods (2H) in which the Q node is pre-charged, the first transistor T6 receives a positive bias voltage (Vgs = VQ(N) - VGL1, Vgs > 0), and then the Q node During the second horizontal period in which V is bootstrapped by CLK(N), the first transistor T6 receives a positive bias voltage (Vgs = VQ(N) - VGH, Vgs > 0). Accordingly, a positive bias voltage is applied to the first transistor T6 during the PB period of the fourth horizontal period 4H. In Fig. 8E, CLK3 is CLK(N).

Since the gate of the first transistor T6 is connected to the Q node and the second transistor T3C is connected to the Q node, it is difficult to apply a negative bias voltage to the first transistor T6 while the GIP circuit is being driven. During the vertical blank period VB, the Q node is discharged to VGL2 through the fifth transistor T3R to apply a negative bias voltage (Vgs = VGL2 - VGL1, Vgs < 0) to the first transistor T6.

Since the first transistor T6 is a pull-up transistor, when the first transistor T6 is turned on, VGH of the first clock CLK(N) is output as a gate pulse Vgout(N). Unlike the second and third clocks CLK(N−1)′ and /CLK(N)′, the first clock CLK(N) has a low level voltage of VGL1. This is because the voltage of CLK(N) must be higher than VGL2 of the Q node in order to apply the negative bias voltage to the first transistor T6 during the vertical blank period VB. Therefore, in the present invention, a threshold voltage shift of the first transistor T6 is prevented by applying a negative bias to the first transistor T6 equal to the positive bias applied to the first transistor T6. If the low level voltage of the first clock CLK(N) is equal to the low level voltage of the second and third clocks CLK(N−1)′ and /CLK(N)′, the first transistor ( A negative bias voltage for restoring characteristics of T6) cannot be applied to the first transistor T6.

Referring to FIG. 8F , the third transistor T7C operates similarly to the second transistor T3C. During the PB period when the third clock (/CLK(N)') is VGH, the second electrode of the third transistor T7C serves as a source and supplies the third transistor T7C with a positive bias voltage (Vgs = VGH - VGL1, Vgs > 0) is applied. Even when the voltage of the third clock (/CLK(N)') is VGL2, the source of the third transistor T7C is the second electrode. Since the voltage of the VSS2 terminal is VGL1 during the vertical active period (AT), when the voltage of the second control clock (CLK(N)') is VGL2, the negative bias voltage (Vgs = VGL2 - VGL1, Vgs < 0).

The voltage of the VSS2 terminal must be VGL1 so that the negative bias voltage is applied to the third transistor T7C during the period AT other than the vertical blank period VB. FIG. 8F shows an example (Vgs = 0) in which no bias voltage is applied to the third transistor T7C during the vertical blank period VB. As another embodiment, the present invention may apply a negative bias voltage to the third transistor T7C by applying VGL1 instead of VGL2 to the VSS2 terminal during the vertical blank period VG.

As shown in FIG. 8G , the seventh transistor T7D has Vgs = 0 during one frame period, so a bias voltage biased to one polarity is not applied.

During the vertical blank period VB, since the third transistor T7C is turned off, the output terminal of the Nth stage S(N) is in a floating state and the voltage of the gate line becomes unstable. To solve this problem, the first embodiment of the present invention adds an eighth transistor T7B to the GIP circuit and increases the voltage of the blank signal VBLK to VGH during the vertical blank period VB as shown in FIG. 8H. The voltage of the gate line 14 is reduced to VGL1 by turning on the eighth transistor T7B. During the PB period during which the gate pulse Vgou(N) is output, VGL2 of the blank signal is applied to the gate of the eighth transistor T7B, and VGL1 is applied to the terminal VSS1. For this reason, during the vertical active period AT, the eighth transistor T7B receives a negative bias voltage (Vgs = VGL2 - VGL1, Vgs < 0). During the vertical blank period VB, the gate voltage of the eighth transistor T7B is VGH and the source voltage of the eighth transistor T7B is VGL1. Accordingly, the eighth transistor T7B receives a positive bias voltage (Vgs = VGH = VGL1, Vgs > 0) during the vertical blank period VB. The eighth transistor T7B may be omitted according to driving characteristics or models of the display device as shown in FIGS. 9 to 13 .

It should be noted that the GIP circuit of the present invention is not limited to FIGS. 5 and 6 because it can be variously modified as shown in FIGS. 9 to 13 . In FIGS. 9 to 13 , detailed descriptions of components substantially the same as those of the foregoing embodiment are omitted.

9 is a diagram showing a GIP circuit and its input/output signals according to a second embodiment of the present invention.

Referring to FIG. 9, the Nth stage (S(N)) of the GIP circuit according to the second embodiment of the present invention when the first clock (CLK(N)) is input while the Q node is charged The first transistor T6 charges the output terminal with the high level voltage VGH of 1 clock CLK(N), and the second transistor T6 discharges the Q node in response to the second clock CLK(N-1)'. A transistor T3C, and a third transistor T7C for discharging an output terminal in response to a third clock (/CLK(N)'). The third transistor T7C includes a gate connected to the third CLK terminal, a first electrode connected to the output terminal, and a second electrode connected to the VSS terminal.

The low level voltage VGL2 of the second and third clocks CLK(N−1)′ and /CLK(N)′ is lower than the low level voltage VGL1 of the first clock CLK(N). The high level voltage VGH of each of the second and third clocks CLK(N−1)′ and /CLK(N)′ is equal to the high level voltage VGH of the first clock CLK(N).

The Nth stage (S(N)) is a VST terminal to which a start signal (VST) for precharging the Q node is applied, and a low potential power supply voltage generated as VGL1 during the vertical active period (AT) and the vertical blank period (VB). VSS terminal to which this is applied, VNEXT terminal to which the output signal (Vgout(N+2)) of the next stage (S(N+2)) is applied, VGL1 is generated during the vertical active period (AT) and the vertical blank period (VB) A VRST terminal to which the reset signal VRST generated by VGH is applied at the beginning of , a fourth transistor T1 precharging the Q node to VGH in response to a start signal, and a Q node to VGL1 in response to the reset signal VRST. The fifth transistor T3R for discharging to VGL1 in response to the output signal Vgout(N+2) of the next stage, the sixth transistor T3N for discharging the Q node to VGL1, and the first clock CLK(N) A seventh transistor T7D having a first electrode applied thereto, a second electrode connected to the output terminal, and a gate is further included.

The gate and first electrode of the fourth transistor T1 are connected to the VST terminal. A Q node is connected to the second electrode of the fourth transistor T1. The fifth transistor T3R includes a gate connected to the VRST terminal, a first electrode connected to the Q node, and a second electrode connected to the VSS terminal. The sixth transistor T3N includes a gate connected to the VNEXT terminal, a first electrode connected to the Q node, and a second electrode connected to the VSS terminal.

In the second embodiment of the present invention, a positive bias voltage and a negative bias voltage are alternately applied to the transistors T3C and T7C that are most vulnerable to gate bias stress in the GIP circuit. Compared to the first embodiment described above, the GIP circuit of the second embodiment does not require a VDD terminal, a VSS2 terminal, a transistor T7B, or the like. VGL1 is applied to the VSS terminal. A reset signal VRST is applied to the VRST terminal. The reset signal VRST is generated with the VGH voltage having the same pulse width as the clock during the initial two horizontal periods (2H) of the vertical blank period (VB).

10 is a diagram showing a GIP circuit and its input/output signals according to a third embodiment of the present invention.

Referring to FIG. 10, in the GIP circuit according to the third embodiment of the present invention, the Nth stage (S(N)) is input when the first clock (CLK(N)) is input while the Q node is charged. The first transistor T6 charges the output terminal with VGH of one clock CLK(N), the second transistor T3C discharges the Q node in response to the second clock CLK(N-1)', and a third transistor T7C for discharging an output terminal in response to a third clock (/CLK(N)). The low level voltage VGL2 of the second clock CLK(N-1)' is lower than the low level voltage VGL1 of the first and third clocks CLK(N) and /CLK(N)'.

The Nth stage (S(N)) is a VST terminal to which a start signal for precharging the Q node is applied, and a low potential power supply voltage generated by VGL1 during the vertical active period (AT) and the vertical blank period (VB) is applied. VSS terminal, VNEXT terminal to which the output signal (Vgout(N+2)) of the next stage (S(N+2) is applied), generated as VGL1 during the vertical active period (AT) and VGH at the beginning of the vertical blank period (VB) A VRST terminal to which the reset signal VRST generated by is applied, a fourth transistor T1 precharging the Q node to VGH in response to the start signal VST, and a Q node up to VGL1 in response to the reset signal VRST. The fifth transistor T3R for discharging, the sixth transistor T3N for discharging the Q node to VGL1 in response to the output signal Vgout(N+2) of the next stage, and the first clock CLK(N) are A seventh transistor T7D having a gate and a second electrode connected to the applied first electrode and the output terminal is further included.

In the third embodiment of the present invention, a positive bias voltage and a negative bias voltage are alternately applied to the transistor T3C that is vulnerable to gate bias stress in the GIP circuit. Compared to the first embodiment described above, the GIP circuit of the third embodiment does not require the VDD terminal, the VSS2 terminal, and the transistor T7B. VGL1 is applied to the VSS terminal. A reset signal VRST is applied to the VRST terminal at the beginning of the vertical blank period VB.

The shift clock applied to the gate of the third transistor T7C in the third embodiment is different from that in the first embodiment. In the third embodiment, an output clock (/CLK(N)) having a higher low level voltage is applied to the gate of the third transistor T7C instead of the control clock (/CLK(N)′). /CLK(N) is a clock signal out of phase with CLK(N) and swings with the same swing width. When CLK(N) is CLK3, /CLK(N) is CLK1 which is earlier in phase than CLK3 by 2 horizontal periods (2H). The high level voltage of /CLK(N) and CLK(N) is VGH, and the low level voltage is VGL1.

T1, T3R, T3N, T3C, T6 and T7D of the third embodiment are substantially the same as those of the second embodiment.

11 is a diagram showing a GIP circuit and its input/output signals according to a fourth embodiment of the present invention.

Referring to FIG. 11, the Nth stage S(N) of the GIP circuit according to the fourth embodiment of the present invention generates the first clock CLK(N) when the first clock CLK(N) is input while the Q node is charged. The first transistor T6 charges the output terminal with VGH of the clock CLK(N), the second transistor T3C discharges the Q node in response to the second clock CLK(N-1), and and a third transistor T7C that discharges an output terminal in response to three clocks (/CLK(N)'). The low-level voltage VGL2 of the third clock (/CLK(N)') is It is lower than the low level voltage VGL1 of the second clocks CLK(N) and CLK(N-1).

The Nth stage (S(N)) is a VST terminal to which a start signal (VST) for precharging the Q node is applied, and a low potential power supply voltage generated as VGL1 during the vertical active period (AT) and the vertical blank period (VB). The VSS terminal to which this is applied, the VNEXT terminal to which the output signal (Vgout(N+2) of the next stage (S(N+2)) is applied, generated as VGL1 during the vertical active period (AT) and the initial stage of the vertical blank period (VB) The VRST terminal to which the reset signal VRST generated by VGH is applied, the fourth transistor T1 precharging the Q node to VGH in response to the start signal VST, and the Q node in response to the reset signal VRST. The fifth transistor T3R discharges to VGL1, the sixth transistor T3N discharges the Q node to VGL1 in response to the output signal Vgout(N+2) of the next stage, and the first clock CLK(N). ) is applied, and a seventh transistor T7D having a gate and a second electrode connected to the output terminal is further included.

In the fourth embodiment of the present invention, a positive bias voltage and a negative bias voltage are alternately applied to the transistor T7C that is vulnerable to gate bias stress in the GIP circuit. Compared to the first embodiment described above, the GIP circuit of the third embodiment does not require the VDD terminal, the VSS2 terminal and the transistor T7B.

In the fourth embodiment, the shift clock applied to the gate of the second transistor T3C is different from that in the first embodiment. In the fourth embodiment, an output clock (/CLK(N-1)) having a higher low level is applied to the gate of the second transistor T3C instead of the control clock (/CLK(N-1)').

T1, T3R, T3N, T6, T7C and T7D in the fourth embodiment are substantially the same as those in the second embodiment.

12 is a diagram showing a GIP circuit and its input/output signals according to a fifth embodiment of the present invention.

Referring to FIG. 12, the Nth stage S(N) of the GIP circuit according to the fifth embodiment of the present invention generates the first clock CLK(N) when the first clock CLK(N) is input while the Q node is charged. A first transistor T6 charges the first output terminal with VGH of the clock CLK(N), and a second transistor T3C discharges the Q node in response to the second clock CLK(N-1)'. , and a third transistor T7C that discharges the first output terminal in response to the third clock signal CLK(N)'. The second and third clock signals CLK(N-1)', /CLK( The low level voltage VGL2 of N)') is lower than the low level voltage VGL1 of the first clock CLK(N).

The Nth stage (S(N)) is a VST terminal to which a start signal for precharging the Q node is applied, and a first low potential power supply voltage generated by VGL1 during the vertical active period (AT) and the vertical blank period (VB). VSS1 terminal applied, VSS2 terminal to which the second low-potential power supply voltage generated by VGL2 is applied during the vertical active period (AT) and vertical blank period (VB), and the output signal (Vgout) of the next stage (S(N+2)) (N+2)) is applied to the VNEXT terminal, the VRST terminal to which the reset signal (VRST) generated by VGL1 during the vertical active period (AT) and generated by VGH at the beginning of the vertical blank period (VB) is applied, and the start signal ( The fourth transistor T1 precharges the Q node to VGH in response to VST, the fifth transistor T3R discharges the Q node to VGL2 in response to the reset signal VRST, and the output signal of the next stage Vgout( N+2)), a sixth transistor T3N that discharges the Q node to VGL2, a first electrode to which the first clock CLK(N) is applied, a second electrode connected to an output terminal, and a gate. 7 Transistor T7D, an eighth transistor for charging the second output terminal with VGH of the first clock CLK(N) when the first clock CLK(N) is input while the Q node is charged T6_C) and a ninth transistor T7C_C for discharging the second output terminal in response to a third clock (/CLK(N)').

In the fifth embodiment of the present invention, the gate pulse (Vgout(N)) and the carry signal (Carry(N)) are separated. The Nth stage S(N) outputs the gate pulse Vgout(N) through the first output terminal and outputs the carry signal Carry(N) through the second output terminal.

The first transistor T6 includes a gate connected to the Q node, a first electrode connected to the output CLK terminal, and a second electrode connected to the first output terminal. The third transistor T7C includes a gate connected to the third CLK terminal, a first electrode connected to the first output terminal, and a second electrode connected to the VSS1 terminal.

The gate and first electrode of the fourth transistor T1 are connected to the VST terminal. A Q node is connected to the second electrode of the fourth transistor T1. The fifth transistor T3R includes a gate connected to the VRST terminal, a first electrode connected to the Q node, and a second electrode connected to the VSS2 terminal.

The eighth transistor T6_C includes a gate connected to the Q node, a first electrode connected to the first CLK terminal, and a second electrode connected to the second output terminal. The ninth transistor T7C_C includes a gate connected to the third CLK terminal, a first electrode connected to the second output terminal, and a second electrode connected to the VSS2 terminal.

Since T3N, T3C, and T7D are substantially the same as those of the first embodiment, detailed descriptions thereof are omitted.

13 is a diagram showing a GIP circuit and its input/output signals according to a sixth embodiment of the present invention.

Referring to FIG. 13, the Nth stage (S(N)) of the GIP circuit according to the sixth embodiment of the present invention when the first clock (CLK(N)) is input while the Q node is charged The first transistor T6 charges the output terminal with VGH of one clock CLK(N), the second transistor T3C discharges the Q node in response to the second clock CLK(N-1)', and a third transistor T7C for discharging an output terminal in response to a third clock CLK(N)'.

The Nth stage (S(N)) is a VST terminal to which a start signal (VST) for precharging the Q node is applied, VGH is generated during the vertical active period (AT) and VGL2 is generated during the vertical blank period (VB). VDD terminal to which high-potential power supply voltage is applied, VSS terminal to which VGL1 is generated during the vertical active period (AT) and low-potential power supply voltage generated to VGL2 during the vertical blank period (VB) is applied, and the next stage (S(N+2 )) VNEXT terminal to which the output signal (Vgout(N+2)) is applied, VBLK to which the blank signal (VBLK) generated by VGL2 during the vertical active period (AT) and generated by VGH during the vertical blank period (VB) is applied terminal, a fourth transistor (T1) for precharging the Q node to VGH in response to the start signal (VST), a fifth transistor (T3R) for discharging the Q node to VGL2 in response to the blank signal (VBLK), the next stage The sixth transistor T3N discharges the Q node to VGL1 in response to the output signal Vgout(N+2), and the first electrode to which the first clock CLK(N) is applied and the second connected to the output terminal. A seventh transistor T7D having an electrode and a gate is further included.

According to the sixth embodiment of the present invention, the VSS voltage is generated as AC to control the first and third transistors T6 and T7C to be turned off during the vertical blank period VB. Since the first and third transistors T6 and T7C are off during the vertical blank period VB, the output terminal is floating. Since the voltage of the output terminal maintains VGL before the vertical blank period VB, it is possible to maintain VGL during the vertical blank period VB.

Since the seventh transistor T7D operates as a diode, it does not operate while the voltage of the output terminal maintains the VGL voltage. When the voltage of the output terminal is higher than the VGL voltage, the seventh transistor T7D is turned on and VGL is applied to the output terminal through the seventh transistor T7D.

The third transistor T7C includes a gate connected to the second control terminal CLK, a first electrode connected to the output terminal, and a second electrode connected to the VSS terminal. The fifth transistor T3R includes a gate connected to the VRST terminal, a first electrode connected to the Q node, and a second electrode connected to the VSS terminal. The sixth transistor T3N includes a gate connected to the VNEXT terminal, a first electrode connected to the Q node, and a second electrode connected to the VSS terminal.

Compared to the first embodiment, the sixth embodiment can remove the VSS1 terminal and the wiring connected thereto. Since T1, T3C, T6, and T7D are substantially the same as those of the second embodiment, detailed descriptions thereof are omitted.

Through the above description, those skilled in the art will understand that various changes and modifications are possible without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

12: data line 14: gate line
16, SIC: data driving circuit 18, GIP: gate driving circuit (GIP circuit)
20, TCON: timing controller PNL: display panel
LS: Level Shifter
T1, T3R, T3N, T3C, T6, T7B, T7C, T7D, T6_C, T7C_C: Transistors

Claims (20)

a first transistor charging an output terminal with a high level voltage of a first clock while the Q node is charged;
a second transistor discharging the Q node in response to a second clock; and
A third transistor configured to discharge the output terminal in response to a third clock;
a low level voltage of at least one of the second and third clocks is lower than a low level voltage of the first clock;
a high level voltage of each of the second and third clocks is equal to a high level voltage of the first clock;
a phase of the second clock is faster than the first clock and slower than the third clock;
wherein the third clock is generated as an anti-phase clock with respect to the first clock. According to claim 1,
the first clock swings between a high level voltage and a first low level voltage, and each of the second and third clocks swings between the high level voltage and a second low level voltage;
The gate driving circuit wherein the second low level voltage is lower than the first low level voltage. According to claim 2,
a VST terminal to which a start signal for precharging the Q node is applied;
a VDD terminal to which a high potential power supply voltage generated as the high level voltage during a vertical active period and as the second low level voltage during a vertical blank period is applied;
a VSS1 terminal to which a first low-potential power supply voltage generated as the first low-level voltage is applied during the vertical active period and the vertical blank period;
a VSS2 terminal to which a second low potential power supply voltage generated as the first low level voltage during the vertical active period and as the second low level voltage during the vertical blank period is applied;
a VNEXT terminal to which an output signal of the next stage is applied;
a VBLK terminal to which a blank signal generated as the first low level voltage during the vertical active period and as the high level voltage during the vertical blank period is applied;
a fourth transistor pre-charging the Q node to the high level voltage in response to the start signal;
a fifth transistor discharging the Q node to the second low level voltage in response to the blank signal;
a sixth transistor to discharge the Q node to the second low level voltage in response to the output signal of the next stage;
a seventh transistor having a first electrode to which the first clock is applied, a second electrode connected to the output terminal, and a gate; and
and an eighth transistor to discharge the voltage of the output terminal to the first low level voltage in response to the blank signal. According to claim 2,
a VST terminal to which a start signal for precharging the Q node is applied;
a VSS terminal to which a low potential power supply voltage generated as the first low level voltage is applied during a vertical active period and a vertical blank period;
a VNEXT terminal to which an output signal of the next stage is applied;
a VRST terminal to which a reset signal generated as the first low level voltage during the vertical active period and as the high level voltage at the beginning of the vertical blank period is applied;
a fourth transistor pre-charging the Q node to the high level voltage in response to the start signal;
a fifth transistor discharging the Q node to the first low level voltage in response to the reset signal;
a sixth transistor to discharge the Q node to the first low level voltage in response to the output signal of the next stage; and
and a seventh transistor having a gate and a first electrode to which the first clock is applied, a second electrode connected to the output terminal, and a gate. According to claim 1,
a low level voltage of the second clock is lower than a low level voltage of each of the first and third clocks;
the first and third clocks swing between a high level voltage and a first low level voltage, and the second clock swings between the high level voltage and a second low level voltage;
The gate driving circuit wherein the second low level voltage is lower than the first low level voltage. According to claim 5,
a VST terminal to which a start signal for precharging the Q node is applied;
a VSS terminal to which a low potential power supply voltage generated as the first low level voltage is applied during a vertical active period and a vertical blank period;
a VNEXT terminal to which an output signal of the next stage is applied;
a VRST terminal to which a reset signal generated as the first low level voltage during the vertical active period and as the high level voltage at the beginning of the vertical blank period is applied;
a fourth transistor pre-charging the Q node to the high level voltage in response to the start signal;
a fifth transistor discharging the Q node to the first low level voltage in response to the reset signal;
a sixth transistor to discharge the Q node to the first low level voltage in response to the output signal of the next stage; and
and a seventh transistor having a gate and a first electrode to which the first clock is applied, a second electrode connected to the output terminal, and a gate. According to claim 1,
a low level voltage of the third clock is lower than a low level voltage of each of the first and second clocks;
the first and second clocks swing between a high level voltage and a first low level voltage, and the third clock swings between the high level voltage and a second low level voltage;
The gate driving circuit wherein the second low level voltage is lower than the first low level voltage. According to claim 7,
a VST terminal to which a start signal for precharging the Q node is applied;
a VSS terminal to which a low potential power supply voltage generated as the first low level voltage is applied during a vertical active period and a vertical blank period;
a VNEXT terminal to which an output signal of the next stage is applied;
a VRST terminal to which a reset signal generated as the first low level voltage during the vertical active period and as the high level voltage at the beginning of the vertical blank period is applied;
a fourth transistor pre-charging the Q node to the high level voltage in response to the start signal;
a fifth transistor discharging the Q node to the first low level voltage in response to the reset signal;
a sixth transistor to discharge the Q node to the first low level voltage in response to the output signal of the next stage; and
and a seventh transistor having a gate and a first electrode to which the first clock is applied, a second electrode connected to the output terminal, and a gate. According to claim 2,
a VST terminal to which a start signal for precharging the Q node is applied;
a VSS1 terminal to which a first low-potential power supply voltage generated as the first low-level voltage is applied during a vertical active period and a vertical blank period;
a VSS2 terminal to which a second low potential power supply voltage generated as the second low level voltage is applied during the vertical active period and the vertical blank period;
a VNEXT terminal to which an output signal of the next stage is applied;
a VRST terminal to which a reset signal generated as the first low level voltage during the vertical active period and as the high level voltage at the beginning of the vertical blank period is applied;
a fourth transistor pre-charging the Q node to the high level voltage in response to the start signal;
a fifth transistor discharging the Q node to the second low level voltage in response to the reset signal;
a sixth transistor to discharge the Q node to the second low level voltage in response to the output signal of the next stage;
a seventh transistor having a first electrode to which the first clock is applied, a second electrode connected to the output terminal, and a gate;
an eighth transistor to charge a second output terminal with a high level voltage of the first clock when the first clock is input while the Q node is charged; and
and a ninth transistor configured to discharge the second output terminal in response to the third clock. According to claim 2,
a VST terminal to which a start signal for precharging the Q node is applied;
a VDD terminal to which a high potential power supply voltage generated as the high level voltage during a vertical active period and as the second low level voltage during a vertical blank period is applied;
a VSS terminal to which a low potential power supply voltage generated as the first low level voltage during the vertical active period and as the second low level voltage during the vertical blank period is applied;
a VNEXT terminal to which an output signal of the next stage is applied;
a VBLK terminal to which a blank signal generated as the second low level voltage during the vertical active period and as the high level voltage during the vertical blank period is applied;
a fourth transistor pre-charging the Q node to the high level voltage in response to the start signal;
a fifth transistor discharging the Q node to the second low level voltage in response to the blank signal;
a sixth transistor to discharge the Q node to the first low level voltage in response to the output signal of the next stage; and
and a seventh transistor having a gate and a first electrode to which the first clock is applied, a second electrode connected to the output terminal, and a gate. a display panel including data lines and gate lines; and
A gate driving circuit supplying a gate pulse to the gate line through an output terminal;
The gate driving circuit,
a first transistor charging the output terminal with a high level voltage of a first clock while the Q node is charged;
a second transistor discharging the Q node in response to a second clock; and
A third transistor configured to discharge the output terminal in response to a third clock;
a low level voltage of at least one of the second and third clocks is lower than a low level voltage of the first clock;
a high level voltage of each of the second and third clocks is equal to a high level voltage of the first clock;
a phase of the second clock is faster than the first clock and slower than the third clock;
wherein the third clock is generated as an anti-phase clock with respect to the first clock. According to claim 11,
the first clock swings between a high level voltage and a first low level voltage, and each of the second and third clocks swings between the high level voltage and a second low level voltage;
The second low level voltage is lower than the first low level voltage. According to claim 12,
The gate driving circuit,
a VST terminal to which a start signal for precharging the Q node is applied;
a VDD terminal to which a high potential power supply voltage generated as the high level voltage during a vertical active period and as the second low level voltage during a vertical blank period is applied;
a VSS1 terminal to which a first low-potential power supply voltage generated as the first low-level voltage is applied during the vertical active period and the vertical blank period;
a VSS2 terminal to which a second low potential power supply voltage generated as the first low level voltage during the vertical active period and as the second low level voltage during the vertical blank period is applied;
a VNEXT terminal to which an output signal of the next stage is applied;
a VBLK terminal to which a blank signal generated as the first low level voltage during the vertical active period and as the high level voltage during the vertical blank period is applied;
a fourth transistor pre-charging the Q node to the high level voltage in response to the start signal;
a fifth transistor discharging the Q node to the second low level voltage in response to the blank signal;
a sixth transistor to discharge the Q node to the second low level voltage in response to the output signal of the next stage;
a seventh transistor having a first electrode to which the first clock is applied, a second electrode connected to the output terminal, and a gate; and
and an eighth transistor to discharge the voltage of the output terminal to the first low level voltage in response to the blank signal. According to claim 12,
The gate driving circuit,
a VST terminal to which a start signal for precharging the Q node is applied;
a VSS terminal to which a low potential power supply voltage generated as the first low level voltage is applied during a vertical active period and a vertical blank period;
a VNEXT terminal to which an output signal of the next stage is applied;
a VRST terminal to which a reset signal generated as the first low level voltage during the vertical active period and as the high level voltage at the beginning of the vertical blank period is applied;
a fourth transistor pre-charging the Q node to the high level voltage in response to the start signal;
a fifth transistor discharging the Q node to the first low level voltage in response to the reset signal;
a sixth transistor to discharge the Q node to the first low level voltage in response to the output signal of the next stage; and
and a seventh transistor having a first electrode to which the first clock is applied, a second electrode connected to the output terminal, and a gate. According to claim 11,
a low level voltage of the second clock is lower than a low level voltage of each of the first and third clocks;
the first and third clocks swing between a high level voltage and a first low level voltage, and the second clock swings between the high level voltage and a second low level voltage;
The second low level voltage is lower than the first low level voltage. According to claim 15,
The gate driving circuit,
a VST terminal to which a start signal for precharging the Q node is applied;
a VSS terminal to which a low potential power supply voltage generated as the first low level voltage is applied during a vertical active period and a vertical blank period;
a VNEXT terminal to which an output signal of the next stage is applied;
a VRST terminal to which a reset signal generated as the first low level voltage during the vertical active period and as the high level voltage at the beginning of the vertical blank period is applied;
a fourth transistor pre-charging the Q node to the high level voltage in response to the start signal;
a fifth transistor discharging the Q node to the first low level voltage in response to the reset signal;
a sixth transistor to discharge the Q node to the first low level voltage in response to the output signal of the next stage; and
and a seventh transistor having a first electrode to which the first clock is applied, a second electrode connected to the output terminal, and a gate. According to claim 11,
a low level voltage of the third clock is lower than a low level voltage of each of the first and second clocks;
the first and second clocks swing between a high level voltage and a first low level voltage, and the third clock swings between the high level voltage and a second low level voltage;
The second low level voltage is lower than the first low level voltage. 18. The method of claim 17,
The gate driving circuit,
a VST terminal to which a start signal for precharging the Q node is applied;
a VSS terminal to which a low potential power supply voltage generated as the first low level voltage is applied during a vertical active period and a vertical blank period;
a VNEXT terminal to which an output signal of the next stage is applied;
a VRST terminal to which a reset signal generated as the first low level voltage during the vertical active period and as the high level voltage at the beginning of the vertical blank period is applied;
a fourth transistor pre-charging the Q node to the high level voltage in response to the start signal;
a fifth transistor discharging the Q node to the first low level voltage in response to the reset signal;
a sixth transistor to discharge the Q node to the first low level voltage in response to the output signal of the next stage; and
and a seventh transistor having a first electrode to which the first clock is applied, a second electrode connected to the output terminal, and a gate. According to claim 12,
The gate driving circuit,
a VST terminal to which a start signal for precharging the Q node is applied;
a VSS1 terminal to which a first low-potential power supply voltage generated as the first low-level voltage is applied during a vertical active period and a vertical blank period;
a VSS2 terminal to which a second low potential power supply voltage generated as the second low level voltage is applied during the vertical active period and the vertical blank period;
a VNEXT terminal to which an output signal of the next stage is applied;
a VRST terminal to which a reset signal generated as the first low level voltage during the vertical active period and as the high level voltage at the beginning of the vertical blank period is applied;
a fourth transistor pre-charging the Q node to the high level voltage in response to the start signal;
a fifth transistor discharging the Q node to the second low level voltage in response to the reset signal;
a sixth transistor to discharge the Q node to the second low level voltage in response to the output signal of the next stage;
a seventh transistor having a first electrode to which the first clock is applied, a second electrode connected to the output terminal, and a gate;
an eighth transistor to charge a second output terminal with a high level voltage of the first clock when the first clock is input while the Q node is charged; and
and a ninth transistor configured to discharge the second output terminal in response to the third clock. According to claim 12,
The gate driving circuit,
a VST terminal to which a start signal for precharging the Q node is applied;
a VDD terminal to which a high potential power supply voltage generated as the high level voltage during a vertical active period and as the second low level voltage during a vertical blank period is applied;
a VSS terminal to which a low potential power supply voltage generated as the first low level voltage during the vertical active period and as the second low level voltage during the vertical blank period is applied;
a VNEXT terminal to which an output signal of the next stage is applied;
a VBLK terminal to which a blank signal generated as the second low level voltage during the vertical active period and as the high level voltage during the vertical blank period is applied;
a fourth transistor pre-charging the Q node to the high level voltage in response to the start signal;
a fifth transistor discharging the Q node to the second low level voltage in response to the blank signal;
a sixth transistor to discharge the Q node to the first low level voltage in response to the output signal of the next stage; and
and a seventh transistor having a first electrode to which the first clock is applied, a second electrode connected to the output terminal, and a gate.

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