KR102056676B1 - Gate driver for display device - Google Patents

Abstract

The present invention relates to a gate driver for a display device that can be driven in a sequential scan method and an interlaced scan method. And a connection controller connected between a plurality of clock transmission lines and a plurality of stages to which clock pulses are applied, and controlling whether the clock transmission lines and the plurality of stages are connected according to a scan control signal from the outside. When the sequential scan control signals of the scan control signals are active, the connection controller connects all of the plurality of stages and the plurality of clock transmission lines to each other; When any interlaced scan control signal of the scan control signal is active, the connection controller connects the odd-numbered stages and the plurality of clock transmission lines among the plurality of stages, or the even-numbered stages and the plurality of clock transmission lines. Can be connected.

Description

Gate driver for display device {GATE DRIVER FOR DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driver, and more particularly, to a gate driver for a display device which can be driven in a sequential scanning method and an interlaced scanning method.

The conventional gate driver is driven by only one of the sequential scan method and the interlaced scan method.

In the sequential scanning method, since the gate driver must output scan pulses to all the gate lines every frame period, power consumption is high, while all the gate lines are driven every frame period, which is suitable for displaying a video.

On the other hand, since the interlaced scanning method alternately drives odd-numbered gate lines and even-numbered gate lines every frame, only gate lines corresponding to one-half of all gate lines are driven every frame period. While the interlaced scanning method has a lower quality than the progressive scanning method, the number of lines to be driven by the gate driver in each frame period is relatively small, thereby reducing power consumption. This interlaced scanning method is also suitable for the representation of still images.

By the way, in particular, the gate driver of the GIP (Gate In Panel) method is designed to be driven by only one of the sequential driving method and the interlaced scanning method. There was a problem that can not reduce the power consumption.

The present invention has been made to solve the above problems, and an object thereof is to provide a gate driver for a display device that can be driven in both a sequential driving method and an interlaced scanning method.

According to an aspect of the present invention, a gate driver for a display device includes: a plurality of stages configured to receive at least one of clock pulses of different phases and output scan pulses; And a connection controller connected between a plurality of clock transmission lines and a plurality of stages to which clock pulses are applied and controlling whether the clock transmission lines and the plurality of stages are connected according to a scan control signal from the outside. . When the sequential scan control signals of the scan control signals are active, the connection controller connects all of the plurality of stages and the plurality of clock transmission lines to each other; When any interlaced scan control signal of the scan control signal is active, the connection controller connects the odd-numbered stages and the plurality of clock transmission lines among the plurality of stages, or the even-numbered stages and the plurality of clock transmission lines. Can be connected.

When the first interlaced scanning control signal among the scan control signals is active, the connection controller may connect the odd-numbered stages and the plurality of clock transmission lines to each other. When the second interlaced scanning control signal among the scan control signals is active, the connection controller may connect even-numbered stages and a plurality of clock transmission lines to each other.

The connection control unit includes a plurality of connection control switching elements that are controlled according to the scan control signal and are connected between the plurality of clock transmission lines and the plurality of stages.

The plurality of connection control switching elements may include a plurality of sequential drive switching elements connected between a corresponding clock transmission line and a clock input terminal of each stage; A plurality of first interlacing switching elements connected between the clock transmission line and the clock input terminal of the odd-numbered stages; And a plurality of second interlacing switching elements connected between the clock transmission line and the clock input terminal of the even-numbered stage.

An nth stage of the plurality of stages may include: a first switching element connected between a first AC power line and a set node, the first AC power line being controlled according to a scan pulse from an n-second stage and transmitting a first AC voltage; a second switching element controlled according to the scan pulse from the n-th stage and connected between a second AC power line for transmitting a second AC voltage and the set node; A third switching element controlled according to the scan pulse from the n-2th stage and connected between a reset node and a discharge power supply line for transmitting a discharge voltage; A fourth switching element controlled according to the scan pulse from the n-th stage and connected between the reset node and the discharge power supply line; a fifth switching element controlled according to the scan pulse from the n + 1 th stage and connected between said discharge power supply line and said set node; a sixth switching element controlled according to the scan pulse from the n + 2th stage and connected between said discharge power supply line and said set node; A seventh switching element controlled according to the voltage of the reset node and connected between the set node and the discharge power supply line; An eighth switching element controlled according to the voltage of the set node and connected between the reset node and the discharge power supply line; A ninth switching element controlled according to the charging voltage from the charging power supply line and connected between the charging power supply line and the common node; A tenth switching element controlled according to the voltage of the common node and connected between the charging power supply line and the reset node; A pull-up switching element controlled according to the voltage of the set node and connected between the clock input terminal and the scan output terminal of the n-th stage; And a pull-down switching element controlled according to the voltage of the reset node and connected between the scan output terminal of the nth stage and the discharge power supply line.

When the sequential scan control signal is in an active state, both the first AC voltage and the second AC voltage are kept in an active state; When the first interlaced scanning control signal is in an active state, the first AC voltage is kept in an active state and the second AC voltage is kept in an inactive state; When only the second interlaced scanning control signal is in an active state, the second AC voltage is kept in an active state and the first AC voltage is kept in an inactive state.

According to an exemplary embodiment, a gate driver for a display device includes a first dummy stage configured to generate a first dummy pulse for setting a first stage operating among the odd-numbered stages included in the plurality of stages; And a second dummy stage for generating a second dummy pulse for setting a second stage operating first among even-numbered stages included in the plurality of stages.

The first dummy stage is set according to a first start pulse and a second start pulse to generate a clock pulse from any one clock transmission line as the first dummy pulse; The second dummy stage is set according to a third start pulse and a fourth start pulse to generate clock pulses from any other clock transmission line as the second dummy pulse.

When the sequential scan control signal is active, the first to fourth start pulses are sequentially supplied to the first and second dummy stages. When the first interlaced scanning control signal is active, the first and second start pulses remain active and the third and fourth start pulses remain inactive. When only the second interlaced scanning control signal is active, the third and fourth start pulses remain active and the first and second start pulses remain inactive.

The first dummy stage may include: a first switching device controlled according to the first start pulse and connected between a second AC power supply line transmitting a second AC voltage and a set node; A second switching element controlled according to the second start pulse and connected between the first AC power line for transmitting a first AC voltage and the set node; A third switching element controlled according to the first start pulse and connected between a reset node and a discharge power supply line for transmitting a discharge voltage; A fourth switching element controlled according to the second start pulse and connected between the reset node and the discharge power supply line; A fifth switching element controlled according to a second dummy pulse from the second dummy stage and connected between the discharge power supply line and the set node; A sixth switching element controlled according to the scan pulse from the first stage and connected between the discharge power supply line and the set node; A seventh switching element controlled according to the voltage of the reset node and connected between the set node and the discharge power supply line; An eighth switching element controlled according to the voltage of the set node and connected between the reset node and the discharge power supply line; A ninth switching element controlled according to the charging voltage from the charging power supply line and connected between the charging power supply line and the common node; A tenth switching element controlled according to the voltage of the common node and connected between the charging power supply line and the reset node; A pull-up switching element controlled according to the voltage of the set node and connected between the clock input terminal and the scan output terminal of the first dummy stage; And a pull-down switching element controlled according to the voltage of the reset node and connected between the scan output terminal of the first dummy stage and the discharge power supply line.

The second dummy stage may include: a first switching device controlled according to the third start pulse and connected between a second AC power supply line transmitting a second AC voltage and a set node; A second switching element controlled according to the fourth start pulse and connected between the first AC power line for transmitting a first AC voltage and the set node; A third switching element controlled according to the third start pulse and connected between a reset node and a discharge power supply line for transmitting a discharge voltage; A fourth switching element controlled according to the fourth start pulse and connected between the reset node and the discharge power supply line; A fifth switching element controlled according to the scan pulse from the first stage and connected between the discharge power supply line and the set node; A sixth switching element controlled according to the scan pulse from the second stage and connected between the discharge power supply line and the set node; A seventh switching element controlled according to the voltage of the reset node and connected between the set node and the discharge power supply line; An eighth switching element controlled according to the voltage of the set node and connected between the reset node and the discharge power supply line; A ninth switching element controlled according to the charging voltage from the charging power supply line and connected between the charging power supply line and the common node; A tenth switching element controlled according to the voltage of the common node and connected between the charging power supply line and the reset node; A pull-up switching element controlled according to the voltage of the set node and connected between the clock input terminal and the scan output terminal of the second dummy stage; And a pull-down switching element controlled according to the voltage of the reset node and connected between the scan output terminal of the second dummy stage and the discharge power supply line.

The gate driver for a display device according to the present invention has the following effects.

First, since the gate driver according to the present invention can be driven in both a sequential scanning method and an interlaced scanning method from the outside, the gate driver can be used in a display device that needs to change the scanning method according to image characteristics in order to reduce power consumption.

Second, since the gate driver implements both the sequential scanning method and the interlaced scanning method using only one set of clock pulses, the number of clock pulses and the number of clock transmission lines can be greatly reduced.

1 illustrates a gate driver for a display device according to an exemplary embodiment of the present invention.
2 is a view for explaining the operation of the access control unit when only the progressive scan control signal among the control signals included in the scan control signal is active and the remaining control signals are in an inactive state.
FIG. 3 is a view for explaining an operation of the connection controller when only the first interlaced scanning control signal is in an active state and the remaining control signals are in an inactive state among control signals included in the scan control signal; FIG.
FIG. 4 is a view for explaining an operation of the connection controller when only the second interlaced scanning control signal is in an active state and the remaining control signals are in an inactive state among control signals included in the scan control signal; FIG.
FIG. 5 is a diagram illustrating a connection relationship between stages included in the shift register of FIG. 1. FIG.
FIG. 6 is a diagram illustrating a configuration of an arbitrary n-th stage included in FIG. 1. FIG.
7 illustrates various signals supplied to a shift register driven according to a sequential scanning method;
8A to 8E are diagrams for explaining the operation of the n-th stage when the shift register is driven in the sequential scan method;
9 illustrates various signals supplied to a shift register driven in accordance with a first interlaced scanning method;
10 is a view for explaining the operation of the n-th stage when the shift register is driven in the first interlaced scanning method;
11 is a view showing various signals supplied to a shift register driven in accordance with a second interlaced scanning method;
12 is a view for explaining the operation of the n-th stage when the shift register is driven in the second interlaced scanning method;
FIG. 13 is a diagram for describing a connection relationship between first and second dummy stages and first and second stages.
14 is a view illustrating a configuration of a first dummy stage provided in FIG. 13.
FIG. 15 is a view illustrating a configuration of a second dummy stage provided in FIG. 13.
16 to 19 are diagrams for explaining an output method of a shift register according to a sequential scan method, a first interlaced scan method, a second interlaced scan method, and a combination thereof
20 illustrates waveforms of scan pulses according to a sequential scanning method and waveforms of scan pulses according to a first interlaced scanning method;

1 illustrates a gate driver for a display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a gate driver according to an exemplary embodiment of the present invention includes a shift register SR that sequentially outputs a plurality of scan pulses, the shift register SR, and clock transmission lines CTL1 to CTL4. Connection control unit (CCU) for controlling the connection between the ().

As shown in FIG. 1, the shift register SR receives at least one of clock pulses CLK1 to CLK4 having different phases, and scan pulses SPn-2 to SPn + 2. And a plurality of stages (..., STn-2 to STn + 2, ...) outputting ..). These stages (..., STn-2 to STn + 2, ...) sequentially output scan pulses (..., SPn-2 to SPn + 2, ...). That is, output pulses are sequentially output from the first stage to the last stage (hereinafter, referred to as m stage). Specifically, each stage (..., STn-2 to STn + 2, ...) includes a scan output terminal (OT), and each stage (..., STn-2 to STn + 2,... ..) sequentially outputs one scan pulse for one frame period through its scan output terminal (OT). In this case, as described above, all the stages sequentially output scan pulses, or only some of the stages may sequentially output the scan pulses according to the driving method of the gate driver.

Based on one frame period, the first stage of the first to mth stages outputs the scan pulse first, and the mth stage outputs the latest scan pulse. Here, in the term "i-th stage" to be described later, i does not mean a positional order in which the stage is placed, but rather means that the output order of the scan pulses output from the stage is the i-th. For example, the second (second) stage is a stage that outputs the scan pulse to the second of all stages in one frame period, and the output timing of the scan pulse from the second stage is the first (first). Later than that of the stage and faster than that of the third stage.

The scan pulses output from one stage are generated based on the clock pulses, and the clock pulses CLK1 to CLK4 are input to the clock input terminal IT of the stage through the connection control unit CPU.

Each stage (..., STn-2 to STn + 2, ...) uses a scan pulse to drive the gate line connected thereto. In addition, each stage (..., STn-2 to STn + 2, ...) operates at least one of a rear stage whose output order is later than its own and a front stage whose output order is faster than itself by using the scan pulse. To control. For example, the n-th stage STn generates the n-th scan pulse SPn, and the set terminal of the n + 1st stage STn + 1 and the n + 2th stage STn whose output order is later than that of the nth stage STn are generated. The reset terminal of the n-1th stage (STn-1) and the n-2nd stage (STn-2) of the set terminal of +2) and the nth scan pulse are outputted faster than themselves. Supply via set terminal. The n + 1st and n + 2nd stages (STn + 1, STn + 2) are set by this nth scan pulse SPn, while the n-1st and n-2nd stages (STn-1, STn) are set. -2) is reset.

However, the first stage ST1 is set according to the first dummy pulse DP1 from the separate first dummy stage DST1 of FIG. 13, and the second stage ST2 is the second dummy stage ST2. It is set in accordance with the second dummy pulse DP2 from DST2 in FIG. Here, the first dummy stage DST1 is set according to the first and second start pulses (Vst1 and Vst2 in FIG. 10) from the timing controller (not shown), and the second dummy stage DST2 is set to the third. And the fourth start pulse (Vst3, Vst4 in FIG. 10). Here, the first dummy stage DST1 is reset according to the first scan pulse SP1 from the first stage ST1, and the second dummy stage DST2 is the second from the second stage ST2. It is reset in accordance with the scan pulse SP2.

Depending on the configuration of the shift register SR, these first and second dummy stages DST1 and DST2 may or may not be connected to the gate line.

Although not shown, the shift register SR further includes a plurality of dummy stages (not shown; hereinafter, lower dummy stages) for outputting dummy pulses for resetting the mth stage and the m-1th stage. These lower dummy stages may be reset according to the first to fourth start pulses Vst1 to Vst4. Also, without these lower dummy stages, the first and second start pulses Vst1 and Vst2 may be supplied to the m−1 th stage, and the third and fourth start pulses Vst3 and Vst4 may be supplied to the m th stage. It may be. In this case, the m-th stage is reset by the first and second start pulses Vst1 and Vst2, and the m-th stage is reset by the third and fourth start pulses Vst3 and Vst4. .

The connection controller CCU is connected between a plurality of clock transmission lines CTL1 to CTL4 to which the above-described clock pulses CLK1 to CLK4 are applied and stages, and according to a clock control signal from an external source. Control the connection between the stages CTL1 to CTL4 and stages. This scan control signal can be generated, for example, from a timing controller.

In response to the sequential scan control signal PS, the connection controller CCU shifts the clock pulses necessary for such driving so that the shift register SR can drive the gate lines in a progressive scan manner. Supply to register SR. In addition, the connection control unit (CCU) responds to the first interlaced scanning control signal (I1S) and the second interlaced scanning control signal (I2S) so that the shift register (SR) gates the gate lines in an interlaced scan manner. In order to be driven, the clock pulses necessary for such driving are supplied to the shift register SR.

The sequential scanning method described above is a method in which all gate lines are sequentially driven every frame. For example, the shift register SR operating according to this sequential scanning method sequentially drives the entire gate lines in every frame period. To this end, when only the sequential scan control signal PS is active and the remaining signals are inactive among the control signals included in the above-described scan control signal, the connection controller CCU performs stages (..., STn−). 2 to STn + 2, ...) and clock transmission lines CTL1 to CTL4 are connected to each other.

The interlaced scanning method described above is a method in which odd-numbered gate lines and even-numbered gate lines are alternately driven on a frame basis. For example, the shift register SR operating according to this interlaced scanning method selects only odd-numbered gate lines in odd-numbered frame periods and drives them sequentially, whereas selects even-numbered gate lines in even-numbered frames. To drive them sequentially. Of course, the reverse is also possible. To this end, when only the first interlaced scanning control signal I1S among the control signals included in the scan control signal is active and the remaining signals are inactive, the connection control unit CCU performs odd-numbered stages among the entire stages. (..., STn-2, STn, STn + 2, ...) and the clock transmission lines CTL1 to CTL4 are connected to each other. In addition, when only the second interlaced scanning control signal I2S of the control signals included in the scan control signal is active and the remaining signals are inactive, the connection control unit CCU may perform even-numbered stages among the entire stages. ..., STn-1 to STn + 1, ... and the clock transmission lines CTL1 to CTL4 are connected to each other.

Meanwhile, when the shift register SR is driven by the interlaced scanning method, one frame period may be divided into a scan period in which scan pulses are output and a skip period in which the scan pulses are not output. Here, the scan period and the skip period correspond to each half frame period. In this case, the shift register SR operating according to the interlaced scanning method described above drives the corresponding gate lines in the scan period of every frame period. In other words, scan pulses are not generated in the skip period, and output buffers included in the data driver (not shown) are stopped in the skip period, thereby reducing power consumption. On the other hand, the output buffers of the data driver remain operational during the scan period.

The connection control unit (CCU) described above includes a plurality of connection control switching elements (P-Tr, I-Tr1, and I-Tr2), as shown in FIG. Each of these connection control switching elements P-Tr, I-Tr1, and I-Tr2 is controlled according to any one of the control signals included in the scan control signal, and the clock transmission lines CTL1 to CTL4 and the stages. (..., STn-2 to STn + 2, ...) are connected. Each connection control switching device (P-Tr, I-Tr1, I-Tr2) is turned on or off in accordance with any one of the control signals included in the scan control signal, and the corresponding clock transmission line The clock input terminals (IT) of the stage are connected to each other.

These connection control switching elements P-Tr, I-Tr1 and I-Tr2 are sequentially driven switching elements P-Tr, first interlaced switching elements I-Tr1 and second interlaced. It may be classified into driving switching elements I-Tr2.

Each sequential driving switching element P-Tr is controlled according to the sequential scan control signal PS, and is connected between the clock transmission line and the clock input terminal of the stage. The sequential driving switching element P-Tr is turned on or off according to the sequential driving control signal, and supplies the clock pulse from the clock transmission line to the clock input terminal of the stage at turn-on. For example, the sequential driving switching element P-Tr associated with the nth stage STn includes a third clock transmission line for transmitting a third clock pulse and a clock input terminal IT of the nth stage STn. Connected between.

Each first interlacing switching element I-Tr1 is controlled according to the first interlacing control signal I1S, and is connected between the corresponding clock transmission line and the clock input terminal of the odd-numbered stage. The first interlaced switching element I-Tr1 is turned on or off according to the first interlaced scanning control signal I1S, and at turn-on, the clock pulse from the clock transmission line of the odd interlaced stage is shifted. Supply to the clock input terminal. For example, the first interlacing switching element I-Tr1 associated with the nth stage STn may include a first clock transmission line for transmitting the first clock pulse and a clock input terminal of the nth stage STn. IT).

Each second interlaced driving switching element I-Tr2 is controlled according to the second interlaced scanning control signal I2S, and is connected between the corresponding clock transmission line and the clock input terminal of the even-numbered stage. The second interlaced switching element I-Tr2 is turned on or off according to the second interlaced scanning control signal I2S, and at turn-on, the clock pulses from the corresponding clock transmission line of the even-numbered stages are turned on. Supply to the clock input terminal. For example, the second interlacing switching element associated with the n + 1th stage is connected between the second clock transmission line for transmitting the second clock pulse and the clock input terminal IT of the nth stage STn. do.

As such, according to the configuration of the connection control switching elements, two connection control switching elements (one sequential driving switching element (P-Tr) and one interlacing switching switching element) are provided per stage. One of the two is a sequential driving switching element P-Tr, and the other is one of the first interlacing switching element I-Tr1 and the second interlacing switching element I-Tr2. . That is, when one stage is an odd stage, the other connection control switching element becomes the first interlaced driving switching element I-Tr1, while the other stage is an even stage when the other stage is an even stage. The other connection control switching element becomes the second interlacing switching element I-Tr2.

Hereinafter, the operation of the connection control unit (CCU) according to the scan control signal will be described in detail with reference to FIGS. 2 to 4.

FIG. 2 illustrates a case where only the progressive scan control signal PS is in an active state (for example, a high state) and the remaining control signals are in an inactive state (for example, a low state) among control signals included in the scan control signal. A diagram for explaining the operation of the connection control unit (CCU). On the other hand, in Figures 2 to 4, the switching elements (sequential drive switching device (P-Tr) or interlaced driving switching device) highlighted by a circular dotted line means a turned-on state, the other non-highlighted switching device These are turned off.

As shown in FIG. 2, when only the progressive scan control signal PS is active, only the switching elements supplied with the signal are selectively turned on, and the remaining first and second interlaced switching devices I-Tr1 are turned on. , I-Tr2) are all turned off. Accordingly, all stages including the n-2 th through n + 2 th stages (STn-2 through STn + 2) are connected to the corresponding clock transmission line without any omission. For example, as shown in FIG. 2, the n-second stage STn-2 is connected to the first clock transmission line CTL1 through the turn-on sequential driving switching element P-Tr. The n-th stage STn-1 is connected to the second clock transmission line CTL2 through the turn-on sequential driving switching element P-Tr, and the n-th stage STn is turned on sequential driving. Is connected to the third clock transmission line CTL3 through the switching device P-Tr, and the n + 1th stage STn + 1 is connected to the fourth clock transmission line P-Tr through the turned-on sequential driving switching device P-Tr. It is connected to the clock transmission line CTL4, and the n + 2th stage STn + 2 is connected to the first clock transmission line CTL1 through the turn-on sequential driving switching element P-Tr.

3 illustrates that only the first interlaced scanning control signal I1S among the control signals included in the scan control signal is in an active state (for example, a high state) and the remaining control signals are in an inactive state (for example, a low state). Is a diagram for explaining the operation of the connection control unit (CCU).

As shown in FIG. 3, when only the first interlaced scanning control signal I1S is active, only the first interlaced driving switching elements I-Tr1 supplied with the signal are selectively turned on, and the remaining sequential driving is performed. The switching elements P-Tr and the second interlacing switching elements I-Tr2 are both turned off. Accordingly, odd-numbered stages (..., STn-2, STn, ST + 2,... Of all stages including the n-2 th through n + 2 th stages (STn-2 through STn + 2). .) Only is connected to the corresponding clock transmission line. For example, as illustrated in FIG. 3, the n-second stage STn-2 is connected to the fourth clock transmission line CTL4 through the first interlaced switching element I-Tr1. The nth stage STn is connected to the first clock transmission line CTL1 through the first interlaced switching element I-Tr1, and the n + 2th stage STn + 2 is It is connected to the second clock transmission line CTL2 through the first interlaced switching element I-Tr1.

4 shows that only the second interlaced scanning control signal I2S among the control signals included in the scan control signal is in an active state (for example, a high state) and the remaining control signals are in an inactive state (for example, a low state). Is a diagram for explaining the operation of the connection control unit (CCU).

As shown in FIG. 4, when only the second interlaced scanning control signal I2S is in an active state, only the second interlaced driving switching elements I-Tr2 supplied with the signal are selectively turned on, and the remaining sequential driving is performed. The switching elements P-Tr and the first interlacing switching elements I-Tr1 are both turned off. Accordingly, even-numbered stages (..., STn-1, STn + 1, ...) of all stages, including the n-2 th to n + 2 th stages (STn-2 to STn + 2) Only is connected to the corresponding clock transmission line. For example, as shown in FIG. 4, the n-th stage STn-1 is connected to the first clock transmission line CTL1 through the turned-on second interlaced switching element I-Tr2. The n + 1th stage STn + 1 is connected to the second clock transmission line CTL2 through the turned-on second interlaced switching element I-Tr2.

Here, referring to FIG. 5, a connection relationship between stages provided in the shift register SR of FIG. 1 will be described.

FIG. 5 is a diagram illustrating a connection relationship between stages included in the shift register SR of FIG. 1.

As shown in Fig. 5, the nth stage STn is first set according to the n-2nd scan pulse SPn-2 from the n-2nd stage STn-2, and then n-1th. The second set is made in accordance with the n-1 th scan pulse SPn-1 from the stage STn-1. The nth stage STn is first reset in accordance with the n + 1th scan pulse SPn + 1 from the n + 1st stage STn + 1, and then the n + 2nd stage STn +. It is reset second by the n + 2th scan pulse SPn + 2 from 2).

The nth scan pulse SPn output from the nth stage STn is supplied to the nth gate line to drive the nth gate line, and is supplied to the n-2nd stage STn-2. The n-th stage STn-2 is reset secondarily, and the n-th stage STn-1 is supplied to the n-th stage STn-1 to reset the n-th stage STn-1 first. Then, the nth scan pulse SPn output from the nth stage STn is supplied to the n + 1st stage STn + 1 to set this n + 1st stage STn + 1 secondly. In addition, it is supplied to the n + 2th stage STn + 2, and this n + 2th stage STn + 2 is set first.

Meanwhile, the remaining stages are also set or reset by stages located at the front end and the rear end from themselves in the same manner as the n-th stage STn described above, and also drive the corresponding gate line connected to itself, Control the operation of stages located at the front and rear ends.

The connection relationship between the stages shown in FIG. 5 is one example. The shift register SR according to the present invention may have various structures in addition to the structure shown in FIG. 5.

Each of these stages may have the following configuration.

FIG. 6 is a diagram illustrating a configuration of an arbitrary n-th stage STn included in FIG. 1.

As shown in FIG. 6, the n-th stage STn includes first to tenth switching elements, a pull-up switching element, and a pull-down switching element.

The first switching device Tr1 provided in the n-th stage STn is controlled according to the scan pulse SPn-2 from the n-th stage STn-2, and transmits the first AC voltage Vac1. Is connected between the first AC power line ACL1 and the set node Q. The first switching device Tr1 is turned on or turned off in accordance with the scan pulse SPn-2 from the n-2th stage STn-2, and turns on the first AC voltage Vac1 at turn-on. Supply to the set node (Q).

The second switching device Tr2 provided in the n-th stage STn is controlled according to the scan pulse SPn-1 from the n-th stage STn-1, and transmits the second AC voltage Vac2. Is connected between the second AC power line ACL2 and the set node Q. The second switching device Tr2 is turned on or turned off in accordance with the scan pulse SPn-1 from the n-1 th stage STn-1, and turns on the second AC voltage Vac2 at turn-on. Supply to the set node (Q).

The third switching element Tr3 provided in the n-th stage STn is controlled according to the scan pulse SPn-2 from the n-th stage STn-2, and is used for the reset node QB and the discharge. It is connected between the discharge power supply line (VSL) for transmitting the voltage (VSS). The third switching device Tr3 is turned on or turned off in accordance with the scan pulse SPn-2 from the n-2th stage STn-2, and is turned to the reset node QB at turn-on. Supply dedicated voltage.

The fourth switching element Tr4 of the nth stage STn is controlled according to the scan pulse SPn-1 from the n-1th stage STn-1, and is used for the reset node QB and the discharge. It is connected between the power line VSL. The fourth switching device Tr4 is turned on or turned off in accordance with the scan pulse SPn-1 from the n-1 th stage STn-1, and is turned to the reset node QB at turn-on. Supply dedicated voltage (VSS).

The fifth switching element Tr5 provided in the nth stage STn is controlled according to the scan pulse SPn + 1 from the n + 1th stage STn + 1, and is set with the discharge power supply line VSL. It is connected between the nodes Q. The fifth switching element Tr5 is turned on or off in accordance with the scan pulse SPn + 1 from the n + 1th stage STn + 1, and discharges to the set node Q at turn-on. Supply voltage VSS.

The sixth switching element Tr6 provided in the nth stage STn is controlled according to the scan pulse SPn + 2 from the n + 2th stage STn + 2 and is set with the discharge power supply line VSL. It is connected between the nodes Q. The sixth switching element Tr6 is turned on or off in accordance with the scan pulse SPn + 2 from the n + 2th stage STn + 2 and discharges to the set node Q at turn-on. Supply voltage VSS.

The seventh switching element Tr7 provided in the nth stage STn is controlled according to the voltage of the reset node QB and is connected between the set node Q and the discharge power supply line VSL. The seventh switching element Tr7 is turned on or turned off according to the voltage of the reset node QB, and supplies the discharge voltage VSS to the set node Q at turn-on.

The eighth switching element Tr8 provided in the n-th stage STn is controlled according to the voltage of the set node Q and is connected between the reset node QB and the discharge power supply line VSL. The eighth switching element Tr8 is turned on or off according to the voltage of the set node Q, and supplies the discharge voltage VSS to the reset node QB at turn-on.

The ninth switching element Tr9 provided in the n-th stage STn is controlled according to the charging voltage VDD from the charging power supply line VDL, and the charging power supply line VDL and the common node CN. ) Is connected. The ninth switching element Tr9 is turned on according to the charging voltage VDD to supply the charging voltage VDD to the common node CN.

The tenth switching element Tr10 of the n-th stage STn is controlled according to the voltage of the common node CN and is connected between the charging power supply line VDL and the reset node QB. The tenth switching element Tr10 is turned on or off according to the voltage of the common node CN, and supplies the charging power supply voltage VDD to the reset node QB at turn-on.

The pull-up switching device Trpu provided in the n-th stage STn is controlled according to the voltage of the set node Q, and is connected between the clock input terminal IT and the scan output terminal OTn of the n-th stage STn. Is connected to. The pull-up switching device Trpu is turned on or off depending on the voltage of the set node Q, and supplies a clock pulse CLK to the scan output terminal OTn of the nth stage STn at turn-on. do. In other words, the clock pulse CLK is provided to the clock input terminal IT of the nth stage STn through the corresponding clock transmission line and the connection controller CCU.

The pull-down switching device Trpd provided in the nth stage STn is controlled according to the voltage of the reset node QB, and the scan output terminal OTn and the discharge power supply line VSL of the nth stage STn are controlled. ) Is connected between. The pull-down switching device Trpd is turned on or off according to the voltage of the reset node QB, and the discharge voltage VSS is applied to the scan output terminal OTn of the nth stage STn at turn-on. To supply.

The operation of the n-th stage STn configured as described above will be described in detail as follows.

7 is a diagram illustrating various signals supplied to a shift register SR driven according to a sequential scanning method.

The entire stages (..., STn-2 to STn + 2, ...) including the first and second dummy stages include the charging voltage (VDD of FIG. 6), the discharge voltage (VSS of FIG. 6), One of the first AC voltage Vac1, the second AC voltage Vac2, and the first to fourth clock pulses CLK1 to CLK4 circulating with a sequential phase difference is applied thereto. Meanwhile, the first stage receives the first and second start pulses Vst1 and Vst2 in addition to the above-listed signals, and the second stage receives the third and fourth start pulses Vst3, in addition to the above-listed signals. Received more Vst4).

The charging voltage VDD is used to charge the nodes of each stage (first dummy stage, second dummy stage, ..., STn-2 to STn + 2, ...), and the discharge voltage VSS. Is used to discharge the nodes and scan output terminals OT of each stage (first dummy stage, second dummy stage, ..., STn-2 to STn + 2, ...).

Both the charge voltage VDD and the discharge voltage VSS are direct current voltages, whereas the charge voltage VDD exhibits a positive polarity, while the discharge voltage VSS exhibits a negative polarity. Meanwhile, the discharge voltage VSS may be a ground voltage.

The first and second alternating voltages Vac1 and Vac2 charge the set nodes Q of each stage (the first dummy stage, the second dummy stage, ..., STn-2 to STn + 2, ...). As alternating current signals for controlling over-discharge, these alternating current signals may have a level of the above-mentioned charging voltage VDD in a high state, and may have a level of the above-mentioned discharge voltage VSS in a low state. On the other hand, both of the first AC voltage Vac1 and the second AC voltage Vac2 have a high state during the period in which the shift register SR is driven in the progressive scan method. For example, the first and second AC voltages Vac1 and Vac2 may be maintained at constant voltages having the same level as the charging voltage VDD during the period of driving in the progressive scanning method.

The first to fourth clock pulses CLK1 to CLK4 are scan pulses (first dummy pulses) of each stage (first dummy stage, second dummy stage, ..., STn-2 to STn + 2, ...). , Signals used to generate the second dummy pulse, ..., SPn-2 to SPn + 2, each stage being supplied with one of these first to fourth clock pulses CLK1 to CLK4 for scanning Generate and output pulses.

In the present invention, an example of using four types of clock pulses having different phase differences is shown, but any number of these clock pulses can be used.

As shown in FIG. 7, the first to fourth clock pulses CLK1 to CLK4 are sequentially outputted with phase differences from each other. At this time, although not shown in the drawing, clock pulses output in adjacent periods may be output so that their pulse widths overlap.

In addition, the first to fourth clock pulses CLK1 to CLK4 are sequentially output and cyclically output. That is, the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output, and then the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially and repeatedly output. Therefore, the first clock pulse CLK1 in the current cycle is output in a period corresponding to the fourth clock pulse CLK4 of the previous cycle and the second clock pulse CLK2 in the current cycle.

As illustrated in FIG. 7, the first to fourth start pulses Vst1 to Vst4 are output before the first to fourth clock pulses CLK1 to CLK4. The first to fourth start pulses Vst1 to Vst4 may have a level of the above-described charging voltage VDD in a high state and may have a level of the above-mentioned discharge voltage VSS in a low state.

The first to fourth clock pulses CLK1 to CLK4 are output several times during one frame period, but the first to fourth start pulses Vst1 to Vst4 are output only once during one frame period. In other words, each clock pulse CLK1 to CLK4 periodically exhibits several active states (high states) during one frame period, while the first to fourth start pulses Vst1 to Vst4 have only one during one frame period. Indicates the active state of the burn.

7, and 8A to 8E, the operation of the n-th stage (STn) according to the sequential scanning method will be described in detail as follows.

8A to 8E are diagrams for explaining the operation of the n-th stage STn when the shift register SR is driven in the sequential scanning method.

1) first period ( T1 )

The first period T1 is a period corresponding to the first set period (or pre-set period) of the nth stage STn. During this period (T1), as shown in Figs. 7 and 8A, the high scan pulse SPn-2 output from the n-th stage STn-2 is transferred to the n-th stage STn. Is entered.

In other words, the n-2 th scan pulse SPn-2 is supplied to the gate electrode of the first switching element Tr1 and the gate electrode of the third switching element Tr3 provided in the n th stage STn. Then, the first switching device Tr1 and the third switching device Tr3 are turned on, and the first AC voltage Vac1 in the high state is set through the turned-on first switching device Tr1. Is applied to (Q). Accordingly, the set node Q is charged, and the pull-up switching device Trpu and the eighth switching device Tr8, to which the gate electrode is connected, are turned on.

Here, the discharge voltage VSS is supplied to the reset node QB through the turned-on third switching device Tr3 and the eighth switching device Tr8, respectively, to discharge the reset node QB.

As a result, the seventh switching element Tr7 and the pull-down switching element Trpd having the gate electrode connected to the discharged reset node QB are turned off.

On the other hand, the charging voltage VDD, which is always kept positive, is applied to the gate electrode of the ninth switching element Tr9. As a result, the ninth switching element Tr9 is always turned on. The charging voltage VDD is applied to the common node CN, that is, the gate electrode of the tenth switching element Tr10 through the ninth switching element Tr9 in the turn-on state. Therefore, like the ninth switching element Tr9, the tenth switching element Tr10 is always turned on. Accordingly, the charging node VDD output through the turned-on tenth switching element Tr10 is also supplied to the reset node QB. That is, the reset node QB is supplied with the positive charging voltage VDD and the negative discharge voltage VSS. However, the size of the third switching element Tr3 and the eighth switching element Tr8 for supplying the discharge voltage VSS is set larger than that of the tenth switching element Tr10 for supplying the charging voltage VDD. The voltage of the reset node QB is maintained at the discharge voltage VSS. Thus, the seventh switching element Tr7 and the pull-down switching element Trpd are turned off.

As a result, in the first period T1, the nth stage STn charges its set node Q, while discharging its reset node QB. That is, in the period T1, the nth stage STn is set (pre-set). That is, as shown in the first period T1 of FIG. 7, the voltage V_Qn of the set node Q is high while the voltage of the voltage V_Qbn of the reset node QB is low. Able to know.

2) second period ( T2 )

The second period T2 is a period corresponding to the second set period of the nth stage STn. During this period (T2), as shown in Figs. 7 and 8B, the high scan pulse SPn-1 output from the n-1th stage STn-1 is transferred to the nth stage STn. Is entered.

In other words, the n-1 th scan pulse SPn-1 is supplied to the gate electrode of the second switching element Tr2 and the gate electrode of the fourth switching element Tr4 provided in the n th stage STn. Then, the second switching device Tr2 and the fourth switching device Tr4 are turned on, and the second AC voltage Vac2 in the high state is set through the turned-on second switching device Tr2. Is applied to (Q). Accordingly, the set node Q is charged, and the pull-up switching device Trpu and the eighth switching device Tr8, to which the gate electrode is connected, are turned on.

Here, the discharge voltage VSS is supplied to the reset node QB through the turned-on fourth switching element Tr4 and the eighth switching element Tr8, respectively, to discharge the reset node QB.

As a result, the seventh switching element Tr7 and the pull-down switching element Trpd having the gate electrode connected to the discharged reset node QB are turned off.

On the other hand, the charging voltage VDD, which is always kept positive, is applied to the gate electrode of the ninth switching element Tr9. As a result, the ninth switching element Tr9 is always turned on. The charging voltage VDD is applied to the common node CN, that is, the gate electrode of the tenth switching element Tr10 through the ninth switching element Tr9 in the turn-on state. Therefore, like the ninth switching element Tr9, the tenth switching element Tr10 is always turned on. Accordingly, the charging node VDD output through the turned-on tenth switching element Tr10 is also supplied to the reset node QB. That is, the reset node QB is supplied with the positive charging voltage VDD and the negative discharge voltage VSS. However, the size of the fourth switching element Tr4 and the eighth switching element Tr8 that supplies the discharge voltage VSS is set larger than that of the tenth switching element Tr10 that supplies the charging voltage VDD. The voltage of the reset node QB is maintained at the discharge voltage VSS. Thus, the seventh switching element Tr7 and the pull-down switching element Trpd are turned off.

As a result, in the second period T2, the n-th stage STn charges its set node Q once again, while discharging its reset node QB once again. That is, in the period T2, the nth stage STn is kept in the set state. That is, as shown in the second period T2 of FIG. 7, the voltage V_Qn of the set node Q is high while the voltage of the voltage V_Qbn of the reset node QB is low. Able to know.

3) the third period ( T3 )

The third period T3 is a period corresponding to the output period of the nth stage STn. In this third period T3, as shown in Figs. 7 and 8C, the third clock pulse CLK3 in the high state is input to the nth stage STn.

Here, as the set node Q of the nth stage STn is kept in the charged state by the charging voltage VDD applied during the first and second periods T1 and T2, the nth stage STn The pull-up switching device Trpu maintains the turn-on state. As the third clock pulse CLK3 is applied to the drain electrode of the turned-up switching device Trpu during the third period T3, the pull-up switching device Trpu outputs the scan pulse SPn. .

Here, the third clock pulse CLK3 in the high state output through the pull-up switching device Trpu is the nth scan pulse SPn. The nth scan pulse SPn is applied to the nth gate line to drive the nth gate line, and also as the gate electrode of the sixth switching element Tr6 provided in the n-2nd stage STn-2. Supplied to reset the n-2th stage STn-2 to the secondary, and are supplied to the gate electrode of the fifth switching element Tr5 provided in the n-1th stage STn-1 to supply the n-th stage STn-2. The first stage STn-1 is first reset and supplied to the gate electrode of the second switching element Tr2 provided in the n + 1st stage STn + 1 to supply the n + 1st stage STn. +1) is set to secondary, and is supplied to the gate electrode of the first switching element Tr1 provided in the n + 2th stage STn + 2 to make the n + 2th stage STn + 2 the primary. Set it.

At this time, since the first and second switching devices Tr1 and Tr2 are turned off in this period T3 and the set node Q is kept in a floating state, the first state of the high state applied in the period T3 is maintained. The voltage of the set node Q is bootstrapping due to the coupling phenomenon according to the three clock pulses CLK3. Accordingly, the scan pulse SPn is stably output. That is, as shown in the third period T3 of FIG. 7, it can be seen that the voltage V_Qn of the set node Q has increased significantly.

4) the fourth period ( T4 )

Next, the operation during the fourth period T4 will be described.

The fourth period T4 corresponds to the first reset period of the nth stage STn. In this fourth period T4, as shown in Figs. 7 and 8D, the n + 1th scan pulse SPn + 1 in the high state generated from the n + 1st stage STn + 1 is nth. It is input to stage STn, and this nth stage STn is reset first. This reset operation is described in more detail as follows.

That is, the n + 1 th scan pulse SPn + 1 is supplied to the gate electrode of the fifth switching element Tr5 provided in the n th stage STn. Then, the fifth switching device Tr2 is turned on, and the discharge voltage VSS is supplied to the set node Q through the turned-on fifth switching device Tr5. Therefore, the set node Q is discharged, and the eighth switching element Tr8 and the pull-up switching element Trpu, whose gate electrodes are connected to the discharged set node Q, are turned off. On the other hand, since the n-2 th scan pulse SPn-2 and the n-1 th scan pulse SPn-1 are in a low state during this period T4, the third and fourth switching elements Tr3, Tr4) is also turned off.

Here, as described above, as the third, fourth, and eighth switching devices Tr3, Tr4, and Tr8 are all turned off, the reset node QB turns on the tenth switching device Tr10 that is turned on. The seventh switching element Tr7 and the pull-down switching element Trpd, which are charged with the charging voltage VDD of the high state supplied through the gate electrode, are turned on. Is on.

Here, the discharge voltage VSS is supplied to the set node Q through the turned-on seventh switching element Tr7, whereby the discharge state of the set node Q is more stably maintained.

As the pull-down switching device Trpd of the n-th stage STn is turned on during the fourth period T4, the discharge voltage VSS is output. That is, the turned-down pull-down switching device Trpd outputs the discharge voltage VSS through the scan output terminal OT. The discharge voltage VSS output through the pull-down switching element Trpd is a gate line of the sixth switching element Tr6 provided in the n-2th stage STn-2, and the n-1th stage. Gate electrode of the fifth switching element Tr5 provided in (STn-1), gate electrode of the second switching element Tr2 provided in the n + 1st stage STn + 1, and n + 2nd stage STn It is supplied to the gate electrode of the first switching element Tr1 provided at +2).

As a result, during the fourth period T4, the nth stage STn discharges its set node Q, while charging its reset node QB. That is, in the period T4, the nth stage STn is reset first. That is, as shown in the fourth period T4 of FIG. 7, the voltage V_Qn of the set node Q is low while the voltage of the voltage V_Qbn of the reset node QB is high. Able to know.

5) fifth period ( T5 )

Next, the operation during the fifth period T5 will be described.

The fifth period T5 corresponds to the secondary reset period of the nth stage STn. In this fifth period T5, as shown in FIGS. 7 and 8E, the n + 2th scan pulse SPn + 2 in the high state generated from the n + 2th stage STn + 2 is nth. Input to the stage STn, this nth stage STn is reset secondarily. This reset operation is described in more detail as follows.

That is, the n + 2th scan pulse SPn + 2 is supplied to the gate electrode of the sixth switching element Tr6 provided in the nth stage STn. Then, the sixth switching device Tr6 is turned on, and the discharge voltage VSS is supplied to the set node Q through the turned-on sixth switching device Tr6. Therefore, the set node Q is discharged, and the eighth switching element Tr8 and the pull-up switching element Trpu, whose gate electrodes are connected to the discharged set node Q, are turned off. On the other hand, since the n-2 th scan pulse SPn-2 and the n-1 th scan pulse SPn-1 are in the low state during this period T5, the third and fourth switching elements Tr3, Tr4) is also turned off.

Since the operation of the n-th stage STn in the fifth period T5 is substantially the same as the operation in the fourth period T4 described above, the remaining description refers to the operation in the fourth period T4.

In this way the remaining stages operate. That is, when the sequential scanning method is applied, all stages sequentially output scan pulses. This is because all four start pulses Vst1 to Vst4 are output as shown in FIG. 7 so that both the first and second dummy stages DST1 and DST2 of FIG. 13 operate. This will be described in detail later with reference to FIG. 13.

9 is a diagram illustrating various signals supplied to the shift register SR driven according to the first interlaced scanning method.

In the period in which the shift register SR is operated by the first interlaced scanning method, as shown in FIG. 9, the third and fourth start pulses Vst3 and Vst4 are not output. That is, the third and fourth start pulses Vst3 and Vst4 are kept low.

In addition, during the period in which the shift register SR is operated by the first interlaced scanning method, the first AC voltage Vac1 is kept high while the second AC voltage Vac2 is kept low. That is, the second AC voltage Vac2 is inverted by 180 degrees with respect to the first AC voltage Vac1.

On the other hand, the charging voltage VDD, the discharge voltage VSS, and the first to fourth clock pulses CLK1 to CLK4 in the period of the first interlaced scanning method are the same as those of the sequential driving method described above. As they are the same, a description of these is referred to the foregoing description.

9 and 10, the operation of the n-th stage STn according to the first interlaced scanning method will be described in detail as follows.

10 is a view for explaining the operation of the n-th stage STn when the shift register SR is driven in the first interlaced scanning method.

1) first period ( T1 )

The first period T1 is a period corresponding to the set period of the nth stage STn. During this period (T1), as shown in Figs. 9 and 10, the scan pulse SPn-2 in the high state output from the n-2th stage STn-2 is transferred to the nth stage STn. Is entered.

In other words, the n-2 th scan pulse SPn-2 is supplied to the gate electrode of the first switching element Tr1 and the gate electrode of the third switching element Tr3 provided in the n th stage STn. Then, the first switching device Tr1 and the third switching device Tr3 are turned on, and the first AC voltage Vac1 in the high state is set through the turned-on first switching device Tr1. Is applied to (Q). Accordingly, the set node Q is charged, and the pull-up switching device Trpu and the eighth switching device Tr8, to which the gate electrode is connected, are turned on.

Here, the discharge voltage VSS is supplied to the reset node QB through the turned-on third switching device Tr3 and the eighth switching device Tr8, respectively, to discharge the reset node QB.

As a result, the seventh switching element Tr7 and the pull-down switching element Trpd having the gate electrode connected to the discharged reset node QB are turned off.

On the other hand, the charging voltage VDD, which is always kept positive, is applied to the gate electrode of the ninth switching element Tr9. As a result, the ninth switching element Tr9 is always turned on. The charging voltage VDD is applied to the common node CN, that is, the gate electrode of the tenth switching element Tr10 through the ninth switching element Tr9 in the turn-on state. Therefore, like the ninth switching element Tr9, the tenth switching element Tr10 is always turned on. Accordingly, the charging node VDD output through the turned-on tenth switching element Tr10 is also supplied to the reset node QB. That is, the reset node QB is supplied with the positive charging voltage VDD and the negative discharge voltage VSS. However, the size of the third switching element Tr3 and the eighth switching element Tr8 for supplying the discharge voltage VSS is set larger than that of the tenth switching element Tr10 for supplying the charging voltage VDD. The voltage of the reset node QB is maintained at the discharge voltage VSS. Thus, the seventh switching element Tr7 and the pull-down switching element Trpd are turned off.

As a result, in the first period T1, the nth stage STn charges its set node Q, while discharging its reset node QB. That is, the nth stage STn is set in the period T1. That is, as shown in the first period T1 of FIG. 8, the voltage V_Qn of the set node Q is high while the voltage of the voltage V_Qbn of the reset node QB is low. Able to know.

2) second period ( T2 )

The second period T2 is a period corresponding to the output period of the nth stage STn. In this second period T2, as shown in Figs. 9 and 10, the first clock pulse CLK1 in the high state is input to the n-th stage STn.

Here, the pull-up switching device of the n-th stage STn is maintained as the set node Q of the n-th stage STn is kept in the charged state by the charging voltage VDD applied during the first period T1. Trpu remains turned on. As the first clock pulse CLK1 is applied to the drain electrode of the turned-up switching device Trpu during the second period T2, the pull-up switching device Trpu outputs the scan pulse SPn. .

Here, the first clock pulse CLK1 in the high state output through the pull-up switching device Trpu is the nth scan pulse SPn. The nth scan pulse SPn is applied to the nth gate line to drive the nth gate line, and also as the gate electrode of the sixth switching element Tr6 provided in the n-2nd stage STn-2. Supplied to reset the n-th stage STn-2 and supplied to the gate electrode of the fifth switching element Tr5 provided in the n-th stage STn-1 to supply the n-1th stage. The stage STn-1 is reset and supplied to the gate electrode of the second switching element Tr2 provided in the n + 1th stage STn + 1, and the n + 2th stage STn + 2 Is supplied to the gate electrode of the first switching element Tr1 provided in the above to set the n + 2th stage STn + 2. When the n th scan pulse SPn described above is supplied to the n + 1 th stage STn + 1, the second switching element Tr2 in the n + 1 th stage STn + 1 is turned on. In this case, the turned-on second switching device Tr2 supplies the second AC voltage Vac2 in the low state to the n + 1th stage STn + 1. Therefore, the n + 1th stage STn + 1 is not set in this second period T2. That is, only the odd stages are set during the period driven by this first interlaced scanning method, and the remaining even stages are not set.

At this time, since the first and second switching elements Tr1 and Tr2 are turned off in this period T2 and the set node Q is kept in a floating state, the first state of the high state applied in the period T3 is maintained. The voltage of the set node Q is bootstrapping due to the coupling phenomenon according to the three clock pulses CLK3. Accordingly, the scan pulse SPn is stably output. That is, as shown in the second period T2 of FIG. 8, it can be seen that the voltage V_Qn of the set node Q has increased significantly.

3) the third period ( T3 )

Next, the operation during the third period T3 will be described.

The third period T3 corresponds to the reset period of the nth stage STn. In this third period T3, as shown in Figs. 9 and 10, the n + 2th scan pulse SPn + 2 in the high state generated from the n + 2th stage STn + 2 is nth. It is input to stage STn, and this nth stage STn is reset. This reset operation is described in more detail as follows.

That is, the n + 2th scan pulse SPn + 2 is supplied to the gate electrode of the sixth switching element Tr6 provided in the nth stage STn. Then, the sixth switching device Tr6 is turned on, and the discharge voltage VSS is supplied to the set node Q through the turned-on sixth switching device Tr6. Therefore, the set node Q is discharged, and the eighth switching element Tr8 and the pull-up switching element Trpu, whose gate electrodes are connected to the discharged set node Q, are turned off. On the other hand, since the n-2 th scan pulse SPn-2 and the n-1 th scan pulse SPn-1 are in the low state during this period T5, the third and fourth switching elements Tr3, Tr4) is also turned off.

Since the operation of the nth stage STn in the third period T3 is substantially the same as the operation in the fourth period T4 described above, the rest of the description refers to the operation in the fourth period T4.

In this way the remaining stages operate. That is, when the first interlaced scanning method is applied, only odd-numbered stages (..., STn-2, STn, STn + 2, ...) output scan pulses, and even-numbered stages (..., STn-1, STn + 1, ...) do not output the scan pulse. As shown in FIG. 9, only the first and second start pulses Vst1 and Vst2 of the four start pulses Vst1 to Vst4 are output so that the first dummy stage (DST1 of FIG. 13) of the two dummy stages is output. Because only works. This will be described in detail later with reference to FIG. 13.

FIG. 11 is a diagram illustrating various signals supplied to a shift register SR driven according to a second interlaced scanning method.

In the period in which the shift register SR is operated by the second interlaced scanning method, as shown in FIG. 11, the first and second start pulses Vst1 and Vst2 are not output. That is, the first and second start pulses Vst1 and Vst2 are kept low.

In addition, while the shift register SR is operated by the second interlaced scanning method, the first AC voltage Vac1 is kept high while the second AC voltage Vac2 is kept low. That is, the second AC voltage Vac2 is inverted by 180 degrees with respect to the first AC voltage Vac1.

On the other hand, the charging voltage VDD, the discharge voltage VSS, and the first to fourth clock pulses CLK1 to CLK4 in the period of the second interlaced scanning method are the same as those of the sequential driving method described above. As they are the same, a description of these is referred to the foregoing description.

11 and 12, the operation of the n-th stage STn according to the second interlaced scanning method will be described in detail as follows.

12 is a view for explaining the operation of the n-th stage STn when the shift register SR is driven in the second interlaced scanning method.

1) first period ( T1 )

During this first period T1, as shown in Figs. 11 and 12, the scan pulse SPn-2 in the low state output from the n-second stage STn-2 is the n-th stage STn. ) Is entered.

That is, the n-2 th scan pulse SPn-2 in this low state is supplied to the gate electrode of the first switching element Tr1 and the gate electrode of the third switching element Tr3 provided in the n th stage STn. do. Then, the first switching device Tr1 and the third switching device Tr3 are turned off.

2) second period ( T2 )

During the second period T2, as shown in FIGS. 11 and 12, the scan pulse SPn-1 having the high state output from the n−1th stage STn−1 is nth stage STn. Is entered.

In other words, the n-1 th scan pulse SPn-1 is supplied to the gate electrode of the second switching element Tr2 and the gate electrode of the fourth switching element Tr4 provided in the n th stage STn. Then, the second switching device Tr2 and the fourth switching device Tr4 are turned on, and the second AC voltage Vac2 in the low state is set through the turned-on second switching device Tr2. Is applied to (Q). As a result, the set node Q is discharged, and the pull-up switching device Trpu and the eighth switching device Tr8 having the gate electrode connected to the discharged set node Q are turned off.

Here, the discharge voltage VSS is supplied to the reset node QB through the turned-on fourth switching device Tr4, and the reset node QB is discharged.

As a result, the seventh switching element Tr7 and the pull-down switching element Trpd having the gate electrode connected to the discharged reset node QB are turned off.

3) the third period ( T3 )

Next, the operation during the third period T3 will be described.

In this third period T3, as illustrated in FIGS. 11 and 12, the n + 2th scan pulse SPn + 2 in the low state generated from the n + 2th stage STn + 2 is nth. It is input to the stage STn. That is, the n + 2th scan pulse SPn + 2 in the low state is supplied to the gate electrode of the sixth switching element Tr6 provided in the nth stage STn. Then, this sixth switching element Tr6 is turned off.

On the other hand, during this period T3, the n-1 th scan pulse SPn-1 transitions to the low state, and the fourth switching element Tr3 is turned off, thereby resetting the n th stage STn. The voltage of the node QB is charged by the charging voltage VDD supplied through the turned-on tenth switching element Tr3.

In this way the remaining stages operate. That is, when the second interlaced scanning method is applied, only even-numbered stages (..., STn-1, STn + 1, ...) output scan pulses, and odd-numbered stages (..., STn- 2, STn, STn + 2, ...) do not output the scan pulse. As shown in FIG. 11, only the third and fourth start pulses Vst3 and Vst4 of the four start pulses Vst1 to Vst4 are output so that the second dummy stage (DST2 of FIG. 13) of the two dummy stages is output. Because only works. This will be described in detail later with reference to FIG. 13.

FIG. 13 is a diagram for describing a connection relationship between first and second dummy stages and first and second stages.

The shift register SR according to the present invention further includes first and second dummy stages DST1 and DST2, as shown in FIG. 13, where the first dummy stage DST1 is a first stage ( The first dummy pulse DP1 is set to first set the ST1), and the second dummy stage DST2 sets the first stage ST1 to the second stage and sets the second stage ST2 to the first stage. A second dummy pulse DP2 for setting with the difference is generated. That is, the first dummy pulse DP1 output through the dummy output terminal OTd1 of the first dummy stage DST1 is supplied to the gate electrode of the first switching element Tr1 provided in the first stage ST1. The second dummy pulse DP2 output through the dummy output terminal OTd2 of the second dummy stage DST2 is connected to the gate electrode of the second switching element Tr2 provided in the first stage ST1. The gate electrode of the first switching device Tr1 provided in the first stage ST2 is supplied.

Here, the first dummy stage DST1 is set according to the first and second start pulses Vst1 and Vst2, and then the corresponding clock pulse (for example, the third clock pulse CLK3) supplied to the first dummy stage DST1 is set. It outputs as 1st dummy pulse DP1. Similarly, the second dummy stage DST2 is set in response to the third and fourth start pulses Vst3 and Vst4, and then the corresponding clock pulse supplied to it (for example, the fourth clock pulse CLK4). ) Is output as the second dummy pulse DP2. Therefore, when all of the first to fourth start pulses Vst1 to Vst4 are output and the AC voltages are all maintained at the constant voltage in the high state, both the first and second dummy stages DST1 and DST2 are operated. The lower stages (..., STn-2 to STn + 2, ...) starting to operate by the stages DST1 and DST2 sequentially output scan pulses. On the other hand, when the first and second start pulses Vst1 and Vst2 are output and the AC voltages Vac1 and Vac2 are maintained at opposite polarities, only the first dummy stage DST1 is operated. The odd-numbered stages (..., STn-2, STn, STn + 2, ...) starting to operate by DST1 output sequentially scan pulses. In addition, when the third and fourth start pulses Vst3 and Vst4 are output and the AC voltages Vac1 and Vac2 are maintained at opposite polarities, only the second dummy stage DST2 is operated. The even-numbered stages (..., STn-1, STn + 1, ...) starting to operate by DST2 output sequentially scan pulses.

On the other hand, the first dummy stage DST1 is secondarily reset in accordance with the scan pulse SP1 from the first stage ST1. That is, the scan pulse SP1 from the first stage ST1 is supplied to the gate electrode of the sixth switching element Tr6 provided in the first dummy stage DST1. The second dummy stage DST2 is secondarily reset by the scan pulse SP2 from the second stage ST2. In this case, the fifth switching device Tr5 provided in the first dummy stage DST1 may also receive the scan pulse SP1, and the fifth switching device Tr5 provided in the second dummy stage DST2 may also be scanned. The pulse SP2 may be supplied. In another method, the second dummy pulse DP2 from the second dummy stage DST2 is supplied to the gate electrode of the fifth switching element Tr5 provided in the first dummy stage DST1 to supply the first dummy stage. DST1 is first reset, and the scan pulse SP1 from the first stage ST1 is supplied to the gate electrode of the fifth switching element Tr5 provided in the second dummy stage DST2 and The second dummy stage DST2 may be reset to primary.

13 illustrates an example in which the first and second dummy stages DST1 and DST2 are fixedly connected directly to the clock transmission line without passing through the connection control unit CCU. DST2 may also be selectively supplied with a clock pulse by the connection controller CCU similarly to the n-th stage STn described above. For example, it is controlled according to the sequential scan control signal PS and the first interlaced scan control signal I1S, and is turned on when any one of these signals is high, so that the corresponding clock transmission line (eg, Another connection control switching element connecting the third clock transmission line CTL3) and the clock input terminal ITd1 of the first dummy stage DST1 may be further added. Similarly, it is controlled according to the sequential scan control signal PS and the second interlaced scan control signal I2S, and is turned on when any one of these signals is high to turn on the corresponding clock transmission line (eg, the fourth). Another connection control switching device for connecting the clock transmission line CTL4) and the clock input terminal ITd2 of the second dummy stage DST2 may be further added.

These first and second dummy stages DST1 and DST2 have almost the same circuit configuration as the n-th stage STn described above. However, the application method of the AC voltages in the first and second dummy stages DST1 and DST2 is different from that in the nth stage STn. This will be described in detail with reference to FIGS. 14 and 15.

FIG. 14 is a diagram illustrating a configuration of a first dummy stage provided in FIG. 13.

As illustrated in FIG. 14, the first dummy stage DST1 includes first to tenth switching elements Tr1 to Tr10, a pull-up switching device Trpu, and a pull-down switching device Trpd.

Here, since the fifth to tenth switching elements Tr5 to Tr10, the pull-up switching element Trpu, and the pull-down switching element Trpd of FIG. 14 are substantially the same as those of FIG. 6, the description thereof will be described. Reference is made to FIG. 6 and the related descriptions described above.

The first switching element Tr1 provided in the first dummy stage DST1 is controlled according to the first start pulse Vst1 from the timing controller and transmits a second AC power line Vac2. It is connected between ACL2) and the set node Q. The first switching device Tr1 is turned on or turned off according to the first start pulse Vst1, and supplies the second AC voltage Vac2 to the set node Q at turn-on.

The second switching element Tr2 provided in the first dummy stage DST1 is controlled according to the second start pulse Vst2 from the timing controller and transmits the first AC power line Vac1. It is connected between ACL1) and the set node Q. The second switching device Tr2 is turned on or turned off in response to the second start pulse Vst2, and supplies the first AC voltage Vac1 to the set node Q at turn-on.

The third switching device Tr3 provided in the first dummy stage DST2 is controlled according to the third start pulse Vst3 from the timing controller, and is connected between the set node Q and the discharge power supply line VSL. do. The third switching device Tr3 is turned on or turned off in response to the third start pulse Vst3, and supplies the discharge voltage VSS to the set node Q at turn-on.

The fourth switching device Tr4 provided in the first dummy stage DST2 is controlled according to the fourth start pulse Vst4 from the timing controller, and is connected between the set node Q and the discharge power supply line VSL. do. The fourth switching device Tr4 is turned on or off in response to the fourth start pulse Vst4 and supplies the discharge voltage VSS to the set node Q at turn-on.

Due to this configuration, the set node Q of the first dummy stage DST1 is turned on first and second by the first and second start pulses Vst1 and Vst2 during the period in which the progressive scanning method is applied. It is charged by the first and second AC voltages Vac1 and Vac2 in the high state sequentially supplied from the second switching elements Tr1 and Tr2. On the other hand, the set node Q of the first dummy stage DST1 is sequentially turned on by the first and second start pulses Vst1 and Vst2 during the first interlaced scanning period. The state of charge is finally maintained by the second AC voltage Vac2 in the low state and the first AC voltage Vac1 in the high state sequentially supplied from the switching elements Tr1 and Tr2. However, since the first and second start pulses Vst1 and Vst2 are not output during the period in which the second interlaced scanning method is applied, the first and second switching elements Tr1 and Tr2 are not turned on during the period. Therefore, the set node Q cannot be charged. In other words, this set node Q maintains the previous discharge state. Therefore, the first dummy stage DST1 does not generate the first dummy pulse DP1 during the period in which the second interlaced scanning method is applied.

FIG. 15 is a diagram illustrating a configuration of a second dummy stage provided in FIG. 13.

As shown in FIG. 15, the second dummy stage DST2 includes first to tenth switching elements Tr1 to Tr10, a pull-up switching device Trpu, and a pull-down switching device Trpd.

Here, the fifth to tenth switching elements Tr5 to Tr10, the pull-up switching device Trpu, and the pull-down switching device Trpd of FIG. 15 are substantially the same as those of FIG. 6 described above, and thus description thereof will be provided. Reference is made to FIG. 6 and the related descriptions described above.

The first switching device Tr1 provided in the second dummy stage DST2 is controlled according to the third start pulse Vst3 from the timing controller and transmits a second AC power line Vac2. It is connected between ACL2) and the set node Q. The first switching device Tr1 is turned on or turned off in response to the third start pulse Vst3, and supplies the second AC voltage Vac2 to the set node Q at turn-on.

The second switching element Tr2 provided in the second dummy stage DST2 is controlled according to the fourth start pulse Vst4 from the timing controller and transmits the first AC power line Vac1. It is connected between ACL1) and the set node Q. The second switching device Tr2 is turned on or off in response to the fourth start pulse Vst4, and supplies the first AC voltage Vac1 to the set node Q at turn-on.

The third switching device Tr3 provided in the second dummy stage DST2 is controlled according to the third start pulse Vst3 from the timing controller, and is connected between the set node Q and the discharge power supply line VSL. do. The third switching device Tr3 is turned on or turned off in response to the third start pulse Vst3, and supplies the discharge voltage VSS to the set node Q at turn-on.

The fourth switching device Tr4 provided in the second dummy stage DST2 is controlled according to the fourth start pulse Vst4 from the timing controller, and is connected between the set node Q and the discharge power supply line VSL. do. The fourth switching device Tr4 is turned on or off in response to the fourth start pulse Vst4 and supplies the discharge voltage VSS to the set node Q at turn-on.

Due to this configuration, the set node of the second dummy stage DST2 is turned on by the third and fourth start pulses Vst3 and Vst4 during the period in which the sequential scanning method is applied. It is charged by the first and second AC voltages Vac1 and Vac2 in the high state sequentially supplied from the elements Tr1 and Tr2. On the other hand, the set node Q of the second dummy stage DST2 is sequentially turned on by the third and fourth start pulses Vst3 and Vst4 during the second interlaced scanning period. The state of charge is finally maintained by the second AC voltage Vac2 in the low state and the first AC voltage Vac1 in the high state sequentially supplied from the switching elements Tr1 and Tr2. However, since the third and fourth start pulses Vst3 and Vst4 are not output during the period in which the first interlaced scanning method is applied, the first and second switching elements Tr1 and Tr2 are not turned on during the period. Therefore, the set node Q cannot be charged. In other words, this set node Q maintains the previous discharge state. Therefore, the second dummy stage DST2 does not generate the second dummy pulse DP2 during the period in which the first interlaced scanning method is applied.

16 to 19 are diagrams for describing an output method of the shift register SR according to a sequential scan method, a first interlaced scan method, a second interlaced scan method, and a combination thereof. Here, it is assumed that a total of 10 stages are provided in the shift register SR.

According to FIG. 16, the shift register SR is driven according to the sequential scanning method every frame period so that all ten stages ST1 to ST10 sequentially output scan pulses every frame period. The driving scheme as shown in FIG. 16 may be applied to the shift register SR having a driving frequency of 60 Hz.

According to FIG. 17, as the shift register SR is driven according to the sequential scanning method only in one of two frame periods adjacent to each other, ten total stages ST1 to ST10 are stored in each frame period. Scan pulses are output sequentially. On the other hand, during another frame period, the gate driver and the data driver enter a dormant state to reduce power consumption. The driving scheme as shown in FIG. 17 may be applied to the shift register SR having a driving frequency of 30 Hz.

According to FIG. 18, as the shift register SR is driven according to the first interlaced scanning method during one frame period of two adjacent frame periods, odd-numbered stages ST1 during a scan period of one frame period. , ST3, ..., ST9) sequentially output scan pulses. As the shift register SR is driven in accordance with the second interlaced scanning method during the other one of the two adjacent frame periods, the even-numbered stages ST2, ST4, during the scan period of the other frame period are driven. ..., ST10) sequentially outputs scan pulses. On the other hand, during the skip period of each frame period, the gate driver and the data driver enter a dormant state to reduce power consumption. The driving scheme as shown in FIG. 18 may be applied to the shift register SR having a driving frequency of 30 Hz.

According to FIG. 19, as the shift register SR is sequentially driven according to the first and second interlaced scanning methods during one of two frame periods adjacent to each other, the first half of the one frame period The odd-numbered stages ST1, ST3, ..., ST9 sequentially output scan pulses during the period, and then the even-numbered stages ST2, ST4,... During the second half of that one frame period. ST10) sequentially outputs scan pulses. On the other hand, during another frame period, the gate driver and the data driver enter a dormant state to reduce power consumption. The driving scheme as shown in FIG. 18 may be applied to the shift register SR having a driving frequency of 30 Hz.

20 illustrates waveforms of scan pulses according to a sequential scan method and scan pulses according to a first interlaced scan method.

That is, according to the sequential scanning method, a relatively larger number of scan pulses are output for a longer period as shown in FIG. On the other hand, according to the first interlaced scanning method, relatively fewer scan pulses are output for a shorter period as shown in FIG.

Meanwhile, the gate driver of the present invention can be used in a display device such as a liquid crystal display device, a plasma display device, a light emitting diode display device, and the like. Switching elements) may be formed on a substrate of the display device in a gate in panel (GIP) manner. In this case, the semiconductor layers of the switching devices may be made of amorphous silicon or oxide.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

ST #: #th stage CTL #: ## clock transmission line
CLK #: # # pulse pulse P-Tr: sequential driving switching element
I-Tr #: # # interlaced switching element CCU: connection control unit
PS: Sequential scan control signal I # S: # # interlaced scan control signal
SR: Shift Register SP #: #th Scan Pulse
IT: Clock input terminal OT: Scan output terminal

Claims (11)

A plurality of stages receiving at least one of clock pulses of different phases and outputting a scan pulse; And,
A connection control unit connected between the plurality of clock transmission lines to which the clock pulses are applied and the plurality of stages, and controlling whether the clock transmission lines and the plurality of stages are connected according to a scan control signal from an outside; Including,
The connection control unit
Connecting all of the plurality of stages and the plurality of clock transmission lines to each other when a sequential scan control signal of the scan control signals is active;
When one interlaced scanning control signal of the scan control signal is active, odd-numbered stages of the plurality of stages are connected to the plurality of clock transmission lines, or even-numbered stages and the plurality of clock transmissions are connected. Gate driver for display devices that connect lines. The method of claim 1,
The connection control unit
Connecting the odd-numbered stages and the plurality of clock transmission lines to each other when a first interlaced scanning control signal is active;
And a gate driver for connecting the even-numbered stages and the plurality of clock transmission lines to each other when the second interlaced scanning control signal is active. The method of claim 2,
The connection control unit,
And a plurality of connection control switching elements controlled according to the scan control signal and connected between the plurality of clock transmission lines and the plurality of stages. The method of claim 3, wherein
The plurality of connection control switching elements,
A plurality of sequential drive switching elements connected between the clock transmission line and the clock input terminal of each stage;
A plurality of first interlacing switching elements connected between the clock transmission line and the clock input terminal of the odd-numbered stages; And,
A gate driver for a display device comprising a plurality of second interlacing switching elements connected between the clock transmission line and the clock input terminal of an even-numbered stage. The method of claim 4, wherein
Nth stage of the plurality of stages,
a first switching element controlled according to the scan pulse from the n-second stage and connected between the first AC power line and the set node for transmitting the first AC voltage;
a second switching element controlled according to the scan pulse from the n-th stage and connected between a second AC power line for transmitting a second AC voltage and the set node;
A third switching element controlled according to the scan pulse from the n-2th stage and connected between a reset node and a discharge power supply line for transmitting a discharge voltage;
A fourth switching element controlled according to the scan pulse from the n-th stage and connected between the reset node and the discharge power supply line;
a fifth switching element controlled according to the scan pulse from the n + 1 th stage and connected between said discharge power supply line and said set node;
a sixth switching element controlled according to the scan pulse from the n + 2th stage and connected between said discharge power supply line and said set node;
A seventh switching element controlled according to the voltage of the reset node and connected between the set node and the discharge power supply line;
An eighth switching element controlled according to the voltage of the set node and connected between the reset node and the discharge power supply line;
A ninth switching element controlled according to the charging voltage from the charging power supply line and connected between the charging power supply line and the common node;
A tenth switching element controlled according to the voltage of the common node and connected between the charging power supply line and the reset node;
A pull-up switching element controlled according to the voltage of the set node and connected between the clock input terminal and the scan output terminal of the n-th stage; And,
And a pull-down switching element controlled according to the voltage of the reset node and connected between the scan output terminal of the nth stage and the discharge power supply line. The method of claim 5,
When the sequential scan control signal among the scan control signals is active and the remaining signals are inactive, both the first AC voltage and the second AC voltage are kept in an active state;
When the first interlaced scanning control signal of the scan control signal is active and the remaining signals are inactive, the first AC voltage is maintained in an active state and a second AC voltage is maintained in an inactive state;
The second AC voltage is maintained in an active state and the first AC voltage is in an inactive state when the second interlaced scanning control signal is an active state and the remaining signals are in an inactive state. Gate driver. The method of claim 2,
A first dummy stage for generating a first dummy pulse for setting a first stage operating among the odd-numbered stages included in the plurality of stages; And,
And a second dummy stage for generating a second dummy pulse for setting a second stage operating first among even-numbered stages included in the plurality of stages. The method of claim 7, wherein
The first dummy stage is set according to a first start pulse and a second start pulse to generate a clock pulse from any one clock transmission line as the first dummy pulse;
And the second dummy stage is set in accordance with a third start pulse and a fourth start pulse to generate clock pulses from any other clock transmission line as the second dummy pulse. The method of claim 8,
When the sequential scan control signals of the scan control signals are active, the first to fourth start pulses are sequentially supplied to the first and second dummy stages;
When the first interlaced scanning control signal is active, the first and second start pulses remain active and the third and fourth start pulses remain inactive;
And the third and fourth start pulses remain active and the first and second start pulses remain inactive when the second interlaced scanning control signal is active. The method of claim 8,
The first dummy stage,
A first switching element controlled according to the first start pulse and connected between a second AC power line for transmitting a second AC voltage and a set node;
A second switching element controlled according to the second start pulse and connected between the first AC power line for transmitting a first AC voltage and the set node;
A third switching element controlled according to the first start pulse and connected between a reset node and a discharge power supply line for transmitting a discharge voltage;
A fourth switching element controlled according to the second start pulse and connected between the reset node and the discharge power supply line;
A fifth switching element controlled according to a second dummy pulse from the second dummy stage and connected between the discharge power supply line and the set node;
A sixth switching element controlled according to the scan pulse from the first stage and connected between the discharge power supply line and the set node;
A seventh switching element controlled according to the voltage of the reset node and connected between the set node and the discharge power supply line;
An eighth switching element controlled according to the voltage of the set node and connected between the reset node and the discharge power supply line;
A ninth switching element controlled according to the charging voltage from the charging power supply line and connected between the charging power supply line and the common node;
A tenth switching element controlled according to the voltage of the common node and connected between the charging power supply line and the reset node;
A pull-up switching element controlled according to the voltage of the set node and connected between the clock input terminal and the scan output terminal of the first dummy stage; And,
And a pull-down switching element controlled according to the voltage of the reset node and connected between the scan output terminal of the first dummy stage and the discharge power supply line. The method of claim 8,
The second dummy stage,
A first switching element controlled according to the third start pulse and connected between a second AC power line and a set node for transmitting a second AC voltage;
A second switching element controlled according to the fourth start pulse and connected between the first AC power line for transmitting a first AC voltage and the set node;
A third switching element controlled according to the third start pulse and connected between a reset node and a discharge power supply line for transmitting a discharge voltage;
A fourth switching element controlled according to the fourth start pulse and connected between the reset node and the discharge power supply line;
A fifth switching element controlled according to the scan pulse from the first stage and connected between the discharge power supply line and the set node;
A sixth switching element controlled according to the scan pulse from the second stage and connected between the discharge power supply line and the set node;
A seventh switching element controlled according to the voltage of the reset node and connected between the set node and the discharge power supply line;
An eighth switching element controlled according to the voltage of the set node and connected between the reset node and the discharge power supply line;
A ninth switching element controlled according to the charging voltage from the charging power supply line and connected between the charging power supply line and the common node;
A tenth switching element controlled according to the voltage of the common node and connected between the charging power supply line and the reset node;
A pull-up switching element controlled according to the voltage of the set node and connected between the clock input terminal and the scan output terminal of the second dummy stage; And,
And a pull-down switching element controlled according to the voltage of the reset node and connected between the scan output terminal of the second dummy stage and the discharge power supply line.

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