KR20100074933A - Shift register - Google Patents

Abstract

PURPOSE: A shift register is provided to maintain a falling time of a scan pulse which is supplied to each gate by supplying different AC voltage to an A-stage and a B-stage. CONSTITUTION: A first shift register supplies a scan pulse to each sides of gate lines. A second shift register supplies the scan pulse to the other sides of gate lines. A node controller control the logic state of an enable node and a disable node. The node controller controls the logic stage of an disable node which is arranged a different stage.

Description

Shift register {SHIFT REGISTER}

The present invention relates to a shift register, and more particularly, to a shift register capable of preventing deterioration in image quality due to variation in polling time between scan pulses.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and a pixel region is positioned in an area defined by vertical crossings of the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed in the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a scan pulse applied to a gate terminal via the gate line, so that the data signal of the data line is charged to the pixel voltage.

The driving circuit may include a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, and a liquid crystal display device. It is provided with a power supply for supplying a variety of driving voltages used in.

The gate driver includes a shift register for sequentially supplying scan pulses to gate lines to sequentially drive pixels on the liquid crystal panel by one line. This shift register contains a number of stages that output a scan pulse.

On the other hand, in the shift register structure of a node sharing structure, there is a problem that a deviation occurs between the output waveform of the scan pulse output from the odd stage and the output waveform of the scan pulse output from the even stage. If this is explained in more detail as follows.

1 is a diagram illustrating voltage waveforms and scan pulse waveforms of an enable node in an odd-numbered stage, voltage waveforms and scan pulse waveforms of an enable node in an even-numbered stage, and FIG. The waveforms of the scan pulses output from the odd stage and the output characteristics of the scan pulses output from the even stage are compared.

FIG. 1A is a diagram showing voltage waveforms and waveforms of scan pulses of an enable node in odd-numbered stages. As shown in FIG. 1A, a scan pulse is a high voltage to a low voltage. At the point of change, the voltage of the enable node is not changed to low voltage at once, but is discharged to low voltage twice. Therefore, since the enable node is not rapidly discharged, there is sufficient time for the scan pulse to transition from the high voltage to the low voltage. Therefore, as shown in Fig. 2, the polling time of the scan pulse O output from this odd stage is stately short.

On the other hand, Figure 1 (b) is a diagram showing the voltage waveform and the waveform of the scan pulse of the enable node in the even-numbered stage, as shown in Figure 1 (b), the scan pulse at a high voltage When the voltage of the enable node changes immediately from the high voltage to the low voltage at the point of change to the low voltage, there is not enough time for the scan pulse to transition from the high voltage to the low voltage. Thus, as shown in Fig. 2, the polling time of the scan pulse E output from this even-numbered stage is relatively long.

1C shows the voltage state of the disable node. The disable node is maintained at a low voltage while the enable node is maintained at a high voltage.

As described above, a difference occurs between the output characteristics of the scan pulses output from the odd-numbered stage and the output characteristics of the scan pulses output from the even-numbered stage in the conventional shift register, and the even-numbered gate lines connected to the odd-numbered stages are even. The voltage deviation between even gate lines connected to the first stage is generated. This, in turn, causes a difference in image quality between pixels connected to the odd-numbered gate line and pixels connected to the even-numbered gate line, resulting in deterioration of image quality.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and uses two shift registers to drive the gate lines, and in particular, supplies the gate lines by applying opposite AC voltages to stages connected to the same gate line. An object of the present invention is to provide a shift register that can maintain the same polling time of scan pulses.

A shift register according to the present invention for achieving the above object comprises a first shift register for sequentially supplying a scan pulse to each side of the gate lines; A second shift register sequentially supplying scan pulses to the other sides of the gate lines; At least one A stage included in the first shift register includes an enable node; A pull-up switching device configured to output the scan pulse according to a logic state of the enable node; At least two nodes for disabling; At least two pull-down switching elements connected to each of the disable nodes and outputting an off voltage according to a logic state of each of the disable nodes; A node control unit for controlling the logic states of the enable node and the disable nodes provided in the same and the logical states of the disable node included in the stage different from the self; At least one B stage provided in the second shift register comprises: an enabling node; A pull-up switching device configured to output the scan pulse according to a logic state of the enable node; At least two nodes for disabling; At least two pull-down switching elements connected to each of the disable nodes and outputting an off voltage according to a logic state of each of the disable nodes; A node control unit for controlling the logic states of the enable node and the disable nodes provided in the same and the logical states of the disable node included in the stage different from the self; The node control unit provided in the A stage of the first shift register connected to an arbitrary gate line may use the first AC voltage to determine the logic states of the enable node and the disable nodes, and different A stages from itself. Controlling the logical state of the node for disabling provided at the same time; The node control unit provided in the B stage of the second shift register connected to the arbitrary gate line uses the second alternating current voltage to determine the logic state of the enable node and the disable nodes, and the different B from the node. To control the logic state of the disable node included in the stage; The first AC voltage may be inverted with respect to the second AC voltage.

The node control unit provided in the odd-numbered A stage of the first shift register connected to the odd-numbered gate line is different from the logic state of the enable node and the disable nodes provided by the node control unit using the first AC voltage. To control the logic state of the disable node included in the stage; The node controller provided in the even-numbered A stage of the first shift register connected to the even-numbered gate line is different from the logic state of the enable node and the disable nodes provided by the node control unit using the second AC voltage. To control the logic state of the disable node included in the stage; The node control unit provided in the odd-numbered B stage of the second shift register connected to the odd-numbered gate line is different from the logic state of the enable node and the disable-node nodes by using the second AC voltage. To control the logic state of the disable node included in the stage; In addition, the node controller provided in the even-numbered B stage of the second shift register connected to the even-numbered gate line may use logic states of the enable node and the disable nodes provided by the node control unit by using the first AC voltage. And a logic state of the disable node provided in another stage.

Each A stage provided in the first shift register includes a first disable node, a first pull-down switching element connected to the first disable node, a second disable node, and the second disable node. A second pull-down switching element connected to; The node controller provided in the 2n-3 (n is a natural number of 2 or more) stage A controls the logic states of the enable node and the first disable node provided in the 2n-3th A stage, and also the 2n− Control the logic state of the first disable node provided in the second A stage; The node control unit provided in the 2n-2th A stage controls the logic states of the enable node and the second disable node provided in the 2n-2th A stage, and the 2n-3th A stage. Control a logic state of the provided second disable node; Each B stage provided in the second shift register includes a first disable node, a first pull-down switching element connected to the first disable node, a second disable node, and the second disable A second pull-down switching element connected to the node; The node control unit provided in the 2n-3 (n is a natural number of 2 or more) stage B controls the logic states of the enable node and the first disable node provided in the 2n-3rd B stage, as well as 2n−. Control the logic state of the first disable node provided in the second B stage; The node control unit provided in the 2n-2th B stage controls the logic states of the enable node and the second disable node provided in the 2n-2th B stage, and the 2n-3th B stage. And controlling the logic state of the provided second disable node.

A first disable node provided in the 2n-3rd A stage and a first disable node provided in the 2n-2nd A stage are electrically connected to each other; A second disable node provided in the 2n-2 th A stage and a second disable node provided in the 2n-3 th A stage are electrically connected to each other; A first disable node provided in the 2n-3rd B stage and a first disable node provided in the 2n-2nd B stage are electrically connected to each other; The second disable node provided in the 2n-2 th B stage and the second disable node provided in the 2n-3 th B stage are electrically connected to each other.

The node control unit provided in the 2n-3rd A stage includes the logical state of the first disable node provided in the 2n-3rd A stage and the node of the first disable node provided in the 2n-2 A A stage. Control a logic state to said first alternating voltage; The node control unit provided in the 2n-2th A stage may perform logic states of a second disable node provided in the 2n-2 A A stage and a second disable node provided in the 2n-3 A A stage. Control with the second alternating voltage; In addition, the node controller provided in the 2n-3rd B stage may include a logic state of the first disable node provided in the 2n-3rd B stage and a first disable provided in the 2n-2nd B stage. Control a logic state of a dragon node to the second alternating voltage; The node controller provided in the 2n-2th B stage is configured to determine the logical states of the second disable node provided in the 2n-2th B stage and the second disable node provided in the 2n-3rd B stage. The control is characterized by the first AC voltage.

The 2n-1st A stage and the 2nth A stage are enabled in response to the scan pulse from the 2n-3rd A stage, and are disabled in response to the scan pulse from the 2n + 2nd A stage; 2n-3rd A stage and 2n-2nd A stage are disabled in response to the scan pulse from the 2nth A stage; A 2n + 1 th A stage and a 2n + 2 th A stage are enabled in response to a scan pulse from the 2n-1 th A stage; And the 2n-1st B stage and the 2nth B stage are enabled in response to the scan pulses from the 2n-3rd B stage and are disabled in response to the scan pulses from the 2n + 2nd B stage; 2n-3rd B stage and 2n-2nd B stage are disabled in response to the scan pulse from the 2nth B stage; The 2n + 1st B stage and the 2n + 2th B stage are enabled in response to the scan pulses from the 2n-1st B stage.

The node control unit provided in the 2n-1st A stage includes: a first switching device configured to charge the enable node to a first DC voltage in response to a scan pulse from the 2n-3rd A stage; A second switching element configured to discharge the enable node to a second DC voltage in response to a first AC voltage supplied to a first disable node; Discharging the enable node of the 2n-1st A stage to a second DC voltage in response to a second AC voltage supplied to the second disable node of the 2n-1 A stage through the 2nth A stage. A third switching element; A fourth switching device for discharging the enable node to a second DC voltage in response to a scan pulse from a 2n + 2th A stage; A fifth switching device that is turned on or off in response to a first alternating voltage and charges a common node with the first alternating voltage when turned on; A sixth switching device discharging the common node to a second DC voltage in response to a first DC voltage charged in the enable node; A seventh battery charging the first disable node of the 2n-1st A stage and the first disable node of the 2nth A stage to the first AC voltage in response to a first AC voltage supplied to the common node; Switching element; An eighth switch for discharging the first disable node of the 2n-1st A stage and the first disable node of the 2nth A stage to a second DC voltage in response to a scan pulse from the 2n-3rd A stage; device; And discharging the first disable node of the 2n-1st A stage and the first disable node of the 2nth A stage to a second DC voltage in response to a first DC voltage charged in the enable node. A ninth switching device for guiding; The node controller provided in the 2n-1st B stage includes: a first switching device configured to charge the enable node to a first DC voltage in response to a scan pulse from the 2n-3rd B stage; A second switching element for discharging the enable node to a second DC voltage in response to a first AC voltage supplied to a first disable node; Discharging the enable node of the 2n-1th B stage to a second DC voltage in response to a second AC voltage supplied to the second disable node of the 2n-1st B stage through a 2nth B stage. A third switching element; A fourth switching device for discharging the enable node to a second DC voltage in response to a scan pulse from a 2n + 2th B stage; A fifth switching device that is turned on or off in response to a first alternating voltage and charges a common node with the first alternating voltage when turned on; A sixth switching device discharging the common node to a second DC voltage in response to a first DC voltage charged in the enable node; A seventh charge of the first disabling node of the 2n-th B stage and the first disabling node of the 2n-th B stage to the first AC voltage in response to the first AC voltage supplied to the common node; Switching element; An eighth switch configured to discharge the first disable node of the 2n-1st B stage and the first disable node of the 2nth B stage to a second DC voltage in response to a scan pulse from the 2n-3rd B stage device; And discharging the first disable node of the 2n-1st B stage and the first disable node of the 2nth B stage to a second DC voltage in response to a first DC voltage charged in the enable node. It characterized in that it comprises a ninth switching device.

2n-1st A stages of the A stages provided in the first shift register are supplied with a first AC voltage, and 2nth A stages are supplied with a second AC voltage; 2n-1st B stages of the B stages provided in the second shift register are supplied with the first AC voltage, and the 2nth B stages are supplied with the second AC voltage;

A 2nth A stage of the first shift register supplies a scan pulse to one side of an nth gate line; The 2n-1th B stage of the second shift register supplies a scan pulse to the other side of the nth gate line.

The scan pulse from the first A stage of the A stages and the scan pulse from the last B stage of the B stages are not supplied to the gate line.

A shift register sequentially supplying scan pulses to one side of the gate lines; At least one stage provided in the shift register comprises: an enabling node; A pull-up switching device configured to output the scan pulse according to a logic state of the enable node; At least two nodes for disabling; At least two pull-down switching elements connected to each of the disable nodes and outputting an off voltage according to a logic state of each of the disable nodes; A node control unit for controlling the logic states of the enable node and the disable nodes provided in the same and the logical states of the disable node included in the stage different from the self; The node control unit provided in the stage connected to an arbitrary gate line may be configured to use the logic state of the enable node and the disable nodes provided by the node controller using either one of the first AC voltage and the second AC voltage. To control the logic state of the disable node included in the other stages together; The first AC voltage has an inverted phase with respect to the second AC voltage; The first AC voltage and the second AC voltage are randomly supplied to each stage, and different AC voltages are supplied in the 2n-1 st stage and the 2n th stage.

The shift register according to the present invention has the following effects.

The shift register according to the present invention is a scan supplied between each gate line by supplying alternating AC voltages to the A stage supplying the scan pulse to one side of one gate line and the B stage supplying the scan pulse to the other side of the gate line. Keep the polling time of the pulses the same. As a result, deterioration of image quality can be prevented.

3 is a diagram illustrating a shift register according to a first embodiment of the present invention, FIG. 4 is a diagram illustrating a configuration of stages included in the first shift register SR1 of FIG. 3, and FIG. 2 is a diagram illustrating a configuration of stages provided in the shift register SR2. 6 is a diagram illustrating waveforms of an input signal supplied to each stage of FIG. 4 and an output signal output from each stage.

As shown in FIG. 3, the shift register according to the first exemplary embodiment of the present invention is located at one side of the gate lines GL1, GL2, GL3,..., And the gate lines GL1, GL2, GL3. The first shift register SR1 sequentially supplies scan pulses to one side of the ..., and the other side of the gate lines GL1, GL2, GL3,... And a second shift register SR2 which sequentially supplies scan pulses to the other sides of GL1, GL2, GL3, ...).

The first shift register SR1 is connected to one side of the gate lines GL1, GL2, GL3,... And sequentially scans one side of the gate lines GL1, GL2, GL3,... A number of A stages (AST1, AST2, AST3, ...) that supplies pulses. In addition, the second shift register SR2 is connected to the other side of the gate lines GL1, GL2, GL3,..., And sequentially to the other side of the gate lines GL1, GL2, GL3,. It includes a number of B stages supplying scan pulses.

In particular, the A stage and the B stage connected to the same gate line are supplied with opposite AC voltages. For example, while the first A stage connected to one side of the first gate line GL1 receives the first AC voltage Vac1, the first B stage connected to the other side of the first gate line GL1 is provided. Is supplied with the second AC voltage Vac2. The first AC voltage and the second AC voltage Vac1 and Vac2 are AC signals that change from positive polarity to negative polarity or from negative polarity to positive polarity in units of p frame periods (p is a natural number). ) Has a phase inverted 180 degrees with respect to the second AC voltage Vac2.

At least each A stage provided in the first shift register SR1 may include an enable node Q as shown in FIG. 4; A pull-up switching device Tru outputting the scan pulse according to the logic state of the enable node Q; At least two disable nodes QB1 and QB2; At least two pull-down switching elements (Trd1, Trd2) connected to each of the disable nodes (QB1, QB2) and outputting an off voltage according to a logic state of each of the disable nodes (QB1, QB2); The node control unit 205 for controlling the logical states of the enable node Q and the disable nodes QB1 and QB2 included in the self, and the logical states of the disable node provided in the A stage different from itself. ).

At least one B stage provided in the second shift register SR2 may include an enable node Q as shown in FIG. 5; A pull-up switching device Tru outputting the scan pulse according to the logic state of the enable node Q; At least two disable nodes QB1 and QB2; At least two pull-down switching elements (Trd1, Trd2) connected to each of the disable nodes (QB1, QB2) and outputting an off voltage according to a logic state of each of the disable nodes (QB1, QB2); The node control unit 205 for controlling the logical states of the enable node Q and the disable nodes QB1 and QB2 provided in the self, and the logical states of the disable node provided in the B stage different from itself. ).

At this time, the node control unit 205 provided in the odd-numbered A stage of the first shift register SR1 connected to the odd-numbered gate line uses the first alternating voltage Vac1 to enable the node Q for itself. ) And the logic states of the disable nodes QB1 and QB2 and the disable states of the disable node included in the stage different from itself. In addition, the node controller 205 provided in the even-numbered A stage of the first shift register SR1 connected to the even-numbered gate line uses the second alternating voltage Vac2 to enable the node Q for itself. ) And the logic states of the disable nodes QB1 and QB2 and the disable states of the disable node included in the stage different from itself.

On the other hand, the node controller 205 provided in the odd-numbered B stage of the second shift register SR2 connected to the odd-numbered gate line is enabled for the Q provided therein by using the second AC voltage Vac2. The logical state of the node and the disable nodes QB1 and QB2 and the logical state of the disable node included in the stage different from itself are controlled together. In addition, the node controller 205 included in the even-numbered B stage of the second shift register SR2 connected to the even-numbered gate line may use the second node Q for enabling the node Q provided therein. ) And the logic states of the disable nodes QB1 and QB2 and the disable states of the disable node included in the stage different from itself.

Here, the A stages provided in the first shift register SR1 will be described in detail.

Each of the A stages AST1, AST2, AST3, ... includes an enable node Q, a pull-up switching element Tru connected to the enable node Q, and a first disable node QB1. A first pull-down switching device Trd1 connected to the first disable node QB1, a second disable node QB2, and a second connect node to the second disable node QB2. And a pull-down switching device Trd2.

The node control unit 205 provided in the second 2n-3 (n is a natural number of two or more) stages A is configured to charge the enable node Q and the first disable node QB1 provided in the second n-3 stage. It controls the / discharge state and also controls the charge / discharge state of the first disable node QB1 provided in the 2n-2A stage.

In addition, the node controller 205 provided in the second n-2A stage may control the charging / discharging states of the enable node Q and the second disable node QB2 included in the second n-2A stage. The controller also controls the charge / discharge state of the second disable node QB2 included in the second n-3A stage.

To this end, the first disable node QB1 of the 2n-3 A stage and the first disable node QB1 of the 2n-2 A stage are connected to each other, and the second n-2 A stage. The second disable node QB2 and the second disable node QB2 of the 2n-2A stage are electrically connected to each other.

For example, the node controller 205 included in the third A stage AST3 may charge the enable node Q and the first disable node QB1 provided in the third A stage AST3. It controls the discharge state and controls the charge / discharge state of the first disable node QB1 included in the fourth A stage AST4.

The node controller 205 included in the fourth A stage AST4 is configured to charge / enable the enable node Q and the second disable node QB2 included in the fourth A stage AST4. The discharge state is controlled, and the charge / discharge state of the second disable node QB2 included in the third A stage AST3 is controlled.

To this end, the first disable node QB1 of the third A stage AST3 and the first disable node QB1 of the fourth A stage AST4 are connected to each other, and the fourth A The second disable node QB2 of the stage AST4 and the second disable node QB2 of the third A stage AST3 are electrically connected to each other.

In particular, the node control unit 205 provided in the 2n-3A stage is connected to the charge / discharge state of the first disable node QB1 provided in the 2n-3A stage and the 2n-2A stage. The charge / discharge state of the provided first disable node QB1 is controlled to a first AC voltage.

The node control unit 205 included in the second n-2A stage includes a second disable node QB2 provided in the second n-2A stage and a second node provided in the second n-3A stage. The charging / discharging state of the disable node QB2 is controlled by the second alternating voltage.

That is, each node control unit 205 provided in the odd-numbered A stages AST1, AST3, AST5, ... of the A stages AST1, AST2, AST3,... Vac1) is supplied, and each node controller 205 provided in even-numbered A stages AST2, AST4, AST6, ... receives the second AC voltage Vac2.

Here, the first AC voltage Vac1 and the second AC voltage Vac2 are AC voltages in which the voltage changes in units of frames, and the first AC voltage Vac1 is 180 degrees with respect to the second AC voltage Vac2. It has a phase inverted form.

Meanwhile, each of the A stages AST1, AST2, AST3, ... receives the first DC voltage Vdc1 to charge its enable node Q, and supplies the second DC voltage Vdc2. It is output as an off voltage.

In addition, each of the A stages AST1, AST2, AST3, ... may receive the scan pulse from the previous stage A instead of the first DC voltage Vdc1 to charge its enable node Q. have.

Here, the first DC voltage Vdc1 means a positive voltage, and the second DC voltage Vdc2 means a negative voltage.

Each of the A stages AST1, AST2, AST3, ... configured as described above receives the clock pulse of any one of the first to fifth clock pulses CLK1 to CLK5, and uses the supplied clock pulse as a scan pulse. Output

As shown in Fig. 3, the first to fifth clock pulses CLK1 to CLK1 to CLK5 are delayed and output by one pulse width from each other, that is, the second clock pulse CLK2 is output to the second clock pulse CLK2. Phase delayed by one pulse width than one clock pulse (CLK1) and output, the third clock pulse (CLK3) is delayed by one pulse width than the second clock pulse (CLK2) output, the fourth clock pulse CLK4 is delayed in phase by one pulse width than the third clock pulse CLK3, and the fifth clock pulse CLK5 is delayed in phase by one pulse width than the fourth clock pulse CLK4. The first clock pulse CLK1 is delayed in phase by one pulse width than the fifth clock pulse CLK5 and output.

In this case, the first to fifth clock pulses CLK1 to CLK5 are sequentially output, and are also output while cycling. That is, after the first clock pulse CLK1 to the fifth clock pulse CLK5 are sequentially output, the first clock pulse CLK1 to the fifth clock pulse CLK5 are sequentially output. Therefore, the first clock pulse CLK1 is output in a period corresponding to the fifth clock pulse CLK5 and the second clock pulse CLK2.

Each of the first to fifth clock pulses CLK1 to CLK5 is continuously output at regular intervals. Therefore, when five clock pulses are used as described above, the first to fifth A stages AST1 to AST5 output the first to fifth clock pulses CLK1 to CLK5 as scan pulses.

At this time, since the first to fifth clock pulses CLK1 to CLK5 are phase-delayed by one clock pulse as described above, each of the first to fifth clock pulses CLK1 to CLK5 is outputted from the first to fifth A stages AST1 to AST5. The scan pulses Von1 to Von5 are also phase-delayed by one pulse width and output.

That is, each of the scan pulses Von1 to Von5 is sequentially output. The sixth A stage AST6 again outputs the first clock pulse CLK1 as a sixth scan pulse Vout6. In this case, the first clock pulse CLK1 output by the sixth A stage AST6 is a pulse delayed by one period from the first clock pulse CLK1 output from the first A stage AST1.

Meanwhile, in order for each of these A stages (AST1, AST2, AST3, ...) to output the scan pulse as described above, each of the A stages (AST1, AST2, AST3, ...) must be enabled. In addition, each A stage (AST1, AST2, AST3, ...) must be disabled to output the off voltage.

To this end, each A stage (AST1, AST2, AST3, ...) is enabled in response to the scan pulse from the front stage A stage, and is disabled in response to the scan pulse from the rear stage A stage.

Specifically, the 2n-1 A stage and the 2n A stage are simultaneously enabled in response to the 2n-3 scan pulse from the 2n-3 A stage and the 2n + 2 scan from the 2n + 2 A stage It is disabled at the same time in response to a pulse.

The enabled 2n-1A stage outputs a 2n-1 scan pulse and supplies the 2n-1 scan pulse to the 2n + 1 and 2n + 2 A stages to supply the 2n-1A stage. And simultaneously activate the second n + 2 A stage.

The enabled 2n A stage outputs a 2n scan pulse and supplies the 2n scan pulse to the 2n-3 and 2n-2 A stages, thereby providing the 2n-3 and 2n-2 stages. Disable the A stage at the same time.

For example, the third A stage AST3 and the fourth A stage AST4 are simultaneously enabled in response to the first scan pulse Vout1 from the first A stage AST1, and the sixth A stage ( It is simultaneously disabled in response to the sixth scan pulse Vout6 from AST6.

The enabled third A stage AST3 outputs a third scan pulse Vout3, and supplies the third scan pulse Vout3 to the fifth and sixth A stages AST5 and AST6. The fifth and sixth A stages AST5 and AST6 are simultaneously enabled.

The enabled fourth A stage AST4 outputs the fourth scan pulse Vout4 and supplies the fourth scan pulse Vout4 to the first and second A stages AST1 and AST2. The first and second A stages AST1 and AST2 are simultaneously disabled.

Meanwhile, since the A stage does not exist in the first front end of the first A stage AST1 and the second front end of the second A stage AST2, the first and second A stages AST1 and AST2 are timing controllers. Enable in response to the start pulse VAST from. Also, for this reason, the second scan pulse Vout2 from the second A stage AST2 is supplied only to the second gate line GL2.

The start pulse VAST is output before the first clock pulse CLK1. That is, the start pulse VAST is output two clock pulses ahead of the first clock pulse CLK1. In addition, the start pulse VAST is output only once per frame. That is, the start pulse VAST is first outputted every frame, and then the first to fifth clock pulses CLK1 to CLK5 are sequentially output.

The reason why the time difference between the start pulse VAST and the first clock pulse CLK1 is set by two pulse widths is to equalize the output characteristics between all the A stages.

That is, the odd-numbered A stages (AST1, AST3, AST5, ...) are enabled by the scan pulses from the A stage located at the second front end from themselves and the even-numbered A stages (AST2, AST4, AST6, ...). ) Is enabled by a scan pulse from stage A located at the third front end thereof, and the start pulse VAST and the first clock pulse CLK1 are outputted with a time difference of two pulse widths. 1 stage A (AST1) can be operated as if enabled by the scan pulse from the stage A located on the second front end, and the second stage A (AST2) to the scan pulse from the stage A located on the third front end. It can be operated as if enabled by.

Of course, although not shown in the drawing, the start pulse VAST and the first clock pulse CLK1 may be adjusted to be output with a time difference of one pulse width.

Since the B stages provided in the second shift register SR2 also have the same configuration as the A stages described above, description thereof will be omitted. That is, in the description of the above-described A stage, changing the alphabet 'A stage' to 'B stage' is a description of the B stages.

A circuit configuration of the A stages provided in the first shift register SR1 will be described below.

FIG. 7 is a diagram illustrating a circuit configuration of a node controller provided in third and fourth A stages of the first shift register SR1 of FIG. 2.

Here, the odd-numbered A stages (2n-1 A stage; AST1, AST3, AST5, ...) and the even-numbered A stages (2n A stage; AST2, AST4, AST6, ...) Has a different configuration.

First, the node control unit 205 provided in the odd-numbered A stages AST1, AST3, AST5, ... has first to ninth switching elements Tr1 to Tr9, as shown in FIG. .

That is, the first switching device Tr1 provided in the 2n-1A stage is configured to first enable the node Q for enabling the 2n-1A stage in response to a scan pulse from the 2n-3A stage. Charge to DC voltage (Vdc1).

For example, the first switching device Tr1 included in the third A stage AST3 of FIG. 7 may respond to the third A stage (in response to the first scan pulse Vout1 from the first A stage AST1). The enable node Q of the AST3 is charged to the first DC voltage Vdc1.

To this end, the gate terminal of the first switching element Tr1 provided in the third A stage AST3 is connected to the first A stage AST1, and the drain terminal transmits the first DC voltage Vdc1. The source terminal is connected to the enable node Q of the third A stage AST3.

The second switching element Tr2 included in the 2n-1A stage is configured to respond to the 2n-1 A stage in response to the first AC voltage Vac1 supplied to the first disable node QB1 of the 2n-1A stage. The enabling node Q of the -1 A stage is discharged to the second DC voltage Vdc2.

For example, the second switching device Tr2 included in the third A stage AST3 of FIG. 7 is provided with a first AC voltage supplied to the first disable node QB1 of the third A stage AST3. In response to Vac1, the enable node Q of the third A stage AST3 is discharged to the second DC voltage Vdc2.

To this end, the gate terminal of the second switching element Tr2 provided in the third A stage AST3 is connected to the first disable node QB1 of the third A stage AST3, and the drain terminal is It is connected to the enable node Q of the third A stage AST3, and the source terminal is connected to a power line for transmitting the second DC voltage Vdc2.

The third switching element Tr3 included in the 2n-1A stage is provided with the second AC voltage Vac2 supplied to the second disable node QB2 of the 2n-1A stage through the 2nA stage. ), The enable node Q of the 2n-1A stage is discharged to the second DC voltage Vdc2.

That is, the third switching device Tr3 included in the 2n-1A stage responds to the second AC voltage Vac2 supplied to the second disable node QB2 of the 2n-1A stage. The enable node Q of the 2n-1A stage is discharged to a second DC voltage Vdc2, wherein the state of the second disable node QB2 provided in the 2n-1 A stage is It is controlled by the node control unit 205 of the second nA stage.

For example, the third switching device Tr3 included in the third A stage AST3 of FIG. 7 is configured as a second disable node of the third A stage AST3 through the fourth A stage AST4. The enable node Q of the third A stage AST3 is discharged to the second DC voltage Vdc2 in response to the second AC voltage Vac2 supplied to QB2).

To this end, the gate terminal of the third switching device Tr3 provided in the third A stage AST3 is connected to the second disable node QB2 of the third A stage AST3, and the drain terminal is It is connected to the enable node Q of the third A stage AST3, and a source terminal is connected to a power line for transmitting the second DC voltage Vdc2.

The fourth switching device Tr4 provided in the 2n-1A stage is configured to pass the enable node Q of the 2n-1A stage to a second DC in response to a scan pulse from the 2n + 2th A stage. Discharge to voltage Vdc2.

For example, the fourth switching device Tr4 included in the third A stage AST3 of FIG. 7 may respond to the third A stage (in response to the sixth scan pulse Vout6 from the sixth A stage AST6). The enable node Q of the AST3 is discharged to the second DC voltage Vdc2.

To this end, the gate terminal of the fourth switching element Tr4 provided in the third A stage AST3 is connected to the sixth A stage AST6, and the drain terminal of the third A stage AST3 is It is connected to the enable node Q, and a source terminal is connected to a power line for transmitting the second DC voltage Vdc2.

The fifth switching element Tr5 provided in the 2n-1 A stage is turned on or off in response to a first AC voltage Vac1, and when turned on, the common node of the 2n-1 A stage is turned on. (N) is charged to the first AC voltage Vac1.

For example, the fifth switching device Tr5 provided in the third A stage AST3 of FIG. 7 is turned on or turned off in response to a first AC voltage Vac1, and when turned on, the third switching device Tr5 is turned on. The common node N of the A stage AST3 is charged to the first AC voltage Vac1.

To this end, the gate terminal and the drain terminal of the fifth switching device Tr5 provided in the third A stage AST3 are connected to a power line for transmitting the first AC voltage Vac1, and the source terminal of the fifth A switching device Tr5. It is connected to common node N of 3A stage AST3.

The sixth switching device Tr6 of the 2n-1A stage is configured to respond to the second n−− voltage in response to the first DC voltage Vdc1 charged to the enabling node Q of the 2n-1A stage. The common node N of the 1A stage is discharged to the second DC voltage Vdc2.

For example, the sixth switching device Tr6 included in the third A stage AST3 of FIG. 7 may include the first DC voltage Vdc1 charged in the enabling node Q of the third A stage AST3. In response to), the common node N of the third A stage AST3 is discharged to the second DC voltage Vdc2.

To this end, the gate terminal of the sixth switching device Tr6 of the third A stage AST3 is connected to the enable node Q of the third A stage AST3, and the drain terminal of the third A stage AST3 is connected to the enable node Q. It is connected to the common node N of the 3A stage AST3, and the source terminal is connected to the power supply line which transmits the said 2nd DC voltage Vdc2.

The seventh switching element Tr7 included in the 2n-1A stage is configured to respond to the second n-1A in response to the first AC voltage Vac1 supplied to the common node N of the 2n-1A stage. The first disable node QB1 of the stage and the first disable node QB1 of the 2n A stage are charged to the first AC voltage Vac1.

That is, the seventh switching device Tr7 included in the 2n-1A stage is in the state of the first disable node QB1 provided in the 2n-1A stage and the first in the 2nA stage. The state of the disable node QB1 is controlled together.

For example, the seventh switching device Tr7 included in the third A stage AST3 of FIG. 7 is connected to the first AC voltage Vac1 supplied to the common node N of the third A stage AST3. In response, the first disable node QB1 of the third A stage AST3 and the first disable node QB1 of the fourth A stage AST4 are charged to the first AC voltage Vac1. .

To this end, the gate terminal of the seventh switching element Tr7 provided in the third A stage AST3 is connected to the common node N of the third A stage AST3, and the drain terminal is the first first alternating current. It is connected to a power line for transmitting voltage Vac1, and a source terminal is connected to a first disable node QB1 of the third A stage AST3.

The eighth switching device Tr8 of the 2n-1A stage includes the first disable node QB1 and the first disable node of the 2n-1A stage in response to the scan pulse from the 2n-3A stage. The first disable node QB1 of the 2n A stage is discharged to the second DC voltage Vdc2.

That is, the eighth switching device Tr8 of the 2n-1A stage is in the state of the first disable node QB1 of the 2n-1A stage and the first of the second nA stage. The state of the disable node QB1 is controlled together.

For example, the eighth switching device Tr8 of the third A stage AST3 of FIG. 7 may respond to the third A stage (Response to the first scan pulse Vout1 from the first A stage AST1). The first disable node QB1 of the AST3 and the first disable node QB1 of the fourth A stage AST4 are discharged to the second DC voltage Vdc2.

To this end, the gate terminal of the eighth switching device Tr8 of the third A stage AST3 is connected to the first A stage AST1, and the drain terminal of the third A stage AST3 is disposed. 1 is connected to the disable node (QB1), the source terminal is connected to the power line for transmitting the second DC voltage (Vdc2).

The ninth switching element Tr9 of the 2n-1A stage is configured to respond to the 2n−-th response in response to the first DC voltage Vdc1 charged to the enabling node Q of the 2n-1A stage. The first disable node QB1 of the first A stage and the first disable node QB1 of the 2n A stage are discharged to the second DC voltage Vdc2.

That is, the ninth switching device Tr9 provided in the 2n-1A stage is in the state of the first disable node QB1 provided in the 2n-1A stage and the second switch element provided in the 2nA stage. The state of the disable node QB1 is controlled together.

For example, the ninth switching device Tr9 included in the third A stage AST3 of FIG. 7 may include the first DC voltage Vdc1 charged in the enabling node Q of the third A stage AST3. ) Discharges the first disable node QB1 of the third A stage AST3 and the first disable node QB1 of the fourth A stage AST4 to the second DC voltage Vdc2 in response to. Let's do it.

To this end, the gate terminal of the ninth switching element Tr9 of the third A stage AST3 is connected to the enable node Q of the third A stage AST3, and the drain terminal of the third A stage AST3 is connected to the enable node Q. It is connected to the 1st disable node QB1 of the 3A stage AST3, and a source terminal is connected to the power supply line which transmits the said 2nd DC voltage Vdc2.

Meanwhile, the pull-up switching device Tru provided in the 2n-1A stage receives the corresponding clock pulse in response to the first DC voltage Vdc1 charged in the enable node Q of the 2n-1A stage. It outputs as 2n-1 scan pulse. This 2n-1 scan pulse is supplied to a 2n-1 gate line, a 2n + 1, and a 2n + 2A stage.

Here, the 2n-1 scan pulse output from the 2n-1A stage drives the 2n-1 gate line and simultaneously enables the 2n + 1 and 2n + 2 A stages.

For example, the pull-up switching device Tru provided in the third A stage AST3 of FIG. 7 may include the first DC voltage Vdc1 charged in the enabling node Q of the third A stage AST3. In response, the third clock pulse CLK3 is output as the third scan pulse Vout3. The third scan pulse Vout3 is supplied to the third gate line GL3, the fifth A stage AST5, and the sixth A stage AST6.

To this end, the gate terminal of the pull-up switching device Tru provided in the third A stage AST3 is connected to the enable node Q of the third A stage AST3, and the drain terminal of the third A stage AST3 is connected to the enable node Q. It is connected to a clock transmission line for transmitting three clock pulses CLK3, and a source terminal is connected to the third gate line GL3, the fifth A stage AST5, and the sixth A stage AST6.

The first pull-down switching device Trd1 included in the 2n-1A stage is configured to respond to a first AC voltage Vac1 charged in the first disable node QB1 of the 2n-1A stage. 2 DC voltage Vdc2 is output as an off voltage. The off voltage is supplied to the 2n-1 gate line, the 2n + 1, and the 2n + 2A stages.

For example, the first pull-down switching device Trd1 included in the third A stage AST3 of FIG. 7 may have a first AC voltage charged in the first disable node QB1 of the third A stage AST3. In response to Vac1, the second DC voltage Vdc2 is output as an off voltage, and the off voltage is supplied to the third gate line GL3, the fifth A stage AST5, and the sixth A stage AST6. do.

To this end, the gate terminal of the first pull-down switching device Trd1 provided in the third A stage AST3 is connected to the first disable node QB1 of the third A stage AST3, and the source terminal is provided. Is connected to a power line for transmitting the second DC voltage Vdc2, and a drain terminal is connected to the third gate line GL3, the fifth A stage AST5, and the sixth A stage AST6.

The second pull-down switching device Trd2 included in the 2n-1A stage is the second AC voltage Vac2 charged in the second disable node QB2 of the 2n-1A stage through the 2nA stage. ), The second DC voltage Vdc2 is output as the off voltage. The off voltage is supplied to the 2n-1 gate line, the 2n + 1, and the 2n + 2A stages.

That is, the second pull-down switching device Trd2 included in the 2n-1A stage responds to the second AC voltage Vac2 supplied to the second disable node QB2 of the 2n-1A stage. Outputting the second DC voltage Vdc2 at an off voltage, the state of the second disable node QB2 included in the 2n-1A stage is transmitted to the node controller 205 of the 2nA stage. Is controlled by

For example, the second pull-down switching device Trd2 included in the third A stage AST3 of FIG. 7 may have a second AC voltage charged in the second disable node QB2 of the third A stage AST3. In response to Vac2, the second DC voltage Vdc2 is output as an off voltage, and the off voltage is output to the third gate line GL3, the fifth A stage AST5, and the sixth A stage AST6. Supply.

To this end, the gate terminal of the second pull-down switching device Trd2 provided in the third A stage AST3 is connected to the second disable node QB2 of the third A stage AST3, and the source terminal is provided. Is connected to a power line for transmitting the second DC voltage Vdc2, and a drain terminal is connected to the third gate line GL3, the fifth A stage AST5, and the sixth A stage AST6.

However, since the A stage does not exist in the first front end of the first A stage AST1, the first and eighth switching elements Tr1 and Tr8 included in the first A stage AST1 are separated from the timing controller. It operates in response to the start pulse VAST.

Meanwhile, the node control unit 205 provided in even-numbered A stages AST2, AST4, AST6,... Also has first to ninth switching elements Tr1 to Tr9, as shown in FIG. 7. .

That is, the first switching device Tr1 provided in the 2n A stage may turn the enable node Q of the 2n A stage into a first DC voltage Vdc1 in response to a scan pulse from the 2n-3 A stage. )

For example, the first switching device Tr1 included in the fourth A stage AST4 of FIG. 7 may respond to the fourth A stage (Response to the first scan pulse Vout1 from the first A stage AST1). The enable node Q of the AST4 is charged to the first DC voltage Vdc1.

To this end, the gate terminal of the first switching device Tr1 provided in the fourth A stage AST4 is connected to the first A stage AST1, and the drain terminal transmits the first DC voltage Vdc1. The source terminal is connected to the enable node Q of the fourth A stage AST4.

The second switching device Tr2 provided in the 2n A stage responds to the first AC voltage Vac1 supplied to the first disable node QB1 of the 2n A stage through the 2n-1 A stage. The discharge node Q of the 2nA stage is discharged to the second DC voltage Vdc2.

That is, the second switching element Tr2 provided in the second nA stage may respond to the second AC voltage Vac1 supplied to the first disable node QB1 of the second nA stage. The enable node Q of the stage is discharged to the second DC voltage Vdc2, wherein the state of the first disable node QB1 provided in the 2n A stage is determined by the second n-1 A stage. It is controlled by the node control unit 205.

For example, the second switching device Tr2 included in the fourth A stage AST4 of FIG. 7 may be configured as a node for the first disable of the fourth A stage AST4 through the third A stage AST3. The enable node Q of the fourth A stage AST4 is discharged to the second DC voltage Vdc2 in response to the first AC voltage Vac1 supplied to QB1).

To this end, the gate terminal of the second switching element Tr2 provided in the fourth A stage AST4 is connected to the first disable node QB1 of the fourth A stage AST4, and the drain terminal is It is connected to the enabling node Q of the fourth A stage AST4, and a source terminal is connected to a power line for transmitting the second DC voltage Vdc2.

The third switching device Tr3 included in the second nA stage is configured to respond to the second AC voltage Vac2 supplied to the second disable node QB2 of the second nA stage. The enable node Q is discharged to the second DC voltage Vdc2.

For example, the third switching device Tr3 included in the fourth A stage AST4 of FIG. 7 has a second AC voltage supplied to the second disable node QB2 of the fourth A stage AST4. In response to Vac2, the enable node Q of the fourth A stage AST4 is discharged to the second DC voltage Vdc2.

To this end, the gate terminal of the third switching device Tr3 provided in the fourth A stage AST4 is connected to the second disable node QB2 of the fourth A stage AST4, and the drain terminal is provided. Is connected to the enable node Q of the fourth A stage AST4, and a source terminal is connected to a power line for transmitting the second DC voltage Vdc2.

The fourth switching device Tr4 included in the 2nA stage discharges the enable node Q to the second DC voltage Vdc2 in response to the scan pulse from the 2n + 2A stage.

For example, the fourth switching device Tr4 included in the fourth A stage AST4 of FIG. 7 may respond to the fourth A stage (Response to the sixth scan pulse Vout6 from the sixth A stage AST6). The enable node Q of the AST4 is discharged to the second DC voltage Vdc2.

To this end, a gate terminal of the fourth switching element Tr4 of the fourth A stage AST4 is connected to the sixth A stage AST6, and a drain terminal of the fourth A stage AST4 is connected to the gate terminal of the fourth A stage AST4. It is connected to the enable node Q, and a source terminal is connected to a power line for transmitting the second DC voltage Vdc2.

The fifth switching device Tr5 provided in the 2n A stage is turned on or off in response to a second AC voltage Vac2, and when turned on, the fifth switching element Tr5 is connected to the common node N of the 2n A stage. Charge to the second AC voltage Vac2.

For example, the fifth switching device Tr5 of the fourth A stage AST4 of FIG. 7 is turned on or turned off in response to a second AC voltage Vac2, and when turned on, the fourth switching device Tr5 is turned on. The common node N of the A stage AST4 is charged to the second AC voltage Vac2.

To this end, the gate terminal and the drain terminal of the fifth switching device Tr5 provided in the fourth A stage AST4 are connected to a power line for transmitting the second AC voltage Vac2, and the source terminal of the fourth terminal AAST4. The common node N of the fourth A stage AST4 is connected.

The sixth switching device Tr6 included in the 2nA stage is a common node of the 2nA stage in response to the first DC voltage Vdc1 charged in the enabling node Q of the 2nA stage. (N) is discharged to the second DC voltage Vdc2.

For example, the sixth switching element Tr6 included in the fourth A stage AST4 of FIG. 7 may include the first DC voltage Vdc1 charged in the enabling node Q of the fourth A stage AST4. In response to), the common node N of the fourth A stage AST4 is discharged to the second DC voltage Vdc2.

To this end, the gate terminal of the sixth switching element Tr6 of the fourth A stage AST4 is connected to the enable node Q of the fourth A stage AST4, and the drain terminal of the fourth A stage AST4. It is connected to the common node N of the 4A stage AST4, and the source terminal is connected to the power supply line which transmits the said 2nd DC voltage Vdc2.

The seventh switching device Tr7 included in the 2n A stage disables the second of the second n A stage in response to the second AC voltage Vac2 supplied to the common node N of the 2n A stage. The second node QB2 of the second node QB2 and the second n-1A stage is charged to the second AC voltage Vac2.

That is, the seventh switching device Tr7 included in the 2n A stage includes the state of the second disable node QB2 provided in the 2n A stage, and the second display provided in the 2n-1 A stage. The state of the enable node QB2 is controlled together.

For example, the seventh switching device Tr7 included in the fourth A stage AST4 of FIG. 7 is connected to the second AC voltage Vac2 supplied to the common node N of the fourth A stage AST4. In response, the second disable node QB2 of the fourth A stage AST4 and the second disable node QB2 of the third A stage AST3 are charged to the second AC voltage Vac2. .

To this end, the gate terminal of the seventh switching element Tr7 provided in the fourth A stage AST4 is connected to the common node N of the fourth A stage AST4, and the drain terminal of the second AC It is connected to a power supply line for transmitting the voltage Vac2, and a source terminal is connected to the second disable node QB2 of the fourth A stage AST4.

The eighth switching element Tr8 included in the 2nA stage includes the second disable node QB2 and the 2n-1A of the 2nn stage in response to the scan pulse from the 2n-3A stage. The second disable node QB2 of the stage is discharged to the second DC voltage Vdc2.

That is, the eighth switching device Tr8 included in the 2n A stage includes the state of the second disable node QB2 provided in the 2n A stage and the second display provided in the 2n-1 A stage. The state of the enable node QB2 is controlled together.

For example, the eighth switching device Tr8 of the fourth A stage AST4 of FIG. 7 may respond to the fourth A stage (Response to the first scan pulse Vout1 from the first A stage AST1). The second disable node QB2 of the AST4 and the second disable node QB2 of the third A stage AST3 are discharged to the second DC voltage Vdc2.

To this end, the gate terminal of the eighth switching element Tr8 of the fourth A stage AST4 is connected to the first A stage AST1, and the drain terminal of the third A stage AST3 is disposed. 2 is connected to the disable node (QB2), the source terminal is connected to the power line for transmitting the second DC voltage (Vdc2).

The ninth switching device Tr9 of the 2nA stage is configured to respond to the first DC voltage Vdc1 charged to the enabling node Q of the 2nA stage in response to the second DC voltage of the 2nA stage. The disable node QB2 and the second disable node QB2 of the 2n-1A stage are discharged to the second DC voltage Vdc2.

That is, the ninth switching device Tr9 provided in the 2n A stage includes the state of the second disable node QB2 provided in the 2n A stage and the second provided in the 2n-1 A stage. The state of the disable node QB2 is controlled together.

For example, the ninth switching device Tr9 included in the fourth A stage AST4 of FIG. 7 may include the first DC voltage Vdc1 charged in the enable node Q of the fourth A stage AST4. Discharges the second disable node QB2 of the fourth A stage AST4 and the second disable node QB2 of the third A stage AST3 to the second DC voltage Vdc2 in response to Let's do it.

To this end, the gate terminal of the ninth switching device Tr9 provided in the fourth A stage AST4 is connected to the enable node Q of the fourth A stage AST4, and the drain terminal of the fourth A stage AST4. It is connected to the 2nd disable node QB2 of the 4A stage AST4, and a source terminal is connected to the power supply line which transmits the said 2nd DC voltage Vdc2.

On the other hand, the pull-up switching device (Tru) provided in the 2n A stage is a clock pulse 2n scan pulse in response to the first DC voltage (Vdc1) charged in the enable node (Q) of the 2n A stage. Output as. The 2nn scan pulse is supplied to the 2nn gate line, the 2n-3, and the 2n-2A stage.

Here, the 2n scan pulse output from the 2n A stage drives the 2n gate line and simultaneously disables the 2n-3 and 2n-2 A stages.

For example, the pull-up switching device Tru provided in the fourth A stage AST4 of FIG. 7 may include the first DC voltage Vdc1 charged in the enabling node Q of the fourth A stage AST4. In response, the fourth clock pulse CLK4 is output to the fourth scan pulse Vout4. The fourth scan pulse Vout4 is supplied to the fourth gate line GL4, the first A stage AST1, and the second A stage AST2.

To this end, the gate terminal of the pull-up switching device Tru provided in the fourth A stage AST4 is connected to the enable node Q of the fourth A stage AST4, and the drain terminal of the fourth A stage AST4. It is connected to the clock transmission line for transmitting the clock pulse CLK4, and the source terminal is connected to the fourth gate line GL4, the first A stage AST1, and the second A stage AST2.

The first pull-down switching device Trd1 included in the 2nA stage is connected to the first AC voltage Vac1 charged in the first disable node QB1 of the 2nA stage through the 2n-1A stage. In response, the second direct current voltage Vdc2 is output as the off voltage. Then, the off voltage is supplied to the 2n gate line, the 2n-3, and the 2n-2A stage.

That is, the first pull-down switching device Trd1 included in the second nA stage may receive a second direct current in response to the first AC voltage Vac1 supplied to the first disable node QB1 of the second nA stage. The voltage Vdc2 is output as an off voltage, wherein the state of the first disable node QB1 included in the 2n A stage is controlled by the node controller 205 of the 2n-1 A stage.

For example, the first pull-down switching device Trd1 included in the fourth A stage AST4 of FIG. 7 is the first AC voltage charged in the first disable node QB1 of the fourth A stage AST4. In response to Vac1, the second DC voltage Vdc2 is output as an off voltage, and the off voltage is output to the fourth gate line GL4, the first A stage AST1, and the second A stage AST2. Supply.

To this end, the gate terminal of the first pull-down switching device Trd1 provided in the fourth A stage AST4 is connected to the first disable node QB1 of the fourth A stage AST4, and the source terminal thereof. Is connected to a power line for transmitting the second DC voltage Vdc2, and a drain terminal is connected to the fourth gate line GL4, the first A stage AST1, and the second A stage AST2.

The second pull-down switching device Trd2 provided in the 2n A stage includes a second DC voltage in response to the second AC voltage Vac2 charged in the second disable node QB2 of the 2n A stage. Vdc2) is output as an off voltage. Then, the off voltage is supplied to the 2n gate line, the 2n-3, and the 2n-2A stage.

For example, the second pull-down switching device Trd2 included in the fourth A stage AST4 of FIG. 7 has a second AC voltage charged in the second disable node QB2 of the fourth A stage AST4. In response to Vac2, the second DC voltage Vdc2 is output as an off voltage, and the off voltage is output to the fourth gate line GL4, the first A stage AST1, and the second A stage AST2. Supply.

To this end, the gate terminal of the second pull-down switching device Trd2 provided in the fourth A stage AST4 is connected to the second disable node QB2 of the fourth A stage AST4, and the source terminal thereof. Is connected to a power line for transmitting the second DC voltage Vdc2, and a drain terminal is connected to the fourth gate line GL4, the first A stage AST1, and the second A stage AST2.

However, since the A stage does not exist in the second front end of the second A stage AST2, the first and eighth switching elements Tr and Tr8 included in the second A stage AST2 are separated from the timing controller. It operates in response to the start pulse VAST.

FIG. 8 is a diagram illustrating a circuit configuration of a node controller provided in third and fourth B stages of the second shift register SR2 of FIG. 2.

Since the circuit configuration of the B stages provided in the second shift register SR2 also has the same circuit configuration as those of the A stages provided in the first shift register SR1 described above, description thereof will be omitted. That is, when the alphabet 'A stage' is changed to 'B stage' in the above description of the A stages, the B stages are described.

The operation of the first shift register SR1 according to the present invention configured as described above is as follows.

This will be described with reference to FIGS. 6 and 7.

First, the operation of the first initial period T0A in the first frame is as follows.

During the first frame, the first AC voltage Vac1 represents the positive polarity and the second AC voltage Vac2 represents the negative polarity.

During the first initial period T0A, as shown in FIG. 3, only the start pulse VAST output from the timing controller is kept high and the remaining clock pulses are kept low.

The start pulse VAST output from the timing controller is input to the first and second A stages AST1 and AST2.

That is, the start pulse VAST is supplied to the gate terminal of the first switching element Tr1 and the gate terminal of the eighth switching element Tr8 provided in the first A stage AST1.

Then, the first and eighth switching devices Tr1 and Tr8 are turned on, and at this time, the first DC voltage Vdc1 is enabled through the turned-on first switching device Tr1. Is applied. Accordingly, the enable node Q is charged, and the pull-up switching device Tru, the sixth switching device Tr6, and the ninth switching device having a gate terminal connected to the charged enable node Q. Element Tr9 is turned on.

Here, the second DC voltage Vdc2 is supplied to the first disable node QB1 through the turned-on eighth and ninth switching elements Tr8 and Tr9. Accordingly, the first switching node QB1 is discharged by the second DC voltage Vdc2, and the second switching element Tr2 having a gate terminal connected to the first disable node QB1 and The first pull-down switching device Trd1 is turned off.

On the other hand, since the first AC voltage Vac1 remains positive during the first frame, the fifth switching device Tr5 of the first A stage AST1 that receives the first AC voltage Vac1 is formed in the first frame. It stays on for 1 frame. The first AC voltage Vac1 is supplied to the common node N of the first A stage AST1 through the turned-on fifth switching element Tr5. In addition, a second DC voltage Vdc2 output through the turned-on sixth switching device Tr6 is also supplied to the common node N of the first A stage AST1. That is, the first AC voltage Vac1 of the positive polarity and the second DC voltage Vdc2 of the negative polarity are simultaneously supplied to the common node N of the first A stage AST1.

However, the channel width of the sixth switching device Tr6, which supplies the second DC voltage Vdc2, is set larger than the channel width of the fifth switching device Tr5, which supplies the first AC voltage Vac1. The common node N of the first A stage AST1 is maintained at the second DC voltage Vdc2. Therefore, the common node N is discharged, and the seventh switching element Tr7 of the first A stage AST1 having the gate terminal connected to the discharged common node N is turned off.

As described above, the first A stage AST1 charges its enable node Q and discharges its first disable node QB1 in response to the start pulse VAST. That is, the first A stage AST1 is enabled.

Meanwhile, in the first initial period T0A, the second A stage AST2 is also enabled by receiving the start pulse VAST. If this is explained in more detail as follows.

That is, the start pulse VAST is supplied to the gate terminal of the first switching element Tr1 and the gate terminal of the eighth switching element Tr8 provided in the second A stage AST2.

Then, the first and eighth switching devices Tr1 and Tr8 are turned on, and at this time, the first DC voltage Vdc1 is turned into the second A stage AST2 through the turned-on first switching device Tr1. Is applied to the enabling node Q. Accordingly, the enable node Q is charged, and the pull-up switching device Tru, the sixth switching device Tr6, and the ninth switching device having a gate terminal connected to the charged enable node Q. Element Tr9 is turned on.

Here, the second DC voltage Vdc2 is supplied to the second disable node QB2 of the second A stage AST2 through the turned-on eighth and ninth switching elements Tr8 and Tr9. Accordingly, the second switching node QB2 is discharged by the second DC voltage Vdc2, and the third switching device Tr3 having a gate terminal connected to the second disable node QB2, and The second pull-down switching device Trd2 is turned off.

On the other hand, since the second AC voltage Vac2 remains negative during the first frame, the fifth switching device Tr5 of the second A stage AST2 supplied with the second AC voltage Vac2 is formed in the second frame. It remains turned off for one frame.

The second DC voltage Vdc2 output through the turned-on sixth switching device Tr6 is supplied to the common node N of the second A stage AST2. Accordingly, the common node N of the second A stage AST2 is discharged by the second DC voltage Vdc2. Therefore, the seventh switching element Tr7 of the second A stage AST2 having the gate terminal connected to the discharged common node N is turned off.

As described above, in the first initial period T0A, the second A stage AST2 charges its enable node Q in response to the start pulse VAST and uses its own second disable. The node QB2 is discharged.

At this time, the first and second disable nodes QB1 and QB2 of the first A stage AST1 and the first and second disable nodes QB1 and QB2 of the second A stage AST2 are configured. Since they are electrically connected to each other, the second disable node QB2 of the first A stage AST1 is in the same state as the second disable node QB2 of the second A stage AST2. The first disable node QB1 of the second A stage AST2 has the same state as the first disable node QB1 of the first A stage AST1.

That is, the second disable node QB2 of the first A stage AST1 is applied to the second DC voltage Vdc2 supplied to the second disable node QB2 of the second A stage AST2. Indicates a discharge state. In addition, the first disable node QB1 of the second A stage AST2 is applied to the second DC voltage Vdc2 supplied to the first disable node QB1 of the first A stage AST1. Indicates a discharge state.

In other words, in the first initial period T0A, the first A stage AST1 charges its enable node Q, and its own first disable node QB1 and the second A stage. The first disable node QB1 of AST2 is discharged. In addition, in the first initial period T0A, the second A stage AST2 charges its enable node Q, and its own second disable node QB2 and the first A stage The second disable node QB2 of AST1 is discharged.

Next, the operation during the second initial period T0B will be described.

In the second initial period T0B, the start pulse VAST and all clock pulses remain low.

Accordingly, the first and second A stages AST2 maintain the enabled state for the second initial period TOB. On the other hand, since the start pulse VAST is changed to the low state in the second initial period T0B, the first and eighth switching elements Tr1 and Tr8 of the first and second A stages AST2 are turned on. The turn-off state is changed, whereby each enable node Q of the first and second A stages AST2 is maintained in a floating state. Therefore, in the first initial period T0A, the first DC voltage Vdc1 supplied to each of the enable nodes Q of the first and second A stages AST1 and AST2 is determined by each of the enable nodes. It remains in Q).

Next, the operation during the first period T1 will be described.

In the first period T1, only the first clock pulse CLK1 indicates a high state, and the remaining clock pulses maintain a low state.

Here, as the enable node Q of the first A stage AST1 is continuously charged by the first DC voltage Vdc1 applied during the first initial period T0A, the first A is maintained. The pull-up switching device Tru of the stage AST1 remains turned on. In this case, as the first clock pulse CLK1 is applied to the drain terminal of the turned-on pull-up switching device Tru, a first charged in the enable node Q of the first A stage AST1. The DC voltage Vdc1 is amplified by bootstrapping.

Therefore, the first clock pulse CLK1 applied to the drain terminal of the pull-up switching device Tru of the first A stage AST1 is stably output through the source terminal of the pull-up switching device Tru. In this case, the output first clock pulse CLK1 is applied to the first gate line GL1 and functions as a first scan pulse Vout1 for driving the first gate line GL1.

The first scan pulse Vout1 output from the first A stage AST1 in the first period T1 is also input to the third and fourth A stages AST3 and AST4. In detail, as illustrated in FIG. 4, the first scan pulse Vout1 may include gate terminals of the first and eighth switching devices Tr1 and Tr8 provided in the third A stage AST3. It is input to the gate terminals of the first and eighth switching elements Tr1 and Tr8 provided in the A stage AST4.

Therefore, in the first period T1, the third and fourth A stages AST3 and AST4 are enabled at the same time. In this case, the third A stage AST3 operates in the same manner as the first A stage AST1 during the first initial period T0A described above, and the fourth A stage AST4 operates in the first initial period described above. It operates in the same manner as the second A stage AST2 during (TOA).

That is, the third A stage AST3 charges its enable node Q, and the first disable node of its first disable node QB1 and the fourth A stage AST4. (QB1) is discharged. The fourth A stage AST4 charges its enable node Q, and has a second disable node QB2 and a second disable node of the third A stage AST3. (QB2) is discharged.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in FIG. 3, only the second clock pulse CLK2 remains high and the remaining clock pulses remain low.

The second clock pulse CLK2 is supplied to the enabled second A stage AST2. In detail, the second clock pulse CLK2 is supplied to the drain terminal of the pull-up switching device Tru provided in the second A stage AST2. Therefore, the pull-up switching device Tru provided in the second A stage AST2 outputs the second clock pulse CLK2 as the second scan pulse Vout2. The second scan pulse Vout2 is supplied to the second gate line GL2 to drive the second gate line GL2.

Next, the operation during the third period T3 will be described.

During the third period T3, as shown in FIG. 3, only the third clock pulse CLK3 remains high and the remaining clock pulses remain low.

The third clock pulse CLK3 is supplied to the enabled third A stage AST3. Specifically, the third clock pulse CLK3 is supplied to the drain terminal of the pull-up switching device Tru provided in the third A stage AST3. Accordingly, the pull-up switching device Tru provided in the third A stage AST3 outputs the third clock pulse CLK3 as a third scan pulse Vout3. The third scan pulse Vout3 is supplied to the third gate line GL3, the fifth A stage AST5, and the sixth A stage AST6.

That is, the third scan pulse Vout3 drives the third gate line GL3 and simultaneously enables the fifth and sixth A stages AST6.

Next, the operation during the fourth period T4 will be described.

During the fourth period T4, as shown in FIG. 4, only the fourth clock pulse CLK4 remains high and the remaining clock pulses remain low.

The fourth clock pulse CLK4 is supplied to the enabled fourth A stage AST4. Specifically, the fourth clock pulse CLK4 is supplied to the drain terminal of the pull-up switching device Tru provided in the fourth A stage AST4. Therefore, the pull-up switching device Tru provided in the fourth A stage AST4 outputs the fourth clock pulse CLK4 as a fourth scan pulse Vout4. The fourth scan pulse Vout4 is supplied to the fourth gate line GL4, the first A stage AST1, and the second A stage AST2.

That is, the fourth scan pulse Vout4 drives the fourth gate line GL4 and simultaneously disables the first and second A stages AST2. This disable operation will be described in more detail as follows.

That is, the fourth scan pulse Vout4 output from the fourth A stage AST4 in the fourth period T4 is supplied to the first A stage AST1. In detail, the fourth scan pulse Vout4 is supplied to the gate terminal of the fourth switching device Tr4 provided in the first A stage AST1. Then, the fourth switching device Tr4 is turned on, and the second DC voltage Vdc2 is enabled for the node of the first A stage AST1 through the turned-on fourth switching device Tr4. It is supplied to (Q).

Accordingly, the enable node Q is discharged, and the pull-up switching device Tru and the sixth switching device of the first A stage AST1 having a gate terminal connected to the discharged enabling node Q are discharged. Tr6) and the ninth switching element Tr9 are both turned off.

As the sixth switching device Tr6 is turned off, the first AC voltage Vac1 output through the fifth switching device Tr5 is supplied to the common node N of the first A stage AST1. do. Accordingly, the seventh switching element Tr7 of the first A stage AST1, in which the common node N of the first A stage AST1 is charged, and whose gate terminal is connected to the charged common node N, is charged. ) Is turned on.

The first AC voltage Vac1 is supplied to the first disable node QB1 of the first A stage AST1 through the turned-on seventh switching device Tr7. Then, the first disable node QB1 of the first A stage AST1 is charged, and the first A stage AST1 of which the gate terminal is connected to the charged first disable node QB1. The first pull-down switching device Trd1 and the second switching device Tr2 are turned on. The second switching device Tr2 further accelerates the discharge of the enable node Q by supplying a second DC voltage Vdc2 to the enable node Q of the first A stage AST1. Let's do it.

As described above, the pull-up switching device Tru of the first A stage AST1 is turned off and the first pull-down switching device Trd1 is turned on for the fourth period T4, whereby the first A stage ( AST1 outputs a second DC voltage Vdc2 through the turned-on first pull-down switching device Trd1. The second DC voltage Vdc2 is supplied to the first gate line GL1 and functions as an off voltage for deactivating the first gate line GL1.

In summary, the first A stage AST1 discharges its enable node Q and charges its first disable node QB1 in response to the fourth scan pulse Vout4. . That is, the first A stage AST1 is disabled. At this time, the second disable node QB2 of the first A stage AST1 maintains the discharge state in the first initial period T0A.

Meanwhile, the second A stage AST2 also receives the fourth scan pulse Vout4 in the fourth period T4 and is disabled. If this is explained in more detail as follows.

That is, the fourth scan pulse Vout4 output from the fourth A stage AST4 in the fourth period T4 is supplied to the second A stage AST2. In detail, the fourth scan pulse Vout4 is supplied to the gate terminal of the fourth switching device Tr4 provided in the second A stage AST2. Then, the fourth switching device Tr4 is turned on, and the second DC voltage Vdc2 is enabled for the second A stage AST2 through the turned-on fourth switching device Tr4. It is supplied to (Q).

Accordingly, the enable node Q is discharged, and the pull-up switching device Tru and the sixth switching device of the second A stage AST2 having the gate terminal connected to the discharged enabling node Q are connected. Tr6) and the ninth switching element Tr9 are both turned off.

The fifth switching element Tr5 of the second A stage AST2 supplied with the second AC voltage Vac2 maintains a turn-off state.

Meanwhile, since the state of the first disable node QB1 included in the second A stage AST2 is controlled by the node controller 205 provided in the first A stage AST1, the second A stage AST2 is controlled. The state of the first disable node QB1 included in the stage AST2 is the same as that of the first disable node QB1 of the first A stage AST1.

That is, as described above, since the first disable node QB1 of the first A stage AST1 is charged in the fourth period T4, the first disable of the second A stage AST2 is performed. The dragon node QB1 is also charged.

In addition, since the state of the second disable node QB2 included in the first A stage AST1 is controlled by the node controller 205 included in the second A stage AST2, the first A The state of the second disable node QB2 provided in the stage AST1 is the same as that of the second disable node QB2 provided in the second A stage AST2.

That is, since the second disable node QB2 of the second A stage AST2 still shows a discharge state in the fourth period T4, the first A stage (A) in the fourth period T4. The second disable node QB2 of AST1 also shows a discharge state.

Therefore, in the fourth period T4, the enable node Q of the first and second A stages AST1 and AST2 indicates a discharge state, and the first and second A stages AST1 and AST2. The first disable node QB1 of FIG. 2 indicates a charging state, and the second disable node QB2 of the first and second A stages AST1 and AST2 represents a discharge state.

As a result, in the fourth period T4, each pull-up switching device Tru of the first and second A stages AST1 and AST2 is turned off, and the first and second A stages AST1 and AST2 are turned off. Each of the first pull-down switching devices Trd1 of) is first turned on, and each of the second pull-down switching devices Trd2 of the first and second A stages AST1 and AST2 is turned off.

Accordingly, in the fourth period T4, the first A stage AST1 supplies the second DC voltage Vdc2 as an off voltage to the first gate line GL1, and the second A stage AST2. Supplies a second DC voltage Vdc2 to the second gate line GL2 as an off voltage.

Thereafter, in the fifth period T5, the enabled fifth A stage AST5 outputs the fifth clock pulse CLK5 as the fifth scan pulse Vout5, and outputs the fifth scan pulse Vout5 to the fifth period. The gate line GL5 is supplied to the seventh A stage and the eighth A stage.

Next, in the sixth period T6, the enabled sixth A stage AST6 outputs the sixth clock pulse as the sixth scan pulse Vout6, and outputs the sixth scan pulse Vout6 to the sixth gate line. It supplies to GL6, 3rd A stage AST3, and 4th A stage AST4.

In this way, the remaining A stages operate.

Thereafter, since the first AC voltage Vac1 is kept negative and the second AC voltage Vac2 is positive in the second frame, each of the A stages AST1, AST2, AST3,. The first disable node QB1 of ..) is discharged, and the second disable node QB2 is charged. That is, the first pull-down switching device Trd1 of each of the A stages AST1, AST2, AST3,... Is turned off and the second pull-down switching device Trd2 is turned on in the second frame.

Another operation of the shift register according to the first embodiment of the present invention configured as described above is as follows.

This will be described with reference to FIGS. 3 and 6.

First, the operation of the first initial period T0A in the first frame is as follows.

During the first frame, the first AC voltage Vac1 represents the positive polarity and the second AC voltage Vac2 represents the negative polarity.

During the first initial period T0A, as shown in FIG. 3, only the start pulse VAST output from the timing controller is kept high and the remaining clock pulses are kept low.

The start pulse VAST output from the timing controller is input to the first and second A stages AST1 and AST2.

That is, the start pulse VAST is supplied to the gate terminal of the first switching element Tr1 and the gate terminal of the sixth switching element Tr6 provided in the first A stage AST1.

Then, the first and sixth switching elements Tr1 and Tr6 are turned on, and at this time, the first DC voltage Vdc1 is enabled through the turned-on first switching element Tr1. ) Is applied. Accordingly, the enable node Q is charged, and the pull-up switching device Tru and the seventh switching device Tr7 having a gate terminal connected to the charged enable node Q are turned on. .

Here, the second DC voltage Vdc2 is supplied to the first disable node QB1 through the turned-on sixth and seventh switching elements Tr6 and Tr7. Accordingly, the first switching node QB1 is discharged by the second DC voltage Vdc2, and the second switching element Tr2 having a gate terminal connected to the first disable node QB1 and The first pull-down switching device Trd1 is turned off. The turned-on second switching device Tr2 further accelerates the discharge of the enable node Q by supplying a second DC voltage Vdc2 to the enable node Q.

On the other hand, since the first AC voltage Vac1 remains positive during the first frame, the fifth switching device Tr5 of the first A stage AST1 that receives the first AC voltage Vac1 is formed in the first frame. It stays on for 1 frame. The first AC voltage Vac1 is supplied to the first disable node QB1 of the first A stage AST1 through the turned-on fifth switching element Tr5.

As described above, the second DC voltage Vdc2 output through the turned-on sixth and seventh switching elements Tr7 to the first disable node QB1 of the first A stage AST1. ) Is also supplied. That is, the first AC node Vac1 having the positive polarity and the second DC voltage Vdc2 having the negative polarity are simultaneously supplied to the first disable node QB1 of the first A stage AST1.

However, since the number of switching elements Tr6 and Tr7 for supplying the second DC voltage Vdc2 is greater than the number of switching elements Tr5 for supplying the first AC voltage Vac1, the first A The first disable node QB1 of the stage AST1 is maintained at the second DC voltage Vdc2. Therefore, the first disable node QB1 is discharged.

In this manner, the first A stage AST1 charges its enable node Q and discharges its first disable node QB1 in response to the start pulse VAST. That is, the first A stage AST1 is enabled.

Meanwhile, in the first initial period T0A, the second A stage AST2 is also enabled by receiving the start pulse VAST. If this is explained in more detail as follows.

That is, the start pulse VAST is supplied to the gate terminal of the first switching element Tr1 and the gate terminal of the sixth switching element Tr6 provided in the second A stage AST2.

Then, the first and sixth switching elements Tr1 and Tr6 are turned on, and at this time, the first DC voltage Vdc1 is converted to the second A stage AST2 through the turned-on first switching element Tr1. Is applied to the enabling node Q. Accordingly, the enable node Q is charged, and the pull-up switching device Tru and the seventh switching device Tr7 having a gate terminal connected to the charged enable node Q are turned on. .

Here, the second DC voltage Vdc2 is supplied to the second disable node QB2 of the second A stage AST2 through the turned-on sixth and seventh switching elements Tr6 and Tr7. Accordingly, the second switching node QB2 is discharged by the second DC voltage Vdc2, and the third switching device Tr3 having a gate terminal connected to the second disable node QB2, and The second pull-down switching device Trd2 is turned off.

On the other hand, since the second AC voltage Vac2 remains negative during the first frame, the fifth switching device Tr5 of the second A stage AST2 supplied with the second AC voltage Vac2 is formed in the second frame. It remains turned off for one frame.

As described above, in the first initial period T0A, the second A stage AST2 charges its enable node Q in response to the start pulse VAST and uses its own second disable. The node QB2 is discharged.

At this time, the first and second disable nodes QB1 and QB2 of the first A stage AST1 and the first and second disable nodes QB1 and QB2 of the second A stage AST2 are configured. Since they are electrically connected to each other, the second disable node QB2 of the first A stage AST1 is in the same state as the second disable node QB2 of the second A stage AST2. The first disable node QB1 of the second A stage AST2 has the same state as the first disable node QB1 of the first A stage AST1.

That is, the second disable node QB2 of the first A stage AST1 is applied to the second DC voltage Vdc2 supplied to the second disable node QB2 of the second A stage AST2. Indicates a discharge state. In addition, the first disable node QB1 of the second A stage AST2 is applied to the second DC voltage Vdc2 supplied to the first disable node QB1 of the first A stage AST1. Indicates a discharge state.

In other words, in the first initial period T0A, the first A stage AST1 charges its enable node Q, and its own first disable node QB1 and the second A stage. The first disable node QB1 of AST2 is discharged. In addition, in the first initial period T0A, the second A stage AST2 charges its enable node Q, and has its own second disable node QB2 and the second A stage. The second disable node QB2 of AST2 is discharged.

Next, the operation during the second initial period T0B will be described.

In the second initial period T0B, the start pulse VAST and all clock pulses remain low.

Accordingly, the first and second A stages AST2 maintain the enabled state for the second initial period TOB. Meanwhile, since the start pulse VAST is changed to the low state in the second initial period T0B, the first and sixth switching elements Tr1 and Tr6 of the first and second A stages AST2 are turned off. The turn-off state is changed, whereby each enable node Q of the first and second A stages AST2 is maintained in a floating state. Therefore, in the first initial period T0A, the first DC voltage Vdc1 supplied to each of the enable nodes Q of the first and second A stages AST1 and AST2 is determined by each of the enable nodes. It remains in Q).

Next, the operation during the first period T1 will be described.

In the first period T1, only the first clock pulse CLK1 indicates a high state, and the remaining clock pulses maintain a low state.

Here, as the enable node Q of the first A stage AST1 is continuously charged by the first DC voltage Vdc1 applied during the first initial period T0A, the first A is maintained. The pull-up switching device Tru of the stage AST1 remains turned on. In this case, as the first clock pulse CLK1 is applied to the drain terminal of the turned-on pull-up switching device Tru, a first charged in the enable node Q of the first A stage AST1. The DC voltage Vdc1 is amplified by bootstrapping.

Therefore, the first clock pulse CLK1 applied to the drain terminal of the pull-up switching device Tru of the first A stage AST1 is stably output through the source terminal of the pull-up switching device Tru. In this case, the output first clock pulse CLK1 is applied to the first gate line GL1 and functions as a first scan pulse Vout1 for driving the first gate line GL1.

The first scan pulse Vout1 output from the first A stage AST1 in the first period T1 is also input to the third and fourth A stages AST3 and AST4. In detail, as illustrated in FIG. 6, the first scan pulse Vout1 may include gate terminals of the first and sixth switching devices Tr1 and Tr6 provided in the third A stage AST3, and a fourth terminal. It is input to the gate terminals of the first and sixth switching elements Tr1 and Tr6 provided in the A stage AST4.

Therefore, in the first period T1, the third and fourth A stages AST3 and AST4 are enabled at the same time. In this case, the third A stage AST3 operates in the same manner as the first A stage AST1 during the first initial period T0A described above, and the fourth A stage AST4 operates in the first initial period described above. It operates in the same manner as the second A stage AST2 during (TOA).

That is, the third A stage AST3 charges its enable node Q, and the first disable node of its first disable node QB1 and the fourth A stage AST4. (QB1) is discharged. The fourth A stage AST4 charges its enable node Q, and has a second disable node QB2 and a second disable node of the third A stage AST3. (QB2) is discharged.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in FIG. 3, only the second clock pulse CLK2 remains high and the remaining clock pulses remain low.

The second clock pulse CLK2 is supplied to the enabled second A stage AST2. In detail, the second clock pulse CLK2 is supplied to the drain terminal of the pull-up switching device Tru provided in the second A stage AST2. Therefore, the pull-up switching device Tru provided in the second A stage AST2 outputs the second clock pulse CLK2 as the second scan pulse Vout2. The second scan pulse Vout2 is supplied to the second gate line GL2 to drive the second gate line GL2.

Next, the operation during the third period T3 will be described.

During the third period T3, as shown in FIG. 3, only the third clock pulse CLK3 remains high and the remaining clock pulses remain low.

The third clock pulse CLK3 is supplied to the enabled third A stage AST3. Specifically, the third clock pulse CLK3 is supplied to the drain terminal of the pull-up switching device Tru provided in the third A stage AST3. Accordingly, the pull-up switching device Tru provided in the third A stage AST3 outputs the third clock pulse CLK3 as a third scan pulse Vout3. The third scan pulse Vout3 is supplied to the third gate line GL3, the fifth A stage AST5, and the sixth A stage AST6.

That is, the third scan pulse Vout3 drives the third gate line GL3 and enables the fifth and sixth A stages AST5 and AST6 simultaneously.

Next, the operation during the fourth period T4 will be described.

During the fourth period T4, as shown in FIG. 3, only the fourth clock pulse CLK4 remains high and the remaining clock pulses remain low.

The fourth clock pulse CLK4 is supplied to the enabled fourth A stage AST4. Specifically, the fourth clock pulse CLK4 is supplied to the drain terminal of the pull-up switching device Tru provided in the fourth A stage AST4. Therefore, the pull-up switching device Tru provided in the fourth A stage AST4 outputs the fourth clock pulse CLK4 as a fourth scan pulse Vout4. The fourth scan pulse Vout4 is supplied to the fourth gate line GL4, the first A stage AST1, and the second A stage AST2.

That is, the fourth scan pulse Vout4 drives the fourth gate line GL4 and simultaneously disables the first and second A stages AST1 and AST2. This disable operation will be described in more detail as follows.

That is, the fourth scan pulse Vout4 output from the fourth A stage AST4 in the fourth period T4 is supplied to the first A stage AST1. In detail, the fourth scan pulse Vout4 is supplied to the gate terminal of the fourth switching device Tr4 provided in the first A stage AST1. Then, the fourth switching device Tr4 is turned on, and the second DC voltage Vdc2 is enabled for the node of the first A stage AST1 through the turned-on fourth switching device Tr4. It is supplied to (Q).

Accordingly, the enable node Q is discharged, and the pull-up switching device Tru and the seventh switching device of the first A stage AST1 having a gate terminal connected to the discharged enabling node Q are discharged. Tr7) are all turned off.

Meanwhile, since the fifth switching device Tr5 of the first A stage AST1 is turned on for one frame by the first AC voltage Vac1, the turned-on fifth switching device Tr5 is turned on. The first alternating voltage Vac1 is supplied to the first disable node QB1 of the first A stage AST1 through X1). Accordingly, the first disable node QB1 of the first A stage AST1 is charged and the first pull-down of the first A stage AST1 connected to the charged first disable node QB1 is performed. The switching element Trd1 and the second switching element Tr2 are turned on. The second switching device Tr2 accelerates the discharge of the enable node Q by supplying a second DC voltage Vdc2 to the enable node Q of the first A stage AST1.

As described above, the pull-up switching device Tru of the first A stage AST1 is turned off and the first pull-down switching device Trd1 is turned on for the fourth period T4, whereby the first A stage ( AST1 outputs a second DC voltage Vdc2 through the turned-on first pull-down switching device Trd1. The second DC voltage Vdc2 is supplied to the first gate line GL1 and functions as an off voltage for deactivating the first gate line GL1.

In other words, the first A stage AST1 discharges its enable node Q in response to the fourth scan pulse Vout4 and charges its first disable node QB1. . That is, the first A stage AST1 is disabled. At this time, the second disable node QB2 of the first A stage AST1 maintains the discharge state in the first initial period T0A.

Meanwhile, the second A stage AST2 also receives the fourth scan pulse Vout4 in the fourth period T4 and is disabled. If this is explained in more detail as follows.

That is, the fourth scan pulse Vout4 output from the fourth A stage AST4 in the fourth period T4 is supplied to the second A stage AST2. In detail, the fourth scan pulse Vout4 is supplied to the gate terminal of the fourth switching device Tr4 provided in the second A stage AST2. Then, the fourth switching device Tr4 is turned on, and the second DC voltage Vdc2 is enabled for the second A stage AST2 through the turned-on fourth switching device Tr4. It is supplied to (Q).

Accordingly, the enable node Q is discharged, and the pull-up switching device Tru and the seventh switching device of the second A stage AST2 having the gate terminal connected to the discharged enable node Q are connected. Tr7) are all turned off.

The fifth switching element Tr5 of the second A stage AST2 supplied with the second AC voltage Vac2 maintains a turn-off state.

Meanwhile, since the state of the first disable node QB1 included in the second A stage AST2 is controlled by the node controller 205 provided in the first A stage AST1, the second A stage AST2 is controlled. The state of the first disable node QB1 included in the stage AST2 is the same as that of the first disable node QB1 of the first A stage AST1.

That is, as described above, since the first disable node QB1 of the first A stage AST1 is charged in the fourth period T4, the first disable of the second A stage AST2 is performed. The dragon node QB1 is also charged.

In addition, since the state of the second disable node QB2 included in the first A stage AST1 is controlled by the node controller 205 included in the second A stage AST2, the first A The state of the second disable node QB2 provided in the stage AST1 is the same as that of the second disable node QB2 provided in the second A stage AST2.

That is, since the second disable node QB2 of the second A stage AST2 still shows a discharge state in the fourth period T4, the first A stage (A) in the fourth period T4. The second disable node QB2 of AST1 also shows a discharge state.

Therefore, in the fourth period T4, the enabling node Q of the first and second A stages AST2 indicates a discharge state, and the first and second A stages AST1 and AST2 are connected. The first disable node QB1 represents a charged state, and the second disable node QB2 of the first and second A stages AST1 and AST2 represents a discharge state.

As a result, in the fourth period T4, each pull-up switching device Tru of the first and second A stages AST1 and AST2 is turned off, and the first and second A stages AST1 and AST2 are turned off. Each of the first pull-down switching devices Trd1 of) is first turned on, and each of the second pull-down switching devices Trd2 of the first and second A stages AST1 and AST2 is turned off.

Accordingly, in the fourth period T4, the first A stage AST1 supplies the second DC voltage Vdc2 as an off voltage to the first gate line GL1, and the second A stage AST2. Supplies a second DC voltage Vdc2 to the second gate line GL2 as an off voltage.

Thereafter, in the fifth period T5, the enabled fifth A stage AST5 outputs the fifth clock pulse CLK5 as the fifth scan pulse Vout5, and outputs the fifth scan pulse Vout5 to the fifth period. The gate line GL5 is supplied to the seventh A stage and the eighth A stage.

Next, in the sixth period T6, the enabled sixth A stage AST6 outputs the sixth clock pulse as the sixth scan pulse Vout6, and outputs the sixth scan pulse Vout6 to the sixth gate line. It supplies to GL6, 3rd A stage AST3, and 4th A stage AST4.

In this way, the remaining A stages operate.

Thereafter, in the second frame, the first AC voltage Vac1 is maintained as negative and the second AC voltage Vac2 is maintained as positive, so that the respective A stages AST1, AST2, AST3, .. The first disable node QB1 of.) Is discharged, and the second disable node QB2 is charged. That is, the first pull-down switching device Trd1 of each of the A stages AST1, AST2, AST3,... Is turned off and the second pull-down switching device Trd2 is turned on in the second frame.

Meanwhile, the operations of the B stages provided in the second shift register SR2 are also the same as the operations of the A stages described above.

At this time, since the A stage and the B stage connected to the same gate line are supplied with different AC voltages, scan pulses having different output characteristics are simultaneously supplied to one gate line. For example, a first scan pulse having a relatively high polling time point output from the first A stage is supplied to one side of the first gate line GL1, and a first B stage to the other side of the first gate line GL1. Since the first scan pulse having a relatively late polling point outputted from the second source is supplied, the first gate line GL1 is supplied with a combined scan pulse in which two different output pulses are combined. At this time, this synthesized scan pulse has a characteristic in which the characteristics of the first scan pulse provided from the first A stage and the characteristics of the first scan pulse provided from the first B stage are combined. The scan pulses having the same characteristics as the scan pulses supplied to the first gate line GL1 described above are also supplied to the remaining odd-numbered gate lines.

As another example, a second scan pulse having a relatively late polling time output from the second stage A is supplied to one side of the second gate line GL2, and the second B is supplied to the other side of the second gate line GL2. Since the second scan pulse having a relatively fast polling time output from the stage is supplied, the second gate line GL2 is supplied with a composite scan pulse in which scan pulses having two different output characteristics are combined. At this time, the synthesized scan pulse has a characteristic in which the characteristics of the second scan pulse provided from the second A stage and the characteristics of the second scan pulse provided from the second B stage are combined. Scan pulses having the same characteristics as the scan pulses supplied to the second gate line GL2 described above are also supplied to the remaining even-numbered gate lines.

In this way, since the remaining gate lines are also supplied with two scan pulses having different characteristics, all the gate lines GL1, GL2, GL3, ... are all charged under the same conditions. Therefore, it is possible to prevent the charge variation between the gate lines.

9 is a diagram illustrating a shift register according to a second embodiment of the present invention.

As shown in FIG. 9, the shift register according to the second exemplary embodiment of the present invention is located at one side of the gate lines GL1, GL2, GL3,..., And the gate lines GL1, GL2, GL3. The first shift register SR1 sequentially supplies scan pulses to one side of the ..., and the other side of the gate lines GL1, GL2, GL3,... And a second shift register SR2 which sequentially supplies scan pulses to the other sides of GL1, GL2, GL3, ...).

The first shift register SR1 is connected to one side of the gate lines GL1, GL2, GL3,... And sequentially scans one side of the gate lines GL1, GL2, GL3,... It includes a number of A stages that supply pulses. In addition, the second shift register SR2 is connected to the other side of the gate lines GL1, GL2, GL3,..., And sequentially to the other side of the gate lines GL1, GL2, GL3,. It includes a number of B stages supplying scan pulses.

The 2n-1st A stages of the A stages provided in the first shift register SR1 are supplied with the first AC voltage, and the 2nth A stages are supplied with the first AC voltage. The 2n-1st B stages of the B stages provided in the second shift register SR2 are supplied with the first AC voltage, and the 2nth B stages are supplied with the second AC voltage. In particular, the 2nth A stage of the first shift register SR1 supplies the scan pulse to one side of the nth gate line, and the 2n-1st B stage of the second shift register SR2 is the other side of the nth gate line. The supply of scan pulses to the second feature is the greatest feature in the second embodiment.

Since the configuration of each A stage is the same as that in the above-described first embodiment, description thereof will be omitted.

On the other hand, the scan pulse from the first A stage of the A stages and the scan pulse from the last B stage of the B stages are not supplied to the gate line.

10 is a diagram illustrating a shift register according to a third embodiment of the present invention.

The shift register according to the third embodiment of the present invention includes a plurality of stages ST1, ST2, ST3, ... as shown in FIG.

At this time, the circuit configuration of each stage ST1, ST2, ST3, ... provided in the shift register is the same as that of the A stage or B stage in the above-described first embodiment.

That is, each stage ST1, ST2, ST3, ... is an enable node; A pull-up switching device configured to output the scan pulse according to a logic state of the enable node; At least two nodes for disabling; At least two pull-down switching elements connected to each of the disable nodes and outputting an off voltage according to a logic state of each of the disable nodes; And a node control unit for controlling the logical states of the enable node and the disable nodes provided in the same and the logical states of the disable node provided in the A stage different from the self node.

At this time, the node control unit provided in the stage connected to an arbitrary gate line may be configured to use the logic state of the enable node and the disable node provided therein by using any one of the first AC voltage and the second AC voltage, It also controls the logic state of the disabling node included in the other stage with itself. In particular, the first feature of the third embodiment is that the first AC voltage and the second AC voltage are randomly supplied to the stages ST1, ST2, ST3, .... However, the nth stage and the n-1th stage are supplied with different AC voltages.

For example, as shown in FIG. 10, the first stage ST1 receives the first AC voltage Vac1, the second stage ST2 receives the second AC voltage Vac2, and the third stage ST1. The stage ST3 is supplied with the second AC voltage Vac2, the fourth stage ST4 is supplied with the first AC voltage Vac1, and the fifth stage ST5 is supplied with the first AC voltage Vac1. The sixth stage ST6 receives the second AC voltage Vac2. As such, by randomly supplying one of the first and second AC voltages Vac1 and Vac3 to the stays ST1, ST2, ST3,..., Scan pulses having different output characteristics are randomly applied to each gate line. Is supplied. Accordingly, the image quality can be improved by eliminating the vertical dim phenomenon caused by the specific regularity.

11 is a view for explaining the effect of the shift register according to the first embodiment of the present invention, it can be seen that the polling time of the scan pulse from the shift register according to the first embodiment of the present invention is lower than in the prior art .

12 is a view for explaining the effect of the shift register according to the second embodiment of the present invention, it can be seen that the polling time of the scan pulse from the shift register according to the second embodiment of the present invention is lower than in the prior art.

The output characteristics of the scan pulses supplied to the odd-numbered gate lines and the output characteristics of the scan pulses supplied to the even-numbered gate lines are different from the conventional shift registers. Specifically, the rising time of the scan pulses supplied to the odd-numbered gate lines is about 2.08usec, and the falling time of the scan pulses supplied to the even-numbered gate lines is about 2.06usec. However, the falling time of the scan pulses supplied to the odd-numbered gate lines and the falling time of the scan pulses supplied to the even-numbered gate lines were 4.63usec, and the variation was quite high. However, the rising time of the scan pulse supplied to the even-numbered gate line from the shift register according to the first embodiment of the present invention is about 2.09usec, and the rising time of the scan pulse supplied to the even-numbered gate line is also about 2.07usec. There was almost no difference, and the polling time of the scan pulses supplied to the odd-numbered gate lines was 2.21usec, and the polling time of the scan pulses supplied to the even-numbered gate lines was 2.21usec.

In addition, the rising time of the scan pulse supplied to the even-numbered gate line from the shift register according to the second embodiment of the present invention is about 2.07usec, and the rising time of the scan pulse supplied to the even-numbered gate line is about 2.07usec. Also, the polling time of the scan pulses supplied to the odd-numbered gate lines was 2.63usec, and the polling time of the scan pulses supplied to the even-numbered gate lines was 2.63usec.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a diagram showing voltage waveforms and scan pulse waveforms of an enable node in odd-numbered stages, voltage waveforms and scan pulse waveforms of an enable node in even-numbered stages.

FIG. 2 is a diagram for comparing waveforms of scan pulses output from the odd stage of FIG. 1 and output characteristics of the scan pulses output from the even stage;

3 illustrates a shift register according to a first embodiment of the present invention.

4 is a diagram illustrating a configuration of stages included in a first shift register of FIG. 3.

5 is a diagram illustrating a configuration of stages included in the second shift register of FIG. 4.

FIG. 6 is a diagram illustrating waveforms of an input signal supplied to each stage of FIG. 2 and an output signal output from each stage.

FIG. 7 is a diagram illustrating a circuit configuration of a node controller provided in third and fourth A stages of the first shift register of FIG. 2. FIG.

8 is a diagram illustrating a circuit configuration of a node controller provided in third and fourth B stages of the second shift register of FIG. 2.

9 illustrates a shift register according to a second embodiment of the present invention.

10 illustrates a shift register according to a third embodiment of the present invention.

11 is a view for explaining the effect of the shift register according to the first embodiment of the present invention;

12 is a diagram for explaining the effect of a shift register according to a second embodiment of the present invention;

Claims (10)

A first shift register sequentially supplying scan pulses to one side of the gate lines; A second shift register sequentially supplying scan pulses to the other sides of the gate lines; At least one A stage included in the first shift register includes an enable node; A pull-up switching device configured to output the scan pulse according to a logic state of the enable node; At least two nodes for disabling; At least two pull-down switching elements connected to each of the disable nodes and outputting an off voltage according to a logic state of each of the disable nodes; A node control unit for controlling the logic states of the enable node and the disable nodes provided in the same and the logical states of the disable node included in the stage different from the self; At least one B stage provided in the second shift register comprises: an enabling node; A pull-up switching device configured to output the scan pulse according to a logic state of the enable node; At least two nodes for disabling; At least two pull-down switching elements connected to each of the disable nodes and outputting an off voltage according to a logic state of each of the disable nodes; A node control unit for controlling the logic states of the enable node and the disable nodes provided in the same and the logical states of the disable node included in the stage different from the self; The node control unit provided in the A stage of the first shift register connected to an arbitrary gate line may use the first AC voltage to determine the logic states of the enable node and the disable nodes, and different A stages from itself. Controlling the logical state of the node for disabling provided at the same time; The node control unit provided in the B stage of the second shift register connected to the arbitrary gate line uses the second alternating current voltage to determine the logic state of the enable node and the disable nodes, and the different B from the node. To control the logic state of the disable node included in the stage; And, And the first alternating voltage has a phase inverted with respect to the second alternating voltage. The method of claim 1, The node control unit provided in the odd-numbered A stage of the first shift register connected to the odd-numbered gate line is different from the logic state of the enable node and the disable nodes provided by the node control unit using the first AC voltage. To control the logic state of the disable node included in the stage; The node controller provided in the even-numbered A stage of the first shift register connected to the even-numbered gate line is different from the logic state of the enable node and the disable nodes provided by the node control unit using the second AC voltage. To control the logic state of the disable node included in the stage; The node control unit provided in the odd-numbered B stage of the second shift register connected to the odd-numbered gate line is different from the logic state of the enable node and the disable nodes provided by the node control unit using the second AC voltage. To control the logic state of the disable node included in the stage; And, The node control unit provided in the even-numbered B stage of the second shift register connected to the even-numbered gate line may be different from the logic states of the enable node and the disable-node nodes by using the first AC voltage. A shift register characterized in that it also controls the logic state of the disable node provided in the stage. The method of claim 1, Each A stage provided in the first shift register includes a first disable node, a first pull-down switching element connected to the first disable node, a second disable node, and the second disable node. A second pull-down switching element connected to; The node controller provided in the 2n-3 (n is a natural number of 2 or more) stage A controls the logic states of the enable node and the first disable node provided in the 2n-3th A stage, and also the 2n− Control the logic state of the first disable node provided in the second A stage; The node control unit provided in the 2n-2th A stage controls the logic states of the enable node and the second disable node provided in the 2n-2th A stage, and the 2n-3th A stage. Control a logic state of the provided second disable node; And, Each B stage provided in the second shift register includes a first disable node, a first pull-down switching element connected to the first disable node, a second disable node, and the second disable node. A second pull-down switching element connected to; The node control unit provided in the 2n-3 (n is a natural number of 2 or more) stage B controls the logic states of the enable node and the first disable node provided in the 2n-3rd B stage, as well as 2n−. Control the logic state of the first disable node provided in the second B stage; The node control unit provided in the 2n-2th B stage controls the logic states of the enable node and the second disable node provided in the 2n-2th B stage, and the 2n-3th B stage. A shift register, characterized in that for controlling the logic state of the provided second node for disabling. The method of claim 3, wherein A first disable node provided in the 2n-3rd A stage and a first disable node provided in the 2n-2nd A stage are electrically connected to each other; A second disable node provided in the 2n-2 th A stage and a second disable node provided in the 2n-3 th A stage are electrically connected to each other; And, A first disable node provided in the 2n-3rd B stage and a first disable node provided in the 2n-2nd B stage are electrically connected to each other; And a second disable node provided in the 2n-2 th B stage and a second disable node provided in the 2n-3 th B stage are electrically connected to each other. The method of claim 3, wherein The node control unit provided in the 2n-3rd A stage includes the logical state of the first disable node provided in the 2n-3rd A stage and the node of the first disable node provided in the 2n-2 A A stage. Control a logic state to said first alternating voltage; The node control unit provided in the 2n-2th A stage may perform logic states of a second disable node provided in the 2n-2 A A stage and a second disable node provided in the 2n-3 A A stage. Control with the second alternating voltage; And, The node control unit provided in the 2n-3rd B stage is configured to determine the logical state of the first disable node provided in the 2n-3rd B stage and the node for the first disable node provided in the 2n-2nd B stage. Control a logic state to the second alternating voltage; The node controller provided in the 2n-2th B stage is configured to determine the logical states of the second disable node provided in the 2n-2th B stage and the second disable node provided in the 2n-3rd B stage. The shift register characterized in that the control by the first AC voltage. The method of claim 5, The 2n-1st A stage and the 2nth A stage are enabled in response to the scan pulse from the 2n-3rd A stage, and are disabled in response to the scan pulse from the 2n + 2nd A stage; 2n-3rd A stage and 2n-2nd A stage are disabled in response to the scan pulse from the 2nth A stage; A 2n + 1 th A stage and a 2n + 2 th A stage are enabled in response to a scan pulse from the 2n-1 th A stage; And, The 2n-1st B stage and the 2nth B stage are enabled in response to the scan pulses from the 2n-3rd B stages, and are disabled in response to the scan pulses from the 2n + 2th B stages; 2n-3rd B stage and 2n-2nd B stage are disabled in response to the scan pulse from the 2nth B stage; And a 2n + 1 th B stage and a 2n + 2 th B stage are enabled in response to a scan pulse from the 2n-1 th B stage. The method of claim 6, The node control unit provided in the 2n-1st A stage includes: a first switching device configured to charge the enable node to a first DC voltage in response to a scan pulse from the 2n-3rd A stage; A second switching element for discharging the enable node to a second DC voltage in response to a first AC voltage supplied to a first disable node; Discharging the enable node of the 2n-1st A stage to a second DC voltage in response to a second AC voltage supplied to the second disable node of the 2n-1 A stage through the 2nth A stage. A third switching element; A fourth switching device for discharging the enable node to a second DC voltage in response to a scan pulse from a 2n + 2th A stage; A fifth switching element which is turned on or turned off in response to a first alternating voltage and charges a common node with the first alternating voltage when turned on; A sixth switching device discharging the common node to a second DC voltage in response to a first DC voltage charged in the enable node; A seventh battery charging the first disable node of the 2n-1st A stage and the first disable node of the 2nth A stage to the first AC voltage in response to a first AC voltage supplied to the common node; Switching element; An eighth switch for discharging the first disable node of the 2n-1st A stage and the first disable node of the 2nth A stage to a second DC voltage in response to a scan pulse from the 2n-3rd A stage; device; And discharging the first disable node of the 2n-1st A stage and the first disable node of the 2nth A stage to a second DC voltage in response to a first DC voltage charged in the enable node. A ninth switching device for guiding; And, The node control unit provided in the 2n-1st B stage includes: a first switching element configured to charge the enable node to a first DC voltage in response to a scan pulse from the 2n-3rd B stage; A second switching element for discharging the enable node to a second DC voltage in response to a first AC voltage supplied to a first disable node; Discharging the enable node of the 2n-1th B stage to a second DC voltage in response to a second AC voltage supplied to the second disable node of the 2n-1st B stage through the 2nth B stage. A third switching element; A fourth switching device for discharging the enable node to a second DC voltage in response to a scan pulse from a 2n + 2th B stage; A fifth switching element that is turned on or off in response to a first alternating voltage and charges a common node with the first alternating voltage at turn-on; A sixth switching device discharging the common node to a second DC voltage in response to a first DC voltage charged in the enable node; A seventh charge of the first disabling node of the 2n-th B stage and the first disabling node of the 2n-th B stage to the first AC voltage in response to the first AC voltage supplied to the common node; Switching element; An eighth switch configured to discharge the first disable node of the 2n-1st B stage and the first disable node of the 2nth B stage to a second DC voltage in response to a scan pulse from the 2n-3rd B stage device; And discharging the first disable node of the 2n-1st B stage and the first disable node of the 2nth B stage to a second DC voltage in response to a first DC voltage charged in the enable node. And a ninth switching element. The method of claim 1, 2n-1st A stages of the A stages provided in the first shift register are supplied with a first AC voltage, and 2nth A stages are supplied with a second AC voltage; 2n-1st B stages of the B stages provided in the second shift register are supplied with the first AC voltage, and the 2nth B stages are supplied with the second AC voltage; A 2nth A stage of the first shift register supplies a scan pulse to one side of an nth gate line; And, And a 2n-1 < th > B stage of the second shift register supplies a scan pulse to the other side of the nth gate line. The method of claim 8, And a scan pulse from a first A stage of the A stages and a scan pulse from the last B stage of the B stages are not supplied to a gate line. A shift register sequentially supplying scan pulses to one side of the gate lines; At least one stage provided in the shift register comprises: an enabling node; A pull-up switching device configured to output the scan pulse according to a logic state of the enable node; At least two nodes for disabling; At least two pull-down switching elements connected to each of the disable nodes and outputting an off voltage according to a logic state of each of the disable nodes; A node control unit for controlling the logic states of the enable node and the disable nodes provided in the same and the logical states of the disable node included in the stage different from the self; The node controller provided in the stage connected to an arbitrary gate line may be configured to use the logic state of the enable node and the disable nodes provided by the node controller by using any one of the first AC voltage and the second AC voltage. And control the logic state of the disable node included in the other stage; The first AC voltage has an inverted phase with respect to the second AC voltage; And, The first and second AC voltages are randomly supplied to each stage, the shift register, characterized in that different AC voltage is supplied in the 2n-1 stage and 2n stage.

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