KR101192791B1 - A shift register and a method for diving the same - Google Patents

Abstract

The present invention relates to a shift register capable of preventing deterioration of the pull-down switching device by having two pull-down switching devices that operate alternately with each other, and a method of driving the same, which outputs an output pulse according to a signal state of a first node. A pull-up switching element, a first pull-down switching element for outputting a discharge voltage source in accordance with a signal state of the second node, a second pull-down switching element for outputting the discharge voltage source in accordance with a signal state of the third node, and inverting each other A plurality of stages including a node controller for controlling the first, second, and third nodes using first and second alternating current voltage sources having a different phase; A counter for counting a preset time and periodically outputting a reset signal; A power supply unit for changing the logic states of the first and second alternating voltage sources according to the reset signal from the counter and supplying them to the stages; And a storage unit which stores a value counted from the counter at the time of power-off and supplies the counted value to the counter at the time of power-on.

LCD, Shift Register, Counter, Stage, Node Control Unit

Description

A shift register and a method for diving the same

1 is a diagram illustrating one stage provided in a conventional shift register.

2 illustrates a shift register according to an embodiment of the present invention.

3A and 3B illustrate timing diagrams of various signals supplied to the shift register of FIG. 2 and signals output from the shift register.

4 is a diagram illustrating a circuit configuration of the second stage of FIG. 2.

FIG. 5 is a diagram illustrating another circuit configuration included in the second stage of FIG. 2.

FIG. 6 is a diagram illustrating first to third stages having the circuit configuration of FIG. 4. FIG.

7 shows a first embodiment of an AC power supply for outputting first and second AC voltage sources;

8 is a view for explaining the operation of the AC power supply unit according to the first embodiment of the present invention;

9 shows a second embodiment of an AC power supply for outputting first and second AC voltage sources;

* Explanation of symbols on the main parts of the drawings

ST: Stage Vout: Output Pulse

201: node control unit Vst: start pulse

CLK: Clock pulse VSS: Voltage source for discharge

n: Node Vac: AC voltage source

Trpu: Pull-up Switching Device Trpd: Pull-down Switching Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register of a liquid crystal display, and more particularly, to a shift register and a driving method thereof capable of preventing deterioration of the pull-down switching element by having two pull-down switching elements alternately operating.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, And a power supply unit for supplying various driving voltages used in the plasma display apparatus.

Here, the gate driver includes a shift register for sequentially outputting the scan pulses as described above. This will be described in more detail with reference to the accompanying drawings.

Hereinafter, a conventional shift register will be described with reference to the accompanying drawings.

1 is a view showing one stage provided in a conventional shift register.

Conventional shift registers are composed of a plurality of stages connected dependently to each other. As illustrated in FIG. 1, each stage includes a pull-up switching device Trpu which outputs an output pulse Vout according to the signal state of the first node n1, and a signal state of the second node n2. A pull-down switching element Trpd for outputting a discharge voltage source, and a node controller 101 for controlling signal states of the first and second nodes n1 and n2.

The node controller 101 maintains the second node n2 in a discharged state when the first node n1 is in a charged state, and the second node when the second node n2 is in a charged state. Keep (n2) in the discharge state.

Accordingly, the pull-up switching device Trpu connected to the first node n1 and the pull-down switching device Trpd connected to the second node n2 are alternately turned on.

Each stage outputs only one output pulse Vout for one period within one frame period, and outputs a discharge voltage source for the remaining period of the one frame period.

To this end, the first node n1 to which the pull-up switching device Trpu is connected is maintained in the charged state for the one period and in the discharged state for the remaining period. In addition, the second node n2 to which the pull-down switching device Trpd is connected is maintained in a discharge state for the one period, and remains in a charged state for the remaining period.

Accordingly, deterioration of the pull-down switching device Trpd connected to the second node n2 proceeds rapidly, resulting in a problem of shortening the life of the shift register.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a shift register and a driving method thereof having two pull-down switching elements operating alternately with each other to prevent deterioration of the pull-down switching element. There is this.

The shift register according to the present invention for achieving the above object, at least one of the first, second and third nodes, at least one pull-up switching device for outputting an output pulse in accordance with the signal state of the first node At least one first pull-down switching device for outputting a discharge voltage source according to the signal state of the second node, at least one second pull-down switching device for outputting the discharge voltage source according to the signal state of the third node; And controlling the second and third nodes to be in a discharge state when the first node is in a charged state by using first and second AC voltage sources having phases inverted from each other, and the first node is in a discharge state. And a node control unit for maintaining any one of the second node and the third node in a charged state and maintaining the other node in a discharge state. Includes a plurality of stages; A counter for counting a preset time and periodically outputting a reset signal; A power supply unit for changing the logic states of the first and second alternating voltage sources according to the reset signal from the counter and supplying them to the stages; And a storage unit for storing a value counted from the counter at the time of power-off and supplying the counted value to the counter at the time of power-on.

In addition, the shift register according to the present invention for achieving the above object, at least one of the first, second and third nodes, at least one pull-up outputting an output pulse in accordance with the signal state of the first node At least one first pull-down switching element for outputting a discharge voltage source in accordance with a signal state of the second node, at least one second pull-down switching outputting the discharge voltage source in accordance with a signal state of the third node An element and first and second alternating current voltage sources having inverted phases with each other to control the second and third nodes to remain in a discharge state when the first node is in a charged state, and wherein the first node is A node control unit configured to maintain either one of the second node and the third node in a charged state and to maintain the other one in a discharged state A plurality of stages comprising; And a power output unit for changing the logic states of the first and second alternating current voltage sources maintained before the power is turned on each time the power is turned on and outputting the outputs to the stages.

In addition, the driving method of the shift register according to the present invention for achieving the above object, at least one of the first, second and third nodes, at least output pulses output in accordance with the signal state of the first node One pull-up switching element, at least one first pull-down switching element for outputting a discharge voltage source according to the signal state of the second node, and at least one first outputting the discharge voltage source according to the signal state of the third node A second pull-down switching element and first and second alternating current voltage sources having inverted phases to control each of the second and third nodes to be in a discharged state when the first node is in a charged state; When one node is in a discharged state, either one of the second node and the third node is kept in a charged state and the other node is kept in a discharged state. In the driving method of a shift register comprising a plurality of stages including a de control, comprising: counting a predetermined time; Storing the counted value the moment the power is turned off; And setting a logic state of the first and second alternating voltage sources in accordance with the stored counted value at the moment of power-up.

In addition, the driving method of the shift register according to the present invention for achieving the above object, at least one of the first, second and third nodes, at least output pulses output in accordance with the signal state of the first node One pull-up switching element, at least one first pull-down switching element for outputting a discharge voltage source according to the signal state of the second node, and at least one first outputting the discharge voltage source according to the signal state of the third node A second pull-down switching element and first and second alternating current voltage sources having inverted phases to control each of the second and third nodes to be in a discharged state when the first node is in a charged state; When one node is in a discharged state, either one of the second node and the third node is kept in a charged state and the other node is kept in a discharged state. In the driving method of a shift register comprising a plurality of stages including a de control, comprising the steps of: each time the power is turned on, changes the logic state of the first and second alternating current voltage source that was held before the power is turned on, group; And outputting the first and second alternating current voltage sources of which the logic state is changed to the stages.

Hereinafter, a shift register according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a shift register according to an exemplary embodiment of the present invention, and FIGS. 3A and 3B are diagrams illustrating timing diagrams of various signals supplied to the shift register of FIG. 2 and signals output from the shift register.

The shift register according to the exemplary embodiment of the present invention includes n stages ST1 to STn connected to each other, as illustrated in FIG. 2.

Here, each of the stages ST1 to STn outputs output pulses Vout1 to Voutn + 1 in sequence for one frame period. That is, output pulses Vout1 to Voutn + 1 are sequentially output from the first stage ST1 to the nth stage STn.

Output pulses Vout1 to Voutn output from the stages ST1 to STn are sequentially supplied to gate lines of the liquid crystal panel (not shown) to sequentially scan the gate lines.

In order to reduce the size of the liquid crystal display, the stages ST1 to STn are preferably embedded in the liquid crystal panel.

Each stage ST1 to STn includes a pull-up switching device Trpu for outputting an output pulse according to the signal state of the first node n1, and a discharge voltage source VSS according to the signal state of the second node n2. The first pull-down switching device (Trpd1) for outputting the output, the second pull-down switching device (Trpd2) for outputting the discharge voltage source (VSS) in accordance with the signal state of the third node (n3) and the inverted phase Controlling the second and third nodes n2 and n3 to be in a discharge state when the first node n1 is in a charged state by using the first and second AC voltage sources Vac1 and Vac2 having A node controller configured to maintain one of the second node n2 and the third node n3 in a charged state when the first node n1 is in a discharged state, and to maintain the other node in a discharged state ( 201).

The node control unit 201 provided in each of the stages ST1 to STn charges the first node n1 of the stage in which it is equipped in response to the output pulse from the front stage, and the second and third nodes n2, n3) is discharged.

That is, the node controller 201 included in the k-th stage charges the first node n1 of the k-th stage in response to the k-th output pulse from the k-th stage, The second and third nodes n2 and n3 are discharged.

The node control unit 201 provided in each of the stages ST1 to STn discharges the first node n1 of the stage in which it is provided in response to the clock pulse from the clock transmission line, and the first and second alternating voltage sources ( One of the second and third nodes n2 and n3 is charged and the other one is discharged according to the logic states of Vac1 and Vac2. Here, the clock pulses supplied to the node controllers 201 of the stages ST1 to STn are the same as the clock pulses supplied to the drain terminal of the pull-up switching device Trpu provided in the next stage.

That is, the node controller 201 included in the k-th stage discharges the first node n1 of the k-th stage in response to the clock pulse from the clock transmission line, and the first and second AC voltage sources Vac1 and Vac2. And charges one of the second and third nodes n2 and n3 of the k-th stage and discharges the other one according to the logic state of the " Here, the clock pulse supplied to the node controller 201 of the k-th stage is the same as the clock pulse supplied to the drain terminal of the pull-up switching device Trpu provided in the k + 1th stage.

As illustrated in FIGS. 3A and 3B, the first AC voltage source Vac1 and the second AC voltage source Vac2 have phases inverted with each other for each frame period.

In particular, the first and second AC voltage sources Vac1 and Vac2 represent different logic states in units of p frame periods (p is a natural number). That is, if the first AC voltage source Vac1 remains high for the odd frame period and low for the even frame period, the second AC voltage source Vac2 remains low for the odd frame period. And remain high for the even-th frame period.

Each of the stages ST1 to STn has the following configuration.

4 is a diagram illustrating a circuit configuration included in the second stage of FIG. 2.

The node control unit 201 of each stage ST1 to STn includes first to eighth switching elements Tr1 to Tr8.

The first switching device Tr1 provided in the node control unit 201 of the kth stage drains the charging voltage source VDD from the second switching device Tr2 in response to the output pulse from the k-1st stage. Supply to the terminal. To this end, the gate terminal of the first switching element Tr1 provided in the k-th stage is connected to the output terminal of the k-th stage, the drain terminal is connected to the charging power line, and the source terminal is It is connected to the drain terminal of the second switching element Tr2 provided in the kth stage.

For example, the first switching device Tr1 included in the second stage ST2 of FIG. 4 receives the charging voltage source VDD in response to the first output pulse Vout1 from the first stage ST1. The drain terminal of the second switching device Tr2 is supplied.

The second switching device Tr2 provided in the node controller 201 of the kth stage is charged from the first switching device Tr1 in response to a clock pulse synchronized with the output pulse from the k-1st stage. The supply voltage source VDD is supplied to the first node n1. To this end, the gate terminal of the second switching device Tr2 provided in the kth stage is connected to the clock transmission line for transmitting the clock pulse, and the drain terminal is connected to the source terminal of the first switching device Tr1. The source terminal is connected to the first node n1 of the kth stage.

For example, the second switching device Tr2 provided in the second stage ST2 of FIG. 4 is a charging voltage source supplied from the first switching device Tr1 in response to the first clock pulse CLK1. VDD is supplied to the first node n1 of the first stage ST1.

The third switching element Tr3 included in the node controller 201 of the kth stage supplies the discharge voltage source VSS to the second node n2 of the kth stage in response to an output pulse from the k-1th stage. To feed. For this purpose, the gate terminal of the third switching element Tr3 provided in the kth stage is connected to the k-1st stage, the drain terminal is connected to the second node n2 of the kth stage, and The source terminal is connected to a power supply line for transmitting the discharge voltage source VSS.

For example, the third switching device Tr3 included in the second stage ST2 of FIG. 4 is configured to discharge the voltage source VSS in response to the first output pulse Vout1 from the first stage ST1. Is supplied to the second node n2 of the second stage ST2.

The fourth switching device Tr4 included in the node controller 201 of the kth stage supplies the discharge voltage source VSS to the third node n3 of the kth stage in response to an output pulse from the k-1th stage. Supplies). For this purpose, the gate terminal of the fourth switching element Tr4 provided in the kth stage is connected to the k-1st stage, the drain terminal is connected to the third node n3 of the kth stage, and The source terminal is connected to a power supply line for transmitting the discharge voltage source VSS.

For example, the fourth switching device Tr4 included in the second stage ST2 of FIG. 4 may respond to the discharge voltage source VSS in response to the first output pulse Vout1 from the first stage ST1. Is supplied to the third node n3 of the second stage ST2.

The fifth switching element Tr5 of the node controller 201 of the kth stage supplies the first AC voltage source Vac1 of the kth stage in response to a clock pulse synchronized with the output pulse from the k + 1th stage. It supplies to the 2nd node n2. To this end, a gate terminal of the fifth switching device Tr5 provided in the k-th stage is connected to a clock transmission line for transmitting the clock pulse, and a drain terminal of the power supply line for transmitting the first AC voltage source Vac. The source terminal is connected to the second node n2 of the k-th stage.

For example, the fifth switching device Tr5 included in the second stage ST2 of FIG. 4 supplies the first AC voltage source Vac1 to the second stage ST2 in response to a third clock pulse CLK3. To the second node n2.

The sixth switching element Tr6 included in the node controller 201 of the kth stage is the discharge voltage source VSS in response to the first AC voltage source Vac1 supplied to the second node n2 of the kth stage. ) Is supplied to the first node n1 of the k-th stage. To this end, the gate terminal of the sixth switching device Tr6 provided in the kth stage is connected to the second node n2 of the kth stage, and the drain terminal thereof is the first node n1 of the kth stage. The source terminal is connected to a power supply line for transmitting the discharge voltage source VSS.

For example, the sixth switching device Tr6 included in the second stage ST2 of FIG. 4 responds to the first AC voltage source Vac1 supplied to the second node n2 of the second stage ST2. Thus, the discharge voltage source VSS is supplied to the first node n1 of the second stage ST2.

The seventh switching element Tr7 included in the node controller 201 of the kth stage supplies the second AC voltage source Vac2 to the kth stage in response to a clock pulse synchronized with the output pulse from the k + 1th stage. Supply to the third node n3. To this end, the gate terminal of the seventh switching element Tr7 provided in the k-th stage is connected to a clock transmission line for transmitting the clock pulse, and the drain terminal is a power line for transmitting the second AC voltage source Vac2. The source terminal is connected to the third node n3 of the k-th stage.

For example, the seventh switching device Tr7 included in the second stage ST2 of FIG. 4 supplies the second AC voltage source Vac2 to the second stage ST2 in response to the third clock pulse CLK3. Supply to the third node n3.

The eighth switching element Tr8 included in the node controller 201 of the kth stage is configured to discharge the voltage source VSS in response to the second AC voltage source Vac2 supplied to the third node n3 of the kth stage. ) Is supplied to the first node n1 of the k-th stage. To this end, the gate terminal of the eighth switching element Tr8 provided in the kth stage is connected to the third node n3 of the kth stage, and the drain terminal of the first node n1 of the kth stage And a source terminal is connected to a power supply line for transmitting the discharge voltage source VSS.

For example, the eighth switching device Tr8 of the second stage ST2 of FIG. 4 responds to the second AC voltage source Vac2 supplied to the third node n3 of the second stage ST2. Thus, the discharge voltage source VSS is supplied to the first node n1 of the second stage ST2.

FIG. 5 is a diagram illustrating another circuit configuration included in the second stage of FIG. 2.

The node control unit 201 of each stage ST1 to STn includes first to eighth switching elements Tr1 to Tr8.

Here, since the second to eighth switching elements of FIG. 5 are the same as the second to eighth switching elements of FIG. 4, description thereof will be omitted.

 The first switching element Tr1 provided in the node control unit 201 of the kth stage supplies the output pulses to the drain terminal of the second switching element Tr2 in response to the output pulses from the k-1st stage. do. To this end, the gate terminal and the drain terminal of the first switching element Tr1 provided in the kth stage are connected to the output terminal of the k-1st stage, and the source terminal of the second switching unit provided in the kth stage. It is connected to the drain terminal of the element Tr2.

For example, the first switching device Tr1 provided in the second stage ST2 of FIG. 4 may respond to the first output pulse Vout1 in response to the first output pulse Vout1 from the first stage ST1. Is supplied to the drain terminal of the second switching device Tr2.

The operation of the shift register having the circuit configuration configured as described above is as follows.

FIG. 6 is a diagram illustrating first to third stages having the circuit configuration of FIG. 4.

First, the operation during the initial period T0 will be described.

Here, assume that the first AC voltage source Vac1 is kept high during the first frame period, and the second AC voltage source Vac2 is kept low during the first frame period. The one frame period includes the initial period and the i th period (i is a natural number).

During the initial period T0, only the start pulse Vst and the fourth clock pulse CLK4 remain high, and the remaining clock pulses CLK1 through CLK3 remain low, as shown in FIG. 3A. do.

The start pulse Vst and the fourth clock pulse CLK4 are input to the first stage ST1. In detail, as illustrated in FIG. 6, the start pulse Vst may include a gate terminal of the first switching element Tr1, a gate terminal of the third switching element Tr3, And a gate terminal of the fourth switching element Tr4. The fourth clock pulse CLK4 is supplied to the gate terminal of the second switching device Tr2 provided in the first stage ST1.

Then, all of the first, second, third, and fourth switching elements Tr1, Tr2, Tr3, and Tr4 of the first stage ST1 are turned on.

The charging voltage source VDD is supplied to the first node n1 of the first stage ST1 through the turned-on first and second switching devices Tr1. Accordingly, the first node n1 of the first stage ST1 is charged by the charging voltage source VDD, and the pull-up switching device Trpu having a gate terminal connected to the charged first node n1. ) Is turned on.

The discharge voltage source VSS is supplied to the second node n2 of the first stage ST1 through the turned-on third switching element Tr3. Accordingly, the first pull-down switching device in which the second node n2 of the first stage ST1 is discharged by the discharge voltage source VSS and the gate terminal is connected to the discharged second node n2. Trpd1 and the sixth switching element Tr6 are turned off.

The discharge voltage source VSS is supplied to the third node n3 through the turned-on fourth switching element Tr4. Accordingly, the second pull-down switching device in which the third node n3 of the first stage ST1 is discharged by the discharge voltage source VSS, and the gate terminal is connected to the discharged third node n3. Trpd2 and the eighth switching device Tr8 are turned off.

The operation during the first period T1 will now be described.

During the first period T1, as shown in FIG. 3A, only the first clock pulse CLK1 remains high, and the remaining clock pulses CLK2, CLK3, and CLK4 including the start pulse Vst are It remains low.

Therefore, in response to the start pulse Vst in the low state, all of the first, third, and fourth switching elements Tr1, Tr3, and Tr4 of the first stage ST1 are turned off, and in the low state In response to the fourth clock pulse CLK4, the second switching device Tr2 of the first stage ST1 is turned off.

In this case, as the first and second switching devices Tr1 and Tr2 are turned off, the first node n1 of the first stage ST1 is maintained in a floating state.

 As the first node n1 of the first stage ST1 remains charged by the charging voltage source VDD applied during the initial period T0, a gate terminal of the first stage ST1 is maintained. The pull-up switching device Trpu of the first stage ST1 to which is connected is maintained in the turn-on state.

In this case, the first clock pulse CLK1 is supplied to the drain terminal of the turned-on pull-up switching device Trpu. Then, the charging voltage source VDD charged in the first node n1 of the first stage ST1 is amplified (bootstrapping phenomenon bootstrapping). This amplification occurs because the first node n1 is in a floating state.

Therefore, the first clock pulse CLK1 supplied to the drain terminal of the pull-up switching device Trpu provided in the first stage ST1 is stably output through the source terminal of the pull-up switching device Trpu. The first clock pulse CLK1 output from the pull-up switching device Trpu is the first output pulse Vout1.

The output first output pulse Vout1 is supplied to the first gate line GL1 to serve as a scan pulse for driving the first gate line GL1, and the next stage, that is, the second stage ST2. Acts as a start pulse to enable.

Accordingly, the second stage ST2 is enabled in the same manner as the first stage ST1 is enabled during the above-described initial period T0.

That is, the first output pulse Vout1 output from the first stage ST1 in the first period T1 is the first, third, and fourth switching elements Tr1 included in the second stage ST2. And Tr3 and Tr4).

In addition, in the first period T1, a first clock pulse CLK1 synchronized with the first output pulse CLK1 is supplied to the second switching element T2 of the second stage ST2, and thus, the first clock pulse CLK1 is applied to the second switching element T2 of the second stage ST2. 2 Turn on the switching element Tr2.

 Accordingly, in the first period T1, the pull-up switching device Trpu of the second stage ST2 is turned on, and the first and second pull-down switching devices Trpd1 and Trpd2 are turned off.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in FIG. 3A, only the second clock pulse CLK2 remains high. In contrast, the remaining clock pulses CLK1, CLK3, and CLK4 including the start pulse Vst and the first output pulse Vout1 remain low.

Therefore, in response to the first output pulse Vout1 in the low state, all of the first, third, and fourth switching elements Tr1, Tr3, and Tr4 of the second stage ST2 are turned off and in a low state. The second switching device Tr2 of the second stage ST2 is turned off in response to the first clock pulse CLK1.

In this case, as the first and second switching devices Tr1 and Tr2 are turned off, the first node n1 of the second stage ST2 is maintained in a floating state.

 As the first node n1 of the second stage ST2 is kept charged by the charging voltage source VDD which has been applied during the first period T1, the gate of the first node n1 is gated to the first node n1. The pull-up switching device Trpu of the second stage ST2 to which the terminals are connected is maintained in the turn-on state.

At this time, the second clock pulse CLK2 is supplied to the drain terminal of the turn-on pull-up switching device Trpu. Then, the charging voltage source VDD charged in the first node n1 of the second stage ST2 is amplified.

Therefore, the second clock pulse CLK2 supplied to the drain terminal of the pull-up switching device Trpu provided in the second stage ST2 is stably output through the source terminal of the pull-up switching device Trpu. The second clock pulse CLK1 output from the pull-up switching device Trpu is the second output pulse Vout2.

The output second output pulse Vout2 is supplied to a second gate line to serve as a scan pulse for driving the second gate line, and a start for enabling the next stage, that is, the third stage ST2. It acts as a pulse.

On the other hand, the second clock pulse CLK2 output in the second period T2 is also supplied to the first stage ST1 to serve to disable the first stage ST1.

That is, the first node n1 of the first stage ST1 is discharged by the second clock pulse CLK2, the second node n2 is charged, and the third node n3 is discharged. . If this is explained in more detail as follows.

That is, the second clock pulse CLK2 output in the second period T2 is supplied to the gate terminals of the fifth and seventh switching elements Tr5 and Tr7 provided in the first stage ST1.

Then, the fifth switching device Tr5 is turned on, and when the first AC voltage source Vac1 in the high state is turned on through the turned-on second switching device Tr5, the first stage ST1 of the first stage ST1 is turned on. It is supplied to two nodes n2. Then, the first pull-down switching device Trpd1 and the sixth switching device Tr6 having the gate terminal connected to the second node n2 of the charged first stage ST1 are turned on.

The discharge voltage source VSS is supplied to the first gate line GL1 through the turned-on pull-up switching device Trpd1. As a result, the first gate line is discharged.

The discharge voltage source VSS is supplied to the first node n1 of the first stage ST1 through the turned-on sixth switching element Tr6. Accordingly, the first node n1 is discharged, and the pull-up switching device Trpu of the first stage ST1 having the gate terminal connected to the discharged first node n1 is turned off.

Meanwhile, the third node n3 of the first stage ST1 is still maintained in the discharge state by the discharge voltage source VSS supplied in the previous period. Accordingly, the second pull-down switching device Trpd2 of the first stage ST1 having the gate terminal connected to the third node n3 is turned off.

In this manner, when the nth output pulse Voutn is output to the nth stage STn, the first frame period ends.

In this first frame period, the first pull-down switching device Trpd1 operates, and the second pull-down switching device Trpd2 has a rest period.

In the next second frame period, as shown in FIG. 3B, since the first AC voltage source Vac1 is kept low and the second AC voltage source Vac2 is kept high, In the disable operation, the fifth switching device Tr5 is turned off, the seventh switching device Tr7 is turned on to charge the third node n3, and the second node n2 is discharged. Therefore, in the second frame period, the second pull-down switching device Trpd2 connected to the third node n3 operates to discharge the corresponding gate line.

In this second frame period, the second pull-down switching device Trpd2 operates, and the first pull-down switching device Trpd1 has a rest period.

The first and second AC voltage sources Vac1 and Vac2 are output by an AC power supply as follows.

FIG. 7 is a diagram showing a first embodiment of an AC power supply unit for outputting first and second AC voltage sources. FIG.

The AC power supply unit 701 according to the first embodiment of the present invention, as shown in Figure 7, the power supply unit 701, the counter 702 (counter), the storage unit 703, and the on / off detection The unit 704 is provided.

The counter 702 counts a preset time and periodically outputs the reset signal Vrs. That is, the counter 702 counts time in frame period units. When the counter 702 counts up to a preset time, the counter 702 is reset and counts again from the beginning to the set time.

At this time, the counter 702 outputs a reset signal Vrs whenever it is reset. The reset signal Vrs is supplied to the power supply unit 701.

The power supply 701 changes the logic states of the first and second AC voltage sources Vac1 and Vac2 whenever the reset signal Vrs is input.

Assuming that the power supply unit 701 changes the logic states of the first and second AC voltage sources Vac1 and Vac2 in units of four frame periods, the power supply unit 701 performs the first period during the first to fourth frame periods. The first AC voltage source Vac1 is output in a high state, and the second AC voltage source Vac2 is output in a low state. Thereafter, in response to the reset signal Vrs from the counter 702, the power supply unit 701 changes the first AC voltage source Vac1 to a low state and outputs the changed state during the fifth to eighth frame periods. The second AC voltage source Vac2 is changed to a high state and output. Next, in response to the next reset signal Vrs from the counter 702, the power supply unit 701 changes the first AC voltage source Vac1 to a high state and outputs it for the ninth through twelfth frame periods. The second AC voltage source Vac2 is changed to a low state and output.

To this end, the counter 702 outputs a reset signal Vrs once every four frame periods and supplies the reset signal Vrs to the power supply unit 701. In other words, the counter 702 outputs the reset signal Vrs between the fourth and fifth periods and between the eighth and ninth periods, and provides the reset signal Vrs to the power supply unit 701.

Then, the power supply 701 changes and outputs the logic states of the first and second AC voltage sources Vac1 and Vac2 every four frame periods in response to the reset signal Vrs. The first and second alternating voltage sources Vac1 and Vac2 are supplied to the stages ST1 to STn described above.

The on / off detector 704 detects when the power supply VCC of the device using the shift register according to the embodiment of the present invention, for example, the display device, is turned on and outputs a load signal Vld. When the power supply VCC of the display device is turned off, it detects this and outputs a storage signal Vpr.

The on / off detector 704 supplies the load signal Vld and the storage signal Vpr to the storage unit 703.

The storage unit 703 stores a value counted from the counter 702 in response to the storage signal Vpr, and outputs the stored counted value in response to the load signal Vld to output the counter 702. ) As a set signal.

Accordingly, the storage unit 703 stores information about logic states of the first and second AC voltage sources Vac1 and Vac2 until the display device is turned off, as a count value.

The storage unit 703 supplies the count value as a set signal to the counter 702 as soon as the display device is turned on again. Then, the counter 702 starts counting from the count value. If this is explained in more detail as follows.

8 is a view for explaining the operation of the AC power supply according to the first embodiment of the present invention.

If the counter 702 counts by m frame periods and then resets them to output the reset signal Vrs, as shown in FIG. 8, the power supply unit 701 first and second every m frame periods. Change the logic state of the AC voltage sources Vac1 and Vac2.

In this case, it is assumed that the power supply VCC of the display device is turned on in the first frame period F1 and turned off in the third frame period F3.

Then, the counter 702 starts counting from the first frame period F1 and stops counting in the third frame period F3. At this time, the storage signal Vpr output from the on / off sensing unit 704 is supplied to the storage unit 703. Then, the storage unit 703 stores the count value at the moment when the counter 702 stops counting in response to the storage signal Vpr.

Thereafter, when the power supply VCC is supplied to turn on the display device again, the on / off detection unit 704 outputs a load signal Vld in response to the power supply VCC and supplies the load signal Vld to the storage unit 703. do. Then, the storage unit 703 supplies the stored count value to the counter 702 as a set signal.

Thus, the counter 702 is set according to the count value and counts from the next value of this count value, that is, from the fourth frame period F4.

The storage unit 703 may use any one of an erasable and programmable read only memory (EPROM) and an erasable and programmable read only memory (EEPROM).

9 is a diagram showing a second embodiment of an AC power supply unit for outputting first and second AC voltage sources.

As illustrated in FIG. 9, the AC power supply unit according to the second embodiment of the present invention includes a power supply unit 901, a storage unit 903, and an on / off detection unit 904.

The power supply unit 901 changes the logic states of the first and second AC voltage sources Vac1 and Vac2 that are maintained before the power source VCC is turned on each time the power source VCC is turned on. ST1 to STn).

The on / off detection unit 904 detects when the power supply (VCC) of the display device is turned on and outputs a load signal (Vld), and detects when the power supply (VCC) of the display device is turned off and stores the stored signal. Outputs (Vpr) The on / off detector 904 supplies the load signal Vld and the storage signal Vpr to the storage unit 903.

The storage unit 903 stores information on logic states of first and second AC voltage sources Vac1 and Vac2 from the power supply unit 901 in response to the storage signal Vpr, and loads the load signal Vld. In response to), the stored information is output in the form of a signal and supplied to the power supply unit 901.

The operation of the AC power supply unit according to the second embodiment of the present invention configured as described above is as follows.

When the power supply VCC of the display device is turned off while the first AC voltage source Vac1 is kept high and the second AC voltage source Vac2 is kept low, the storage unit 903 Stores information on logic states of the first and second AC voltage sources Vac1 and Vac2 at the moment when the power supply VCC of the display device is turned off.

Thereafter, when the power supply (VCC) is supplied to the display device again to drive the display device, the power supply unit 901 based on the information stored in the storage unit 903, the first and second output currents. Sets the logic state of the AC voltage sources Vac1 and Vac2. That is, the power supply unit 901 changes the logic states of the first and second AC voltage sources Vac1 and Vac2.

In other words, the power supply unit 901 changes the first AC voltage source Vac1 to a low state and outputs it, and changes the second AC voltage source Vac2 to a high state and outputs the same.

By controlling the logic states of the first and second AC voltage sources Vac1 and Vac2 using such an AC power supply, first and second pull-down switching supplied with the first and second AC voltage sources Vac1 and Vac2. Asymmetrical deterioration of deterioration of the elements Trpd1 and Trpd2 can be effectively prevented.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The shift register and the driving method thereof according to the present invention as described above has the following effects.

The shift register according to the present invention may include two pull-down switching elements alternately operating to prevent deterioration of the pull-down switching element.

In addition, the shift register according to the present invention can prevent the degradation of the pull-down switching element by controlling the AC voltage source in accordance with the on / off state of the power supply.

Claims (15)

At least one first, second and third node, at least one pull-up switching element for outputting an output pulse according to the signal state of the first node, and outputting a discharge voltage source according to the signal state of the second node Using at least one first pull-down switching element, at least one second pull-down switching element for outputting the discharge voltage source according to the signal state of the third node, and first and second alternating voltage sources having inverted phases So that the second and third nodes are both maintained in a discharge state when the first node is in a charged state, and any one of the second node and the third node is in a charged state when the first node is in a discharge state. A plurality of stages including a node control unit for maintaining the node and maintaining the other node in a discharge state; A counter for counting a preset time and periodically outputting a reset signal; A power supply unit for changing the logic states of the first and second alternating voltage sources according to the reset signal from the counter and supplying them to the stages; And And a storage unit for storing the counted value from the counter at the power-off and supplying the counted value to the counter at the power-on. The method of claim 1, The electronic device may further include an on / off detector configured to determine whether the power is turned off or on, to inform the storage unit of when to store the counted value and when the storage unit outputs the counted value. A shift register characterized in that. The method of claim 1, And the storage unit is one of erasable and programmable read only memory (EPROM) and erasable and programmable read only memory (EEPROM). The method of claim 1, And the counter counts time in frame period units. The method of claim 1, The node control unit, A first switching element for outputting a charging voltage source in response to a start pulse from the outside or a shear output pulse from the shear stage; A second switching element for supplying a charging voltage source from the first switching element to the first node in response to a clock pulse synchronized with the start pulse or a clock pulse synchronized with the front output pulse; A third switching element configured to supply the discharge voltage source to the second node in response to the start pulse or the front end output pulse; A fourth switching device configured to supply the discharge voltage source to the third node in response to the start pulse or the front end output pulse; A fifth switching device for supplying a first AC voltage source to the second node in response to a clock pulse synchronized with an output pulse from a next stage; A sixth switching device configured to supply the discharge voltage source to the first node in response to a first AC voltage source supplied to the second node; A seventh switching element configured to supply a second AC voltage source to the third node in response to a clock pulse synchronized with an output pulse from a next stage; And And an eighth switching device configured to supply the discharge voltage source to the first node in response to a second AC voltage source supplied to the third node. The method of claim 1, The node control unit, A first switching element configured to output the start pulse or the front end output pulse in response to a start pulse from the outside or a front end output pulse from the front end stage; A second switching element for supplying a start pulse from the first switching element or the front end output pulse to the first node in response to a clock pulse synchronized with the start pulse or a clock pulse synchronized with the front end output pulse; A third switching device configured to supply the discharge voltage source to the second node in response to the start pulse or the front end output pulse; A fourth switching device configured to supply the discharge voltage source to the third node in response to the start pulse or the front end output pulse; A fifth switching device for supplying a first AC voltage source to the second node in response to a clock pulse synchronized with an output pulse from a next stage; A sixth switching device configured to supply the discharge voltage source to the first node in response to a first AC voltage source supplied to the second node; A seventh switching element configured to supply a second AC voltage source to the third node in response to a clock pulse synchronized with an output pulse from a next stage; And And an eighth switching device configured to supply the discharge voltage source to the first node in response to a second AC voltage source supplied to the third node. At least one first, second and third node, at least one pull-up switching element for outputting an output pulse according to the signal state of the first node, and outputting a discharge voltage source according to the signal state of the second node Using at least one first pull-down switching element, at least one second pull-down switching element for outputting the discharge voltage source according to the signal state of the third node, and first and second alternating voltage sources having inverted phases So that the second and third nodes are both maintained in a discharge state when the first node is in a charged state, and any one of the second node and the third node is in a charged state when the first node is in a discharge state. A plurality of stages including a node control unit for maintaining the node and maintaining the other node in a discharge state; And And a power output unit for changing the logic states of the first and second AC voltage sources maintained before the power is turned on each time the power is turned on, and outputting them to the stages. The method of claim 7, wherein And a storage unit for storing information on logic states of the first and second AC voltage sources output from the power output unit at the moment of power-off and providing the information to the power output unit at the power-on. A shift register characterized in that. 9. The method of claim 8, And an on / off detection unit for determining when the power is turned off and on, and when the storage unit stores the information, and when the storage unit provides the information, to the storage unit. Shift register. The method of claim 9, And the storage unit is one of erasable and programmable read only memory (EPROM) and erasable and programmable read only memory (EEPROM). At least one first, second and third node, at least one pull-up switching element for outputting an output pulse according to the signal state of the first node, and outputting a discharge voltage source according to the signal state of the second node Using at least one first pull-down switching element, at least one second pull-down switching element for outputting the discharge voltage source according to the signal state of the third node, and first and second alternating voltage sources having inverted phases So that the second and third nodes are both maintained in a discharge state when the first node is in a charged state, and any one of the second node and the third node is in a charged state when the first node is in a discharge state. A method of driving a shift register including a plurality of stages including a node control unit to maintain a node and to keep the other node in a discharge state. Standing, Counting a preset time; Storing the counted value the moment the power is turned off; And setting a logic state of the first and second alternating current voltage sources according to the stored counted value at the moment the power is turned on. The method of claim 11, wherein And determining whether the power is off or on. The method of claim 11, wherein In the step of counting a predetermined time, the shift register driving method characterized in that the time is counted in units of frame periods. At least one first, second and third node, at least one pull-up switching element for outputting an output pulse according to the signal state of the first node, and outputting a discharge voltage source according to the signal state of the second node Using at least one first pull-down switching element, at least one second pull-down switching element for outputting the discharge voltage source according to the signal state of the third node, and first and second alternating voltage sources having inverted phases So that the second and third nodes are both maintained in a discharge state when the first node is in a charged state, and any one of the second node and the third node is in a charged state when the first node is in a discharge state. A method of driving a shift register including a plurality of stages including a node control unit to maintain a node and to keep the other node in a discharge state. Standing, Each time the power is turned on, changing the logic states of the first and second alternating voltage sources that were maintained before the power was turned on; And And outputting the first and second alternating current voltage sources of which the logic state is changed to the respective stages. 15. The method of claim 14, Storing information about the logic states of the first and second alternating current voltage sources at the moment the power is turned off; And And changing a logic state of the first and second AC voltage sources based on the information at the moment the power is turned on.

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