KR101287214B1 - A shift register - Google Patents

Abstract

In particular, the present invention relates to a shift register capable of preventing multiple outputs due to a coupling phenomenon, the shift register comprising a plurality of stages that sequentially output scan pulses and sequentially supply the plurality of gate lines; Each stage is turned on or off in accordance with the logic state of the first node, a pull-up switching device that receives the first clock pulse when the turn-on outputs a scan pulse, and supplies the scan pulse to the gate line; A pull-down switching device for supplying a discharge voltage source to the gate line in response to a control signal; A node controller for controlling a logic state of the first node; A first noise removing switching element connecting the first node and the second node in response to the first clock pulse; And a second switching turned on or off according to a logic state of the second node and the gate line, and connecting the gate line and the first node through the first noise removing switching element at turn-on. It is characterized by including an element.

LCD, shift register, coupling phenomenon, multi output

Description

A shift register

1 shows one stage in a conventional shift register.

2 illustrates a shift register according to a first embodiment of the present invention.

FIG. 3 is a timing chart of various signals supplied to or output from each stage of FIG. 2; FIG.

4 is a diagram showing the circuit configuration of the second stage of Fig. 2

FIG. 5 illustrates another circuit configuration of the second stage of FIG. 2.

FIG. 6 illustrates another circuit configuration of the second stage of FIG. 2.

FIG. 7 illustrates another circuit configuration of the second stage of FIG. 2.

FIG. 8 illustrates another circuit configuration of the second stage of FIG. 2.

FIG. 9 illustrates another circuit configuration of the second stage of FIG. 2.

FIG. 10 illustrates another circuit configuration of the second stage of FIG. 2.

FIG. 11 illustrates another circuit configuration of the second stage of FIG. 2.

FIG. 12 illustrates another circuit configuration of the second stage of FIG. 2.

FIG. 13 illustrates another circuit configuration of the second stage of FIG. 2.

FIG. 14 illustrates another circuit configuration of the second stage of FIG. 2.

FIG. 15 illustrates another circuit configuration of the second stage of FIG. 2.

* Explanation of symbols on the main parts of the drawings

Vout: Scan pulse VDD: Voltage source for charging

VSS: Voltage source for discharge Trd: Switching element for noise reduction

Vst: Start pulse Vstd: Start pulse for discharge

GL: Gate Line Trpu: Pull-Up Switching Element

Trpd: Pull-down switching element ST: Stage

CLK: Clock Pulse

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register of a liquid crystal display, and more particularly, to a shift register capable of preventing multiple outputs due to coupling phenomenon.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged in an intersecting manner, and a pixel region is located in an area defined by vertically intersecting the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed on the liquid crystal panel.

Here, the gate lines are sequentially driven by scan pulses, and the scan pulses are generated by the shift register.

1 is a diagram illustrating one stage in a conventional shift register.

The conventional stage includes a node control unit 101 for controlling the charging and discharging states of the first node n1 and the second node n2, and the scan pulse Vout according to the signal state of the first node n1. And a pull-down switching device Trdw for outputting a discharge voltage source VSS according to the signal state of the second node n2.

Here, the first node n1 and the second node n2 are alternately charged and discharged. Specifically, when the first node n1 is charged, the second node n2 is discharged. The first node n1 is discharged when the second node n2 is in a charged state.

In this case, when the first node n1 is in a charged state, a scan pulse Vout is output from the pull-up switching device Trup. When the second node n2 is in a charged state, a pull-down switching device in the output unit is output. The discharge voltage source VSS is output from Trdw.

The scan pulse Vout output from the pull-up switching device Trup and the discharge voltage source VSS output from the pull-down switching device Trdw are supplied to the corresponding gate line.

Here, the gate terminal of the pull-up switching device Trup is connected to the first node n1, the drain terminal is connected to a clock transmission line to which a clock pulse CLK is applied, and the source terminal is connected to the gate line. do. The clock pulse CLK has a high state and a low state periodically and is supplied to the drain terminal of the pull-up switching device Trup. At this time, the pull-up switching device Trup outputs any one of the clock pulses CLK in the high state input every cycle. The clock pulse CLK output at this particular time point is the scan pulse Vout for driving the gate line.

This specific time point means a time point after the first node n1 is charged. That is, the pull-up switching device Trup is at the specific time point (ie, the time point at which the first node n1 is charged) among the clock pulses CLK that are continuously input to its drain terminal periodically. The input clock pulse CLK of the high state is output as the scan pulse Vout. After the output of the scan pulse Vout, the first node n1 is maintained in a discharge state until the next frame period starts, so that the pull-up switching device Trup is once a scan pulse Vout per frame. Will print). However, since the clock pulse CLK is output several times during one frame period, the clock pulse even when the pull-up switching device Trup is turned off, that is, even when the first node n1 is discharged. CLK is continuously input to the drain terminal of the pull-up switching element Trup.

In other words, the pull-up switching device Trup is turned on only once for one frame and outputs a clock pulse CLK input to its drain terminal as a scan pulse Vout during this turn-on period. .

Thereafter, the pull-up switching device Trup is turned off until the start of the next frame period, so that the pull-up switching device Trup is clock pulse CLK at its drain terminal no matter how long it is turned off. Is input, it cannot be output as a scan pulse (Vout). However, as the clock pulse CLK is periodically applied to the drain terminal of the pull-up switching device Trup, the first node n1 and the gate terminal of the pull-up switching device Trup are connected. Coupling occurs between the drain terminals of the pull-up switching device Trup. Due to such a coupling phenomenon, the first node n1 is continuously charged with a predetermined voltage corresponding to the clock pulse CLK.

Then, the first node n1 may be maintained in a charged state at any moment. That is, the first node n1 may be maintained in a charged state at an unwanted timing. In this case, the first node n1 may be maintained in the charging state more than once in one frame period, whereby the pull-up switching device Trup may be turned on more than once in one frame period. As a result, a multi-output phenomenon in which one stage outputs two or more scan pulses Vout in one frame period may occur due to the coupling phenomenon as described above.

As such, when one stage outputs two or more scan pulses Vout during one frame period, the quality of an image displayed on the liquid crystal panel is degraded.

The present invention has been made to solve the above problems, by supplying a discharge voltage source supplied to the gate line to the node each time the clock pulse is output to discharge the voltage source accumulated in the node, thereby preventing multiple outputs Its purpose is to provide a shift register.

The shift register according to the present invention for achieving the above object includes a plurality of stages in order to sequentially output a scan pulse to the plurality of gate lines; Each stage is turned on or off in accordance with the logic state of the first node, a pull-up switching device that receives the first clock pulse when the turn-on outputs a scan pulse, and supplies the scan pulse to the gate line; A pull-down switching device for supplying a discharge voltage source to the gate line in response to a control signal; A node controller for controlling a logic state of the first node; A first noise removing switching element connecting the first node and the second node in response to the first clock pulse; And a second switching turned on or off according to a logic state of the second node and the gate line, and connecting the gate line and the first node through the first noise removing switching element at turn-on. It is characterized by including an element.

In addition, the shift register according to the present invention for achieving the above object includes a plurality of stages in order to sequentially output a scan pulse to the plurality of gate lines; Each stage is turned on or off in accordance with the logic state of the first node, a pull-up switching device that receives the first clock pulse when the turn-on outputs a scan pulse, and supplies the scan pulse to the gate line; A pull-down switching device for supplying a discharge voltage source to the gate line in response to a control signal; A node controller for controlling a logic state of the first node; A first noise removing switching element connecting the first node and the second node in response to the first clock pulse; A second noise removing switching element supplying a discharge voltage source to the second node in response to a second clock pulse; And a third switching device that is turned on or off according to a logic state of the second node and the gate line, and connects the first node and the gate line when the second node and the gate line are turned on. do.

In addition, the shift register according to the present invention for achieving the above object includes a plurality of stages in order to sequentially output a scan pulse to the plurality of gate lines; Each stage is turned on or off in accordance with the logic state of the node, a pull-up switching device that receives the first clock pulse when the turn-on outputs a scan pulse, and supplies the scan pulse to the gate line; A pull-down switching device which is turned on or turned off in response to a logic state of a control signal and supplies a discharge voltage source to the gate line at turn-on; A node controller for controlling a logical state of the node; And turn-on or turn-off according to a logic state of a first clock pulse supplied through a resistor, a logic state of a node, and a logic state of a gate line, and connecting the gate line and the node at turn-on. 1 is characterized by including a switching element for removing noise.

In addition, the shift register according to the present invention for achieving the above object includes a plurality of stages in order to sequentially output a scan pulse to the plurality of gate lines; Each stage is turned on or off in accordance with the logic state of the node, a pull-up switching device that receives the first clock pulse when the turn-on outputs a scan pulse, and supplies the scan pulse to the gate line; A first pull-down switching device which is turned on or turned off in response to a logic state of a control signal, and supplies a discharge voltage source to the gate line at turn-on time; A node controller for controlling a logical state of the node; A first noise that is turned on or turned off according to the logic state of the first clock pulse supplied through the capacitor, the logic state of the node, and the logic state of the gate line, and connects the gate line and the node between the gate line and the node during turn-on; Removal switching element; And a second noise removing switching element for supplying a discharge voltage source to the gate terminal of the first noise removing switching element in response to the charging voltage source charged in the node.

In addition, the shift register according to the present invention for achieving the above object includes a plurality of stages in order to sequentially output a scan pulse to the plurality of gate lines; Each stage is turned on or off in accordance with the logic state of the node, a pull-up switching device that receives the first clock pulse when the turn-on outputs a scan pulse, and supplies the scan pulse to the gate line; A pull-down switching device which is turned on or turned off in response to a logic state of a control signal and supplies a discharge voltage source to the gate line at turn-on; A node controller for controlling a logical state of the node; The first noise canceling device is turned on or off according to a logic state of a clock pulse supplied through a capacitor, a logic state of a node, and a logic state of a gate line, and is connected between the gate line and the node at turn-on. Switching element; And a second noise removing switching element for supplying a discharge voltage source to the gate terminal of the first noise removing switching element in response to the scan pulse supplied to the gate line.

In addition, the shift register according to the present invention for achieving the above object includes a plurality of stages in order to sequentially output a scan pulse to the plurality of gate lines; Each stage is turned on or off according to the logic state of the node, a pull-up switching device that receives the clock pulse when the turn-on outputs a scan pulse, and supplies the scan pulse to the gate line; A pull-down switching device which is turned on or turned off in response to a logic state of a control signal and supplies a discharge voltage source to the gate line at turn-on; A node controller for controlling a logical state of the node; The first noise canceling device is turned on or off according to a logic state of a clock pulse supplied through a capacitor, a logic state of a node, and a logic state of a gate line, and is connected between the gate line and the node at turn-on. Switching element; A second noise removing switching element which is turned on or turned off according to the logic state of the node and receives a clock pulse and outputs a scan pulse when the node is turned on; And a third noise removing switching element for supplying a discharge voltage source to a gate terminal of the first noise removing switching element in response to a clock pulse supplied through the second noise removing switching element. It features.

In addition, the shift register according to the present invention for achieving the above object, includes a plurality of stages in order to sequentially output a scan pulse to a plurality of gate lines; Each stage is turned on or off according to the logic state of the node, a pull-up switching device that receives a clock pulse at turn-on, outputs a scan pulse, and supplies the scan pulse to a gate line; A pull-down switching device which is turned on or turned off in response to a logic state of a control signal and supplies a discharge voltage source to the gate line at turn-on; A node controller for controlling a logical state of the node; The first noise canceling device is turned on or off according to a logic state of a clock pulse supplied through a capacitor, a logic state of a node, and a logic state of a gate line, and is connected between the gate line and the node at turn-on. Switching element; And a second noise removing switching element for supplying a discharge voltage source to the gate terminal of the first noise removing switching element in response to the scan pulse from the front end stage.

Hereinafter, a shift register according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a shift register according to a first embodiment of the present invention, and FIG. 3 is a diagram illustrating a timing diagram of various signals supplied or output to each stage of FIG. 2.

The shift register according to the embodiment of the present invention includes n stages ST1 to STn and one dummy stage STn + 1 as shown in FIG. 2. Here, each of the stages ST1 to STn outputs one scan pulse Vout1 to Voutn + 1 for one frame period, in which case the scan pulses are sequentially sequentially from the first stage ST1 to the dummy stage STn + 1. Outputs

Here, the scan pulses Vout1 to Voutn output from the stages ST1 to STn except for the dummy stage STn + 1 are sequentially supplied to the gate lines of the liquid crystal panel (not shown) The gate lines are sequentially scanned.

That is, first, the first stage ST1 outputs the first scan pulse Vout1, the second stage ST2 outputs the second scan pulse Vout2, and then the third stage ST3, The third scan pulse Vout3 is output, and finally the nth scan stage STn outputs the nth scan pulse Voutn.

After the n-th stage STn outputs the n-th scan pulse Voutn, the dummy stage STn + 1 outputs the (n + 1) -th scan pulse Voutn + 1. At this time, The (n + 1) th scan pulse Voutn + 1 output from the (n + 1) -th scan line STn + 1 is not supplied to the gate line but is supplied only to the n-th stage STn.

Such a shift register is built in the liquid crystal panel. That is, the liquid crystal panel has a display portion for displaying an image and a non-display portion surrounding the display portion. The shift register is embedded in the non-display portion.

The entire stages ST1 to STn + 1 of the shift registers configured as described above are circulated with a sequential phase difference between the charging voltage source VDD, the discharge voltage source VSS, the discharge start pulse Vstd, and the sequential phase differences. Two clock pulses among the fourth clock pulses CLK1 to CLK4 are applied.

The charging voltage source VDD and the discharging voltage source VSS are all DC voltage sources, the charging voltage source VDD is positive and the discharging voltage source VSS is negative. Meanwhile, the discharging voltage source VSS may be a ground voltage.

The first to fourth clock pulses CLK1 to CLK4 are output with phase differences from each other. That is, the second clock pulse CLK2 is output by being phase-delayed by one pulse width than the first clock pulse CLK1, and the third clock pulse CLK3 is one pulse than the second clock pulse CLK2. Phase delayed by a width is output, the fourth clock pulse (CLK4) is phase-delayed by one pulse width than the third clock pulse (CLK3) and output, and the first clock pulse (CLK1) is the fourth clock pulse Phase delayed by one pulse width from (CLK4) is output.

The first to fourth clock pulses CLK1 to CLK4 are sequentially output, and are also output in a circular manner. That is, after the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output, the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output. Accordingly, the first clock pulse CLK1 is output in a period between the fourth clock pulse CLK4 and the second clock pulse CLK2.

According to the circuit configuration of the stage, the number of clock pulses supplied to one stage may vary.

The first stage ST1 positioned on the uppermost side of the stages ST1 to STn + 1 includes the above-described charging voltage source VDD, the discharge voltage source VSS, the discharge start pulse Vstd, and the first stage ST1. The start pulse Vst is further supplied in addition to any two clock pulses among the first to fourth clock pulses CLK1 to CLK4.

Each of the clock pulses CLK1 to CLK4 is output several times during one frame period, but the start pulse Vst and the discharge start pulse Vstd are output only once during one frame period.

In other words, each clock pulse CLK1 to CLK4 exhibits several active states (high states) periodically during one frame period, but the start pulse Vst and the discharge start pulse Vstd are short for one frame period. Indicates one active state.

 The third clock pulse CLK3 and the discharge start pulse Vstd may be output in synchronization with each other, and the fourth clock pulse CLK3 and the start pulse Vst may be output in synchronization with each other. have. In this case, the third clock pulse CLK3 is first outputted among the first to fourth clock pulses CLK1 to CLK4.

In order for each of the stages ST1 to STn + 1 to output the scan pulse, the enable operation of each stage ST1 to STn + 1 must be preceded. The stage being enabled means that the stage is set to a state capable of outputting, that is, a state capable of outputting a clock pulse supplied thereto as a scan pulse. To this end, each stage ST1 to STn + 1 is enabled by receiving scan pulses from the stage located at the front end thereof.

For example, the k th stage is enabled in response to the scan pulse from the k-1 st stage.

Since the stage does not exist in front of the first stage ST1 positioned at the uppermost side, the first stage ST1 is enabled in response to the start pulse Vst from the timing controller.

In addition, each stage ST1 to STn + 1 is disabled in response to the scan pulse from the next stage. When the stage is disabled, it means that the stage is reset to a state in which the output is impossible, that is, the clock pulse supplied to the stage cannot be output as a scan pulse.

For example, the kth stage is disabled in response to the scan pulse from the k + 1th stage.

The configuration of each stage ST1 to STn + 2 in the shift register configured as described above will be described in more detail as follows.

Since the configurations of the stages ST1 to STn + 2 are the same, only the second stage ST2 will be described as an example.

Fig. 4 is a diagram showing the circuit configuration of the second stage of Fig. 2. Fig.

As shown in FIG. 4, the second stage ST2 includes a node n, a node controller NC, a noise removing switching element TrN, a pull-up switching element Trpu, and a pull-down switching element Trpd. It includes.

The node controller NC controls the signal state of the node n. In other words, the node controller NC makes the node n in a charged state or in a discharged state.

The pull-up switching device Trpd is turned on when the node n is in a charged state, and then outputs a clock pulse input to the node n in the turned-on state. The clock pulse output from the turn-on pull-up switching element is a scan pulse.

The pull-up switching device Trpu provided in the k-th stage outputs a clock pulse in response to the charging voltage source VDD supplied to the node of the k-th stage, and the k-th gate line, the k + 1 stage, and It supplies to a k-1st stage. To this end, the gate terminal of the pull-up switching device (Trpu) is connected to the node n, the drain terminal is connected to the clock pulse supply line, the source terminal is the k-th gate line, the k + 1 stage, It is connected to the k-1st stage.

For example, the pull-up switching device Trpu provided in the second stage ST2 of FIG. 4 outputs the second scan pulse Vout2, and the second gate line GL2, the third stage ST3, And the first stage ST1.

The pull-down switching device Trpd is turned on in response to a clock pulse. In this turned-on state, the discharge voltage source VSS inputted thereto is output.

The pull-down switching device Trpd included in the k-th stage outputs a discharge voltage source in response to a clock pulse, and supplies it to the k-th gate line, the k + 1th stage, and the k-1st stage. To this end, the gate terminal of the pull-down switching device (Trpd) is connected to the clock pulse supply line, the source terminal is connected to the power supply line for discharge, and the drain terminal is the k-th gate line, k + 1 stage and Is connected to the k-th stage.

For example, the pull-down switching device Trpd provided in the second stage ST2 of FIG. 4 outputs a discharge voltage source VSS, and the second gate line GL2, the third stage ST3, and It supplies to the 1st stage ST1.

On the other hand, the pull-down switching device (Trpd) can be turned on by the scan pulse from the next stage. That is, the pull-down switching device Trpd included in the k-th stage may be turned on by receiving a k + 1 th scan pulse from the k + 1 th stage.

The gate line is charged by the scan pulse output from the pull-up switching device Trpu, and is discharged by the discharge voltage source VSS output from the pull-down switching device Trpd.

The noise removing switching element TrN provided in the k-th stage is turned on or off according to the logic state of the clock pulse and the logic state of the voltage applied to the k-th gate line. The node n of and the k th gate line are connected to each other.

The noise removing switching element TrN has no influence on the output of the pull-up switching element Trpu when the node n is in a charged state. However, the noise removing switching element TrN couples to the node n by periodically supplying the discharge voltage source VSS to the node n of the k-th stage at the moment when the k-th gate line is discharged. This prevents accumulation of voltage by the ring.

The node control unit NC includes first to fourth switching elements Tr1 to Tr4.

The first switching device Tr1 included in the node control unit NC of the kth stage responds to the k-1th scan pulse output from the pull-up switching device Trpu of the k-1st stage, thereby providing a charging voltage source ( VDD1) is supplied to the node n of the kth stage. To this end, the gate terminal of the first switching device Tr1 provided in the k-th stage is connected to the source terminal of the pull-up switching device Trpu provided in the k-th stage, and the drain terminal is supplied with a charging power supply. Is connected to the line, and the source terminal is connected to the node n of the k-th stage.

For example, the first switching device Tr1 included in the second stage ST2 of FIG. 4 may be configured to respond to the first scan pulse Vout1 from the first stage ST1 of the second stage ST2. The node n is charged with the charging voltage source VDD.

The second switching device Tr2 provided in the node control unit NC of the kth stage responds to the k + 1th scan pulse output from the pull-up switching device Trpu of the k + 1th stage, thereby providing a voltage for exclusive use of the room voltage ( VSS) is supplied to the node n of the kth stage. To this end, the gate terminal of the second switching element Tr2 provided in the k-th stage is connected to the source terminal of the pull-up switching element Trpu provided in the k + 1th stage, and the small tm terminal is a discharge power source. It is connected to a supply line, and the drain terminal is connected to the node n of the kth stage.

For example, the second switching device Tr2 provided in the second stage ST2 may respond to the node n of the second stage ST2 in response to the third scan pulse Vout3 from the third stage ST3. ) Is discharged to the discharge voltage source VSS.

The third switching element Tr3 provided in the node controller NC of the kth stage supplies the discharge voltage source VSS to the node n of the kth stage in response to the discharge start pulse Vstd. do. To this end, the gate terminal of the third switching element Tr3 provided in the k-th stage is connected to the discharge start pulse supply line, the source terminal is connected to the discharge power supply line, and the drain terminal is It is connected to the node n of two stages.

For example, the third switching device Tr3 included in the second stage ST2 discharges the node n of the second stage ST2 in response to the discharge start pulse Vstd. To discharge.

The operation of the shift register according to the embodiment of the present invention configured as described above is as follows.

First, the operation during the reset period TRS will be described.

During the reset period TRS, as shown in FIG. 3, only the discharge start pulse Vstd remains high, and the start pulse Vst and the remaining clock pulses CLK1 to CLK4 are kept low. maintain.

The discharge start pulse Vstd is input to all the stages ST1 to STn + 1. Specifically, the discharge start pulse Vstd is supplied to the gate terminal of the third switching device Tr3 provided in each of the stages ST1 to STn + 1.

Then, the third switching device Tr1 of each of the stages ST1 to STn + 1 is turned on, and at this time, the discharge voltage source VSS is turned on through the turned-on third switching device Tr3. The node n of the stages ST1 to STn + 1 is supplied.

Accordingly, the node n of all the stages ST1 to STn + 1 is discharged by the discharge voltage source VSS, and the pull-up switching device Trpu having a gate terminal connected to the discharged node n is Is turned on.

That is, in the reset period TRS, all the stages ST1 to STn + 1 are reset by the discharge start pulse Vstd.

Next, the operation during the initial period T0 will be described.

During the initial period T0, as shown in FIG. 3, only the start pulse Vst is kept high, and the discharge start pulse Vstd and the remaining clock pulses CLK1 to CLK4 are kept low. do.

The start pulse Vst is input to the first stage ST1. Specifically, the start pulse Vst is supplied to the gate terminal of the first switching device Tr1 provided in the first stage ST1.

Then, the first switching device Tr1 of the first stage ST1 is turned on, and at this time, the charging voltage source VDD is turned on through the turned-on first switching device Tr1. It is supplied to the node n of ST1).

Accordingly, the node n of the first stage ST1 is charged by the charging voltage source VDD, and the pull-up switching device Trpu having a gate terminal connected to the charged node n is turned on. Is on.

On the other hand, since there is no output from the second stage ST2 in this initial period T0, the second switching element Tr2 of the first stage ST1 is turned off. In addition, since the discharge start pulse Vstd is in the low state during this initial period T0, the third switching element Tr3 of the first stage ST1 is turned off. In addition, since the first clock pulse CLK1 is low in this initial period T0, the noise removing switching element TrN of the first stage ST1 is turned off. In addition, since the second clock pulse CLK2 is low in this initial period T0, the pull-down switching device Trpd of the first stage ST1 is turned off.

The operation during the first period T1 will now be described.

During the first period T1, as shown in FIG. 3, only the first clock pulse CLK1 remains high, and the remaining clock pulses including the discharge start pulse Vstd and the start pulse Vst. (CLK2, CLK3, CLK4) remain low.

Therefore, the first switching device Tr1 of the first stage ST1 is turned off in response to the start pulse Vst in the low state.

At this time, as the first switching device Tr1 is turned off, the node n of the first stage ST1 is maintained in a floating state.

Accordingly, the node n of the first stage ST1 is kept in a charged state by the charging voltage source VDD applied during the initial period T0, and the gate terminal is connected to the node n. The pull-up switching device Trpu of the first stage ST1 is turned on.

In this case, the first clock pulse CLK1 is supplied to the drain terminal of the turned-on pull-up switching device Trpu. Then, the charging voltage source VDD charged in the node n of the first stage ST1 is amplified (bootstrapping phenomenon bootstrapping).

Therefore, the first clock pulse CLK1 supplied to the drain terminal of the pull-up switching device Trpu provided in the first stage ST1 is stably output through the source terminal of the pull-up switching device Trpu. The first clock pulse CLK1 output from the pull-up switching device Trpu is a first scan pulse Vout1.

The output first scan pulse Vout1 is supplied to the first gate line GL1 and serves as a scan pulse for driving the first gate line GL1.

In addition, the first scan pulse Vout1 output from the pull-up switching device Trpu of the first stage ST1 is supplied to the second stage ST2 to supply the node n of the second stage ST2. It acts as a start pulse Vst for charging.

That is, the first scan pulse Vout1 output from the first stage ST1 in the first period T1 is supplied to the gate terminal of the first switching element Tr1 provided in the second stage ST2. do.

On the other hand, the first clock pulse CLK1 output in the first period T1 is also supplied to the gate terminal of the noise removing switching element TrN of the first stage ST1. In this case, the noise removing switching element TrN is not turned on. This is because the source terminal of the noise removing switching element TrN is connected to the first gate line GL1.

In the first period Tr1, since the first gate line GL1 is maintained in a charged state by the first scan pulse Vout1 from the first stage ST1, the switching element for removing noise The source terminal of (TrN) is also kept charged. The gate terminal of the noise removing switching element TrN is held in a charged state by the first clock pulse CLK1 in the high state.

As such, no voltage difference occurs between the gate terminal and the source terminal of the noise removing switching element TrN, so that the voltage Vgs between the gate and the source terminal of the noise removing switching element is maintained at about 0 [V]. . Accordingly, despite being supplied with the first clock pulse CLK1, it is not turned on and remains turned off. Therefore, in the first period T1, the noise removing switching element TrN of the first stage ST1 does not affect the output of the first stage ST1.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in FIG. 3, only the second clock pulse CLK2 remains high. On the other hand, the remaining clock pulses CLK1, CLK3, CLK4 and the first scan pulse Vout1 including the discharge start pulse Vstd and the start pulse Vst are kept low.

Accordingly, the first switching device Tr1 of the second stage ST2 is turned off in response to the first scan pulse Vout1 in the low state.

At this time, as the first switching device Tr1 is turned off, the node n of the second stage ST2 is maintained in a floating state.

Accordingly, the node n of the second stage ST2 is kept in a charged state by the charging voltage source VDD applied during the first period T1, and a gate terminal is connected to the node n. The pull-up switching device Trpu of the second stage ST2 is turned on.

At this time, the second clock pulse CLK2 is supplied to the drain terminal of the turn-on pull-up switching device Trpu. Then, the charging voltage source VDD charged in the node n of the second stage ST2 is amplified.

Therefore, the second clock pulse CLK2 supplied to the drain terminal of the pull-up switching device Trpu provided in the second stage ST2 is stably output through the source terminal of the pull-up switching device Trpu. The second clock pulse CLK2 output from the pull-up switching device Trpu is the second scan pulse Vout2.

The output second scan pulse Vout2 is supplied to the second gate line GL2 to act as a scan pulse for driving the second gate line GL2 and is supplied to the third stage ST3. It acts as a start pulse Vst for charging the node n of the third stage ST3.

In addition, the second scan pulse Vout2 output from the second stage ST2 in the second period T2 is supplied to the first stage ST1 to supply the node n of the first stage ST1. It serves to discharge. That is, the first stage ST1 is disabled in response to the second scan pulse Vout2 from the second stage ST2. If this is explained in more detail as follows.

That is, the second scan pulse Vout2 output from the second stage ST2 in the second period T2 is supplied to the gate terminal of the second switching element Tr2 provided in the first stage ST1. do.

Then, the second switching device Tr2 is turned on, and the discharge voltage source VSS is connected to the node n of the first stage ST1 through the turned-on second switching device Tr2. Supplied. Then, the pull-up switching device Trpu having the gate terminal connected to the discharged node n of the first stage ST1 is turned off.

In addition, the second clock pulse CLK2 output in the second period T2 is supplied to the pull-down switching device Trpd provided in the first stage. As a result, the pull-down switching device is turned on. The discharge voltage source VSS is supplied to the first gate line GL1 through the turned on pull-down switching device Trpd. Accordingly, the first gate line GL1 is discharged.

At this time, as the first gate line GL1 is discharged, the source terminal of the noise removing switching element TrN included in the first stage ST1 is discharged. Further, since the first clock pulse CLK1 is low in the second period T2, the gate terminal of the noise removing switching element TrN is also discharged in the second period T2. Accordingly, both the source terminal and the gate terminal of the noise removing switching element TrN are maintained in the discharged state in the second period T2.

In this manner, the third stage ST3 outputs the third scan pulse Vout3 in the third period T3, and the fourth stage ST4 outputs the fourth scan pulse Vout4 in the fourth period T4. Outputs

Subsequently, in the fifth period T5, as shown in FIG. 3, only the first clock pulse CLK1 is maintained high again, and the remaining time including the discharge start pulse Vstd and the start pulse Vst is maintained. Clock pulses CLK2, CLK3 and CLK4 remain low.

The first clock pulse CLK1 is supplied to the first stage ST1 again. That is, the first clock pulse CLK1 is simultaneously supplied to the gate terminal of the pull-up switching device Trpu provided in the first stage ST1 and the gate terminal of the noise removing switching device TrN. In this case, the noise removing switching element TrN of the first stage ST1 may be turned on.

This is because the source terminal of the noise removing switching element TrN is kept in a discharged state (each gate line maintains a charge state for one period in one frame and a discharged state for the remaining period). This is because the gate terminal is charged by the first clock pulse CLK1.

As a result, a voltage difference is generated between the gate terminal and the source terminal of the noise removing switching element TrN, and the voltage Vgs between the gate and source terminals reaches a turn-on voltage, and thus the noise removing switching element TrN. ) Is turned on.

Then, the discharge voltage source VSS that is hanging on the first gate line GL1 is supplied to the node n of the first stage ST1 through the turned-on noise removing switching element TrN. .

Therefore, it is possible to prevent the coupling voltage from accumulating at the node n due to the coupling phenomenon generated when the first clock pulse CLK1 is supplied to the pull-up switching device Trpu. This is because the turned-on noise removing switching element TrN discharges the node n of the first stage ST1 to the discharge voltage source VSS that is hanging on the first gate line GL1. .

As described above, when the first gate line GL1 is in the charged state, the noise removing switching element TrN of the first stage ST1 is turned off to have no influence on the normal output of the first stage ST1. Does not give. However, when the first gate line GL1 is discharged and the first clock pulse CLK1 is supplied, the noise removing switching element TrN of the first stage ST1 is turned on. Accumulation of the coupling voltage is prevented by supplying the discharge voltage source VSS, which is applied to the first gate line, to the node n of the first stage ST1.

At this time, since the first clock pulse CLK1 is periodically supplied to the first stage ST1, the noise removing switching element TrN of the first stage ST1 is connected to the first gate line GL1. In the discharged state, the node n of the first stage ST1 is periodically discharged whenever the first clock pulse CLK1 is supplied thereto.

In this manner, in the noise removing switching element TrN included in the second stage ST2, the second gate line GL2 is discharged and the second clock pulse CLK2 is supplied under the condition that the second clock pulse CLK2 is supplied. The node of the stage ST2 is discharged.

That is, the noise removing switching element TrN of each stage ST1 to STn + 1 is a stage to which the gate line connected to the stage to which it belongs is discharged and the clock pulse supplied thereto is active. Discharges the node n.

However, the noise removing switching element TrN may be turned on even when the gate line is charged in the following cases.

Since the source terminal of the noise removing switching element TrN is connected to a gate line having a larger load than the gate terminal, the source terminal reaches a charged state, i.e., a high state, compared to the gate terminal. There is no choice but to delay time.

Accordingly, although the gate line maintains the state of charge, the discharge switching station may be turned on.

For example, in the above-described first period, the first clock pulse CLK1 is applied to the drain terminal of the pull-up switching device Trpu and the gate terminal of the noise removing switching device TrN provided in the first stage ST1. Supplied together. In this case, the pull-up switching device Trpu outputs the first scan pulse Vout1 and supplies it to the first gate line GL1. The first scan pulse Vout1 supplied to the first gate line GL1 is also supplied to the source terminal of the noise removing switching element TrN. Accordingly, the first scan pulse Vout1 is supplied to the source terminal of the noise removing switching element TrN, and the first clock pulse CLK1 is applied to the gate terminal. As described above, since the load of the first gate line GL1 to which the first scan pulse Vout1 is supplied is greater than that of the gate terminal to which the first clock pulse CLK1 is applied, The gate terminal and the source terminal of the switching element TrN are not simultaneously brought high, and the gate terminal with the small load is first charged to the high state.

Therefore, a voltage difference may be generated between the gate terminal and the source terminal of the noise removing switching element TrN so that the noise removing switching element TrN may be turned on.

When the noise removing switching element TrN is turned on in the first period T1, the voltage level of the node n of the first stage ST1 falls, and thus, the node n The pull-up switching device Trpu connected through the gate terminal may not be completely turned on. Then, the output from the pull-up switching device Trpu may be weakened, and the output state of the remaining stages ST2 to STn + 1 may also be unstable due to the weakened output.

In order to prevent such a problem, it is important to increase the threshold voltage Vth of the noise removing switching element TrN. For this purpose, it is preferable to change the noise removing switching element TrN to the following structure. .

FIG. 5 is a diagram illustrating another circuit configuration of the second stage of FIG. 2.

Each stage ST1 to STn + 1 includes first and second noise removing switching elements TrN1 and TrN2 instead of the noise removing switching element TrN as shown in FIG. 5.

Except for the first and second noise removing switching elements TrN1 and TrN2, the other components are the same as those described above, and thus description thereof will be omitted.

The first noise removing switching element TrN1 included in the k-th stage is connected to the second node n2 of the k-th stage of the first node n1 (same as the node n described above) in response to the clock pulse. Supply the charging voltage source (VDD).

The second noise removing switching element TrN2 provided in the k-th stage is turned on or off according to the logic state of the second node n2 and the k-th gate line, and the k-th gate is turned on when the k-th stage is turned on. The discharge voltage source VSS applied to the line is supplied to the first node n1 of the k-th stage. In this case, the discharge voltage source VSS of the k-th gate line is supplied to the first node n1 of the k-th stage through the first and second noise removing switching elements TrN1 and TrN2.

For example, in a state in which the first scan pulse Vout1 is supplied to the first gate line GL1 through the pull-up switching device Trpu of the first stage ST1 in the first period T1, The first noise removing switching element TrN1 is turned on, but the second noise removing switching element TrN2 is not turned on. The reason why the second noise removing switching element TrN2 is not turned on is that both the gate terminal and the source terminal of the second noise removing switching element TrN2 are maintained at a high level, This is because no voltage difference occurs between the source terminals.

In this case, the second noise removing switching element TrN2 is connected between the first noise removing switching element TrN1 and the first gate line GL1 in the form of a diode.

The overall threshold voltages of the first and second noise removing switching elements TrN1 and TrN2 are higher than the threshold voltages of the noise removing switching elements TrN shown in FIG. 4. As a result, it is possible to prevent the first and second noise removing switching elements TrN1 and TrN2 from being turned on in the output period (period for outputting the scan pulse) of each stage ST1 to STn + 1.

Thereafter, in the fifth period T5, the first clock pulse CLK1 is simultaneously applied to the drain terminal of the pull-up switching device Trpu of the first stage ST1 and the gate terminal of the first noise removing switching device TrN1. When supplied, both the first and second noise removing switching elements TrN1 and TrN2 are turned on. Then, the discharge voltage source VSS that is applied to the first gate line GL1 through the turned-on first and second noise removing switching elements TrN1 and TrN2 is the first of the first stage ST1. Supplied to node n1.

FIG. 6 is a diagram illustrating another circuit configuration of the second stage of FIG. 2.

Each stage ST1 to STn + 1 includes first to third noise removing switching elements TrN1, TrN2, and TrN3, as shown in FIG.

Since the other components except for the first to third noise removing switching elements TrN1 to TrN3 are the same as those described above, a description thereof will be omitted.

The first noise removing switching element TrN1 included in the k-th stage is connected to the second node n2 of the k-th stage of the first node n1 (same as the node n described above) in response to the clock pulse. Supply the charging voltage source (VDD).

The second noise removing switching element TrN2 provided in the k-th stage supplies the discharge voltage source VSS to the second node n2 of the k-th stage in response to the clock pulse.

The third noise removing switching element TrN3 included in the k-th stage is turned on or off according to the logic state of the second node n2 and the k-th gate line, and when turned on, the k-th stage The first node n1 and the k th gate line are connected to each other.

Here, the clock pulse supplied to the second noise removing switching element TrN2 provided in the k-th stage is delayed by one clock pulse width than the clock pulse supplied to the pull-down switching element Trpd provided in the k-th stage. Is output. Therefore, the clock pulse supplied to the second noise removing switching element Trd2 provided in the k-th stage is the same as the clock pulse supplied to the pull-up switching element Trpd provided in the k + 2th stage.

For example, the fourth clock pulse CLK4 is supplied to the gate terminal of the second noise removing switching element Trd2 provided in the second stage ST2.

The overall threshold voltage of the first to third noise removing switching elements TrN1 to TrN3 is higher than that of the noise removing switching element TrN shown in FIG. 4. Accordingly, it is possible to prevent the first to third noise removing switching elements TrN1 to TrN3 from being turned on in the output period (the period during which the scan pulse is output) of each stage ST1 to STn + 1. .

The operations of the first to third noise removing switching elements TrN1 to TrN3 included in the first stage ST1 will be described below.

First, as the first node n1 is charged by the charging voltage source VDD in the initial period T0, the pull-up switching device Trpu provided in the first stage ST1 is turned on.

Thereafter, the first clock pulse CLK1 is output in the first period T1, so that the drain terminal of the pull-up switching device Trpu and the first noise removing switching device TrN1 of the first stage ST1 are output. It is supplied together to the gate terminal.

Then, in the first period T1, the pull-up switching device Trpu outputs a first scan pulse Vout1 and supplies it to the first gate line GL1, and the first noise removing switching device TrN1. Is turned on to charge the second node n2 with the charging voltage source VDD by electrically connecting the first node n1 and the second node n2. Accordingly, both the gate terminal and the source terminal of the third noise removing switching element TrN3 have a high level, and the third noise removing switching element TrN3 maintains a turn-off state.

Next, while the first clock pulse CLK1 is turned low in the second period T2, the first noise removing switching element TrN1 of the first stage ST1 is turned off. In addition, since the first stage ST1 is disabled in the second period T2, the first stage ST1 is discharged through a pull-down switching element Trpd in the second period T2. VSS) is output and supplied by the first gate line GL1. Accordingly, the first gate line GL1 is discharged in the second period T2.

Then, the source terminal of the third noise removing switching element TrN3 of the first stage ST1 represents a low level, and the gate terminal represents a high level. That is, the gate terminal of the third noise removing switching element TrN3 is connected to the second node n2. Since the second node n2 is still charged during the second period T2, the gate The terminal has a high level.

Accordingly, a voltage difference is generated between the gate terminal and the source terminal of the third noise removing switching element TrN3 in the second period T2, so that the third noise removing switching element TrN3 is turned on. . The first node n1 of the first stage ST1 and the first gate line GL1 are electrically connected through the turned-on third noise removing switching element TrN3. Therefore, the first node n1 is discharged by the discharge voltage source VSS that is applied to the first gate line GL1.

Next, the third clock pulse CLK3 is output in the third period T3 and supplied to the second noise removing switching element Trd2 of the first stage ST1. Accordingly, the second noise removing switching element TrN2 is turned on in the third period T3, and the discharge voltage source VSS is turned on through the turned-on second noise removing switching element TrN2. This is supplied to the second node n2 of the first stage ST1. Then, the second node n2 is discharged, and the third noise removing switching element TrN3 connected to the discharged second node n2 through the gate terminal is turned off.

Next, in the fifth period T5 after the fourth period T4, the first clock pulse CLK1 is output again and supplied to the first stage ST1.

Since the first gate line GL1 is discharged in the fifth period T5, the third noise removing switching element TrN3 of the first stage ST1 is turned on in the fifth period T5. -On. This is because voltage sources having different levels are supplied between the gate terminal and the source terminal of the third noise removing switching element TrN3 to generate a voltage difference between the gate terminal and the source terminal.

When the first to third noise removing switching elements TrN1 to TrN3 having the structure as shown in FIG. 6 are used, each stage ST1 to STn + immediately after the output period of each stage ST1 to STn + 1. In addition to discharging the first node n1 of 1), the first node n1 may be discharged at every cycle in which a clock pulse is supplied. In addition, such a structure can increase the threshold voltages of the first to third noise removing switching elements TrN1 to TrN3, and thus removes the first to third noise in the output period of each stage ST1 to STn + 1. The problem caused by turning on the switching devices TrN1 to TrN3 can be solved.

FIG. 7 is a diagram illustrating another circuit configuration of the second stage of FIG. 2.

As illustrated in FIG. 7, each stage ST1 to STn + 1 includes a first switching device Tr1, a second switching device Tr2, a pull-up switching device Trpu, a pull-down switching device Trpd, and noise. And a resistor R connected to the removal switching element TrN and the noise removing switching element TrN.

The first switching element Tr1, the second switching element Tr2, the pull-up switching element Trpu, and the pull-down switching element Trpd are the same as those shown in FIG. 4.

The noise removing switching element TrN is supplied with a clock pulse through the resistor R. That is, the gate terminal of the noise removing switching element TrN is connected to the clock pulse supply line through the resistor R.

The resistor R has the same value as the load of the gate line to which the source terminal of the noise removing switching element TrN is connected.

By providing the resistor R at the gate terminal of the noise removing switching element TrN as described above, the charging time between the gate terminal and the source terminal of the noise removing switching element TrN can be made the same. Accordingly, it is possible to prevent the noise removing switching element TrN from being turned on in the output period of each stage ST1 to STn + 1.

8 is a diagram illustrating another circuit configuration of the second stage of FIG. 2.

As illustrated in FIG. 8, each of the stages ST1 to STn + 1 includes a first switching device Tr1, a second switching device Tr2, a pull-up switching device Trpu, a pull-down switching device Trpd, and a first switching device Trd. And a resistor R connected to the first noise removing switching element TrN1, the second noise removing switching element TrN2, and the first noise removing switching element TrN1.

The first switching element Tr1, the second switching element Tr2, the pull-up switching element Trpu, and the pull-down switching element Trpd are the same as those shown in FIG. 4.

The second noise removing switching element TrN2 may discharge the gate terminal of the first noise removing switching element TrN1 in response to the charging voltage source VDD charged in the node n. To discharge.

To this end, the gate terminal of the second noise removing switching element TrN2 provided in the kth stage is connected to the node n of the kth stage, and the source terminal of the first switching provided in the kth stage. It is connected to the gate terminal of the element Tr1, and the drain terminal is connected to the discharge voltage supply line.

The second noise removing switching element TrN2 is turned on when the node n is in a charged state, and the discharge voltage source VSS is turned on through the turned-on second noise removing switching element TrN2. The gate terminal of the first noise removing switching element TrN1 is supplied. Accordingly, the first noise removing switching element TrN1 is turned off.

That is, the second noise removing switching element TrN2 may be configured to turn off the first noise removing switching element TrN1 when the node n is in a charged state so that the first noise removing switching element TrN2 is turned off. TrN1) does not affect the state of charge of the node (n).

In other words, the second noise removing switching element TrN2 turns off the first noise removing switching element TrN1 in the output period of each of the stages ST1 to STn + 1, whereby each stage ST1 to Normal output is generated from STn + 1).

The resistor R reduces the magnitude of the clock pulse supplied to the gate terminal of the first noise removing switching element TrN1, thereby removing the first noise when the second switching element Tr2 is turned on. The switching element TrN1 is prevented from being turned on.

That is, in the output period of the stage, the second noise removing switching element TrN2 is turned on and a clock pulse is supplied to the gate terminal of the first noise removing switching element TrN1. Accordingly, a clock pulse in a high state and a discharge voltage source VSS in a low state are supplied to a gate terminal of the first noise removing switching element TrN1 during the output period. In this case, the resistor R reduces the magnitude of the clock pulse so that the discharge voltage source VSS is supplied to the gate terminal of the first noise removing switching element TrN1. Therefore, during the output period of the stage, the first noise removing switching element TrN1 may maintain a turn-off state.

On the other hand, since the node n of the stage is in a discharge state other than the output period of the stage, the second noise removing switching element TrN2 maintains the turn-off state from the next period of the output period. Therefore, only the clock pulse is supplied to the gate terminal of the first noise removing switching element TrN1 after the output period. Therefore, the first noise removing switching element TrN1 is periodically turned on every time the clock pulse is supplied after the output period.

The node n and the gate line of the stage are connected to each other through the turned-on first noise removing switching element TrN1, and thus the node n is discharged.

FIG. 9 is a diagram illustrating another circuit configuration of the second stage of FIG. 2.

As illustrated in FIG. 9, each stage includes a first switching element Tr1, a second switching element Tr2, a pull-up switching element Trpu, a pull-down switching element Trpd, and a first noise removing switching element ( TrN1), a second noise removing switching element TrN2, and a capacitor CAP connected to the first noise removing switching element TrN1.

The configuration shown in FIG. 9 is the same as the configuration shown in FIG. 8, only the resistor R has been replaced with a capacitor CAP.

The capacitor CAP increases the time for which the clock pulse supplied to the gate electrode of the first switching element Tr1 reaches a high state, thereby turning on the first switching element Tr1 in the output period. prevent.

Here, the capacitance of the capacitor CAP has a size defined by the following equation.

0.5 * C1 <C <10 * C1

C shown in the above equation represents the capacitance of the capacitor CAP.

C1 denotes a parasitic capacitance of the first noise removing switching element TrN1, that is, a capacitance formed between the semiconductor layer and the gate electrode. An insulating film is formed between the semiconductor layer and the gate electrode as a dielectric. On the other hand, the parasitic capacitance may be a parasitic capacitance between the gate electrode and the source electrode, or may be a parasitic capacitance between the gate electrode and the drain electrode.

Meanwhile, the second noise removing switching element TrN2 illustrated in FIG. 9 may operate by receiving a scan pulse from the front stage instead of the charging voltage source VDD supplied to the node n.

That is, the second noise removing switching element TrN2 included in the kth stage may operate by receiving a k-1th scan pulse from the k-1st stage.

For example, the second noise removing switching element TrN2 included in the second stage ST2 may operate by receiving the first scan pulse Vout1 from the first stage ST1.

FIG. 10 is a diagram illustrating still another circuit configuration of the second stage of FIG. 2.

The stage shown in FIG. 10 is the same as that of FIG. 9 and further includes only the second pull-down switching element Trpd2.

The first pull-down switching device Trpd1 is the same as the pull-down switching device Trpd of FIG. 9.

The second pull-down switching device Trpd2 discharges the gate line to the discharge voltage source VSS in response to the scan pulse from the next stage.

In other words, the second pull-down switching device Trpd2 included in the kth stage is turned on in response to the k + 1th scan pulse from the k + 1th stage.

FIG. 11 is a diagram illustrating another circuit configuration of the second stage of FIG. 2.

The configuration shown in FIG. 11 is the same as the configuration shown in FIG. 9, and only the connection relationship of the pull-down switching element Trpd is different.

That is, the pull-down switching device Trpd illustrated in FIG. 11 supplies the discharge voltage source VSS to the gate line in response to a clock pulse supplied through the capacitor CAP.

FIG. 12 is a diagram illustrating another circuit configuration of the second stage of FIG. 2.

The configuration shown in FIG. 12 is the same as the configuration shown in FIG. 11 and further includes only the second pull-down switching element Trpd2.

The second pull-down switching device Trpd2 is the same as the second pull-down switching device Trpd2 described with reference to FIG. 10.

FIG. 13 is a diagram illustrating another circuit configuration of the second stage of FIG. 2.

The configuration shown in FIG. 13 is the same as that shown in FIG. 9, and the connection relationship of only the second noise removing switching element TrN2 is different.

That is, the second noise removing switching element TrN2 shown in FIG. 13 supplies the discharge voltage source VSS to the gate terminal of the first noise removing switching element TrN1 in response to a scan pulse from the gate line. .

Herein, an operation of the second stage ST2 including the first and second noise removing switching elements TrN1 and TrN2 will be described below.

In the first period T1, the node n of the second stage ST2 is charged by the first scan pulse Vout1. Accordingly, the pull-up switching device Trpu connected to the node n through the gate terminal is turned on.

Thereafter, the second clock pulse CLK2 is output in the second period T2 and supplied to the drain terminal of the pull-up switching device Trpu. In addition, the second clock pulse CLK2 is supplied to the gate terminal of the first noise removing switching element TrN1 and the source terminal of the second noise removing switching element TrN2 through the capacitor CAP.

Accordingly, the turned-on pull-up switching device Trpu outputs the second clock pulse CLK2 as the second scan pulse Vout2 and supplies it to the second gate line GL2. Then, the second gate line GL2 is charged.

As the second gate line GL2 is charged, the second noise removing switching element TrN2 connected to the second gate line GL2 through the gate terminal is turned on.

The discharge voltage source VSS is supplied to the gate terminal of the first noise removing switching element TrN1 through the turned-on second noise removing switching element TrN2. Therefore, the first noise removing switching element TrN1 is turned off.

As a result, during the output period during which the second stage ST2 outputs the second scan pulse Vout2, the second noise removing switching element TrN2 turns off the first noise removing switching element TrN1. By doing so, the first noise removing switching element TrN1 does not affect the state of charge of the node n of the second stage ST2.

FIG. 14 is a diagram illustrating another circuit configuration of the second stage of FIG. 2.

The configuration of FIG. 14 is the same as that of FIG. 9, and further includes only a third noise removing switching element TrN3, and the connection relationship between the second noise removing switching element TrN2 is the second noise of FIG. It is different from the removal switching element TrN2.

That is, the third noise removing switching element TrN3 is a voltage source for discharge to the gate electrode of the first noise removing switching element TrN1 in response to a clock pulse supplied through the second noise removing switching element TrN2. Supply (VSS).

The second noise removing switching element TrN2 supplies the clock pulse to the gate terminal of the third noise removing switching element TrN3 in response to the charging voltage source VDD supplied to the node n. .

Here, an operation of the second stage ST2 including the first to third noise removing switching devices TrN1 to TrN3 will be described below.

In the first period T1, the node n of the second stage ST2 is charged by the first scan pulse Vout1. Accordingly, the pull-up switching device Trpu and the second noise removing switching device TrN2 connected to the node n through the gate terminal are turned on.

Thereafter, the second clock pulse CLK2 is output in the second period T2 and supplied to the drain terminal of the pull-up switching device Trpu and the drain terminal of the second noise removing switching device TrN2. In addition, the second clock pulse CLK2 is supplied to the gate terminal of the first noise removing switching element TrN1 and the source terminal of the third noise removing switching element TrN3 through the capacitor CAP.

Accordingly, the pull-up switching device Trpu outputs the second clock pulse CLK2 as the second scan pulse Vout2. In addition, a second clock pulse CLK2 is output through the turned-on second noise removing switching element TrN2, and the second clock pulse CLK2 is a gate of the third noise removing switching element TrN3. Supplied to the terminal. Then, the third noise removing switching element TrN3 is turned on, and the discharge voltage source VSS is turned on through the turned-on third noise removing switching element TrN3. It is supplied to the gate terminal of TrN1. Therefore, the first noise removing switching element TrN1 is turned off.

As a result, in the output period during which the second stage ST2 outputs the second scan pulse Vout2, the second and third noise canceling switching devices TrN2 and TrN3 perform the first noise canceling switching device. By turning off TrN1, the first noise removing switching element TrN1 does not affect the state of charge of the node n of the second stage.

FIG. 15 is a diagram illustrating still another circuit configuration of the second stage of FIG. 2.

The configuration shown in FIG. 15 is the same as the configuration shown in FIG. 14, and further includes only the second pull-down switching element Trpd2.

The second pull-down switching device Trpd2 is the same as the second pull-down switching device Trpd2 described with reference to FIG. 10.

On the other hand, the high periods of the clock pulses CLK1 to CLK4 output in adjacent periods may partially overlap each other. In this case, the scan pulses Vout1 to Voutn + 1 output from the stages ST1 to STn + 1 also partially overlap their high intervals.

Of course, the start pulse Vst and the discharge start pulse Vstd may also be output to overlap the clock pulses CLK1 to CLK4.

In this case, the kth stage is enabled by the k-1th scan pulse from the k-1st stage, and the kth stage is disabled by the k + 2th scan pulse from the k + 2th stage.

That is, the second switching device Tr2 and the second pull-down switching device Trpd2 provided in the kth stage operate by the k + 2th scan pulse from the k + 2th stage.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The shift register according to the present invention as described above has the following effects.

The shift register of the present invention includes a switching element for removing noise. The noise canceling switching element is turned off during the normal output period of each stage, and thus does not affect the output state of each stage. In the non-output period of each stage, the voltage source for discharge of the corresponding gate line is applied to the node of each stage. The supply prevents the node from being charged by the coupling phenomenon.

Therefore, it is possible to prevent the multi output caused by the accumulation of voltage at each node in the non-output period of each stage.

In addition, by using two or more noise removing switching elements to increase the threshold voltage of the noise removing switching element, it is possible to prevent the noise removing switching element from being turned on during the output period of the stage.

Claims (23)

A plurality of stages which in turn output scan pulses to sequentially supply the plurality of gate lines; Each stage, A pull-up switching device which is turned on or turned off according to a logic state of a first node, receives a first clock pulse to output scan pulses, and supplies the scan pulses to a gate line; A pull-down switching device which is turned on or turned off in response to a logic state of a control signal and supplies a discharge voltage source to the gate line at turn-on; A node controller for controlling a logic state of the first node; A first noise removing switching element connecting the first node and the second node in response to the first clock pulse; And A second switching element which is turned on or turned off according to the logic state of the second node and the gate line, and connects the gate line and the first node through the first noise removing switching element at turn-on; And a shift register. The method of claim 1, Node control unit provided in each stage, A first switching element for supplying a charging voltage source to the first node in response to a start pulse or a scan pulse from a front end stage; A second switching element for supplying a discharge voltage source to the first node in response to a scan pulse from a next stage; And a third switching element for supplying a discharge voltage source to the first node in response to a discharge start pulse. The method of claim 2, The first switching element provided in the node controller of the nth stage is supplied with the scan pulse from the n-1th stage; And, And the second switching device provided in the node controller of the nth stage is supplied with scan pulses from the n + 1th stage. The method of claim 2, The first switching element provided in the node controller of the nth stage is supplied with the scan pulse from the n-1th stage; And, And a second switching device provided in the node controller of the nth stage is supplied with a scan pulse from an n + 2th stage. The method of claim 1, And the control signal is a clock pulse from an external source or a scan pulse from a next stage. A plurality of stages which in turn output scan pulses to sequentially supply the plurality of gate lines; Each stage, A pull-up switching device which is turned on or turned off according to a logic state of a first node, receives a first clock pulse to output scan pulses, and supplies the scan pulses to a gate line; A pull-down switching device which is turned on or turned off in response to a logic state of a control signal and supplies a discharge voltage source to the gate line at turn-on; A node controller for controlling a logic state of the first node; A first noise removing switching element connecting the first node and the second node in response to the first clock pulse; A second noise removing switching element supplying a discharge voltage source to the second node in response to a second clock pulse; And And a third switching element which is turned on or turned off according to the logic state of the second node and the gate line, and connects between the first node and the gate line at turn-on. The method of claim 6, And the second clock pulse is delayed by two clock pulse widths than the first clock pulse. The method of claim 6, Node control unit provided in each stage, A first switching element for supplying a charging voltage source to the first node in response to a start pulse or a scan pulse from a front end stage; A second switching element for supplying a discharge voltage source to the first node in response to a scan pulse from a next stage; And a third switching device for supplying a discharge voltage source to the first node in response to the start pulse. The method of claim 6, And the control signal is a clock pulse from an external source or a scan pulse from a next stage. A plurality of stages which in turn output scan pulses to sequentially supply the plurality of gate lines; Each stage, A pull-up switching element which is turned on or turned off according to a logic state of a node, receives a first clock pulse to output a scan pulse, and supplies the scan pulse to a gate line; A pull-down switching device which is turned on or turned off in response to a logic state of a control signal and supplies a discharge voltage source to the gate line at turn-on; A node controller for controlling a logical state of the node; And A first noise that is turned on or turned off according to a logic state of a first clock pulse supplied through a resistor, a logic state of a node, and a logic state of a gate line, and connects the gate line and the node between the nodes when the turn-on is turned on A shift register comprising a switching element for removal. 11. The method of claim 10, And the resistor has the same value as the load of the gate line connected to the source terminal of the first noise removing switching element. 11. The method of claim 10, And a second noise elimination switching element for supplying a discharge voltage source to the gate terminal of the first noise elimination switching element in response to the charging voltage source charged in the node. 11. The method of claim 10, Node control unit provided in each stage, A first switching element for supplying a charging voltage source to the first node in response to a start pulse or a scan pulse from a front end stage; And And a second switching element for supplying a discharge voltage source to the first node in response to a scan pulse from a next stage. 11. The method of claim 10, And the control signal is a scan pulse from a next stage or a second clock pulse output in the same period as the scan pulse. A plurality of stages which in turn output scan pulses to sequentially supply the plurality of gate lines; Each stage, A pull-up switching element which is turned on or turned off according to a logic state of a node, receives a first clock pulse to output a scan pulse, and supplies the scan pulse to a gate line; A first pull-down switching device which is turned on or turned off in response to a logic state of a control signal, and supplies a discharge voltage source to the gate line at turn-on time; A node controller for controlling a logical state of the node; A first noise that is turned on or off according to the logic state of the first clock pulse supplied through the capacitor, the logic state of the node, and the logic state of the gate line, and connects the gate line and the node between the gate line and the node during turn-on; Removal switching element; And And a second noise removing switching element for supplying a discharge voltage source to the gate terminal of the first noise removing switching element in response to the charging voltage source charged in the node. 16. The method of claim 15, And a capacitance (C) of the capacitor and a capacitance (C1) of the first noise removing switching element have the following mathematical relationship. 0.5 * C1 <C <10 * C1 16. The method of claim 15, And a second pull-down switching element for supplying a discharge voltage source to the gate line in response to a scan pulse from a next stage. 16. The method of claim 15, And the control signal is a first clock pulse supplied through the capacitor. The method of claim 18, And a second pull-down switching element for supplying a discharge voltage source to the gate line in response to a scan pulse from a next stage. A plurality of stages which in turn output scan pulses to sequentially supply the plurality of gate lines; Each stage, A pull-up switching element which is turned on or turned off according to a logic state of a node, receives a first clock pulse to output a scan pulse, and supplies the scan pulse to a gate line; A pull-down switching device which is turned on or turned off in response to a logic state of a control signal and supplies a discharge voltage source to the gate line at turn-on; A node controller for controlling a logical state of the node; The first noise canceling device is turned on or off according to a logic state of a clock pulse supplied through a capacitor, a logic state of a node, and a logic state of a gate line, and is connected between the gate line and the node at turn-on. Switching element; And And a second noise removing switching element for supplying a discharge voltage source to the gate terminal of the first noise removing switching element in response to the scan pulse supplied to the gate line. A plurality of stages which in turn output scan pulses to sequentially supply the plurality of gate lines; Each stage, A pull-up switching device which is turned on or turned off according to a logic state of a node, receives a clock pulse and outputs a scan pulse upon supplying the scan pulse, and supplies the scan pulse to a gate line; A pull-down switching device which is turned on or turned off in response to a logic state of a control signal and supplies a discharge voltage source to the gate line at turn-on; A node controller for controlling a logical state of the node; The first noise canceling device is turned on or off according to a logic state of a clock pulse supplied through a capacitor, a logic state of a node, and a logic state of a gate line, and is connected between the gate line and the node at turn-on. Switching element; A second noise removing switching element which is turned on or turned off according to the logic state of the node and receives a clock pulse and outputs a scan pulse when the node is turned on; And And a third noise canceling switching device configured to supply a discharge voltage source to a gate terminal of the first noise canceling switching device in response to a clock pulse supplied through the second noise canceling switching device. Shift register. 22. The method of claim 21, And a second pull-down switching element for supplying a discharge voltage source to the gate line in response to a scan pulse from a next stage. A plurality of stages which in turn output scan pulses to sequentially supply the plurality of gate lines; Each stage, A pull-up switching device which is turned on or turned off according to a logic state of a node, receives a clock pulse and outputs a scan pulse upon supplying the scan pulse, and supplies the scan pulse to a gate line; A pull-down switching device which is turned on or turned off in response to a logic state of a control signal and supplies a discharge voltage source to the gate line at turn-on; A node controller for controlling a logical state of the node; The first noise canceling device is turned on or off according to a logic state of a clock pulse supplied through a capacitor, a logic state of a node, and a logic state of a gate line, and is connected between the gate line and the node at turn-on. Switching element; And And a second noise canceling switching device for supplying a discharge voltage source to the gate terminal of the first noise canceling switching device in response to a scan pulse from a front end stage.

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