KR101859471B1 - Shift register - Google Patents

Abstract

The present invention relates to a shift register capable of keeping the output characteristics of two output pulses the same in a structure in which one stage generates two output pulses, and in a shift register including a plurality of stages, A node controller for controlling a voltage of the node and the reset node; And an output unit for sequentially outputting at least four output pulses through the four output terminals, two at a time, based on at least two clock pulses having a voltage of the set node, a voltage of the reset node, and different phase differences ; And the node control unit discharges any one of the output terminals of the output unit before discharging the set node.

Description

SHIFT REGISTER {SHIFT REGISTER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register of a liquid crystal display, and more particularly, to a shift register capable of keeping the output characteristics of two output pulses the same in a structure in which one stage generates two output pulses.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged in an intersecting manner, and a pixel region is located in an area defined by vertically intersecting the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed on the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) as a switching element. The thin film transistor is turned on by a scan pulse applied to the gate electrode via the gate line so that the data signal of the data line is charged to the pixel voltage.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, And a power supply unit for supplying various driving voltages used in the plasma display apparatus.

The gate driver sequentially supplies scan pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. Here, the gate driver includes a shift register for sequentially outputting the scan pulses as described above.

Such a shift register includes a plurality of stages formed with a plurality of switching elements.

Meanwhile, in order to reduce the number of switching elements, two or more output units may be provided in one stage so that one stage outputs two output pulses. In this case, when the output pulses are output, The output characteristics between the output pulses are varied. Therefore, when a shift register having such a stage is applied to a display device, the image quality is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a method and apparatus for controlling a polling time of a first output pulse and a polling time of a second output pulse by discharging an output terminal to which a second output pulse is applied, And to improve the output characteristics by minimizing the difference between the output signals.

According to an aspect of the present invention, there is provided a shift register including a plurality of stages, each stage including a node controller for controlling a voltage of a set node and a reset node; And an output unit for sequentially outputting at least four output pulses through the four output terminals, two at a time, based on at least two clock pulses having a voltage of the set node, a voltage of the reset node, and different phase differences ; And the node control unit discharges any one of the output terminals of the output unit before discharging the set node.

The four output pulses output from the output unit provided in the n-th stage (n is a natural number) include a second n-1 carry pulse, a second n-1 scan pulse, a second n-carry pulse, and a second n scan pulse; The output unit provided in the n-th stage outputs a second m-1 clock pulse and a second m clock pulse m, which are output in the adjacent periods among the first through sixth clock pulses sequentially out- Natural water); The pulse widths in the active state of the first to sixth clock pulses are all the same; The pulse widths of the adjacent clock pulses overlap each other for a predetermined period; The second m-1 clock pulse having a phase prior to the second m clock pulse; The four output terminals include a first carry output terminal, a first scan output terminal, a second carry output terminal, and a second scan output terminal; Wherein the output section provided in the nth stage includes a first output section for outputting the second n-1 carry pulse and the second scan pulse through the first carry output terminal and the first scan output terminal, And a second output section for outputting the second n-mer pulse and the second scan pulse through a second carry output terminal and a second scan output terminal; A first output unit provided in the n-th stage outputs a second n-1 carry pulse and a second n-1 scan pulse based on the voltage of the set node, the voltage of the reset node, and the m-th clock pulse; A second output unit provided in the nth stage outputs a second n-mer pulse and a second n scan pulse based on the voltage of the set node, the voltage of the reset node, and the (m + 1) -th clock pulse; And the node control unit provided in the nth stage discharges the second scan output terminal in response to a second n + 3 carry pulse from the (n + 2) th stage before discharging the set node.

And the node control unit discharges the second scan output terminal by supplying a first discharge voltage to the second scan output terminal in response to the second n + 3 carry pulse.

And a voltage value of the first to sixth clock pulses in an inactive state is equal to or smaller than a voltage of the first discharge voltage.

Wherein the first output unit provided in the nth stage includes a first carry pulse output unit for outputting the second n-1 carry pulse and a first scan pulse output unit for outputting the second n-1 scan pulse; The second output unit provided in the n-th stage includes a second carry pulse output unit for outputting the second n-care pulse and a second scan pulse for outputting the second scan pulse.

The first carry pulse output unit generates a second n-1 carry pulse based on the voltage of the set node, the voltage of the reset node, and the (2m-1) -th clock pulse, and outputs the second n-1 carry pulse through the first carry output terminal, Generating the first discharge voltage based on the voltage of the set node, the voltage of the reset node, and the first discharge voltage, and outputting the first discharge voltage through the first carry output terminal; The first scan pulse output unit generates a second n-1 scan pulse based on the voltage of the set node, the voltage of the reset node, and the (2m-1) -th clock pulse and outputs the generated scan pulse through a first scan output terminal, Generates the second discharge voltage based on the voltage of the set node, the voltage of the reset node, and the second discharge voltage, and outputs the second discharge voltage through the first scan output terminal; The second carry pulse output unit generates a second n-carry pulse based on the voltage of the set node, the voltage of the reset node, and the second m clock pulse, outputs the second n-carry pulse through the second carry output terminal, Generates the first discharge voltage based on a voltage, a voltage at a reset node, and a first discharge voltage, and outputs the first discharge voltage through the second carry output terminal; The second scan pulse output unit generates a second n scan pulse based on the voltage of the set node, the voltage of the reset node, and the second m clock pulse, outputs the second scan pulse through the second scan output terminal, And generates the second discharge voltage based on the voltage, the voltage of the reset node, and the second discharge voltage, and outputs the second discharge voltage through the second scan output terminal.

The first carry pulse output unit provided at the n-th stage is turned on or off according to the voltage of the set node, and is turned on when the second m-1 clock transmission line And a first carry output terminal connected to the first carry output terminal and the first carry output terminal, and a second carry output terminal connected to the first carry output terminal and the second output terminal in a turn- And a first carry pull-down switching element for connecting the first discharge power supply line for transmitting a dedicated voltage to each other; The first scan pulse output unit provided in the n-th stage turns on or off according to a voltage of the set node. When the turn-on of the second m-1 clock transmission line and the first scan output terminal occurs, A first scan pull-up switching element that connects the first scan output terminal and the second scan output terminal to the first scan output terminal, and a second scan output terminal that turns on or off according to a voltage of the reset node, A first scan pulldown switching element connecting power lines to each other; Wherein the second carry pulse output unit provided in the nth stage is turned on or off according to a voltage of the set node and is connected to a second m clock transmission line for transmitting the second m clock pulse when turned on, A second carry pull-up switching element for connecting the carry output terminals to each other and a second carry pull-up switching element for turning on or off according to a voltage of the reset node, And a second carry pull-down switching element connected to each other; The second scan pulse output unit provided in the nth stage turns on or off according to a voltage of the set node and connects the second m clock transmission line and the second scan output terminal to each other when the turn- A second scan pull-up switching element and a second scan pull-down switch that is turned on or off according to a voltage of the reset node and connects the second scan output terminal and the second power- And a switching element.

The node controller provided in the n-th stage turns on or off according to a second n-3 carry pulse from the (n-1) th stage, and when turned on, A first switching element for connecting the set node to each other; The second carry output terminal is turned on or off according to a second m-2 clock pulse from the (2m-2) -th clock transmission line, and when the second carry output terminal is turned on, 2 switching device; A third switching element that is turned on according to a charging voltage from a charging power supply line and connects the charging power supply line and the reset node when turned on; A fourth switching device that turns on or off according to the voltage of the set node and connects the reset node and the first power supply line when turned on; A second switching element for turning on or off according to a second n + 3 carry pulse from the (n + 2) th stage and connecting the second scan output terminal and the first discharge power supply line to each other at turn-on; And a second n + 4 carry pulse from the (n + 2) th stage to turn on or off the first node and turn on the second node, ; The second m-2 clock pulse is any one of the first through sixth clock pulses and is a clock pulse having a phase higher than the second m-1 clock pulse.

The transition point of the (2n + 3) -th carry pulse from the inactive state to the active state is shifted from the transition point of the second n scan pulse from the active state to the non- And a transition point between the transition points.

And the transition point of the second (n + 3) -th carry pulse from the inactive state to the active state is the same as the transition point of the second nth scan pulse from the active state to the non-active state.

The shift register according to the present invention has the following effects.

First, in the present invention, all of the two scan pulses output from one stage can have the same polling time. Therefore, the shift register according to the present invention can maintain the same output timing between the scan pulses output from each stage, thereby improving the output characteristics of the shift register. Further, the image quality of a display device using such a shift register can be improved Can be improved.

Second, in the present invention, by setting the first discharge voltage to be smaller than the second discharge-dedicated voltage, leakage of the current from the set node by the first switching element in the first and second output periods can be prevented.

1 is a view showing a shift register according to an embodiment of the present invention;
Fig. 2 is a diagram showing waveforms of various signals supplied to the shift register of Fig. 1 and signals output from the shift register
3 is a view showing a coupling relationship between stages;
FIG. 4 is a view showing one stage provided in the shift register of FIG. 1; FIG.
5 is a view for explaining a turn-on period of a switching element TD dedicated to a terminal according to the present invention;
6 and 7 are views for explaining the effect of the present invention

FIG. 1 is a diagram illustrating a shift register according to an embodiment of the present invention. FIG. 2 is a diagram illustrating waveforms of various signals supplied to the shift register of FIG. 1 and signals output from the shift register.

As shown in FIG. 1, the liquid crystal display device according to the embodiment of the present invention is composed of a plurality of stages STn-2 to STn + 3 that are connected to each other. The stages sequentially output pulses from the stage to which the fast numbering has been applied. At this time, each stage outputs four output pulses. That is, the four output pulses output from one stage are divided into two carry pulses CPn-4 to CPn + 7 and two scan pulses SPn-4 to SPn + 7. At this time, the two carry pulses are output sequentially to each other, and similarly, two scan pulses are sequentially output. Here, one carry pulse and one scan pulse output from one stage are output at the same timing, and the other one carry pulse and the other scan pulse are output at the same timing. In other words, a second n-1 carry pulse, a second n-1 scan pulse, a second n-carry pulse, and a second n scan pulse are output from the n-th stage, And the 2 < n > n carry pulse and the 2 < n > scan pulse are output at the same timing. However, the 2 < n > -1 carry pulse is output before the 2 < n > n carry pulse, and the 2 < n > scan pulse is output before the 2 < n > scan pulse.

To this end, each stage sequentially outputs at least four output pulses, two at a time, via four output terminals, based on two clock pulses having a voltage of the set node, a voltage of the reset node, and different phase differences And an output unit. Particularly, this output unit causes the node control unit to discharge any one of the output terminals of the output unit before discharging the set node, thereby making each polling time of four output pulses output from the stage equal. Thus, the output characteristics of the four output pulses output from each stage become the same, and the output characteristics of the shift register and the image quality of the display supplied with such output pulses can be improved.

The four output terminals include a first carry output terminal COT1, a first scan output terminal SOT1, a second carry output terminal COT2, and a second scan output terminal SOT2.

The output unit provided in the n-th stage includes a first output unit for outputting the second n-1 carry pulse and the (2n-1) th scan pulse through the first carry output terminal COT1 and the first scan output terminal SOT1, And a second output unit for outputting the second n-mer pulse and the second scan pulse through the second carry output terminal COT2 and the second scan output terminal SOT2.

Here, the first output unit provided in the n-th stage outputs a second n-1 carry pulse and a second n-1 scan pulse based on the voltage of the set node, the voltage of the reset node, and the m-th clock pulse. On the other hand, the second output unit provided in the n-th stage outputs the second n-care pulse and the second n-scan pulse based on the voltage of the set node, the voltage of the reset node, and the (m + 1) -th clock pulse.

At this time, the node controller provided in the n-th stage discharges the second scan output terminal SOT2 in response to the second n + 3 carry pulse from the (n + 2) th stage before discharging the set node.

The output unit provided in the n-th stage includes a first m-1 clock pulse and a second m clock pulse which are output in the adjacent periods among the first through sixth clock pulses CLK1 through CLK6, (M is a natural number). The pulse widths in the active state of the first to sixth clock pulses are all the same. The pulse widths of the adjacent clock pulses overlap each other for a predetermined period. FIG. 2 shows an example in which the width of each clock pulse is 3 horizontal periods, and adjacent clock pulses are overlapped for 2 horizontal periods. The pulse width and overlap period of these clock pulses are not limited to this, and can be changed according to the configuration of the circuit.

1, the 6k + 1 stage outputs the first carry pulse and the first scan pulse using the first clock pulse CLK1 and outputs the first carry pulse and the first scan pulse using the second clock pulse CLK2, A third carry pulse and a third scan pulse are output using the third clock pulse CLK3 and a fourth clock pulse CLK4 is used to output the third carry pulse and the third scan pulse, And outputs a fourth carry pulse and a fourth scan pulse. The sixth k + 3 stage outputs a fifth carry pulse and a fifth scan pulse using the fifth clock pulse CLK5, and outputs a sixth clock pulse CLK6 And outputs a seventh carry pulse and a seventh scan pulse using the first clock pulse CLK1, and outputs the sixth carry pulse and the seventh scan pulse, The eighth carry pulse and the eighth scan pulse are output using the pulse (CLK2), and the (6k + 5) The ninth carry pulse and the ninth scan pulse are output using the clock pulse CLK3 and the tenth carry pulse and the tenth scan pulse are output using the fourth clock pulse CLK4, The stage outputs the eleventh carry pulse and the eleventh scan pulse using the fifth clock pulse CLK5 and the twelfth carry pulse and the twelfth scan pulse using the sixth clock pulse CLK6.

In addition, the 6k + 1 stage charges its set node in response to the sixth clock pulse CLK6, and the 6k + 2 stage charges its set node to 2 < RTI ID = 0.0 > The stage 6k + 3 stage charges its set node in response to the fourth clock pulse CLK4, and the 6k + 4 stage charges its set node in response to the sixth clock pulse CLK6, And the 6k + 5 stage charges its set node in response to the second clock pulse (CLK2), and the 6k + 6 stage charges its set node in response to the fourth clock pulse (CLK4) And the set node is secondarily charged.

FIG. 3 is a view showing a coupling relationship between stages. FIG.

The n-th stage charges its set node with the (2n-3) th scan pulse from the (n-1) th stage in response to the second n-3 carry pulse from the (n-1) th stage. This n-th stage also charges its set node with a second n-2 carry pulse from the (n-1) th stage in response to the second m-2 clock pulse. In addition, this n-th stage discharges its second scan output terminal SOT2 in response to the second n + 3 carry pulse from the (n + 2) th stage. At this time, the node controller discharges the second scan output terminal SOT2 by supplying a first discharge voltage to the second scan output terminal SOT2 in response to the second n + 3 carry pulse. Here, the voltage value of the first to sixth clock pulses CLK1 to CLK6 in the inactive state is set to a value equal to or smaller than the voltage of the first discharge voltage.

On the other hand, the unillustrated S1 is a start pulse supplied to the first stage.

FIG. 4 is a diagram showing a stage provided in the shift register of FIG. 1. FIG.

The first output unit OB1 provided in the nth stage includes a first carry pulse output unit for outputting a second n-1 carry pulse CP2n-1 and a second carry pulse output unit for outputting a second n-1 scan pulse SP2n- And a first scan pulse output unit. The second output unit OB2 provided in the n-th stage includes a second carry pulse output unit for outputting a second n-care pulse CP2n and a second scan pulse for outputting a second n-scan pulse SP2n And an output unit.

The first carry pulse output section generates a second n-1 carry pulse CP2n-1 based on the voltage of the set node Q, the voltage of the reset node QB and the second m-1 clock pulse, Output terminal COT1. The first carry pulse output unit generates the first discharge voltage VSS1 based on the voltage of the set node Q, the voltage of the reset node QB, and the first discharge voltage VSS1, And outputs it through the first carry output terminal COT1.

The first scan pulse output section generates the second n-1 scan pulse SP2n-1 based on the voltage of the set node Q, the voltage of the reset node QB and the second m-1 clock pulse, Output terminal SOT1. The first scan pulse output unit generates the second discharge voltage VSS2 based on the voltage of the set node Q, the voltage of the reset node QB, and the second discharge voltage VSS2, And outputs it through the first scan output terminal SOT1.

The second carry pulse output section generates a second n-type carry pulse CP2n based on the voltage of the set node Q, the voltage of the reset node QB and the second m clock pulse, and outputs it to the second carry output terminal COT2 Lt; / RTI > The second carry pulse output unit generates the first discharge voltage VSS1 based on the voltage of the set node Q, the voltage of the reset node QB, and the first discharge voltage VSS1, And outputs it through the second carry output terminal (COT2).

The second scan pulse output unit generates the second n scan pulse SP2n based on the voltage of the set node Q, the voltage of the reset node QB, and the second m clock pulse, and outputs it to the second scan output terminal SOT2 Lt; / RTI > The second scan pulse output unit generates the second discharge voltage VSS2 based on the voltage of the set node Q, the voltage of the reset node QB, and the second discharge voltage VSS2, And outputs it through the second scan output terminal SOT2.

Here, the first discharge voltage VSS1 is set to a value smaller than the second discharge voltage VSS2.

The first carry pulse output unit provided in the nth stage includes a first carry pull-up switching device Uc1 and a first carry pulldown switching device Dc1.

The first carry-up switching element Uc1 provided in the n-th stage is turned on or off according to the voltage of the set node Q, and the second m-1 clock pulse CLK2m-1 is turned on 1) -th clock transmission line and the first carry output terminal (COT1).

The first carry pull-down switching device Dc1 provided in the n-th stage is turned on or off according to the voltage of the reset node QB and is turned on when the first carry output terminal COT1 and the first And a first discharging power supply line for transmitting the exclusive voltage VSS1 are connected to each other.

The first scan pulse output unit provided in the n-th stage includes a first scan pull-up switching element Us1 and a first scan pull-down switching element Ds1.

The first scan pull-up switching device Us1 provided in the n-th stage is turned on or off according to the voltage of the set node Q. The first scan pull- (SOT1).

The first scan pulldown switching device Ds1 provided in the nth stage is turned on or off according to the voltage of the reset node QB and is turned on when the first scan output terminal SOT1 and the second scan output terminal And a second discharging power supply line for transmitting the exclusive voltage VSS2 are connected to each other.

The second carry pulse output unit provided in the nth stage includes a second carry pull-up switching unit Uc2 and a second carry pull-down switching unit Dc2.

The second carry pull-up switching element provided in the n-th stage is turned on or off according to the voltage of the set node (Q), and a second m clock transmission line for transmitting the second m clock pulse (CLK2m) And the second carry output terminal (COT2) are connected to each other.

The second carry pull-down switching device Dc2 provided in the n-th stage is turned on or off according to the voltage of the reset node QB. When the second carry output terminal COT2 is turned on, Connect the dedicated power lines to each other.

The second scan pulse output section provided in the n-th stage includes a second scan pull-up switching element Us2 and a second scan pull-down switching element Ds2.

The second scan pull-up switching element Us2 provided in the n-th stage is turned on or off according to the voltage of the set node Q. The second scan pull-up switching element Us2 provided in the n-th stage is turned on or off according to the voltage of the set node Q, ).

The second scan pulldown switching device Ds2 provided in the nth stage is turned on or off according to the voltage of the reset node QB and is turned on when the second scan output terminal SOT2 is turned on, Connect the dedicated power lines to each other.

The node controller included in the n-th stage includes the first to fourth switching elements Tr1 to Tr4, the terminal-dedicated switching element TD, and the node-dedicated switching element ND.

The first switching element Tr1 provided in the n-th stage is turned on or off according to the second n-3 carry pulse from the n-1th stage, and the first scan And connects the output terminal SOT1 and the set node Q to each other.

The second switching device Tr2 provided in the nth stage is turned on or off according to the second m-2 clock pulse from the second m-2 clock transmission line, and the second switching device Tr2 provided in the n- 2 Connect the carry output terminal (COT2) and the set node (Q) to each other.

The third switching device Tr3 provided in the n-th stage is turned on in accordance with the charging voltage VDD from the charging power supply line, and the charging power supply line and the reset node QB are connected to each other do.

The fourth switching device Tr4 provided in the n-th stage is turned on or off according to the voltage of the set node Q. When the turn-on reset node QB and the first discharge power source line are connected to each other Connect.

The terminal-dedicated switching element TD provided in the n-th stage is turned on or off according to the second n + 3 carry pulse from the (n + 2) th stage, Connect the first discharge power lines to each other.

The nodal switching element ND provided in the nth stage is turned on or off according to the second n + 4 carry pulse from the (n + 2) th stage and is turned on or off at the turn- Connect the dedicated power lines to each other.

Here, the (2m-2) -th clock pulse is any one of the first through sixth clock pulses and is a clock pulse having a phase earlier than the (2m-1) -th clock pulse.

The operation of the shift register according to the embodiment of the present invention will now be described.

Since the operation of all the stages provided in the shift register is the same, the operation of the second stage will be described with reference to FIGS.

The first carry pulse CP1 from the first stage ST1 is supplied to the gate electrode of the first switching element Tr1 provided in the second stage ST2 in the first set period, The first scan pulse from the first switching element Tr1 is supplied to the drain electrode of the first switching element Tr1. Then, the first scan pulse SP1 is supplied to the set node Q of the second stage ST2 through the turned-on first switching element Tr1 so that the set node Q is charged. Then, the first carry pull-up switching element Uc1, the first scan pull-up switching element Us1, the second carry pull-up switching element Uc2, and the second scan pull-up switching element Us1 connected to the charged set node Q through the gate electrode, Up switching element Us2 and the fourth switching element Tr4 are turned on.

The first discharge voltage VSS1 is supplied to the reset node QB through the fourth switching element Tr4 turned on and the reset node QB is discharged. On the other hand, to the reset node QB, the charging voltage VDD output from the third switching element Tr3 of the diode type which is always kept turned on by the charging voltage VDD is supplied, Since the area of the fourth switching device Tr4 is larger than that of the third switching device Tr3, the reset node QB is maintained in a discharged state (V_QB). Therefore, the first carry pull-down switching element Dc1, the first scan pull-down switching element Ds1, the second carry pull-down switching element Dc2, and the second carry pull- down switching element Dc2, which are connected to the discharged reset node QB through the gate electrode, The scan pulldown switching element Ds2 is turned off.

Subsequently, in the second set period, the second clock pulse (CLK2) is supplied to the gate electrode of the third switching device (Tr3), and the second carry pulse from the first stage (ST1) is supplied to the third switching device Tr3. Then, the second carry pulse CP2 is supplied to the set node Q of the second stage ST2 via the turned-on third switching element Tr3 so that the set node Q is charged once again.

Next, in the first output period, the third clock pulse CLK3 is applied to each drain electrode of the first carry-up switching element Uc1 and the first scan pull-up switching element Us1 provided in the first output portion OB1 Are supplied in common. As a result, the voltage of the set node Q in the floating state is amplified by the bootstrapping phenomenon (V_Q). The first carry pull-up switching element Uc1 connected to the set node Q outputs a third carry pulse, and the first scan pull-up switching element Us1 connected to the set node Q outputs a third scan pulse (SP3). At this time, the third carry pulse CP3 is outputted through the first carry output terminal COT1, and the third scan pulse SP3 is outputted through the first scan output terminal SOT1.

Then, in the second output period, the fourth clock pulse CLK4 is applied to the drain electrodes of the second carry-up switching element Uc2 and the second scan pull-up switching element Us2 provided in the second output portion OB2 . As a result, the voltage of the set node Q in the floating state is further amplified (V_Q) by the bootstrapping phenomenon again. The second carry pull-up switching element Uc2 connected to the set node Q outputs a fourth carry pulse and the second scan pull-up switching element Us2 connected to the set node Q outputs a fourth scan pulse (SP4). At this time, the fourth carry pulse CP4 is outputted through the second carry output terminal COT2, and the fourth scan pulse SP4 is outputted through the second scan output terminal SOT2.

At this time, as the set node Q in the second output period is maintained at a relatively higher voltage than the first output period by the second bootstrapping, the fourth scan pulse output in the second output period (I.e., time to completely fall from the high voltage to the low voltage / polling edge time) becomes relatively long as compared with the third scan pulse output in the first output period.

Accordingly, in the present invention, the fourth scan pulse SP4 is rapidly dropped to the low voltage as follows using the terminal-side dedicated switching device TD.

That is, in the subsequent terminal discharge period, the seventh carry pulse CP7 from the fourth stage ST4 is supplied to the gate electrode of the terminal-side exclusive switching element TD. This terminal-dedicated switching element TD is turned on and the first discharging voltage VSS1 is applied to the second scan output terminal ST2 of the second stage ST2 through the turn- And is supplied to the terminal SOT2. As a result, the second scan output terminal SOT2 is rapidly discharged. That is, the fourth scan pulse SP4 previously supplied to the second scan output terminal SOT2 rapidly falls from the active state to the inactive state (from the high voltage to the low voltage).

Therefore, in the present invention, both scan pulses output from one stage can have the same polling time. Therefore, the shift register according to the present invention can maintain the same output timing between the scan pulses output from each stage, thereby improving the output characteristics of the shift register. Further, the image quality of a display device using such a shift register can be improved Can be improved.

Next, in the reset period, the eighth carry pulse CP8 from the fourth stage ST4 is supplied to the gate electrode of the node discharging switching element ND, and this node discharging switching element ND is turned on do. Then, the second discharging voltage VSS2 is supplied to the set node Q through the turned-on node discharging switching element ND, and the set node Q is discharged. Thus, the first carry pull-up switching element Uc1, the first scan pull-up switching element Us1, the second carry pull-up switching element Uc2, and the second carry pull-up switching element Us1 connected to the discharged set node Q through the gate electrode, The scan pull-up switching element Us2 and the fourth switching element Tr4 are turned off.

At this time, as the fourth switching device Tr4 is turned off, the reset node QB of the second stage ST2 is turned off, and the charging voltage VDD supplied through the third switching device Tr3, ). Then, the first carry pull-down switching element Dc1, the first scan pull down switch element Ds1, the second carry pull-down switch element Dc2, and the second carry pull-down switch Dc2, which are connected to the charged reset node QB through the gate electrode, The scan pulldown switching element Ds2 is turned on. Then, the first discharging voltage VSS1 is applied to the first carry output terminal COT1 through the turned-on first carry pull-down switching device Dc1, and the first scan pull-down switching device Ds1 turned on The second discharging voltage VSS2 is applied to the first scan output terminal SOT1 and the first discharging voltage VSS1 is applied to the second carry output terminal SOT1 through the second carry pull- And the second discharging voltage VSS2 is applied to the second scan output terminal SOT2 through the second scan pulldown switching device Ds2 turned on.

Meanwhile, in the present invention, by setting the first discharging voltage VSS1 to be smaller than the second discharging voltage VSS2, the first discharging voltage VSS2 from the set node Q by the first switching element Tr1 during the first and second output periods, Leakage of current can be prevented.

5 is a diagram for explaining a turn-on period of a switching element TD for terminal-only switching according to the present invention.

5, when the transition point of the second n + 3 carry pulse supplied from the inactive state to the active state supplied to the gate electrode of the switching element TD for the terminal-side exclusive switching element TD is the active state of the second n-th scan pulse SP2n To the non-active state and the transition point of the second n + 4 carry pulse (SP2n + 4) from the inactive state to the active state.

In FIG. 5, during the last 1/3 horizontal period of the pulse width of each scan pulse, data is supplied to the pixels of the display device receiving the corresponding scan pulse (Data Writing Time).

On the other hand, the transition point of the (2n + 3) -th carry pulse from the inactive state to the active state may be the same as the transition point of the second n-th scan pulse SP2n from the active state to the non-active state.

6 and 7 are diagrams for explaining the effect of the present invention. As shown in FIG. 6, the polling time of the third scan pulse SP3 and the polling time of the fourth scan pulse SP4 are almost the same . The time until the third scan pulse SP3 completely falls from the high voltage to the low voltage and the time until the fourth scan pulse SP4 completely falls from the high voltage to the low voltage are almost the same .

7, as the output timing of the (2n + 3) -th carry pulse supplied to the gate electrode of the terminal-dedicated switching element TD becomes faster, the second n-th scan pulse SP2n and the SP2n-1), the difference in the polling edge time is reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

Tr #: Primary switching element TD: Primary terminal switching element
ND: switching element dedicated to node switching Q: set node
QB: Reset node VDD: Charging voltage
VSS #: No. # Voltage Dedicated Voltage CP #: No. # Carry Pulse
SP #: 1st scan pulse CLK #: 1st clock pulse
COT #: No. # Carry output terminal SOT #: No. # Scan output terminal
OB #: Generation output unit Uc #: Generation carry carryover switching element
Us #: 1st scan pull-up switching device Dc #: 1st carry pull-down switching device
Ds #: 1st scan pull-down switching device

Claims (10)

In a shift register including a plurality of stages,
In each stage,
A node controller for controlling a voltage of the set node and the reset node; And
And a pair of output units sequentially outputting four output pulses through the four output terminals, two at a time, based on two clock pulses having a voltage of the set node, a voltage of the reset node, ;
Wherein the node controller discharges any one of the output terminals of the pair of output sections before discharging the set node,
The four output pulses output from the pair of output units provided in the n-th stage (n is a natural number) include a second n-1 carry pulse, a second n-1 scan pulse, a second n-carry pulse and a second n scan pulse ;
The pair of output units provided in the n-th stage may include a second m-1 clock pulse and a second m clock pulse, which are output in the adjacent periods among the first through sixth clock pulses sequentially out- (m is a natural number);
The pulse widths in the active state of the first to sixth clock pulses are all the same;
The pulse widths of the adjacent clock pulses overlap each other for a predetermined period;
The second m-1 clock pulse having a phase prior to the second m clock pulse;
The four output terminals include a first carry output terminal, a first scan output terminal, a second carry output terminal, and a second scan output terminal;
A first output unit for outputting the second n-1 carry pulse and the (2n-1) th scan pulse through the first carry output terminal and the first scan output terminal; And a second output unit for outputting the second n-mer pulse and the second scan pulse through the second carry output terminal and the second scan output terminal;
A first output unit provided in the n-th stage outputs a second n-1 carry pulse and a second n-1 scan pulse based on the voltage of the set node, the voltage of the reset node, and the m-th clock pulse;
A second output unit provided in the nth stage outputs a second n-mer pulse and a second n scan pulse based on the voltage of the set node, the voltage of the reset node, and the (m + 1) -th clock pulse;
Wherein the node controller provided in the nth stage discharges the second scan output terminal in response to a second n + 3 carry pulse from the (n + 2) th stage before discharging the set node. delete The method according to claim 1,
Wherein the node control unit discharges the second scan output terminal by supplying a first discharge voltage to the second scan output terminal in response to the second n + 3 carry pulse. The method of claim 3,
Wherein a voltage value of the first to sixth clock pulses in an inactive state is equal to or less than a voltage of the first discharge voltage. 5. The method of claim 4,
Wherein the first output unit provided in the nth stage includes a first carry pulse output unit for outputting the second n-1 carry pulse and a first scan pulse output unit for outputting the second n-1 scan pulse; And,
Wherein the second output unit provided in the n-th stage includes a second carry pulse output unit for outputting the second n-care pulse and a second scan pulse for outputting the second n-scan pulse. 6. The method of claim 5,
The first carry pulse output unit generates a second n-1 carry pulse based on the voltage of the set node, the voltage of the reset node, and the (2m-1) -th clock pulse, and outputs the second n-1 carry pulse through the first carry output terminal, Generating the first discharge voltage based on the voltage of the set node, the voltage of the reset node, and the first discharge voltage, and outputting the first discharge voltage through the first carry output terminal;
The first scan pulse output unit generates a second n-1 scan pulse based on the voltage of the set node, the voltage of the reset node, and the (2m-1) -th clock pulse and outputs the generated scan pulse through a first scan output terminal, Generates the second discharge voltage based on the voltage of the set node, the voltage of the reset node, and the second discharge voltage, and outputs the second discharge voltage through the first scan output terminal;
The second carry pulse output unit generates a second n-carry pulse based on the voltage of the set node, the voltage of the reset node, and the second m clock pulse, outputs the second n-carry pulse through the second carry output terminal, Generates the first discharge voltage based on a voltage, a voltage at a reset node, and a first discharge voltage, and outputs the first discharge voltage through the second carry output terminal;
The second scan pulse output unit generates a second n scan pulse based on the voltage of the set node, the voltage of the reset node, and the second m clock pulse, outputs the second scan pulse through the second scan output terminal, And generates the second discharge voltage based on the voltage, the voltage of the reset node, and the second discharge voltage, and outputs the second discharge voltage through the second scan output terminal. The method according to claim 6,
Wherein the first carry pulse output unit provided in the n < th >
A second m-1 clock transmission line that is turned on or off according to the voltage of the set node and transmits the second m-1 clock pulse when turned on, and a second carry circuit that connects the first carry output terminal A pull-up switching element,
And a first carry pull-down unit connected between the first carry output terminal and the first discharge power supply line for transmitting the first discharge voltage when the first carry discharge terminal is turned on or turned on according to the voltage of the reset node, A switching element;
Wherein the first scan pulse output unit provided in the n < th >
A first scan pull-up switching element which is turned on or off according to a voltage of the set node and which connects the second m-1 clock transmission line and the first scan output terminal when turned on;
A first scan pull-down unit connected to the first scan output terminal and a second power supply line for transmitting the second discharge voltage at a turn-on time, the first scan pulldown unit turning on or off according to a voltage of the reset node, A switching element;
And a second carry pulse output unit provided in the n-th stage,
A second carry pull-up switching element for turning on or off according to the voltage of the set node and for connecting the second m clock transmission line for transmitting the second m clock pulse upon turning on and the second carry output terminal to each other, ,
And a second carry pulldown switching element that is turned on or off according to the voltage of the reset node and connects the second carry output terminal and the first discharge power supply line to each other when the turn-on is turned on;
And a second scan pulse output unit provided in the n-th stage,
A second scan pull-up switching element which turns on or off according to a voltage of the set node and connects the second m clock transmission line and the second scan output terminal to each other when the turn-
And a second scan pulldown switching element that is turned on or off according to a voltage of the reset node and connects the second scan output terminal and the second discharge power supply line to each other at the time of turn- Shift register. 8. The method of claim 7,
Wherein the node controller included in the n < th >
And a second switching circuit that turns on or off according to a second n-3 carry pulse from the n-1th stage and turns on the first scan output terminal and the set node of the n- device;
The second carry output terminal is turned on or off according to a second m-2 clock pulse from the (2m-2) -th clock transmission line, and when the second carry output terminal is turned on, 2 switching device;
A third switching element that is turned on according to a charging voltage from a charging power supply line and connects the charging power supply line and the reset node when turned on;
A fourth switching device that turns on or off according to the voltage of the set node and connects the reset node and the first power supply line when turned on;
A second switching element for turning on or off according to a second n + 3 carry pulse from the (n + 2) th stage and connecting the second scan output terminal and the first discharge power supply line to each other at turn-on; And
And a node-dedicated switching element that turns on or off according to a second n + 4 carry pulse from the (n + 2) th stage and connects the set node and the second discharge power supply line to each other at turn- ;
Wherein the second m-2 clock pulse is one of the first through sixth clock pulses and is a clock pulse having a phase higher than the second m-1 clock pulse. 9. The method of claim 8,
The transition point of the (2n + 3) -th carry pulse from the inactive state to the active state is shifted from the transition point of the second n scan pulse from the active state to the non- Is shifted to a transition point of the shift register. 9. The method of claim 8,
And the transition point of the second n + 3 carry pulse from the inactive state to the active state is the same as the transition point of the second n scan pulse from the active state to the non-active state.

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