KR20150047038A - Shift register - Google Patents

Abstract

The present invention relates to a shift register which can prevent multi-output, and comprises a plurality of stages sequentially outputting scan pulses. Each stage includes a node control unit controlling signal conditions of first to fourth nodes in accordance with a scan pulse from a front-end stage, and a scan pulse of a rear-end stage; an output unit sequentially outputting two scan pulses in accordance with the voltage of the first to fourth nodes, and supplying and outputting the same to stages located at a front end and a rear end thereof; and an output stabilization unit controlled by the scan pulse from the rear-end stage, and charging at least one node of the first to fourth nodes.

Description

SHIFT REGISTER {SHIFT REGISTER}

The present invention relates to a shift register, particularly to a shift register capable of preventing multiple outputs.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

A plurality of gate lines and a plurality of data lines are arranged in an intersecting manner in the liquid crystal panel, and the pixel region is located in an area where the gate lines and the data lines intersect with each other. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed on the liquid crystal panel.

Each of the pixel electrodes is connected to a data line via a source terminal and a drain terminal of a thin film transistor (TFT) as a switching element. The thin film transistor is turned on by an output pulse applied to the gate terminal via the gate line so that the data signal of the data line is charged to the pixel electrode.

On the other hand, the driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, And a power supply unit for supplying driving voltages of the branches.

The timing controller controls the driving timings of the gate driver and the data driver and supplies the pixel data signal to the data driver. The power supply unit boosts or depressurizes the input power source to generate driving voltages such as a common voltage, a gate high voltage signal, a gate low voltage signal, and the like required by the liquid crystal display device. The gate driver sequentially supplies the output pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever an output pulse is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting the light transmittance by the electric field applied between the pixel electrode and the common electrode in accordance with the pixel voltage signal for each liquid crystal cell.

Here, the gate driver has a shift register to sequentially output the output pulses as described above.

Conventional shift registers consist of n stages that are connected to each other in dependence. Here, each stage outputs one output pulse. These output pulses are sequentially supplied to the gate lines of the liquid crystal panel (not shown), thereby sequentially scanning the gate lines.

Each stage includes a node control section for controlling charge and discharge states of the set node and the reset node, a pull-up switching element for outputting a scan pulse in accordance with the signal state of the set node, And a pull-down switching element for outputting a dedicated voltage.

Here, the set node and the reset node are alternately charged and discharged. Specifically, when the set node is charged, the reset node maintains the discharged state. When the reset node is charged, Thereby maintaining the discharged state.

At this time, a scan pulse is outputted from the pull-up switching element when the set node is in the charged state, and a discharge voltage is outputted from the pull-down switching element when the reset node is in the charged state.

The scan pulse output from the pull-up switching device Trpu and the discharge voltage output from the pull-down switching device are supplied to the corresponding gate line.

Here, the gate terminal of the pull-up switching element is connected to the set node, the drain terminal is connected to the clock transmission line to which the clock pulse is applied, and the source terminal is connected to the gate line.

The clock pulse periodically has a high state and a low state and is supplied to the drain terminal of the pull-up switching element. At this time, the pull-up switching element outputs any one of the high-level clock pulses CLK inputted at every period at a specific time. The clock pulse CLK output at this specific time point is the output pulse Vout for driving the gate line.

This specific time point refers to a time point after the set node is charged. That is, the pull-up switching element outputs, as a scan pulse, a high-level clock pulse input at the specific time point (i.e., the time point when the set node is charged) among the clock pulses continuously inputted to the drain terminal of the pull- . Then, after the output of the scan pulse, the set node is kept in a discharged state until the start of the next frame period, so that the pull-up switching element outputs one scan pulse in one frame. However, since the clock pulse is output several times during one frame period, the clock pulse continues to be input to the drain terminal of the pull-up switching element even in the state that the pull-up switching element Trpu is turned off, .

In other words, the pull-up switching element is turned on only once during one frame period, and outputs a clock pulse input to its drain terminal in the turn-on period as a scan pulse. Thereafter, the pull-up switching element is turned off until the start of the next frame period, so that the pull-up switching element outputs a clock pulse regardless of whether a clock pulse is input to its drain terminal during the turn-off period I can not. As a clock pulse is periodically applied to the drain terminal of the pull-up switching element, a coupling phenomenon occurs between the set node connected to the gate terminal of the pull-up switching element and the drain terminal of the pull-up switching element. Due to such a coupling phenomenon, the set node is continuously charged with a predetermined voltage corresponding to the clock pulse.

Then, the set node can be maintained in a charged state at any moment. That is, the set node can be kept in a charged state at an undesired timing. In this case, the set node can be maintained in a charged state more than once during one frame period, whereby the pull-up switching element can be turned on more than once during one frame period. As a result, a multi-output phenomenon in which one pull-up switching element outputs two or more scan pulses during one frame period may occur due to the coupling phenomenon described above.

As described above, when one pull-up switching element outputs two or more scan pulses during one frame period, one gate line is driven twice or more during one frame period to degrade the quality of the image displayed on the liquid crystal panel .

  SUMMARY OF THE INVENTION The present invention is directed to a shift register capable of preventing a multi-output phenomenon by stably maintaining a charge state of a reset node using stabilization switching elements.

According to an aspect of the present invention, there is provided a shift register including a plurality of stages sequentially outputting scan pulses sequentially; Each stage includes a node controller for controlling signal states of the first to fourth nodes according to a scan pulse from the front stage and a scan pulse from the rear stage; An output unit sequentially outputting two scan pulses in accordance with the voltages of the first to fourth nodes and supplying the scan pulses to a stage located at a front end and a rear end of the stage; And an output stabilization unit controlled in accordance with a scan pulse from a rear stage and charging at least one of the first through fourth nodes.

The first through fourth nodes are a first set node, a second set node, a first reset node, and a second reset node; The node controller included in the k-th stage, which is one of the stages, is controlled by the scan pulse output from the first scan pulse or the second scan pulse from the (k-1) th stage, A first set switching element connected between a charging power supply line and a first set node; A first reset switching element connected between the first set node and a discharge power supply line that is controlled by a scan pulse output from the second one of the two scan pulses from the (k + 1) th stage and transmits a discharge voltage; A second set switching element controlled by a scan pulse output from a second start pulse or a second one of two scan pulses from a (k-1) th stage, and connected between the charging power supply line and a second set node; A second reset switching element controlled by a scan pulse output from a second one of two scan pulses from the (k + 1) th stage and connected between the second set node and the discharge power supply line; A first switching element controlled in accordance with the signal state of the first reset node and connected between the first set node and the discharge power supply line; A second switching element controlled in accordance with a signal state of a second reset node and connected between the first set node and the discharge power supply line; A third switching device controlled according to a signal state of the first set node, the third switching device being connected between the first reset node and the discharge power supply line; A fourth switching device controlled according to a first AC voltage from a first AC power supply line and connected between the first AC power supply line and a first common node; A fifth switching device controlled according to a signal state of the first common node, the fifth switching device being connected between the first AC power supply line and the first reset node; A sixth switching device controlled according to a signal state of the first set node and connected between the first common node and the discharge power supply line; A seventh switching element controlled in accordance with the signal state of the second set node, and connected between the first common node and the discharge power supply line. An eighth switching element connected between the first reset node and the discharge power source line, the first switch being controlled by a first scan pulse output from the first start pulse or the second scan pulse from the (k-1) th stage; A ninth switching element controlled in accordance with a signal state of the first reset node and connected between the second set node and the discharge power supply line; A tenth switching element controlled in accordance with the signal state of the second reset node and connected between the second set node and the discharge power supply line; An eleventh switching element controlled in accordance with a signal state of the second set node and connected between the second reset node and the discharge power supply line; A twelfth switching element controlled according to a second AC voltage from a second AC power supply line and connected between the second AC power supply line and a second common node; A thirteenth switching element controlled according to a signal state of the second common node, and connected between the second AC power supply line and the second reset node; A fourteenth switching element controlled in accordance with a signal state of the second set node and connected between the second common node and the discharge power supply line; And a fifteenth switching device controlled according to a signal state of the first set node and connected between the second common node and the discharge power supply line.

A first pull-up switching element connected between any one of the clock transmission lines transmitting clock pulses and a first output terminal, the output being controlled according to a signal state of the first set node; A second pull-up switching element controlled in accordance with a signal state of the second set node, the second pull-up switching element being connected between a second output terminal and one of clock transmission lines transmitting clock pulses; A first pull-down switching element controlled in accordance with a signal state of the first reset node, the first pull-down switching element being connected between a first output terminal and a discharge power supply line; A second pull-down switching element controlled in accordance with a signal state of a second reset node and connected between a first output terminal and a discharge power supply line; A third pull-down switching element controlled in accordance with the signal state of the first reset node and connected between the second output terminal and the discharge power supply line; And a fourth pulldown switching element controlled in accordance with the signal state of the second reset node and connected between the second output terminal and the discharge power supply line.

The output stabilizing unit provided in the k-th stage is controlled by a scan pulse output from two of the two scan pulses from the (k + 1) -th stage, and the output stabilizing unit provided between the first AC power supply line and the first reset node A first stabilization switching element; And a second stabilization switching element controlled by a scan pulse output later than two scan pulses from the (k + 1) th stage and connected between the second AC power supply line and the second reset node .

The shift register according to the present invention has the following effects.

In the present invention, the stabilization switching elements are used to alternately charge the reset nodes on a frame-by-frame basis. Therefore, the disable state of the stage can be stably maintained, and thus, the multi-output can be prevented.

1 is a view showing a shift register according to a first embodiment of the present invention;
Fig. 2 is a timing chart of various signals supplied to the shift register of Fig.
Fig. 3 is a diagram showing the configuration of any stage provided in Fig. 1
FIG. 4 is a graph for comparing the node voltage of one of the stages provided in the shift register of the present invention with the node voltage of one of the stages of the conventional shift register

FIG. 1 is a diagram showing a shift register according to a first embodiment of the present invention, and FIG. 2 is a timing diagram of various signals supplied to the shift register of FIG.

The shift register according to the first embodiment of the present invention includes n stages ST1 to STn as shown in Fig. Here, each stage ST1 to STn outputs scan pulses twice during one frame period.

Each of the stages ST1 to STn drives the gate line connected thereto by using the scan pulse and controls the operation of the stage located at the rear stage from itself and the stage located at the preceding stage from the stage itself.

The scan pulses Vout1 to Vout2n output from the stages ST1 to STn are sequentially supplied to gate lines of a liquid crystal panel (not shown), and the gate lines are sequentially scanned.

Such a shift register can be incorporated in the liquid crystal panel. That is, the liquid crystal panel has a display portion for displaying an image and a non-display portion surrounding the display portion, and the shift register is embedded in a non-display portion by a gate-in-panel method.

As shown in FIG. 2, the stages ST1 to STn included in the shift register constructed as described above are provided with different phase differences among the first to fourth clock pulses CLK1 to CLK4 having a sequential phase difference with each other and circulating The charging voltage, and the first and second AC voltages Vac1 and Vac2.

The charging voltage and discharging voltage are both DC voltage, charging voltage is positive, and discharging voltage is negative. On the other hand, the discharge voltage can be the ground voltage.

The first and second AC voltages Vac1 and Vac2 are signals for controlling the charging and discharging of the reset nodes among the nodes of the stages ST1 to STn and the first AC voltage Vac1 and the second AC voltage Vac1, The voltage Vac2 is all an alternating voltage. The first AC voltage (Vac1) has a phase inverted by 180 degrees with respect to the second AC voltage (Vac2). The voltage value in the high state of the first and second AC voltages Vac1 and Vac2 may be the same as the voltage value of the charging voltage and the voltage in the low state of the first and second AC voltages Vac1 and Vac2 The value may be equal to the voltage value of the discharge voltage. The first and second AC voltages (Vac1, Vac2) are inverted in their p-frame periods. Here, p is a natural number.

The first through fourth clock pulses CLK1 through CLK4 are the signals used to generate the scan pulses of the stages ST1 through STn so that each of the stages ST1 through STn outputs the first through fourth clock pulses CLK1 through CLK4, CLK4) and outputs two scan pulses. For example, the odd-numbered stages of the stages ST1 to STn output two scan pulses using the first and second clock pulses CLK1 and CLK2, and the odd-numbered stages of the stages ST1 to STn, Outputs two scan pulses using the third and fourth clock pulses CLK3 and CLK4.

Although four clock pulses having different phase differences are used in the present invention, the number of clock pulses may be two or more.

The first to fourth clock pulses CLK1 to CLK4 are four-phase clock pulses having a phase difference from each other. That is, the second clock pulse CLK2 is delayed in phase with respect to the first clock pulse CLK1, the third clock pulse CLK3 is delayed in phase with respect to the second clock pulse CLK2, The first clock pulse CLK4 is delayed in phase with respect to the third clock pulse CLK3 and the first clock pulse CLK1 is delayed in phase with respect to the fourth clock pulse CLK4.

The first to fourth clock pulses CLK1 to CLK4 are sequentially output, and are output while being circulated. Is sequentially output from the first clock pulse CLK1 to the fourth clock pulse CLK4 and then sequentially output from the first clock pulse CLK1 to the fourth clock pulse CLK4. Accordingly, the first clock pulse CLK1 is output in a period between the fourth clock pulse CLK4 and the second clock pulse CLK2.

Each of the clock pulses CLK1 to CLK4 is output several times during one frame period, but the first and second start pulses Vst1 and Vst2 are output only once during one frame period. In other words, although each of the clock pulses CLK1 to CLK4 periodically exhibits several active states (high state) during one frame period, the first and second start pulses Vst1 and Vst2 are applied only once Indicates an active state. The first and second start pulses Vst1 and Vst2 are output first from any one of the clock pulses CLK1 to CLK4 in one frame period.

In the present invention, as shown in FIG. 2, the first to fourth clock pulses CLK1 to CLK4 overlapping the pulse width section may be used.

That is, as shown in FIG. 2, the first half period of the pulse width section of the i-th clock pulse (i is a natural number of 2 or more) overlaps with the second half period of the pulse width section of the (i- And the second half of the pulse width of the i th clock pulse overlaps with the first half of the pulse width of the (i + 1) th clock pulse.

For example, if the first to fourth clock pulses CLK1 to CLK4 each have a pulse width interval corresponding to two horizontal periods (2H), the adjacent clock pulses are divided into a period corresponding to one horizontal period Overlap each other. The length of the overlapping pulse width is not limited to the length corresponding to 1/2 section and can be adjusted to any extent.

When the overlapped clock pulses CLK1 to CLK4 are used, the pulse widths of the scan pulses Vout1 to Vout2n output from the stages ST1 to STn overlap each other as shown in Fig.

In order for each stage ST1 to STn to output a scan pulse, the enable operation of each stage ST1 to STn must be preceded. The fact that the stage is enabled means that the stage is set in a state in which it can output, that is, a state in which a clock pulse supplied thereto can be outputted as a scan pulse. Each of the stages ST1 to STn may be enabled by receiving a scan pulse output from the first scan pulse from the stage located at the previous stage. For example, the j-th stage is enabled in response to two scan pulses from the j-1 stage.

However, the first stage ST1 located at the uppermost position is enabled in response to the first and second start pulses Vst1 and Vst2 from the timing controller.

On the other hand, each of the stages ST1 to STn is disabled after the scan pulse is output. The fact that the stage is disabled means that the stage is in a state in which output is impossible, i.e., a state in which the clock pulse supplied thereto can not be output as a scan pulse It is reset. Each of the stages ST1 to STn is supplied with a scan pulse that is output later than two scan pulses from the stage located at the rear end thereof, and is disabled. For example, the j < th > stage is disabled in response to a scan pulse output later of two scan pulses from the (j + 1) th stage.

However, the lowest n-th stage STn is disabled in response to a dummy pulse from a separate dummy stage (not shown). Here, this dummy stage is set to receive two scan pulses from the above-mentioned n-th stage STn, and is supplied with the first and second start pulses Vst1 and Vst2 from the timing controller and is disabled .

The structure of each stage ST1 to STn in the shift register constructed as described above will be described in more detail as follows.

Fig. 3 is a diagram showing the configuration of an arbitrary stage (k-th stage) provided in Fig. 1, and the configuration of the k-th stage is exemplarily described because all stages have the same configuration.

The k-th stage includes a node control unit (NC), an output stabilization unit (OSC) and an output unit (OU), as shown in Fig.

The node control unit NC of the k-th stage controls the signal states of the first set node Q1, the second set node Q2, the first reset node QB1, and the second reset node QB2.

The node control unit NC of the k-th stage includes a first set switching element S1, a second set switching element S2, a first reset switching element R1, a second reset switching element R2, And first to sixteenth switching elements Tr1 to Tr16.

The first set switching element S1 provided in the k-th stage is controlled by the scan pulse Voutp-2 output first from the k-1 stage among the two scan pulses Voutp-2 and Voutp-1 , A charging power supply line (VdL) for transferring a charging voltage (Vdd) and the first set node (Q1). The first set switching element S1 is turned on or off by the scan pulse Voutp-2 output from the k-1 stage relatively earlier, and the turn-on charging voltage Vdd is set to And supplies it to one set node Q1. However, the first set switching element S1 provided in the first stage ST1 is supplied with the first start pulse Vst1 instead of the above-mentioned scan pulse Voutp-2.

The second set switching element S2 provided in the k-th stage is controlled by the scan pulse Voutp-1 output later from the k-1 stage among the two scan pulses Voutp-2 and Voutp-1 , And is connected between the charging power supply line (VdL) and the second set node (Q2). The second set switching element S2 is turned on or off by the scan pulse Voutp-1 output relatively later from the (k-1) th stage, and the turn-on charging voltage Vdd is set to To the two-set node Q2. However, the second set switching element S2 provided in the first stage ST1 is supplied with the second start pulse Vst2 instead of the above-mentioned scan pulse Voutp-1.

The first reset switching element R1 provided in the kth stage is turned on by the scan pulse Voutp + 3 output later among the two scan pulses Voutp + 2 and Voutp + 3 from the (k + 1) And is connected between the first set node Q1 and the discharge power supply line VsL for transmitting the discharge voltage Vss. The first reset switching element Rl is turned on or off by the scan pulse Voutp + 3 output from the k + 1 stage relatively later and is turned on or off at the first set node Q1, And supplies the discharging voltage Vss. However, the first reset switching element R1 provided in the dummy stage receives the first start pulse Vst1 or the second start pulse Vst2 instead of the scan pulse Voutp + 3 described above. However, the first reset switching element R1 provided in the n-th stage is supplied with a dummy pulse which is outputted relatively later from the dummy stage instead of the above-mentioned scan pulse (Voutp + 3) The reset switching element R1 receives the first start pulse Vst1 or the second start pulse Vst2 instead of the scan pulse Voutp + 3 described above.

The second reset switching element R2 provided in the kth stage is turned on by the scan pulse Voutp + 3 output later among the two scan pulses Voutp + 2 and Voutp + 3 from the (k + 1) And is connected between the second set node Q2 and the discharge power supply line VsL. This second reset switching element R2 is turned on or off by the scan pulse Voutp + 3 output relatively later from the (k + 1) th stage and turned on at the second set node Q2, And supplies the discharging voltage Vss. However, the second reset switching element R2 provided in the dummy stage receives the first start pulse Vst1 or the second start pulse Vst2 instead of the scan pulse Voutp + 3. However, the second reset switching device R2 provided in the n-th stage receives the dummy pulse output relatively later from the dummy stage instead of the scan pulse (Voutp + 3) described above, and the second reset switching element The reset switching element R2 receives the first start pulse Vst1 or the second start pulse Vst2 instead of the scan pulse Voutp + 3 described above.

The first switching device Tr1 provided in the k-th stage is controlled according to the signal state of the first reset node QB1 and is connected between the first set node Q1 and the discharge power supply line VsL. The first switching element Tr1 is turned on or off according to the signal state of the first reset node QB1 and supplies the discharging voltage Vss to the first set node Q1 when the first switching element Tr1 is turned on do.

The second switching element Tr2 provided in the k-th stage is controlled according to the signal state of the second reset node QB2 and is connected between the first set node Q1 and the discharge power supply line VsL. The second switching element Tr2 is turned on or off according to the signal state of the second reset node QB2 and supplies the discharging voltage Vss to the first set node Q1 on the turn- do.

The third switching device Tr3 provided in the k-th stage is controlled according to the signal state of the first set node Q1 and is connected between the first reset node QB1 and the discharge power supply line VsL. The third switching device Tr3 is turned on or off according to the signal state of the first set node Q1 and supplies the discharging voltage Vss to the first reset node QB1 when the third switching device Tr3 is turned on do.

The fourth switching device Tr4 provided in the k-th stage is controlled according to the first AC voltage Vac1 from the first AC power supply line acL1, and the first AC power supply line acL1 and the first common node CN1. The fourth switching device Tr4 is turned on or off according to the first AC voltage Vac1 and supplies the first AC voltage Vac1 to the first common node CN1 when the fourth switching device Tr4 is turned on.

The fifth switching element Tr5 provided in the k-th stage is controlled according to the signal state of the first common node CN1 and is connected between the first AC power supply line acL1 and the first reset node QB1. The fifth switching element Tr5 is turned on or off according to the signal state of the first common node CN1 and the first AC voltage Vac1 is applied to the first reset node QB1 at the turn- Supply.

The sixth switching element Tr6 provided in the k-th stage is controlled according to the signal state of the first set node Q1 and is connected between the first common node CN1 and the discharge power supply line VsL. The sixth switching element Tr6 is turned on or off according to the signal state of the first set node Q1 and supplies the discharging voltage Vss to the first common node CN1 on the turn- .

The seventh switching device Tr7 provided in the kth stage is controlled according to the signal state of the second set node Q2 and is connected between the first common node CN1 and the discharge power supply line VsL. The seventh switching device Tr7 is turned on or off according to the signal state of the second set node Q2 and supplies the discharging voltage Vss to the first common node CN1 on the turn- .

The eighth switching device Tr8 provided in the k-th stage is controlled by the scan pulse Voutp-2 output first from the k-1 stage among the two scan pulses Voutp-2 and Voutp-1, And is connected between the first reset node QB1 and the discharge power supply line VsL. The eighth switching element Tr8 is turned on or off by the scan pulse Voutp-2 output earlier from the k-1th stage and the turn-on discharge voltage Vss is applied to the first And supplies it to the reset node QB1. However, the eighth switching element Tr8 provided in the first stage ST1 receives the first start pulse Vst1 instead of the scan pulse Voutp-2 described above.

The ninth switching element Tr9 provided in the kth stage is controlled according to the signal state of the first reset node QB1 and is connected between the second set node Q2 and the discharge power supply line VsL. The ninth switching element Tr1 is turned on or off according to the signal state of the first reset node QB1 and supplies the discharging voltage Vss to the second set node Q2 on the turn- do.

The tenth switching element Tr10 provided in the k-th stage is controlled according to the signal state of the second reset node QB2 and is connected between the second set node Q2 and the discharge power supply line VsL. The tenth switching element Tr10 is turned on or off according to the signal state of the second reset node QB2 and supplies the discharging voltage Vss to the second set node Q2 on the turn- do.

The eleventh switching device Tr11 provided in the k-th stage is controlled according to the signal state of the second set node Q2 and is connected between the second reset node QB2 and the discharge power supply line VsL. The eleventh switching element Tr11 is turned on or off according to the signal state of the second set node Q2 and supplies the discharging voltage Vss to the second reset node QB2 on the turn- do.

The twelfth switching element Tr12 provided in the k-th stage is controlled according to the second AC voltage Vac2 from the second AC power supply line acL2, and the second AC power supply line acL2 and the second common node CN2. The twelfth switching element Tr12 is turned on or off according to the second AC voltage Vac2 and supplies the second AC voltage Vac2 to the second common node CN2 on the turn-on.

The thirteenth switching device Tr13 provided in the k-th stage is controlled according to the signal state of the second common node CN2, and is connected between the second AC power supply line acL2 and the second reset node QB2. The thirteenth switching element Tr13 is turned on or off according to the signal state of the second common node CN2 and the second AC voltage Vac2 is applied to the second reset node QB2 on the turn- Supply.

The fourteenth switching device Tr14 provided in the k-th stage is controlled according to the signal state of the second set node Q2, and is connected between the second common node CN2 and the discharge power supply line VsL. The fourteenth switching device Tr14 is turned on or off according to the signal state of the second set node Q2 and supplies the discharging voltage Vss to the second common node CN1 on the turn- .

The fifteenth switching device Tr15 provided in the k-th stage is controlled according to the signal state of the first set node Q1 and is connected between the second common node CN2 and the discharge power supply line VsL. The fifteenth switching device Tr15 is turned on or off according to the signal state of the first set node Q1 and supplies the discharging voltage Vss to the second common node CN2 on the turn- .

The sixteenth switching device Tr16 provided in the k-th stage is controlled by the first scan pulse Voutp-2 among the two scan pulses Voutp-2 and Voutp-1 from the (k-1) And is connected between the second reset node QB2 and the discharge power supply line VsL. The 16th switching element Tr16 is turned on or off by the scan pulse Voutp-2 output earlier from the k-1th stage, and the turn-on discharge voltage Vss is set to the second And supplies it to the reset node QB2. However, the 16th switching element Tr16 provided in the first stage ST1 receives the first start pulse Vst1 instead of the scan pulse Voutp-2 described above.

The output stabilization unit OSU of the k-th stage includes a first stabilization switching element OS1 and a second stabilization switching element OS2. Here, the output stabilizing unit OSU may be included in the node control unit NC.

The first stabilization switching element OS1 provided in the kth stage is controlled by the scan pulse Voutp + 3 output later among the two scan pulses Voutp + 2 and Voutp + 3 from the (k + 1) And is connected between the first AC power supply line acL1 and the first reset node QB1. The first stabilization switching element OS1 is turned on or off by the scan pulse Voutp + 3 output from the k + 1 stage relatively later, and the first reset node OS1 turns on or off at the first reset node QB1 To supply the first AC voltage (Vac1). However, the first stabilization switching device OS1 provided in the n-th stage receives the dummy pulse outputted relatively later from the dummy stage instead of the scan pulse Voutp + 3 described above, and the first stabilization switching element OS1 provided in the dummy stage The switching element OS1 receives the first start pulse Vst1 or the second start pulse Vst2 instead of the scan pulse Voutp + 3 described above.

The second stabilization switching device OS2 provided in the kth stage is controlled by the scan pulse Voutp + 3 output later among the two scan pulses Voutp + 2 and Voutp + 3 from the (k + 1) And is connected between the second AC power supply line acL2 and the second reset node QB2. The second stabilization switching element OS2 is turned on or off by the scan pulse Voutp + 3 output from the k + 1 stage relatively later, and the second reset node QB2 To supply the second AC voltage (Vac2). However, the second stabilization switching device OS2 provided in the n-th stage receives the dummy pulse output relatively later from the dummy stage instead of the scan pulse Voutp + 3 described above, and the second stabilization switching element OS2 provided in the dummy stage The switching element OS2 receives the first start pulse Vst1 or the second start pulse Vst2 instead of the scan pulse Voutp + 3 described above.

The output (OU) of the k-th stage includes first and second pull-up switching elements Trpu1 and Trpu2 and first to fourth pulldown switching elements Trpd1 to Trpd4.

The first pull-up switching device Trpu1 provided in the k-th stage is controlled according to the signal state of the first set node Q1 and is connected to the clock transmission line CLK1 for transmitting any one of the clock pulses CLK1 to CLK4 (CTLi) and the first output terminal 111a. The first pull-up switching device Trpu1 is turned on or off according to the signal state of the first set node Q1 and outputs one of the clock pulses CLKi to the first output terminal 111a at the time of turn- .

The second pull-up switching device Trpu2 provided in the k-th stage is controlled according to the signal state of the second set node Q2 and transmits another one of the clock pulses CLK1 to CLK4 (CLKi + 1) And is connected between another clock transmission line CTLi + 1 and the second output terminal 111b. The second pull-up switching device Trpu2 is turned on or off according to the signal state of the second set node Q2 and outputs any one of the clock pulses CLKi + 1 to the second output terminal 111b.

The first pull-down switching device Trpd1 provided in the k-th stage is controlled according to the signal state of the first reset node QB1 and is connected between the first output terminal 111a and the discharge power supply line VsL. The first pull-down switching device Trpd1 is turned on or off according to the signal state of the first reset node QB1 and is turned off when the discharge voltage Vss is applied to the first output terminal 111a Supply.

The second pull-down switching device Trpd2 provided in the k-th stage is controlled according to the signal state of the second reset node QB2 and is connected between the first output terminal 111a and the discharge power supply line VsL. The second pull-down switching device Trpd2 is turned on or off according to the signal state of the second reset node QB2 and is turned off when the discharge voltage Vss is applied to the first output terminal 111a Supply.

The third pull-down switching device Trpd3 provided in the k-th stage is controlled according to the signal state of the first reset node QB1 and is connected between the second output terminal 111b and the discharge power supply line VsL. The third pull-down switching element Trpd3 is turned on or off according to the signal state of the first reset node QB1 and is turned off when the discharge voltage Vss is applied to the second output terminal 111b Supply.

The fourth pull-down switching device Trpd4 provided in the k-th stage is controlled according to the signal state of the second reset node QB2 and is connected between the second output terminal 111b and the discharge power supply line VsL. The fourth pull-down switching element Trpd4 is turned on or off according to the signal state of the second reset node QB2 and is turned off to turn on the discharge voltage Vss to the second output terminal 111b Supply.

The operation of the shift register constructed as described above will now be described with reference to FIGS. 2 and 3. FIG. Here, since the operation of all the stages is the same, the operation of the k-th stage will be exemplarily described. At this time, the case where the k-th stage corresponds to the third stage in Fig. 1 will be described as an example.

At this time, a first initial period Ts1, a second initial period Ts2, a first period T1, a second period T2, a third period T3, and a fourth period T4 in the first frame period The operation of the k-th stage will be sequentially described as follows.

The first initial period ( Ts1 )

In the first initial period Ts1, a p-2 scan pulse Voutp-2 (i.e., Vout3) from the k-1 stage (i.e., ST2) is applied to the first set The gate terminal of the switching element S1, the gate terminal of the eighth switching element Tr8, and the gate terminal of the sixteenth switching element Tr16.

Then, the first set switching element S1, the eighth switching element Tr8 and the sixteenth switching element Tr16 are turned on and the first set switching element S1 is turned on, And a threshold voltage Vdd is applied to the first set node Q1. Accordingly, the first pull-up switching device Trpu1, the third switching device Tr3, the sixth switching device Tr3, and the sixth pull-up switching device Tr2, which are charged with the first set node Q1 and connected to the charged first set node Q1 through the gate terminal, The switching element Tr6 and the fifteenth switching element Tr15 are turned on.

Here, the discharge voltage VSS is supplied to the first reset node QB1 through the turned-on third switching element Tr3 and the eighth switching element Tr8 so that the first reset node QB1 Is discharged. Thus, the first pull-down switching device Trpd1, the first switching device Tr1, the third pulldown switching device Trpd3, and the ninth switching device Tr9 (Tr9), which are connected to the first reset node QB1 via the gate terminal, Is turned off.

Further, the discharge voltage VSS is supplied to the second reset node QB2 via the turn-on sixteenth switching element Tr3, and the second reset node QB2 is discharged. Thus, the fourth pull-down switching device Trpd4, the tenth switching device Tr10, the second pulldown switching device Trpd2, and the second switching device Tr2 (Tr2), which are connected to the second reset node QB2 through the gate terminal, Is turned off.

On the other hand, since the first AC voltage (Vac1) is maintained in the high state during the first frame period, the fourth switching device Tr4 receiving the first AC voltage (Vac1) in the high state is turned on during the first frame period, And maintains the ON state. The first AC voltage Vac1 is supplied to the first common node CN1 of the k-th stage STk via the turned-on fourth switching element Tr4. At this time, the discharge voltage VSS output through the sixth switching element Tr6 turned on is also supplied to the first common node CN1. That is, the first common node CN1 is supplied with the first AC voltage Vac1 in the high state and the discharge voltage VSS in the low state together.

Since the size of the sixth switching element Tr6 for supplying the discharge voltage VSS is set to be larger than the size of the fourth switching element Tr4 for supplying the first AC voltage Vac1, (CN1) is maintained at the discharge voltage (VSS). On the other hand, as will be described later, the discharging voltage VSS output by the seventh switching device Tr7 turned on is further supplied to the first common node CN1. Therefore, the first common node CN1 is discharged, and the fifth switching element Tr5 connected to the discharged first common node CN1 via the gate terminal is turned off.

As described above, during the first initial period Ts1, the first set node Q1 of the k-th stage is charged, the first and second reset nodes QB1 and QB2 are discharged, and the k- do.

The second initial period ( Ts2 )

In the second initial period Ts2, the (p-1) th scan pulse Voutp-1 (i.e., Vout4) from the (k-1) th stage (i.e., ST2) is applied to the second set switching element S2 Is supplied to the gate terminal of the transistor Q3.

Then, the second set switching element S2 is turned on and the high-level charging voltage Vdd is applied to the second set node Q2 through the turned-on second set switching element S2 . Accordingly, the second pull-up switching device Trpu2, the eleventh switching device Tr11, the fourteenth switching device Tr11, the fourteenth switching device Tr11, and the fourteenth switching device Tr11, which are connected to the second set node Q2 through the gate terminal, The switching element Tr14 and the seventeenth switching element Tr17 are turned on.

On the other hand, since the second AC voltage (Vac2) is held in the low state during the first frame period, the twelfth switching element (Tr12) receiving the second AC voltage (Vac2) in the low state is turned on during the first frame period, Off state.

Since the fifteenth switching element Tr15 is turned on in the first initial period Ts1 and the first set node Q1 is kept in the constantly charged state in the first initial period Ts1 described above, 15 switching element Tr15 is in the turn-on state. The discharge voltage Vss is supplied to the second common node CN2 through the turned-on fifteenth switching element Tr15, thereby discharging the second common node CN2. Therefore, the thirteenth switching element Tr13 connected to the discharged second common node CN2 through the gate terminal is turned off.

Thus, the second set node Q2 of the k-th stage is charged during the second initial period Ts2, and the first and second reset nodes QB1 and QB2 are maintained in the previous discharge state. That is, the k-th stage is enabled secondarily in this second initial period Trs2.

The first period ( T1 )

In this first period T1, as shown in Fig. 2, the i-th clock pulse CLKi (i.e., CLK1) shows a high state.

As the first set node Q1 of the k-th stage is kept in the charged state by the charging voltage VDD applied during the first initial period Ts1 described above, the first pull-up switching element Trpu1) remains in the turn-on state. At this time, as the i-th clock pulse CLKi (i.e., CLK1) is applied to the drain terminal of the turned-on first pull-up switching device Trpu1, the charging voltage charged in the first set node Q1 in the floating state VDD) is amplified by bootstrapping.

Therefore, the i-th clock pulse CLKi applied to the drain terminal of the first pull-up switching device Trpu1 of the k-th stage is stably outputted through the source terminal (first output terminal 111a). Here, the ith clock pulse CLKi output through the first pull-up switching element Trpu1 is a p scan pulse Voutp (i.e., Vout5). The p scan pulse Voutp is supplied to the p-th gate line, the (k + 1) th stage (i.e., ST4). Thus, the p-th gate line is driven in this first period (T1), and the (k + 1) -th stage is first enabled.

The primary enable operation of the (k + 1) th stage in this first period T1 is the same as the enable operation of the k < th > stage in the above described first initial period Ts1.

The second period ( T2 )

In this second period T2, the (i + 1) -th clock pulse CLKi + 1 (i.e., CLK2) is in a high state as shown in Fig.

As the second set node Q2 of the k-th stage is kept in the charged state by the charging voltage VDD applied during the second initial period Ts2 described above, the second pull-up switching element Trpu2) remains in the turn-on state. At this time, as the (i + 1) -th clock pulse CLKi + 1 is applied to the drain terminal of the second pull-up switching device Trpu2 turned on, the charging voltage VDD) is amplified by bootstrapping.

Therefore, the (i + 1) -th clock pulse CLKi + 1 applied to the drain terminal of the second pull-up switching device Trpu2 of the k-th stage is stably outputted through the source terminal (second output terminal 111b). Here, the (i + 1) -th clock pulse CLKi + 1 output through the second pull-up switching element Trpu2 is the (p + 1) -th scan pulse Voutp + 1 (i.e., Vout6). The (p + 1) th scan pulse (Voutp + 1) is supplied to the (p + 1) th gate line, the (k + 1) th stage and the (k-1) th stage. Thus, in this second period T2, the (p + 1) th gate line is driven, the (k + 1) th stage is enabled secondarily, and the (k-1) th stage is disabled.

The third period ( T3 )

The operation of the k < th > stage in the third period T3 is substantially the same as the operation in the second period T2 described above. Therefore, the description thereof refers to the above-described operation.

The fourth period ( T4 )

In this fourth period T4, a p + 3th scan pulse Voutp + 3 (i.e., Vout8) from the (k + 1) th stage (i.e., ST4) is supplied to the kth stage, The disable operation of the k-th stage will be described in detail as follows.

That is, the (p + 3) -th scan pulse Voutp + 3 is applied to the gate terminal of the first stabilization switching element OS1 provided in the k-th stage, the gate terminal of the second stabilization switching element OS2, Is supplied to the gate terminal of the first reset switch R1 and the gate terminal of the second reset switching element R2. Then, the first stabilization switching element OS1, the second stabilization switching element OS2, the first reset switching element Rl and the second reset switching element R 2 are turned on.

The discharge voltage Vss is supplied to the first set node Q1 of the k-th stage through the turned-on first reset switching element R1. Therefore, the first set node Q1 is discharged, and the first pull-up switching element Trpu1, the third switching element Tr3, the sixth switching element Tr2, and the third switching element Tr3 are connected to the discharged first set node Q1 through the gate terminal thereof. The element Tr6 and the fifteenth switching element Tr15 are turned off.

Also, the discharge voltage Vss is supplied to the second set node Q2 of the k-th stage through the second reset switching element R2 turned on. Therefore, the second set node Q2 is discharged, and the second pull-up switching element Trpu2, the eleventh switching element Tr11, the fourteenth switching element Tr11, and the seventh switching element Tr11, which are connected through the gate terminal to the discharged second set node Q2, The element Tr14 and the seventh switching element Tr7 are turned off.

As the sixth and seventh switching elements Tr6 and Tr7 of the k-th stage ST1 are turned off, the first common node CN1 is supplied with the first AC voltage V1 through the fourth switching element Tr4, (Vac1) are supplied. Thereby, the first common node CN1 is charged, and the fifth switching element Tr5 connected to the charged first common node CN1 through the gate terminal is turned on.

The first AC voltage Vac1 is supplied to the first reset node QB1 of the k-th stage through the turn-on fifth switching element Tr5. Then, the first pull-down switching device Trpd1, the third pull-down switching device Trpd3, and the third pull-down switching device Trpd3, which are charged with the first reset node QB1 and connected to the charged first reset node QB1 through the gate terminal, The first switching element Tr1 and the ninth switching element Tr9 are turned on.

The discharging state of the first set node Q1 is more stably maintained by supplying the discharging voltage VSS to the first set node Q1 through the first switching element Tr1 turned on. In addition, the discharge voltage VSS is supplied to the second set node Q2 through the turned-on ninth switching element Tr9, so that the discharge state of the second set node Q2 is stably maintained.

The first AC voltage Vac1 in the high state is supplied to the first reset node QB1 via the first stabilization switching element OS1 turned on so that the first reset node QB1 The charging state is maintained more stably. Therefore, the occurrence of the multi-output can be suppressed since the k-th stage is stably maintained in the disabled state.

On the other hand, the second AC voltage Vac2 in a low state is supplied to the second reset node QB2 through the turn-on second stabilization switching element OS2, whereby the second reset node QB1 Is discharged.

Thus, in the fourth period T4, the first and second set nodes Q1 and Q2 of the k-th stage are discharged, the first reset node QB1 is charged, and the second reset node QB2 Is discharged, so that the k < th > stage is disabled.

As described above, the first pull-down switching device Trpd1 and the third pull-down switching device Trpd3 of the k-th stage are turned on during the fourth period T4, And supplies the discharge voltage Vss through the terminal 111a to the p-th gate line and the (k + 1) th stage, and the third pulldown switching device Trpd3 supplies the discharge voltage Vss through the second output terminal 111b (VSS), and supplies it to the (p + 1) th gate line, the (k + 1) th stage and the (k-1) th stage.

On the other hand, in the second frame period, the first alternating-current voltage Vac1 transits to the low state, while the second alternating-current voltage Vac2 transitions to the high state, Thereby stably maintaining the state of charge of the reset node QB2.

As described above, according to the present invention, the first and second stabilization switching elements OS1 and OS2 alternately charge the first reset node QB1 and the second reset node QB2 on a frame-by-frame basis. Therefore, the disable state of the stage can be stably maintained, and thus, the multi-output can be prevented.

4 is a view for explaining a comparison between a node voltage of a stage provided in a shift register of the present invention and a node voltage of a stage provided in a conventional shift register.

As shown in Fig. 4, it can be seen that the voltage of the first reset node QB1 in the present invention is stably maintained at a higher voltage than that of the conventional one.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

Tr #: No. Switching Element OS #: No. # Stabilization Switching Element
CN #: Node # Common Node Node: Node Set Node
QB #: Primary reset node CLKi: Primary clock pulse
CLKi + 1: I + 1 clock pulse NC:
OU: Output part Vdd: Charging voltage
Vss: discharge voltage Vac #: No. AC voltage
Voutp: pth scan pulse Voutp + 1: p + 1 scan pulse
Voutp + 3: p + 3 scan pulse Voutp-2: p-2 scan pulse
Voutp-1: (p-1) th scan pulse OSU:
Trp #: Trp # of pull-up switching device Trpd #: Trp # of pull-down switching device
S #: 1st set switching element R #: 1st reset switching element

Claims (4)

A plurality of stages sequentially outputting scan pulses sequentially;
In each stage,
A node controller for controlling signal states of the first to fourth nodes according to a scan pulse from the front stage and a scan pulse from the rear stage;
An output unit sequentially outputting two scan pulses in accordance with the voltages of the first to fourth nodes and supplying the scan pulses to a stage located at a front end and a rear end of the stage; And
And an output stabilization unit controlled by a scan pulse from a rear stage and charging at least one of the first through fourth nodes. The method according to claim 1,
The first through fourth nodes are a first set node, a second set node, a first reset node, and a second reset node;
The node control unit included in the k-th stage, which is one of the stages,
A first set switching element connected between a charging power supply line for transmitting a charging voltage and a first set node controlled by a scan pulse output first of two scan pulses from a first start pulse or a (k-1) ;
A first reset switching element connected between the first set node and a discharge power supply line that is controlled by a scan pulse output from the second one of the two scan pulses from the (k + 1) th stage and transmits a discharge voltage;
A second set switching element controlled by a scan pulse output from a second start pulse or a second one of two scan pulses from a (k-1) th stage, and connected between the charging power supply line and a second set node;
A second reset switching element controlled by a scan pulse output from a second one of two scan pulses from the (k + 1) th stage and connected between the second set node and the discharge power supply line;
A first switching element controlled in accordance with the signal state of the first reset node and connected between the first set node and the discharge power supply line;
A second switching element controlled in accordance with a signal state of a second reset node and connected between the first set node and the discharge power supply line;
A third switching device controlled according to a signal state of the first set node, the third switching device being connected between the first reset node and the discharge power supply line;
A fourth switching device controlled according to a first AC voltage from a first AC power supply line and connected between the first AC power supply line and a first common node;
A fifth switching device controlled according to a signal state of the first common node, the fifth switching device being connected between the first AC power supply line and the first reset node;
A sixth switching device controlled according to a signal state of the first set node and connected between the first common node and the discharge power supply line;
A seventh switching element controlled in accordance with the signal state of the second set node, and connected between the first common node and the discharge power supply line.
An eighth switching element connected between the first reset node and the discharge power source line, the first switch being controlled by a first scan pulse output from the first start pulse or the second scan pulse from the (k-1) th stage;
A ninth switching element controlled in accordance with a signal state of the first reset node and connected between the second set node and the discharge power supply line;
A tenth switching element controlled in accordance with the signal state of the second reset node and connected between the second set node and the discharge power supply line;
An eleventh switching element controlled in accordance with a signal state of the second set node and connected between the second reset node and the discharge power supply line;
A twelfth switching element controlled according to a second AC voltage from a second AC power supply line and connected between the second AC power supply line and a second common node;
A thirteenth switching element controlled according to a signal state of the second common node, and connected between the second AC power supply line and the second reset node;
A fourteenth switching element controlled in accordance with a signal state of the second set node and connected between the second common node and the discharge power supply line; And
And a fifteenth switching element controlled in accordance with a signal state of the first set node and connected between the second common node and the discharge power supply line. 3. The method of claim 2,
Wherein the output unit provided in the k < th >
A first pull-up switching element controlled in accordance with a signal state of the first set node, the first pull-up switching element being connected between a first output terminal and one of clock transmission lines transmitting clock pulses;
A second pull-up switching element controlled in accordance with a signal state of the second set node, the second pull-up switching element being connected between a second output terminal and one of clock transmission lines transmitting clock pulses;
A first pull-down switching element controlled in accordance with a signal state of the first reset node, the first pull-down switching element being connected between a first output terminal and a discharge power supply line;
A second pull-down switching element controlled in accordance with a signal state of a second reset node and connected between a first output terminal and a discharge power supply line;
A third pull-down switching element controlled in accordance with the signal state of the first reset node and connected between the second output terminal and the discharge power supply line; And
And a fourth pull-down switching element controlled in accordance with the signal state of the second reset node and connected between the second output terminal and the discharge power supply line. 3. The method of claim 2,
Wherein the output stabilizing unit provided in the k < th >
A first stabilization switching element connected between the first AC power supply line and the first reset node, the first stabilization switching element being controlled by a scan pulse output from the second one of the two scan pulses from the (k + 1) th stage; And
And a second stabilization switching element controlled by a scan pulse output from the second one of the two scan pulses from the (k + 1) th stage and connected between the second AC power supply line and the second reset node. .

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