KR102223902B1 - Shift register and display device using the same - Google Patents

Abstract

The present invention relates to a shift register capable of reducing a circuit area by simplifying a logic circuit configuration, and a display device using the same. The shift register of the present invention includes a plurality of stages, and each of the plurality of stages is controlled by a control node. A pull-up transistor that generates one of the plurality of clocks as an output according to the control of the other clock, and a pull-down transistor that generates a gate-off voltage as an output according to the control of the other one of the plurality of clocks; A first transistor for setting the control node to a gate-on state according to control of an output signal of a previous stage of and a second transistor for resetting the control node to a gate-off state according to control of an output signal of any one of the next stages. And a third transistor for maintaining a reset state of the control node under control of another one of the plurality of clocks.

Description

SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME

The present invention relates to a shift register, and more particularly, to a shift register capable of reducing a circuit area by simplifying a logic circuit configuration, and a display device using the same.

Flat panel displays that have recently been in the spotlight as display devices include Liquid Crystal Display (LCD) using liquid crystal, OLED display using Organic Light Emitting Diode (OLED), and electrophoresis using electrophoretic particles. Typical examples are the ElectroPhoretic Display (EPD).

Flat panel displays include a display panel that displays an image through a pixel matrix in which each pixel is independently driven by a thin film transistor (TFT), a panel driver that drives the display panel, and a timing controller that controls the panel driver. And the like. The panel driver includes a gate driver that drives gate lines of the display panel and a data driver that drives data lines of the display panel.

Recently, in order to reduce manufacturing cost and reduce bezel width, a gate driver is formed on a substrate together with a TFT array of a pixel matrix, and thus a gate-in-panel (GIP) method built into the panel is mainly used. The GIP type gate driver is developing toward reducing the circuit area in order to further reduce the bezel width.

The gate driver outputs scan pulses that drive each of the gate lines using a shift register. The shift register is composed of a plurality of stages each driving a plurality of gate lines, and each stage includes an output unit and a node control unit. The output of each stage basically includes a pull-up TFT that outputs one clock to the gate line under the control of the Q node, and a pull-down TFT that outputs the gate low voltage to the gate line under the control of the QB node. do. The node control unit of each stage includes a number of TFTs that control charge/discharge of the Q node and charge/discharge of the QB node oppositely in response to a control signal, and in particular, a relatively large number of TFTs for maintaining the QB node in a high state. I'm doing it.

In addition, a shift register capable of bi-scanning so that forward scan and backward scan can be selectively used must include more TFTs in each stage.

For this reason, since the conventional shift register is composed of a rather large number of TFTs, it is difficult to reduce the circuit area, so there is a problem in that there is a limitation in implementing a narrow bezel.

The present invention has been conceived to solve the above-described problem, and an object to be solved by the present invention is to provide a shift register capable of reducing a circuit area by simplifying a logic circuit configuration and a display device using the same.

In order to solve the above problem, the shift register according to the embodiment of the present invention includes a plurality of stages, and each of the plurality of stages is a full-scale generator that generates any one of a plurality of clocks as an output according to the control of a control node. -An up transistor, a pull-down transistor that generates a gate-off voltage as an output according to the control of the other one of the plurality of clocks, and the control node is gate-on according to the control of an output signal of any one previous stage. A first transistor to be set to a state, a second transistor to reset the control node to a gate-off state according to control of an output signal of any one of the next stages, and another clock of the plurality of clocks And a third transistor for maintaining the reset state of the control node.

The control node includes a first control node connected to the first to third transistors and a second control node connected to the pull-up transistor. Each of the stages includes a capacitor connected between the control node and the output terminal of the pull-up transistor, a resistance transistor connecting the first and second control nodes by maintaining a turn-on state by a gate-on voltage, and an abnormal A bias transistor for driving a corresponding gate line through an output terminal of each stage according to a power-off detection signal is additionally provided.

The plurality of clocks include first to fourth clocks sequentially phase shifted. The pull-up transistor outputs the first clock, and the pull-down transistor is controlled by the third clock.

In the nth stage of the plurality of stages, the first transistor supplies the third clock to the control node according to the control of a scan signal output from the n-2th stage, and the second transistor is an n+2th stage. The gate-off voltage is supplied to the control node according to the control of the scan signal output from the stage, and the third transistor supplies the scan signal output from the n-1th stage to the control node according to the control of a fourth clock. do.

A shift register according to another embodiment of the present invention includes a plurality of stages in which a forward scan and a backward scan are selectively performed, and each of the plurality of stages sets any one of a plurality of clocks according to the control of a control node. A pull-up transistor that is generated as an output, a pull-down transistor that generates a gate-off voltage as an output according to the control of another one of the plurality of clocks, and an output signal of any one previous stage, A first transistor that sets the control node to a gate-on state during the forward scan and resets the control node to a gate-off state during the backward scan, and the forward according to control of an output signal of any one of the next stages. A second transistor that resets the control node to a gate-off state during scan and sets the control node to a gate-on state during the backward scan, and forwards another one of the plurality of clocks during the forward scan. Third and fourth transistors for maintaining the reset state of the control node according to the control of the driving voltage, and during the backward scan, the other clock of the plurality of clocks and the control node of the control node according to the control of the backward driving voltage. It includes fifth and sixth transistors for maintaining the reset state.

The control node includes a first control node connected to the first to sixth transistors and a second control node connected to the pull-up transistor. Each of the stages includes a capacitor connected between the control node and the output terminal of the pull-up transistor, a resistance transistor connecting the first and second control nodes by maintaining a turn-on state by a gate-on voltage, and an abnormal A bias transistor for driving a corresponding gate line through an output terminal of each stage according to a power-off detection signal is additionally provided.

The plurality of clocks include first to fourth clocks sequentially phase shifted. The pull-up transistor outputs the first clock, and the pull-down transistor is controlled by the third clock.

In the nth stage among the plurality of stages, the first transistor supplies the forward driving voltage or the fourth clock to the control node according to control of a scan signal output from the n-2th stage, and the second transistor Is supplying the backward driving voltage or the second clock to the control node according to the control of the scan signal output from the n+2th stage, and the third transistor is the n-1th stage according to the control of the fourth clock. The scan signal output from is supplied to the control node through a fourth transistor controlled by the forward driving voltage, and the fifth transistor receives the scan signal output from the n+1th stage under control of a second clock. , Is supplied to the control node through a sixth transistor controlled by the backward driving voltage.

The forward driving voltage is supplied in a gate-on state during the forward scan, and is supplied in a gate off state during the backward scan, and the backward driving voltage is supplied in the gate off state during the forward scan, and the backward scan At the time, it is supplied in the gate-on state.

Even if the shift register according to the present invention includes a single scan stage or a bi-scan stage, the circuit configuration is relatively simple, so that the circuit area can be reduced.

In addition, the display device according to the present invention can implement a narrow bezel because the width of the bezel on which the gate driver is formed can be reduced by using a shift resistor having a simple circuit configuration as a built-in gate driver.

1 is a block diagram showing the basic structure of a shift register according to a first embodiment of the present invention.
2 is a circuit diagram showing one stage in the shift register shown in FIG. 1.
3 is a driving waveform diagram of the stage shown in FIG. 2.
4 is a block diagram showing a basic structure of a bi-scan shift register according to a second embodiment of the present invention.
5 is a circuit diagram showing one stage in the bi-scan shift register shown in FIG. 4.
6 is a circuit diagram emphasizing a portion driven by a forward voltage in the stage shown in FIG. 5.
7 is a driving waveform diagram for forward scanning of the stage shown in FIG. 6.
8 is a circuit diagram emphasizing a portion driven by a backward voltage in the stage shown in FIG. 5.
9 is a driving waveform diagram for a backward scan of the stage shown in FIG. 8.
10 is a circuit diagram showing one stage in a bi-scan shift register according to a third embodiment of the present invention.
11 is a block diagram schematically illustrating a display device using a shift register according to the present invention.

1 is a block diagram showing the basic structure of a shift register according to a first embodiment of the present invention.

The shift register shown in FIG. 1 is used as a built-in gate driver of an active matrix display device, and a plurality of stages each driving a plurality of gate lines {GL(n-2) to GL(n+2)} {ST (n-2) to ST(n+2)}. A plurality of stages {ST(n-2) to ST(n+2)} scans a plurality of gate lines {GL(n-2) to GL(n+2)} in the forward direction.

A gate high voltage VGH and a low potential voltage VSS are supplied to each of the plurality of stages ST(n-2) to ST(n+2). The gate high voltage VGH may be expressed as a gate-on voltage, and the low potential voltage VSS may be expressed as a gate-off voltage.

A plurality of clocks CLKs having a phase difference are supplied to each of the plurality of stages (ST(n-2) to ST(n+2)). For example, each of the plurality of stages (ST(n-2) to ST(n+2)) is connected to at least three of the four clock lines each transmitting the four-phase clock CLKs.

In each of the plurality of stages {ST(n-2) to ST(n+2)}, a scan signal output from one of the previous stages and a scan signal output from any one of the next stages, It is supplied as a control signal (carry signal) for controlling the logic state of the Q node controlling the output unit. In addition, to each of the plurality of stages (ST(n-2) to ST(n+2)), a scan signal output from the other stage among the previous stages is further supplied to maintain the low state of the Q node.

For example, in the nth stage {ST(n)}, the n-2th scan signal {G(n-2)} output from the n-2th stage {ST(n-2)} and the n+2nd The n+2th scan signal {G(n+2)} output from the stage {ST(n+2)} is supplied as a control signal (carry signal) that controls the logic state of the Q node, and the n-1th stage The n-1th scan signal {G(n-1)} output from {ST(n-1)} is supplied to maintain the low state of the Q node.

The high state of the Q node indicates a gate-on state and may be expressed as a set state, and the low state of the Q node indicates a gate-off state and may be expressed as a reset state.

FIG. 2 is a circuit diagram showing one stage in the shift register shown in FIG. 1, and FIG. 3 is a driving waveform diagram of the stage shown in FIG. 2.

The n-th stage {ST(n)} shown in FIG. 2 drives the n-th gate line, and the same applies to other stages.

The n-th stage {ST(n)} includes an output unit including a pull-up TFT (Tup), a pull-down TFT (Tpd), and a capacitor CQ, and the first to third TFTs (T1 to T3) and reset A node control unit including a transistor Trs is provided.

The n-th stage {ST(n)} may further include a resistive TFT (Td) that is connected between the node Q1, which is an output node of the node control unit, and the node Q2, which is the control node of the output unit, and serves as a resistor.

The n-th stage {ST(n)} may further include a bias TFT (Tab) for driving the gate line for rapid discharge of the pixel matrix when the power is abnormally turned off.

The nth stage {ST(n)} is a three-phase clock {CLK(m-1) among four-phase clocks {CLK(m-1), CLK(m), CLK(m+1), CLK(m+2)} ), CLK(m), CLK(m+2)}. For example, when the four-phase clock {CLK(m-1), CLK(m), CLK(m+1), CLK(m+2)} is sequentially phase shifted, n The third stage {ST(n)} receives CLK4, CLK1, and CLK3.

The pull-up TFT (Tup) is switched under the control of the Q2 node to supply the m clock {CLK(m)} (CLK1) to the n-th gate line through the output terminal. Accordingly, the m clock {CLK(m)} is supplied as the gate-on voltage (gate high voltage) of the n-th scan signal {G(n)} through the pull-up TFT(Tup).

The pull-down TFT (Tpd) is switched under the control of the m+2 clock {CLK(m+2)} (CLK3) to supply the low potential voltage VSS to the n-th gate line through the output terminal. Accordingly, the low potential voltage VSS is supplied as the gate-off voltage (gate low voltage) of the n-th scan signal G(n) through the pull-down TFT Tpd.

The capacitor CQ is connected between the gate and the drain of the pull-up TFT Tup, that is, between the Q2 node and the output terminal, so that the voltage of the Q2 node is m clocked {CLK( Follow the high state of m)} to make it bootstrapped. Accordingly, when the pull-up TFT (Tup) outputs m clock {CLK(m)}, the voltage of the Q2 node further rises from the high state to bootstrapping, so that the pull-up TFT (Tup) is stably m The clock {CLK(m)} may be supplied as the n-th scan signal {G(n)}.

The first TFT (T1) is switched according to the control of the n-2th scan signal {G(n-2)} output from the n-2th stage, and the m+2 clock {CLK(m+2)}(CLK3) Is supplied to the Q1 node. Accordingly, the nodes Q1 and Q2 connected through the resistive TFT (Td) are clocked by m+2 through the first TFT (T1) before the pull-up TFT (Tup) outputs the m clock {CLK(m)}. A high voltage of CLK(m+2)} is supplied and set to a high state. Meanwhile, the m-1 clock {CLK(m-1)} (CLK4) may be supplied to the first TFT T1 instead of the m+2 clock {CLK(m+2)} (CLK3).

The second TFT T2 is switched under the control of the n+2 th scan signal G(n+2) output from the n+2 th stage to supply the low potential voltage VSS to the Q1 node. Accordingly, after the pull-up TFT (Tup) outputs m clock {CLK(m)}, the Q1 and Q2 nodes are reset to a low state by supplying a low potential voltage (VSS) through the second TFT (T2). do.

The third TFT (T3) is switched under the control of the m-1 clock {CLK(m-1)} (CLK4) and the n-1th scan signal {G(n-1)} is output from the n-1th stage. Is supplied to the Q1 node. Accordingly, even after the nodes Q1 and Q2 are reset by the second TFT (T2), the gate-off voltage of the n-1th scan signal {G(n-1)} is supplied through the third TFT (T2) to be in a low state. Keep it.

The reset TFT (Trs) is switched under the control of the start pulse (Vst) to supply the low potential voltage (VSS) to the Q1 node. Accordingly, the Q1 and Q2 nodes are reset to the low state by supplying the low potential voltage VSS through the reset TFT Trs when each frame starts or ends. At this time, the reset TFTs (Trs) of all stages are simultaneously turned on by the start pulse Vst, so that nodes Q1 and Q2 of all stages may be reset at the same time.

The resistor TFT (Td) is always turned on according to the gate high voltage (VGH) to connect the Q1 node and the Q2 node, but acts as a resistor so that the voltage of the Q1 node and the voltage of the Q2 node are different from each other. Accordingly, when the voltage of the Q2 node is bootstrapped and increased according to the m clock {CLK(m)}, the voltage of the Q1 node is raised lower than the voltage of the Q2 node by the resistive TFT (Td), so bootstrapping It is possible to reduce the hot carrier stress of the Q1 node due to.

When the bias TFT (Tab) is abnormally turned off, the bias TFT (Tab) is turned on according to the abnormal detection signal (ABNORMAL) supplied from the power supply circuit to drive the corresponding gate line. At this time, since the bias TFTs (Tab) of all stages simultaneously drive all the gate lines according to the abnormal detection signal (ABNORMAL), the TFTs of the pixel matrix are simultaneously turned on and charges charged in each subpixel are turned on. It can be quickly discharged through. Accordingly, even if the power is abnormally turned off due to battery separation or the like, charges in the pixel matrix are rapidly discharged, so that flicker due to insufficient discharge can be prevented.

Referring to FIG. 3, each of the four-phase clocks {CLK(m-1), CLK(m), CLK(m+1), CLK(m+2)} is in a high state of 2H (H is a horizontal period), The low state of 2H is supplied in a circulating form. The four-phase clocks {CLK(m-1), CLK(m), CLK(m+1), CLK(m+2)} are sequentially phase shifted by 1H, and adjacent clocks overlap each other with the high state of 1H. Is supplied.

Accordingly, the scan signals {G(n-2) and G() are selectively output to the four-phase clock {CLK(m-1), CLK(m), CLK(m+1), CLK(m+2)}. Each of n-1), G(n), and G(n+2)} has a gate-on voltage of 2H, and adjacent scan signals overlap each other with a gate-on voltage of 1H.

2 and 3, the first TFT (T1) is turned on by the control of the n-2th scan signal {G(n-2)} in the period t1 and t2, and the m+2 clock {CLK( By supplying m+2)}(CLK3) to the Q1 node, the Q1 and Q2 nodes are set to the high state. The n-2th scan signal {G(n-2)} outputs an m+2 clock {CLK(m+2)} in the n-2th stage. The pull-up TFT (Tup) is turned on by the high state of the Q2 node, and a low voltage of the m clock {CLK(m)} is output, and under the control of the m+2 clock {CLK(m+2)}. Since the pull-down TFT (Tpd) is also turned on to output the low potential voltage VSS, the scan signal G(n) of the n-th gate line maintains the gate-off state.

In the period t3 and t4, the high state of the Q2 and Q1 nodes is bootstrapped according to the high state of the m-th clock {CLK(m)} (CLK1), and the m clock through the pull-up TFT (Tup) sufficiently turned on{ CLK(m)} is supplied as the scan signal {G(n)} of the n-th gate line. The pull-down TFT (Tpd) is turned off by the control of the m+2 clock {CLK(m+2)}.

In periods t5 and t6, the pull-down TFT (Tpd) is turned on under the control of the m+2 clock {CLK(m+2)} (CLK3), so that the low potential voltage (VSS) is the scan signal of the nth gate line. It is supplied as {G(n)}. At this time, the second TFT (T2) is turned on under the control of the scan signal {G(n+2)} output from the n+2th stage, and the Q1 and Q2 nodes are in a low state due to the low potential voltage (VSS). Is reset to. The n+2th scan signal {G(n+2)} is the output of the m+2 clock {CLK(m+2)} in the n+2th stage. Even after the t6 period, the pull-down TFT (Tpd) is periodically turned on according to the m+2 clock {CLK(m+2)}, so that the scan signal {G(n)} of the n-th gate line remains in the gate-off state. do.

In the period t6 and subsequent periods, the third TFT T3 is turned on under the control of the m-1 clock {CLK(m-1)} (CLK4) and the n-1th scan signal {G(n-1) )}'S gate-off voltage is supplied to the Q1 node, so the Q1 and Q2 nodes remain low, and the third TFT (T3) is periodically turned on according to the m-1 clock {CLK(m-1)} afterwards. As a result, nodes Q1 and Q2 are kept in a low state.

As described above, in the shift register according to the first embodiment of the present invention, each stage is composed of eight TFTs (T1 to T3, Trs, Tup, Tpd, Td, Tab) and one capacitor (CQ), so that the circuit configuration is simple. Therefore, the circuit area can be reduced.

Meanwhile, the shift register according to the first embodiment of the present invention is capable of forward scan only.

In order to compensate for this, the present invention further proposes a shift register capable of bi-scan so that scan can be selectively used for forward scan and backward scan.

4 is a block diagram showing a basic structure of a bi-scan shift register according to a second embodiment of the present invention.

Hereinafter, for convenience of explanation, descriptions of components that overlap with the first embodiment will be omitted or briefly described, and components that differ from those of the first embodiment will be mainly described.

Compared with the bi-scan shift register shown in FIG. 4 and the single scan shift register shown in FIG. 1, the forward driving voltage VDD_F and the backward driving voltage VDD_R are in a plurality of stages (ST(n-2)). ~ ST(n+2)} is additionally supplied to each.

The forward driving voltage VDD_F is supplied in a high state only during a forward scan, and is supplied in a low state during a backward scan. Conversely, the backward driving voltage VDD_R is supplied in a high state only during a backward scan, and is supplied in a low state during a forward scan. Accordingly, since the forward scan and the backward scan can be controlled according to the logic states of the forward driving voltage VDD_F and the backward driving voltage VDD_R, a separate direction control signal for controlling the scan direction is not required.

In each of the plurality of stages {ST(n-2) ~ ST(n+2)}, two scan signals output from two of the previous stages and two scan signals output from two of the next stages. Is supplied and connected to the four clock lines each transmitting the four-phase clocks CLKs.

For example, in the nth stage {ST(n)}, the n-2th scan signal {G(n-2)} output from the n-2th stage {ST(n-2)} and the n+2nd The n+2th scan signal {G(n+2)} output from the stage {ST(n+2)} is supplied as a control signal (carry signal) that controls the logic state of the Q node, and the n-1th stage The n-1th scan signal {G(n-1)} output from {ST(n-1)} and the n+1th scan signal output from n+1 stage {ST(n+1)}{ G(n-1)} is supplied to maintain the low state of the Q node.

5 is a circuit diagram showing one stage in the bi-scan shift register shown in FIG. 4.

When the bi-scan stage shown in FIG. 5 and the single scan stage shown in FIG. 2 are compared, the forward driving voltage VDD_F instead of m+2 clock {CLK(m+2)} is applied to the first TFT T1. The second TFT T2 is supplied with a backward driving voltage VDD_R instead of the low potential voltage VSS, and the fourth to sixth TFTs T4 for maintaining the Q nodes Q1 and Q2 in a low state. , T5, T6) are additionally configured.

The first TFT T1 sets the Q nodes Q1 and Q2 to a high state by using the forward driving voltage VDD_F in the high state during forward scanning, and sets the forward driving voltage VDD_F in the low state during the backward scan. Is used to reset the Q nodes Q1 and Q2 to a low state.

Conversely, the second TFT (T2) sets the Q nodes Q1 and Q2 to a high state by using the backward driving voltage VDD_R in a high state during the backward scan, and sets the backward driving voltage in the low state during the forward scan. The Q nodes Q1 and Q2 are reset to the low state by using (VDD_R).

The third and fourth TFTs T3 and T4 maintain the Q nodes Q1 and Q2 in a low state by using the n-1th scan signal {G(n-1)} during forward scanning. The fourth TFT T4 controlled by the forward driving voltage VDD_F is turned on only during the forward scan to connect the third TFT T3 and the Q1 node. Accordingly, during forward scanning, the third TFT (T3) is switched under the control of the m-1 clock {CLK(m-1)} (CLK4), and the n-1th scan signal {G (n-1)} is supplied to the Q1 node through the fourth TFT (T4) to keep the Q1 and Q2 nodes low. During the backward scan, the fourth TFT T4 maintains the turn-off state by the forward driving voltage VDD_F in the low state.

The fifth and sixth TFTs T3 and T4 maintain the Q nodes Q1 and Q2 in a low state by using the n+1th scan signal {G(n+1)} during a backward scan. The sixth TFT T6 controlled by the backward driving voltage VDD_R is turned on only during the backward scan to connect the fifth TFT T5 and the Q1 node. Accordingly, during the backward scan, the fifth TFT (T5) is switched under the control of the m+1 clock {CLK(m+1)} (CLK2) and the n+1th scan signal is output from the n+1th stage{ G(n+1)} is supplied to the Q1 node through the sixth TFT (T6) to keep the Q1 and Q2 nodes low. During forward scanning, the sixth TFT T6 maintains a turn-off state by the low backward driving voltage VDD_R.

FIG. 6 is a diagram showing a portion driven by the forward driving voltage VDD_F during forward scanning of the stage shown in FIG. 5, and FIG. 7 is a driving waveform diagram for forward scanning of the stage shown in FIG. 6.

Referring to FIG. 6, a forward driving voltage VDD_F in a high state supplied through the first TFT T1 before the pull-up TFT Tup outputs m clock {CLK(m)} during forward scanning. These Q1 and Q2 nodes are set to a high state. Then, after the m clock {CLK(m)} is output and the nodes Q1 and Q2 are reset by the second TFT (T2), n-1 supplied through the third and fourth TFTs (T3, T4) A th scan signal {G(n-1)} keeps the nodes Q1 and Q2 low.

Forward scan driving of the stage shown in FIG. 6 will be described with reference to FIGS. 6 and 7.

During periods t1 and t2, the first TFT (T1) is turned on under the control of the n-2th scan signal {G(n-2)}, so that the forward driving voltage VDD_F in the high state turns the nodes Q1 and Q2 high. Set it to the state. Through the pull-up TFT (Tup) turned on by the control of the Q2 node and the pull-down TFT (Tpd) turned on by the control of the m+2 clock {CLK(m+2)} (CLK3). The second scan signal G(n) maintains the gate-off state.

The m clock {CLK(m)} (CLK1) is supplied as the gate-on voltage of the n-th scan signal {G(n)} through the pull-up TFT (Tup) turned on in the periods t3 and t4.

In the periods t5 and t6, the low potential voltage VSS is transferred to the nth scan signal {G() through the pull-down TFT (Tpd) turned on under the control of the m+2 clock {CLK(m+2)}(CLK3). It is supplied with a gate-off voltage of n)}. At this time, the second TFT (T2) is turned on under the control of the scan signal {G(n+2)} output from the n+2th stage, so that the backward driving voltage VDD_R in the low state is Q1 and Q2 nodes. Reset to low state. Even after the t6 period, the pull-down TFT (Tpd) is periodically turned on according to the m+2 clock {CLK(m+2)}, so that the scan signal {G(n)} of the n-th gate line remains in the gate-off state. do.

In the period t6 and subsequent periods, the third TFT T3 turned on under the control of the m-1 clock {CLK(m-1)} (CLK4) and the forward driving voltage VDD_F in the high state. As a result, the gate low voltage of the n-1th scan signal G(n-1) through the fourth TFT T4, which is in the turn-on state, keeps the nodes Q1 and Q2 in a low state. Thereafter, the nodes Q1 and Q2 maintain the low state by the third TFT (T3) periodically turned on according to the m-1 clock {CLK(m-1)}.

FIG. 8 is a diagram showing a portion driven by a backward driving voltage VDD_R during a backward scan of the stage shown in FIG. 5, and FIG. 9 is a driving waveform for a backward scan of the stage shown in FIG. It is a degree.

Referring to FIG. 8, before the pull-up TFT (Tup) outputs m clock {CLK(m)} during a backward scan, the backward driving voltage in a high state supplied through the second TFT (T2) ( VDD_R) sets the Q1 and Q2 nodes to a high state. Subsequently, after the m clock {CLK(m)} is output and the nodes Q1 and Q2 are reset by the first TFT (T1), n+1 supplied through the fifth and sixth TFTs (T5, T6) A th scan signal {G(n+1)} keeps the nodes Q1 and Q2 low.

The backward scan driving of the stage shown in FIG. 8 will be described with reference to FIGS. 8 and 9.

During periods t1 and t2, the second TFT (T2) is turned on under the control of the n+2th scan signal {G(n+2)}, so that the high-state backward driving voltage VDD_R is applied to the Q1 and Q2 nodes. Set it high. Through the pull-up TFT (Tup) turned on by the control of the Q2 node and the pull-down TFT (Tpd) turned on by the control of the m+2 clock {CLK(m+2)} (CLK3). The second scan signal G(n) maintains the gate-off state.

The m clock {CLK(m)} (CLK1) is supplied as the gate-on voltage of the n-th scan signal {G(n)} through the pull-up TFT (Tup) turned on in the periods t3 and t4.

In the periods t5 and t6, the low potential voltage VSS is transferred to the nth scan signal {G() through the pull-down TFT (Tpd) turned on under the control of the m+2 clock {CLK(m+2)}(CLK3). It is supplied with a gate-off voltage of n)}. At this time, the first TFT (T1) is turned on under the control of the scan signal {G(n-2)} output from the n-2th stage, so that the forward driving voltage VDD_F in the low state is applied to the nodes Q1 and Q2. Reset to low state. Even after the t6 period, the pull-down TFT (Tpd) is periodically turned on according to the m+2 clock {CLK(m+2)}, so that the scan signal {G(n)} of the n-th gate line remains in the gate-off state. do.

In period t6 and subsequent periods, the fifth TFT (T5) turned on under the control of the m-1th clock {CLK(m-1)} and the high-state backward driving voltage (VDD_R). The gate low voltage of the n+1th scan signal G(n+1) through the sixth TFT (T6) in the turn-on state keeps the nodes Q1 and Q2 in the low state. Thereafter, the nodes Q1 and Q2 maintain the low state by the third TFT (T3) periodically turned on according to the m-1 clock {CLK(m-1)}.

10 is a circuit diagram showing one stage in a bi-scan shift register according to a third embodiment of the present invention.

When the bi-scan stage of the third embodiment shown in FIG. 10 and the bi-scan stage of the second embodiment shown in FIG. 5 are compared, the first TFT T1 has an m-1 clock instead of the forward driving voltage VDD_F. The difference is that CLK(m-1)}(CLK4) is supplied, and m+1 clock {CLK(m+1)}(CLK2) is supplied to the second TFT(T2) instead of the backward driving voltage (VDD_R). There is.

Accordingly, the time that the Q1 and Q2 nodes are charged to the high state through the first TFT (T1) during the forward scan is reduced from 2H to 1H as shown in FIG. 7, and through the second TFT (T1) during the backward scan. The time during which the Q1 and Q2 nodes are charged to the high state is reduced from 2H to 1H shown in FIG. 9, and the remaining driving is the same. Since LTPS (Low Temperature Poly-Silicon) TFT has a high mobility, the time to charge the Q1 and Q2 nodes can be shortened from 2H to 1H.

As described above, the bi-scan shift register according to the second and third embodiments of the present invention enables bi-scan, but each stage has 11 TFTs (T1 to T6, Trs, Tup, Tpd, Td, Tab) and 1 Since it is composed of four capacitors (CQ) and a relatively simple circuit configuration, the circuit area can be reduced.

For example, in the conventional shift resistor, the single scan stage is composed of 12 TFTs and 2 capacitors, so there is a limit to reducing the bezel width to 0.6mm or less, and the bi-scan stage has a TFT that controls the scanning direction. There was a problem that the bezel width should be further increased. However, the shift resistor of the present invention can reduce the bezel width to 0.4mm by simplifying the single scan stage to 8 TFTs and 1 capacitor. In addition, the shift resistor of the present invention can reduce the bezel width to 0.45mm by relatively simplifying the bi-scan stage to 11 TFTs and 1 capacitor.

11 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

The display device illustrated in FIG. 11 includes a display panel 30 including a display area DA and a gate driver 40, a data driver 20, a timing controller 10, and the like.

The display panel 30 displays an image through a pixel matrix formed in the display area DA. Each pixel of the pixel matrix generally implements a desired color by a combination of R (Red), G (Green), and B (Blue) sub-pixels, and additionally includes a W (White) sub-pixel for improving luminance. Each subpixel is independently driven by at least one TFT. A liquid crystal panel, an OLED panel, or the like may be used as the display panel 30.

For example, each subpixel of the liquid crystal panel is composed of a liquid crystal cell that adjusts light transmittance by varying the alignment direction of the liquid crystal according to the data voltage supplied from the data line in response to the scan pulse of the gate line. Each subpixel of the OLED panel is composed of light emitting cells that emit light in proportion to the current according to the data voltage supplied from the data line in response to the scan pulse of the gate line.

The gate driver 40 is a GIP type built in a non-display area of the display panel 30 and includes a plurality of TFTs formed on a substrate together with a TFT array of the display area DA. The TFT included in the display area DA and the gate driver 40 may use an LTPS TFT, but the present invention is not limited thereto, and an amorphous silicon TFT or an oxide TFT may be used.

The gate driver 40 includes any one of the shift registers according to the first to third embodiments described above in FIGS. 1 to 10, and in response to a gate control signal from the timing controller 10, the gate line of the pixel matrix Drive them. The gate driver 40 turns on the TFTs connected to the corresponding gate line by supplying a scan pulse of the gate-on voltage during the scan period of each gate line, and supplies the gate-off voltage to the corresponding gate line during the remaining period of each gate line. The TFTs connected to the line are turned off.

The gate driver 40 is formed on one side of the display area DA to supply a scan signal through one end of each gate line, or is formed on both sides of the display area DA and is formed on both sides of each gate line. Can supply scan signal. The gate driver 40 may drive a plurality of gate lines by forward scan or by selectively using forward scan and backward scan.

A level shifter (not shown) may be additionally provided between the timing controller 10 and the gate driver 40. The level shifter uses a gate control signal from the timing controller 10, i.e., a start pulse and a multi-clock TTL (Transistor Transistor Logic) voltage, to a gate high voltage (VGH) and a gate low voltage (VGH) for driving the TFT of the display panel 30. VGL=VSS) is level-shifted and supplied to the shift register which is the gate driver 40.

The data driver 20 supplies image data from the timing controller 10 to a plurality of data lines DL of the display panel 30 in response to a data control signal from the timing controller 10. The data driver 20 converts data from the timing controller 10 into an analog data signal using a gamma voltage from a gamma voltage generator (not shown), and converts the data signal to a data line whenever each gate line is driven. To be supplied. The data driver 20 is composed of at least one data IC and is mounted on a circuit film such as a tape carrier package (TCP), a chip on film (COF), a flexible print circuit (FPC), etc. It may be attached in an automatic bonding) method or mounted on a non-display area of the display panel 30 in a chip on glass (COG) method.

The timing controller 10 inputs a plurality of synchronization signals together with image data supplied from the outside. The plurality of synchronization signals may include a dot clock and a data enable signal, or may further include a horizontal synchronization signal and a vertical synchronization signal. The timing controller 10 corrects input data using various data processing methods for improving image quality or reducing power consumption, and outputs the corrected input data to the data driver 20. The timing controller 10 generates a data control signal for controlling the driving timing of the data driver 20 and a gate control signal for controlling the driving timing of the gate driver 40 by using synchronization signals.

As described above, the display device according to the present invention can implement a narrow bezel because the width of the bezel on which the gate driver is formed can be reduced by using a shift resistor having a simple circuit configuration as a gate driver.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

VGH: Gate high voltage VSS: Low potential voltage
ST(n-2) to ST(n+2): stage
CLKs, CLK(m-1), CLK(m), CLK(m+1), CLK(m+2): clock
Tup: Pull-up TFT Tpd: Pull-down TFT
T1 to T6: first to sixth TFT Trs: reset TFT
Td: resistance TFT Tab: bias TFT
ABNORMAL: abnormal detection signal VDD_F: first driving voltage
VDD_R: second driving voltage 10: timing controller
20: data driver 30: display panel
40: gate driver DA: display area

Claims (8)

In the shift register including a plurality of stages,
Each of the plurality of stages
A pull-up transistor that generates any one of a plurality of clocks as an output according to the control of the control node,
A pull-down transistor for generating a gate-off voltage as an output under control of another one of the plurality of clocks;
A first transistor for setting the control node to a gate-on state according to control of an output signal of any one previous stage;
A second transistor for resetting the control node to a gate-off state according to control of an output signal of any one of the next stages;
A third transistor for maintaining a reset state of the control node under control of another one of the plurality of clocks,
The control node includes a first control node connected to the first to third transistors and a second control node connected to the pull-up transistor,
Each of the above stages
A capacitor connected between the control node and the output terminal of the pull-up transistor,
A resistance transistor connecting the first and second control nodes by maintaining a turned-on state by a gate-on voltage,
And a bias transistor for driving a corresponding gate line through an output terminal of each stage according to an abnormal power-off detection signal. delete The method according to claim 1,
The plurality of clocks include first to fourth clocks sequentially phase shifted,
The pull-up transistor outputs the first clock,
The pull-down transistor is controlled by the third clock,
In the nth stage of the plurality of stages,
The first transistor supplies the third clock to the control node according to control of a scan signal output from an n-2th stage,
The second transistor supplies the gate-off voltage to the control node according to control of a scan signal output from an n+2 th stage,
And the third transistor supplies a scan signal output from an n-1 th stage to the control node under control of a fourth clock. In a shift register including a plurality of stages in which forward scan and backward scan are selectively performed,
Each of the plurality of stages
A pull-up transistor that generates any one of a plurality of clocks as an output according to the control of the control node,
A pull-down transistor for generating a gate-off voltage as an output under control of another one of the plurality of clocks;
A first transistor that sets the control node to a gate-on state during the forward scan and resets the control node to a gate off state during the backward scan, according to control of an output signal of any one previous stage;
A second transistor that resets the control node to a gate-off state during the forward scan and sets the control node to a gate-on state during the backward scan, according to control of an output signal of any one of the next stages;
Third and fourth transistors for maintaining a reset state of the control node according to the control of another one of the plurality of clocks and a forward driving voltage during the forward scan,
When the backward scan is performed, fifth and sixth transistors are provided to maintain a reset state of the control node according to the control of the other one of the plurality of clocks and a backward driving voltage,
The control node includes a first control node connected to the first to sixth transistors and a second control node connected to the pull-up transistor,
Each of the above stages
A capacitor connected between the control node and the output terminal of the pull-up transistor,
A resistance transistor connecting the first and second control nodes by maintaining a turned-on state by a gate-on voltage,
And a bias transistor for driving a corresponding gate line through an output terminal of each stage according to an abnormal power-off detection signal. delete The method of claim 4,
The plurality of clocks include first to fourth clocks sequentially phase shifted,
The pull-up transistor outputs the first clock,
The pull-down transistor is controlled by the third clock,
In the nth stage of the plurality of stages,
The first transistor supplies the forward driving voltage or the fourth clock to the control node according to control of a scan signal output from an n-2th stage,
The second transistor supplies the backward driving voltage or the second clock to the control node according to control of a scan signal output from an n+2 th stage,
The third transistor supplies a scan signal output from the n-1 th stage under control of a fourth clock to the control node through a fourth transistor controlled by the forward driving voltage,
The fifth transistor supplies a scan signal output from the n+1 th stage under control of a second clock to the control node through a sixth transistor controlled by the backward driving voltage. . The method of claim 6,
The forward driving voltage is supplied in a gate-on state during the forward scan, and is supplied in a gate off state during the backward scan,
And the backward driving voltage is supplied in the gate off state during the forward scan and in the gate on state during the backward scan. A display device driving a gate line of a display panel by using the shift register according to any one of claims 1, 3 to 4, and 6 to 7.

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