KR20070000832A - A shift register and a method for driving the same - Google Patents

Abstract

A shift register and a driving method thereof are provided to prevent a coupling phenomenon by discharging a first node of the shift register whenever a clock pulse is applied to the shift register. A shift register includes plural stages, which sequentially activate gate lines of an LCD(Liquid Crystal Display) panel by sequentially supplying scan pulses. Each of the stages includes a node controller(400a), a pull-up switching element(Tru), a pull-down switching element(Trd), a discharge unit(400c), and a disconnection unit(400d). The node controller controls the charging or discharging state of first and second nodes. The pull-up switching element receives a first periodic clock pulse and outputs the first clock pulse, which is supplied while the first node is in a charged state, as the scan pulse. The pull-down switching element outputs a first voltage source in response to the charged state of the second node. The discharge unit discharges the first node down to the voltage level of the first voltage source for every first clock pulses. The disconnection unit stops the operation of the discharge unit in response to the scan pulse from the pull-up switching element, so that the first node is maintained in the charged state.

Description

A shift register and a method for driving the same

1 is a view showing a conventional shift register

2 is a diagram illustrating a state of charge of a first node due to a coupling phenomenon;

3 illustrates a shift register according to a first embodiment of the present invention.

4 is a diagram illustrating a detailed configuration of a second stage of FIG. 3.

5 is a diagram illustrating a circuit configuration of a node controller, an output unit, and a discharge unit provided in the second stage.

FIG. 6 is a view illustrating the first to third stages of FIG. 3.

7 is a timing diagram of various signals supplied to the stage of FIG. 6 and scan pulses output from the stage.

FIG. 8 is a diagram illustrating another circuit configuration of the second stage of FIG. 2.

9 illustrates a shift register according to a second embodiment of the present invention.

FIG. 10 is a detailed configuration diagram of the second stage of FIG. 9.

FIG. 11 is a diagram illustrating a circuit configuration of the second stage illustrated in FIG. 10.

12 is a view showing the first to third stages of FIG.

FIG. 13 is a timing diagram of various signals supplied to the stage of FIG. 12 and scan pulses output from the stage.

14 illustrates a shift register according to a third embodiment of the present invention.

FIG. 15 is a circuit diagram illustrating the second stage of FIG. 14.

FIG. 16 is a diagram illustrating still another circuit configuration of the second stage of FIG.

* Explanation of symbols on the main parts of the drawings

BST1 to BSTn: first to nth stage BSTn + 1: dummy stage

CLK1 to CLK4: first to fourth clock pulses SP: start pulse

VDD: first voltage source VSS: second voltage source

Vout1 to Voutn + 1: First to nth + 1 scan pulses

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register of a liquid crystal display, and more particularly to a shift register capable of preventing multiple outputs due to coupling with a clock pulse.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and a pixel region is positioned in an area defined by vertical crossings of the gate lines and data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed in the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a scan pulse applied to a gate terminal via the gate line, so that the data signal of the data line is charged to the pixel voltage.

The driving circuit may include a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, and a liquid crystal display device. It is provided with a power supply for supplying a variety of driving voltages used in.

The timing controller controls driving timing of the gate driver and the data driver and supplies a pixel data signal to the data driver. The power supply unit boosts or decompresses an input power to generate driving voltages such as a common voltage VCOM, a gate high voltage signal VGH, and a gate low voltage signal VGL required by the liquid crystal display. The gate driver sequentially supplies scan pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a scan pulse is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Here, the gate driver includes a shift register to sequentially output the scan pulses as described above. This will be described in more detail with reference to the accompanying drawings.

1 is a diagram illustrating a conventional shift register.

As shown in FIG. 1, the conventional shift register includes n stages AST1 to ASTn and one dummy stage ASTn + 1 connected dependently to each other. Here, each of the stages AST1 to ASTn + 1 outputs one scan pulse Vout1 to Voutn + 1, and in this case, the scan pulse Vout1 sequentially from the first stage AST1 to the dummy stage ASTn + 1. To Voutn + 1). In this case, scan pulses Vout1 to Voutn output from the stages AST1 to ASTn except for the dummy stage ASTn + 1 are sequentially supplied to gate lines of the liquid crystal panel (not shown). The gate lines are sequentially scanned.

The entire stages AST1 to ASTn + 1 of the shift register configured as described above are configured with the first voltage source VDD and the second voltage source VSS, and the first to fourth clock pulses CLK1 to CLK4 having sequential phase differences with each other. Two clock pulses are received. Here, the first voltage source VDD means a positive voltage source, and the second voltage source VSS means a ground voltage.

Meanwhile, the first stage AST1 located at the uppermost side of the stages AST1 to ASTn + 1 may have a start pulse in addition to the first voltage source VDD, the second voltage source VSS, and the two clock pulses. (SP) is supplied.

The operation of the conventional shift register configured as described above will be described in detail as follows.

First, when a start pulse SP from a timing controller (not shown) is applied to the first stage AST1, the first stage AST1 is enabled in response to the start pulse SP.

Subsequently, the enabled first stage AST1 receives the first and second clock pulses CLK1 to CLK2 from the timing controller, and outputs the first scan pulse Vout1, and the first gate line and the first gate line. It is supplied together to the 2 stage AST2. Then, the second stage AST2 is enabled in response to the first scan pulse Vout1.

Subsequently, the enabled second stage AST2 receives the second and third clock pulses CLK2 and CLK3 from the timing controller and outputs a second scan pulse Vout2, and the second gate line, The third stage AST3 and the first stage AST1 are supplied together. Then, the third stage AST3 is enabled in response to the second scan pulse Vout2, and the first stage AST1 is disabled in response to the second scan pulse Vout2. A second voltage source VSS is supplied to the first gate line.

Subsequently, the enabled third stage AST3 receives the third and fourth clock pulses CLK3 and CLK4 from the timing controller and outputs a third scan pulse Vout3, and the third gate line, The fourth stage AST4 and the second stage AST2 are supplied together. Then, the fourth stage AST4 is enabled in response to the third scan pulse Vout3, and the second stage AST2 is disabled in response to the third scan pulse Vout3. A second voltage source VSS is supplied to the second gate line.

In this manner, the fourth to nth scan pulses Voutn are sequentially output to the remaining fourth to nth stages AST4 to ASTn and sequentially applied to the fourth to nth gate lines. As a result, the first to nth gate lines are sequentially scanned by the sequentially output first to nth scan pulses Vout1 to Voutn.

Meanwhile, the dummy stage ASTn + 1 is enabled in response to the nth scan pulse Voutn from the nth stage ASTn, and then receives two clock pulses from the timing controller. One scan pulse Voutn + 1 is supplied to the nth stage ASTn so that the nth stage ASTn is disabled to provide the second voltage source VSS to the nth gate line. In other words, the dummy stage ASTn + 1 merely provides the n + 1 scan pulse Voutn + 1 so that the nth stage ASTn can output the second voltage source VSS. The n + 1th scan pulse Voutn + 1 is not supplied to the gate line. Therefore, the total number of stages including the dummy stage ASTn + 1 is always one more than the number of gate lines.

In general, the first to nth stages ASTn and the dummy stage ASTn + 1 may include a node controller for controlling charge and discharge states of the first and second nodes, and According to the state, the first scan pulse Vout1 or the second voltage source VSS is output and has an output part which supplies the same to the gate line of the liquid crystal panel.

Here, the first node and the second node are alternately charged and discharged. Specifically, when the first node is in a charged state, the second node is maintained in a discharged state, and the second node is charged. In this state, the first node maintains a discharged state.

In this case, when the first node is in a charged state, a scan pulse is output from the pull-up switching device of the output unit, and when the second node is in a charged state, a second voltage source is output from the pull-down switching device of the output unit. Of course, the scan pulse output from the pull-up switching element and the second voltage source output from the pull-down switching element are supplied to the corresponding gate line. The gate terminal of the pull-up switching element is connected to the first node, the source terminal is connected to a clock line to which a clock pulse is applied, and the drain terminal is connected to the gate line. The clock pulse is periodically supplied to the source terminal of the pull-up switching device. In this case, the pull-up switching device outputs any one of the clock pulses input for each period at a specific time point. The clock pulse output at this particular time point is a scan pulse for driving the gate line. This specific time point means a time point at which the first node is charged. That is, the pull-up switching device outputs, as a scan pulse, the clock pulse input at the specific time point (ie, the time point at which the first node is charged) among the clock pulses which are periodically input to its source terminal. Done. After the output of the scan pulse, the pull-up switching device outputs one scan pulse per frame as the first node is kept in a discharge state until the next frame starts. However, since the clock pulse is output several times during one frame, even when the pull-up switching device is turned off, that is, even when the first node is discharged, the clock pulse continues to the source terminal of the pull-up switching device. Will be entered.

In other words, the pull-up switching device is turned on only once for one frame and outputs a clock pulse input to its source terminal as a scan pulse during this turn-on period. Thereafter, the pull-up switching device is turned off until the next frame starts, so that the pull-up switching device outputs it as a scan pulse no matter how clock pulse is input to its source terminal during this turn-off period. Can not. However, as the clock pulse is periodically applied to the source terminal of the pull-up switching device, a coupling phenomenon occurs between the first node to which the gate terminal of the pull-up switching device is connected and the source terminal of the pull-up switching device. . Due to such a coupling phenomenon, the first node is continuously charged with a predetermined voltage corresponding to the clock pulse. Then, the first node may be kept in a charged state at any moment. In other words, the first node may remain charged at an unwanted timing. In this case, the first node may be maintained in the charging state more than once in one frame, whereby the pull-up switching device may be turned on more than once in one frame. As a result, a multi-output phenomenon in which one stage outputs two or more scan pulses during one frame may occur due to the coupling phenomenon as described above.

FIG. 2 is a diagram illustrating a state of charge of a first node due to a coupling phenomenon. Referring to the portion A of FIG.

As such, when one stage outputs two or more scan pulses in one frame, the quality of an image displayed on the liquid crystal panel is degraded.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems. The present invention provides a coupling phenomenon by maintaining the first node in a charged state at a timing when outputting a scan pulse, and continuously discharging the first node in other periods. It is an object of the present invention to provide a shift register and a driving method thereof capable of preventing the first node from being charged.

The shift register according to the present invention for achieving the above object, by sequentially supplying the scan pulse to sequentially activate the gate lines of the liquid crystal panel, the first voltage source in the remaining period except when the scan pulse is supplied. And a plurality of stages for deactivating the gate lines, each stage including: a node controller configured to control charge and discharge states of a first node and a second node; A pull-up switching device configured to receive first clock pulses periodically supplied and output a first clock pulse supplied at a timing at which the first node is charged as the scan pulse; A pull-down switching element configured to output an input first voltage source in response to a state of charge of the second node; A discharge unit configured to discharge the first node to the first voltage source at every first clock pulse; And a blocking unit for holding the first node in a charged state by interrupting the operation of the discharge unit in response to the scan pulse output from the pull-up switching device.

In addition, the shift register according to the present invention for achieving the above object, sequentially supplying scan pulses to sequentially activate the gate lines of the liquid crystal panel, the first voltage source in the remaining period except when the scan pulse is supplied A node controller configured to supply a plurality of stages to deactivate the gate lines, each stage controlling a charge / discharge state of a first node, a second node, and a third node; A pull-up switching device configured to receive first clock pulses periodically supplied and output a first clock pulse supplied at a timing at which the first node is charged as the scan pulse; A first pull-down switching device configured to output a first voltage source input in response to a charging state of the second node; A second pull-down switching device configured to output a first voltage source input in response to a charging state of the third node; A discharge unit configured to discharge the first node to the first voltage source at every first clock pulse; And a blocking unit which maintains the first node in a charged state by blocking an operation of the discharge unit in response to a first clock pulse corresponding to a scan pulse to be currently output among the first clock pulses. It is characterized by.

In addition, the shift register driving method according to the present invention for achieving the above object, by sequentially supplying the scan pulse to sequentially activate the gate lines of the liquid crystal panel, the rest of the period except when the scan pulse is supplied A plurality of stages are provided to deactivate the gate lines by supplying a first voltage source, wherein each stage includes a node controller for controlling charge and discharge states of the first node and the second node, and a clock pulse supplied periodically. A pull-up switching element which is input and outputs the clock pulse supplied as the scan pulse as the scan pulse, and a pull-down outputting the first voltage source input in response to the charging state of the second node; A driving method of a shift register including a switching element, the clock pulse Discharges the first node each time is applied to the pull-up switching device, and maintains the first node in a charged state when the clock pulse is outputted as a scan pulse through the pull-up switching device. .

In addition, the shift register driving method according to the present invention for achieving the above object, by sequentially supplying the scan pulse to sequentially activate the gate lines of the liquid crystal panel, the rest of the period except when the scan pulse is supplied A plurality of stages for supplying a first voltage source to deactivate the gate lines, each stage comprising: a node controller periodically controlling charge / discharge states of the first node, the second node, and the third node; A pull-up switching element that receives the first clock pulses supplied and outputs a first clock pulse supplied as a scan pulse at a timing at which the first node is charged, and in response to a charged state of the second node; A first pull-down switching element for outputting a first voltage source to be input, and a first input in response to a state of charge of the third node; A method of driving a shift register including a second pull-down switching element for outputting a voltage source, the method comprising: discharging the first node whenever the clock pulse is applied to the pull-up switching element, wherein the clock pulse is the pull-up switching element; It characterized in that the first node is maintained in a charged state at the time when the output through the scan pulse.

Hereinafter, a shift register according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a diagram illustrating a shift register according to a first embodiment of the present invention.

As shown in FIG. 3, the shift register according to the first embodiment of the present invention includes n stages BST1 to BSTn and one dummy stage BSTn + 1 connected to each other. Here, each of the stages BST1 to BSTn + 1 outputs one scan pulse Vout1 to Voutn + 1, and in this case, the scan pulse Vout1 is sequentially performed from the first stage BST1 to the dummy stage BSTn + 1. To Voutn + 1). In this case, scan pulses Vout1 to Voutn output from the stages BST1 to BSTn except for the dummy stage BSTn + 1 are sequentially supplied to gate lines of the liquid crystal panel (not shown). The gate lines are sequentially scanned.

That is, first, the first stage BST1 outputs the first scan pulse Vout1, and then the second stage BST2 outputs the second scan pulse Vout2, and then, the third stage BST3. Outputs the third scan pulse Vout3, and finally, the nth stage BSTn outputs the nth scan pulse Voutn. Meanwhile, after the nth stage BSTn outputs the nth scan pulse Voutn, the dummy stage BSTn + 1 outputs the n + 1th scan pulse Voutn + 1, wherein the dummy stage The n + 1th scan pulse Voutn + 1 output from (BSTn + 1) is not supplied to the gate line but is supplied only to the nth stage BSTn.

On the other hand, the entire stages BST1 to BSTn + 1 of the shift registers configured as described above are configured with the first voltage source VDD and the second voltage source VSS, and the first to fourth clock pulses circulating with sequential phase differences. Two clock pulses of CLK1 to CLK4) are applied. Here, the first voltage source VDD means a positive voltage source, and the second voltage source VSS means a negative voltage source.

Here, the first stage BST1 positioned on the uppermost side of the stages BST1 to BSTn + 1 may include the first voltage source VDD, the second voltage source VSS, and the first to fourth clock pulses. In addition to the two clock pulses (CLK1 to CLK4), the start pulse SP is supplied.

On the other hand, as described above, the first to fourth clock pulses (CLK1 to CLK4) are phase-delayed by one pulse width each other and output. That is, the second clock pulse CLK2 is output by being phase-delayed by one pulse width than the first clock pulse CLK1, and the third clock pulse CLK3 is one pulse than the second clock pulse CLK2. Phase delayed by a width is output, the fourth clock pulse (CLK4) is phase-delayed by one pulse width than the third clock pulse (CLK3) and output, and the first clock pulse (CLK1) is the fourth clock pulse Phase delayed by one pulse width from (CLK4) is output.

Meanwhile, the start pulse SP applied to the first stage BST1 among the stages BST1 to BSTn + 1 is output earlier than the clock pulses CLK1 to CLK4. That is, the start pulse SP is output by one clock pulse width ahead of the first clock pulse CLK1. In addition, the start pulse SP is output only once in one frame. That is, after the start pulse SP is output first in every frame, the first to fourth clock pulses CLK4 are sequentially output. In this case, the first to fourth clock pulses CLK1 to CLK4 are sequentially output, and are also output while cycling. That is, after the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output, the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output. Therefore, the first clock pulse CLK1 is output in a period corresponding to the fourth clock pulse CLK4 and the second clock pulse CLK2. The fourth clock pulse CLK4 and the start pulse SP may be output in synchronization with each other. In this case, the fourth clock pulse CLK4 is first outputted among the first to fourth clock pulses CLK1 to CLK4.

Meanwhile, the shift register according to the present invention may use two or more clock pulses. That is, the shift register according to the present invention may use only the first and second clock pulses CLK1 and CLK2 among the first to fourth clock pulses CLK4, and the first to third clock pulses CLK1 to CLK3. ) Can also be used. In addition, the shift register according to the present invention may use four or more clock pulses sequentially output.

Herein, the configuration of each stage included in the shift register according to the first embodiment of the present invention will be described in more detail. Here, since the configurations of the first to nth stages BSTn and the dummy stages BSTn + 1 are all the same, only the second stage BST2 will be representatively described.

4 is a diagram illustrating a detailed configuration of the second stage of FIG. 3.

That is, as shown in FIG. 3, the second stage BST2 includes a node controller 400a that controls charging and discharging of the first node Q and charging and discharging of the second node QB. And an output unit 400b for outputting a scan pulse or a second voltage source according to the states of the first and second nodes QB, and supplying the scan pulse or the second voltage source to the second gate line of the liquid crystal panel, and the first node Q. A discharge unit 400c for discharging the discharge unit and a blocking unit 400d for blocking the operation of the discharge unit 400c.

The first node Q and the second node QB are alternately charged and discharged. Specifically, when the first node Q is charged, the second node QB is discharged. When the second node QB is in a charged state, the first node Q is maintained in a discharged state. The charging and discharging states of the first node Q and the second node QB are controlled by a plurality of switching elements (not shown) provided in the node controller 400a.

The output unit 400b includes a pull-up transistor Tru and a pull-down transistor Trd. The pull-up transistor Tru receives a clock pulse that is periodically output through its source terminal. At this time, the pull-up transistor Tru outputs a clock pulse supplied at a timing when the first node Q is charged as a scan pulse.

The pull-down transistor Trd is supplied with a second voltage source through its drain terminal. In this case, the pull-down transistor Trd outputs a second voltage source VSS when the second node QB is in a charged state.

The discharge unit 400c discharges the first node Q whenever the clock pulse is supplied.

The blocking unit 400d receives the scan pulse output from the stage to which the blocking unit 400d belongs, and blocks the operation of the discharge unit 400c. That is, the blocking unit 400d stops the operation of the discharge unit 400c in response to the scan pulse output from the stage to which the blocking unit 400d belongs so that the discharge of the first node Q no longer proceeds. . In other words, the blocking unit 400d serves to maintain the first node Q in a charged state when one of the clock pulses corresponding to the scan pulses is output.

The remaining first stage BST1, the third to nth stages BST3 to BSTn, and the dummy stage BSTn + 1 also have the same configuration as the above-described second stage BST2.

That is, through the discharge unit 400c and the blocking unit 400d, each stage BST1 to BSTn + 1 maintains its first node Q in a charged state at a timing to output a scan pulse. Scan pulse is outputted normally. On the other hand, each of the stages BST1 to BSTn + 1 discharges the first node Q periodically according to the clock pulse in the remaining period except for the period in which the scan pulse is output. ) Is prevented from being charged to a predetermined voltage due to the coupling phenomenon. At this time, the stages BST1 to BSTn + 1 output their scan pulses and then periodically discharge their first nodes Q according to the clock pulses.

Here, the circuit configurations of the node controller 400a, the output unit 400b, and the discharge unit 400c included in the second stage BST2 will be described.

5 is a diagram illustrating a circuit configuration of a node controller, an output unit, and a discharge unit provided in the second stage.

The node controller 400a of the second stage BST2 includes the first to sixth NMOS transistors Tr6 as shown in FIG. 5.

The first NMOS transistor Tr1 charges the first node Q to the first voltage source VDD in response to the scan pulse from the previous stage. That is, the first NMOS transistor Tr1 of the second stage BST2 sets the first node Q to the first voltage source VDD in response to the first scan pulse Vout1 from the first stage BST1. Charge with. To this end, the gate terminal of the first NMOS transistor Tr1 is connected to the first stage BST1, the source terminal is connected to a power line for transmitting the first voltage source VDD, and the drain terminal is connected to the first node. It is connected to (Q).

The second NMOS transistor Tr2 discharges the second node QB to the second voltage source VSS in response to the first voltage source VDD charged in the first node Q. To this end, a gate terminal of the second NMOS transistor Tr2 is connected to the first node Q, a source terminal is connected to the second node QB, and a drain terminal of the second NMOS transistor Tr2 is connected to the second voltage source VSS. It is connected to the transmitting power line.

The third NMOS transistor Tr3 discharges the second node QB to the second voltage source VSS in response to the scan pulse from the previous stage. That is, in response to the first scan pulse Vout1 from the first stage BST1, the third NMOS transistor Tr3 of the second stage BST2 connects the second node QB to the second voltage source ( VSS). To this end, the gate terminal of the third NMOS transistor Tr3 is connected to the first stage BST1, the source terminal is connected to the second node QB, and the drain terminal transmits the second voltage source VSS. Is connected to the power supply line.

The fourth NMOS transistor Tr4 charges the second node QB to the first voltage source VDD in response to a clock pulse synchronized with the scan pulse output from the next stage. That is, the fourth NMOS transistor Tr4 of the second stage BST2 is in response to the third clock pulse CLK3 synchronized with the third scan pulse Vout3 output from the third stage BST3. The second node QB is charged with the first voltage source VDD. To this end, a gate terminal of the fourth NMOS transistor Tr4 is connected to a clock line for transmitting the third clock pulse CLK3, a source terminal is connected to a power line for transmitting a first voltage source VDD, The drain terminal is connected to the second node QB.

The fifth NMOS transistor Tr5 discharges the first node Q to the second voltage source VSS in response to the first voltage source VDD charged in the second node QB. For this purpose, the gate terminal of the fifth NMOS transistor Tr5 is connected to the second node QB, the source terminal is connected to the first node Q, and the drain terminal of the second voltage source VSS. It is connected to the power line to transmit.

The sixth NMOS transistor Tr6 discharges the first node Q to the second voltage source VSS in response to the scan pulse output from the next stage. That is, the sixth NMOS transistor Tr6 of the second stage BST2 responds to the third scan pulse Vout3 from the third stage BST3, and connects the first node Q to the second voltage source. VSS). To this end, the gate terminal of the sixth NMOS transistor Tr6 is connected to the third stage BST3, the source terminal is connected to the first node Q, and the drain terminal of the second voltage source VSS. It is connected to the transmitting power line.

The output unit 400b of the second stage BST2 includes the pull-up transistor Tru and the pull-down transistor Trd described above.

The pull-up transistor Tru is clocked ahead of the clock pulse applied to the gate terminal of the fourth NMOS transistor Tr4 by one clock pulse width in response to the first voltage source VDD charged in the first node Q. The pulses are output as scan pulses. That is, the pull-up transistor Tru of the second stage BST2 outputs the second clock pulse CLK2, which is one pulse width ahead of the third clock pulse CLK3, as the second scan pulse Vout2. The output second scan pulse Vout2 is supplied to the gate line connected to the stage to which it belongs, the stage at the previous stage, and the stage at the next stage. That is, the pull-up transistor Tru outputs the second scan pulse Vout2 as the second scan pulse Vout2 for driving the second gate line. The second scan pulse Vout2 is also supplied to the second gate line, the first stage BST1, and the third stage BST3.

Here, the second scan pulse Vout2 supplied to the first stage BST1 disables the first stage BST1, and the second scan pulse Vout2 supplied to the third stage BST3 is The third stage BST3 is enabled. To this end, the gate terminal of the pull-up transistor Tru is connected to the first node Q, the source terminal is connected to the clock line for transmitting the second clock pulse CLK2, and the drain terminal is connected to the second gate. It is commonly connected to the line, the first stage BST1, and the third stage BST3.

The pull-down transistor Trd outputs the second voltage source VSS in response to the first voltage source VDD charged in the second node QB. Then, the second voltage source VSS is supplied to the gate line connected to the stage to which it belongs, the stage in the previous stage, and the stage in the next stage. That is, the pull-down transistor Trd of the second stage BST2 supplies the second voltage source VSS to the second gate line, the first stage BST1, and the third stage BST3. The second voltage source VSS supplied to the second gate line functions as a signal for deactivating the second gate line. To this end, the gate terminal of the pull-down transistor Trd is connected to the second node QB, and the source terminal is commonly connected to the second gate line, the first stage BST1, and the third stage BST3. The drain terminal is connected to a power line for transmitting the second voltage source VSS.

The discharge unit 400c of the second stage BST2 includes the seventh through ninth NMOS transistors Tr7 through Tr9.

The seventh NMOS transistor Tr7 supplies the clock pulse to the eighth NMOS transistor Tr8 in response to the clock pulse supplied to the source terminal of the pull-up transistor Tru. That is, the seventh NMOS transistor Tr7 supplies the second clock pulse CLK2 to the eighth NMOS transistor Tr8 in response to the second clock pulse CLK2. To this end, the gate terminal of the seventh NMOS transistor Tr7 is connected to the clock line for transmitting the second clock pulse CLK2, the source terminal is connected to the clock line for transmitting the clock pulse, and the drain terminal is It is connected to the gate terminal of the eighth NMOS transistor Tr8.

The eighth NMOS transistor Tr8 discharges the first node Q to the second voltage source VSS in response to a clock pulse supplied through the seventh NMOS transistor Tr7. That is, the eighth NMOS transistor Tr8 transfers the first node Q to the second voltage source VSS in response to the second clock pulse CLK2 supplied through the seventh NMOS transistor Tr7. Discharge. To this end, the gate terminal of the eighth NMOS transistor Tr8 is connected to the drain terminal of the seventh NMOS transistor Tr7, the source terminal is connected to the first node Q, and the drain terminal is connected to the second node. It is connected to a power supply line that transmits a voltage source VSS.

The ninth NMOS transistor Tr9 turns off the eighth NMOS transistor Tr8 in response to a clock pulse synchronized with the scan pulse output from the next stage. That is, the ninth NMOS transistor Tr9 of the second stage BST2 responds to the third clock pulse CLK3 synchronized with the third scan pulse Vout3 output from the third stage BST3. The eighth NMOS transistor Tr8 is turned off by supplying a second voltage source VSS to the gate terminal of the eighth NMOS transistor Tr8. To this end, the gate terminal of the ninth NMOS transistor Tr9 is connected to the clock line for transmitting the third clock pulse CLK3, the source terminal is connected to the gate terminal of the eighth NMOS transistor Tr8, The drain terminal is connected to a power line for transmitting the second voltage source VSS.

On the other hand, the discharge unit 400c may be configured of only the eighth NMOS transistor Tr8. At this time, the eighth NMOS transistor Tr8 discharges the first node Q to the second voltage source VSS in response to a clock pulse supplied to the source terminal of the pull-up transistor Tru. That is, the eighth NMOS transistor Tr8 discharges the first node Q to the second voltage source VSS in response to the second clock pulse CLK2. To this end, the gate terminal of the eighth NMOS transistor Tr8 is connected to the clock line for transmitting the second clock pulse CLK2, the source terminal is connected to the first node Q, and the drain terminal is It is connected to the power supply line which supplies the 2nd voltage source VSS.

In addition, the discharge unit 400c may be configured of only the eighth and ninth NMOS transistors Tr8 and Tr9. In addition, the discharge unit 400c may be configured of only the seventh and eighth NMOS transistors Tr7 and Tr8.

The blocking unit 400d of the second stage BST2 includes the tenth NMOS transistor Tr10.

The tenth NMOS transistor Tr10 turns off the eighth NMOS transistor Tr8 of the discharge unit 400c in response to a scan pulse output from a stage to which the tenth NMOS transistor Tr10 belongs to operate the discharge unit 400c. Turn it off. That is, the tenth NMOS transistor Tr10 is formed at the gate terminal of the eighth NMOS transistor Tr8 of the discharge part 400c in response to the second scan pulse Vout2 output from the second stage BST2. The eighth NMOS transistor Tr8 is turned off by supplying the second voltage source VSS. To this end, the gate terminal of the tenth NMOS transistor Tr10 is the output terminal of the output unit 400b of the second stage BST2 (that is, the drain terminal of the pull-up transistor Tru), and the pull-down transistor Trd of the Terminal connected to the source terminal), the source terminal is connected to the gate terminal of the eighth NMOS transistor Tr8, and the drain terminal is connected to the power supply line for transmitting the second voltage source VSS.

On the other hand, the first stage BST1, the third to nth stages BSTn, and the dummy stage BSTn + 1 also have the above configuration.

However, since the stage does not exist in the previous stage of the first stage BST1, the first NMOS and third NMOS transistors Tr1 and Tr3 included in the first stage BST1 may have a start pulse (T1) from the timing controller. SP). That is, the first NMOS transistor Tr1 included in the first stage BST1 charges the first node Q to the first voltage source VDD in response to the start pulse SP from the timing controller. Let's do it. The third NMOS transistor Tr3 discharges the second node QB to the second voltage source VSS in response to the start pulse SP from the timing controller.

In addition, for the same reason as described above, the drain terminal of the pull-up transistor Tru provided in the first stage BST1 is commonly connected to the first gate line and the second stage BST2, and the first stage BST1 is used. The source terminal of the pull-down transistor Trd included in the N-th transistor) is commonly connected to the first gate line and the second stage BST2.

There is no stage next to the dummy stage BSTn + 1. In addition, the dummy stage BSTn + 1 does not supply scan pulses to the gate lines, and the stage (i.e., the nth stage BSTn) does not supply the n + 1 scan pulse Voutn + 1 outputted from the dummy stage BSTn + 1. ) To disable the nth stage BSTn. Therefore, the drain terminal of the pull-up transistor Tru and the source terminal of the pull-down transistor Trd included in the dummy stage BSTn + 1 are commonly connected to the nth stage BSTn.

The operation of the shift register according to the first embodiment of the present invention configured as described above will be described in detail as follows.

FIG. 6 is a diagram illustrating the first to third stages of FIG. 3. 7 is a timing diagram of various signals supplied to the stage of FIG. 6 and scan pulses output from the stage.

First, the operation during the enable period T0 will be described.

During the enable period TO, as shown in FIG. 7, only the start pulse SP output from the timing controller is kept high and the remaining start pulse SP is kept low.

The start pulse SP output from the timing controller is input to the first stage BST1. Specifically, as shown in FIG. 6, the start pulse SP includes the gate terminal of the first NMOS transistor Tr1 and the gate terminal of the third NMOS transistor Tr3 provided in the first stage BST1. Is entered. Then, the first and third NMOS transistors Tr1 and Tr3 are turned on, and the first voltage source VDD is connected to the first node Q through the turned-on first NMOS transistor Tr1. Is approved. Accordingly, the first node Q is charged, and the pull-up transistor Tru having a gate terminal connected to the charged first node Q is turned on. The second voltage source VSS is supplied to the second node QB through the turned-on third NMOS transistor Tr3. Accordingly, the second node QB is discharged by the second voltage source VSS, and the pull-down transistor Trd having a gate terminal connected to the second node QB is turned off.

As such, during the enable period T0, as illustrated in FIG. 7, the first node Q of the first stage BST1 is charged to the first voltage source VDD and the second node ( The first stage BST1 is enabled by discharging QB to the second voltage source VSS.

Next, the operation during the first period T1 will be described.

During the first period T1, as shown in FIG. 7, only the first clock pulse CLK1 remains high and the remaining clock pulses remain low. Accordingly, the first and third NMOS transistors Tr1 and Tr3 of the first stage BST1 are turned off in response to the low state start pulse SP, thereby turning off the first stage BST1. The first node Q is kept in a floating state.

Meanwhile, as the first node Q of the first stage BST1 is continuously maintained as the first voltage source VDD applied during the enable period T0, the pull-up transistor of the first stage BST1 Tru) remains turned on. At this time, as the first clock pulse CLK1 is applied to the source terminal of the turned-on pull-up transistor Tru, the first node Q of the first stage BST1 as shown in FIG. 7. The first voltage source VDD charged to is amplified by bootstrapping. Therefore, the first clock pulse CLK1 applied to the source terminal of the pull-up transistor Tru of the first stage BST1 is stably output through the drain terminal of the pull-up transistor Tru. In this case, as illustrated in FIG. 7, the output first clock pulse CLK1 is applied to a first gate line to serve as a first scan pulse Vout1 driving the first gate line. The first scan pulse Vout1 is supplied to the blocking unit 400d of the first stage BST1. In detail, the first scan pulse Vout1 is input to the gate terminal of the tenth NMOS transistor Tr10 provided in the blocking unit 400d of the first stage BST1, and thus, the first scan pulse Vout1 is input to the gate terminal of the blocking unit 400d. 10 Turn on the NMOS transistor Tr10. Then, the second voltage source VSS is supplied to the discharge unit 400c provided in the first stage BST1 through the turned-on tenth NMOS transistor Tr10. In detail, the second voltage source VSS is applied to the gate terminal of the eighth NMOS transistor Tr8 provided in the discharge unit 400c of the first stage BST1.

Meanwhile, in the first period T1, the first clock pulse CLK1 is also supplied to the discharge unit 400c of the first stage BST1. Specifically, the first clock pulse CLK1 is supplied together to the gate terminal and the source terminal of the seventh NMOS transistor Tr7 provided in the discharge unit 400c of the first stage BST1. Therefore, the first clock pulse CLK1 is supplied to the gate terminal of the eighth NMOS transistor Tr8 through the turned-on seventh NMOS transistor Tr7.

As described above, the first clock pulse CLK1 and the second voltage source are provided to gate terminals of the eighth NMOS transistor Tr8 included in the discharge unit 400c of the first stage BST1 during the first period T1. (VSS) is applied at the same time. At this time, the channel width of the tenth NMOS transistor Tr10, which supplies the second voltage source VSS to the gate terminal of the eighth NMOS transistor Tr8, has a first clock at the gate terminal of the eighth NMOS transistor Tr8. Since the channel width of the seventh NMOS transistor Tr7 that supplies the pulse CLK1 is larger than that of the seventh NMOS transistor Tr7, the second voltage source VSS is applied to the gate terminal of the eighth NMOS transistor Tr8. Therefore, the eighth NMOS transistor Tr8 of the first stage BST1 is turned off. That is, the discharge part 400c of the first stage BST1 does not drive. Therefore, the first node Q of the first stage BST1 remains charged with the first voltage source VDD supplied during the enable period. Accordingly, the pull-up transistor Tru connected to the first node Q of the first stage BST1 maintains a turn-on state, whereby the first supplied to the pull-up transistor Tru in the first period. The clock pulse CLK1 is normally supplied to the first gate line as the first scan pulse Vout1.

In other words, the blocking unit 400d of the first stage BST1 is provided at the timing when the first stage BST1 outputs the first clock pulse CLK1 as the first scan pulse Vout1. ) Operates and the discharge unit 400c does not operate. Accordingly, the first node Q of the first stage BST1 maintains a charging state, and thus, the first stage BST1 normally sets the first clock pulse CLK1 as the first scan pulse Vout1. Output

On the other hand, the first scan pulse Vout1 output from the first stage BST1 in the first period T1 is also input to the second stage BST2. In detail, as illustrated in FIG. 6, the first scan pulse Vout1 may include the gate terminal of the first NMOS transistor Tr1 and the third NMOS transistor Tr3 of the second stage BST2. It is input to the gate terminal. Here, the first scan pulse Vout1 supplied to the second stage BST2 plays the same role as the start pulse SP supplied to the first stage BST1 and the first scan pulse Vout1. In response to the second stage BST2 is enabled. That is, the first node Q of the second stage BST2 is charged to the first voltage source VDD by the first scan pulse Vout1, and the second node QB is charged to the second voltage source VSS. Discharged. In other words, the first scan pulse Vout1 turns on the first NMOS transistor Tr1 of the second stage BST2, thereby providing a first node to the first node Q of the second stage BST2. The voltage source VDD is supplied. In addition, the first scan pulse Vout1 turns on the third NMOS transistor Tr3 of the second stage BST2, thereby providing a second voltage source to the second node QB of the second stage BST2. Ensure that VSS is supplied.

In summary, the first scan pulse Vout1 output from the first stage BST1 during the first period T1 drives the first gate line, and as shown in FIG. 7, the second stage. The second stage BST2 is enabled by charging the first node Q of the BST2 and discharging the second node QB.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in FIG. 7, only the second clock pulse CLK2 remains high and the remaining clock pulses remain low.

Accordingly, as the first scan pulse Vout1 from the first stage BST1 that has been applied in the first period T1 changes to a low state in the second period, the second stage that is applied through the gate terminal. The first and third NMOS transistors Tr1 and Tr3 of BST2 are turned off, so that the first node Q of the second stage BST2 remains in a floating state. Meanwhile, as the first node Q of the second stage BST2 is continuously maintained as the first voltage source VDD applied during the first period T1, the pull-up provided in the second stage BST2 is provided. The transistor Tru remains turned on. In this case, as the second clock pulse CLK2 is applied to the source terminal of the pull-up transistor Tru of the second stage BST2, the first node Q of the second stage BST2 is charged. One voltage source VDD is amplified by bootstrapping. Therefore, the second clock pulse CLK2 applied to the source terminal of the pull-up transistor Tru is stably output through the drain terminal of the pull-up transistor Tru. In this case, as shown in FIG. 7, the second clock pulse CLK2 output from the second stage BST2 is applied to a second gate line to drive the second gate pulse Vout2. Acts as).

On the other hand, in the second period T2, the second stage BST2 uses the second scan pulse Vout2 output from itself, similarly to the above-described first stage BST1, and has its own blocking unit 400d. ) Is operated and the discharge unit 400c is turned off. Therefore, in the second period T2, the first node Q of the second stage BST2 is maintained in a charged state, thereby stably supplying the second scan pulse Vout2 to the second gate line. .

The second scan pulse Vout2 output from the second stage BST2 is also input to the first stage BST1. Specifically, as shown in FIG. 6, the second scan pulse Vout2 is input to the gate terminal of the sixth NMOS transistor Tr6 provided in the first stage BST1. Here, as the sixth NMOS transistor Tr6 of the first stage BST1 is turned on by the second scan pulse Vout2, the sixth NMOS transistor with the second voltage source VSS turned on. It is supplied to the first node Q of the first stage BST1 through Tr6. Therefore, as shown in FIG. 7, the first node Q of the first stage BST1 is discharged by the second voltage source VSS. As a result, the pull-up transistor Tru having the gate terminal connected to the first node Q of the first stage BST1 is turned off.

On the other hand, the second clock pulse CLK2 output in the second period T2 is also applied to the gate terminal of the fourth NMOS transistor Tr4 of the first stage BST1. The fourth NMOS transistor Tr4 of BST1 is turned on. At this time, the first voltage source VDD is supplied to the second node QB of the first stage BST1 through the turned-on fourth NMOS transistor Tr4. Therefore, as shown in FIG. 7, the second node QB of the first stage BST1 is charged by the first voltage source VDD. Then, the pull-down transistor Trd connected to the second node QB of the second stage BST2 is turned on. In this case, a second voltage source VSS is supplied to the first gate line through the turned-on pull-down transistor Trd. Thus, the second voltage source VSS serves as a signal for deactivating the gate line.

As described above, the second scan pulse Vout2 output from the second stage BST2 receives the first node Q of the first stage BST1 together with the second clock pulse CLK2 synchronized with the second scan pulse Vout2. The first stage BST1 is enabled by discharging and charging the second node QB.

In addition, the second clock pulse CLK2 output in the second period T2 is also supplied to the discharge unit 400c provided in the first stage BST1. Specifically, the second clock pulse CLK2 is input to the gate terminal of the ninth NMOS transistor Tr9 provided in the discharge unit 400c of the first stage BST1. Therefore, the ninth NMOS transistor Tr9 of the first stage BST1 is turned on. Accordingly, the second voltage source VSS is provided to the gate terminal of the eighth NMOS transistor Tr8 provided in the discharge unit 400c of the first stage BST1 through the turned-on ninth NMOS transistor Tr9. Is approved. The ninth NMOS transistor Tr9 included in the discharge unit 400c is a switching device for preventing deterioration of the eighth NMOS transistor Tr8. That is, as the first clock pulse CLK1 is periodically output, the gate terminal of the eighth NMOS transistor Tr8 included in the discharge unit 400c may have a first clock pulse CLK1 rather than a second voltage source VSS. Is applied for more time. Accordingly, the threshold voltage of the eighth NMOS transistor Tr8 may change in characteristics. To prevent this, the ninth NMOS transistor Tr9 receives the clock pulse synchronized with the next stage when the next stage outputs the scan pulse, and the eighth NMOS transistor Tr8 provided in the discharge unit 400c. The second voltage source VSS is supplied to the gate terminal of the. In this way, the second voltage source VSS can be supplied to the gate terminal of the eighth NMOS transistor Tr8 for a longer time.

On the other hand, during this second period T2, the second scan pulse Vout2 output from the second stage BST2 is also input to the third stage BST3. Specifically, as shown in FIG. 6, the second scan pulse Vout2 is input to the gate terminals of the first and third NMOS transistors Tr1 and Tr3 provided in the third stage BST3. Thus, in the manner as described above, the first node Q of the third stage BST3 is charged and the second node QB is discharged. That is, the third stage BST3 is enabled by the second scan pulse Vout2.

In summary, during the second period T2, the second scan pulse Vout2 is output from the second stage BST2. This second scan pulse Vout2 drives the second gate line. The second scan pulse Vout2 disables the first stage BST1 together with the second clock pulse CLK2 synchronized with the second scan pulse Vout2. In addition, the second scan pulse Vout2 is supplied to the discharge part 400c of the first stage BST1 to prevent deterioration of the eighth NMOS transistor Tr8. In addition, the second scan pulse Vout2 enables the third stage BST3.

In this manner, during the third period T3, the third scan pulse Vout3 is output from the third stage BST3. This third scan pulse Vout3 drives the third gate line. In addition, the third scan pulse Vout3 disables the second stage BST2 together with the third clock pulse CLK3 synchronized with the third scan pulse Vout3. In addition, the third scan pulse Vout3 is supplied to the discharge part 400c of the second stage BST2 to prevent deterioration of the eighth NMOS transistor Tr8. In addition, the third scan pulse Vout3 enables the fourth stage BST4.

During the fourth period T4, the fourth scan pulse Vout4 is output from the fourth stage BST4. This fourth scan pulse Vout4 drives the fourth gate line. The fourth scan pulse Vout4 disables the third stage BST3 together with the fourth clock pulse CLK4 synchronized with the fourth scan pulse Vout4. In addition, the fourth scan pulse Vout4 is supplied to the discharge part 400c of the third stage BST3 to prevent deterioration of the eighth NMOS transistor Tr8. In addition, the fourth scan pulse Vout4 enables the fifth stage.

Next, the operation during the fifth period T5 will be described.

In this fifth period T5, a fifth scan pulse is output from the fifth stage. This fifth scan pulse drives the fifth gate line. Meanwhile, the first clock pulse CLK1 is output again in the fifth period T5. That is, in the fifth period T5, the first clock pulse CLK1 remains high again. Therefore, in the fifth period T5, the fifth stage outputs the first clock pulse CLK1 as a fifth scan pulse. At this time, the first clock pulse CLK1 output in the fifth period T5 is supplied not only to the fifth stage but also to the first stage BST1. In detail, the first clock pulse CLK1 is supplied to the source terminal of the pull-up transistor Tru provided in the fifth stage and the source terminal of the pull-up transistor Tru provided in the first stage BST1. do. In this fifth period T5, the first node Q of the first stage BST1 is in a discharge state, and the first node Q of the fifth stage is in a charged state, so that only the fifth stage is The first clock pulse CLK1 may be output as the fifth scan pulse.

However, as the first clock pulse CLK1 is applied to the source terminal of the pull-up transistor Tru of the first stage BST1, the first node Q and the first node of the first stage BST1 are applied. Coupling occurs between the source terminals of the pull-up transistor Tru to which the clock pulse CLK1 is applied. By this coupling phenomenon, the first node Q of the first stage BST1 may be charged to a predetermined voltage. The first node Q of the first stage BST1 is charged to a larger voltage as the first clock pulse CLK1 is continuously applied, thereby charging the first node QST of the first stage BST1. Q may be charged to a voltage that is large enough to turn on the pull-up transistor Tru of the first stage BST1. Then, a problem occurs in which scan pulses are simultaneously output from two stages, that is, the first and fifth stages, in the fifth period T5. Here, the scan pulse output from the fifth stage in the fifth period is a correct output. However, the scan pulse output from the first stage BST1 is an incorrect output. As a result, the first stage BST1 may generate two or more outputs during one frame. That is, the first stage BST1 may generate an output in the first period T1 and the fifth period T5. Of course, not only the first stage BST1 but also the remaining stages may generate two or more multi-outputs as described above.

In order to prevent the multiple output due to such a coupling phenomenon, the discharge unit 400c of each stage BST1 to BSTn + 1 operates in a period other than its own output. More specifically, this is as follows.

As described above, the first clock pulse CLK1 is output in the fifth period T5. The first clock pulse CLK1 output in the fifth period T5 has a time difference corresponding to four clock pulse widths from the first clock pulse CLK1 output in the first period T1. The first clock pulse CLK1 output in the fifth period T5 is supplied to the discharge unit 400c of the first stage BST1 to operate the discharge unit 400c. That is, the first clock pulse CLK1 is applied to the gate terminal of the seventh NMOS transistor Tr7 included in the first stage BST1 to turn on the seventh NMOS transistor Tr7. Then, the first clock pulse CLK1 is applied to the gate terminal of the eighth NMOS transistor Tr8 through the turned-on seventh NMOS transistor Tr7. Thus, the eighth NMOS transistor Tr8 is turned on. Then, the second voltage source VSS is supplied to the first node Q of the first stage BST1 through the turned-on eighth NMOS transistor Tr8. Therefore, the first node Q of the first stage BST1 is discharged. In this case, since the first stage BST1 does not generate a scan pulse, the blocking unit 400d provided in the first stage BST1 does not operate. Consequently, even if a predetermined voltage is charged to the first node Q of the first stage BST1 in the fifth period T5 by the coupling phenomenon, the voltage is provided to the first stage BST1. By the discharge unit 400c.

As such, when the first clock pulse CLK1 corresponding to the output timing of the first scan pulse Vout1 is applied to the first stage BST1, the first stage BST1 again outputs the first scan pulse Vout1 output from the first stage BST1. It receives the feedback and keeps its first node Q in a charged state. On the other hand, when the first clock pulse CLK1 is applied to the first clock pulse CLK1 applied to a period other than the output timing of the first scan pulse Vout1, the first stage BST1 is applied. Each time, the first node Q is discharged in response. That is, each of the stages BST1 to BSTn + 1 receives feedback of the scan pulse output from the stage, thereby confirming whether the scan pulse is output. Each stage BST1 to BSTn + 1 operates the interrupter 400d when there is an output, and operates the discharge unit 400c when there is no output.

As a result, the first stage BST1 outputs the first clock pulse CLK1 input in the first period T1 in one frame as the first scan pulse Vout1, and to the first scan pulse Vout1. In response, keeps its first node Q in a charged state and is input to the fifth, ninth, ....., and kth periods T5, T9, ..., Tk. In response to the pulse CLK1, the first node Q is brought into a discharge state.

In this manner, the second stage BST2 outputs the second clock pulse CLK2 input in the second period T2 in one frame as the second scan pulse Vout2, and the second scan pulse Vout2. ) Keeps its first node Q charged. The second stage BST2 includes the sixth, tenth, ..., and k + 1th periods T6, T10, ..., Tk + in one frame except the second period T2. In response to the second clock pulse CLK2 input to 1), the first node Q is brought into a discharge state.

In addition, the third stage BST3 outputs the third clock pulse CLK3 input in the third period T3 in one frame as the third scan pulse Vout3 and responds to the third scan pulse Vout3. To keep its first node Q in a charged state. The third stage BST3 includes the seventh, eleventh, ..., and k + 2th periods T7, T11, ..., Tk + in one frame except the third period T3. In response to the third clock pulse CLK3 input to 2), the first node Q is brought into a discharge state.

Further, the fourth stage BST4 outputs the fourth clock pulse CLK4 input in the fourth period T4 in one frame as the fourth scan pulse Vout4, and responds to the fourth scan pulse Vout4. To keep its first node Q in a charged state. The fourth stage BST4 includes the eighth, twelfth, ..., and k + 3th periods T8, T12, ..., Tk + in one frame except the fourth period T4. In response to the fourth clock pulse input to 3), the first node Q is brought into a discharge state.

In addition, the fifth stage outputs the first clock pulse CLK1 input in the fifth period T5 in one frame as a fifth scan pulse, and in response to the fifth scan pulse, its first node Q. Keep it charged. The fifth stage is a first input unit for the ninth, thirteenth, ..., and kth periods T9, T13, ..., Tk in one frame except for the fifth period T5. In response to the clock pulse CLK1, the first node Q is brought into a discharge state.

The remaining sixth to nth stages BST6 to BSTn and the dummy stage BSTn + 1 also operate in the same manner as described above.

As a result, each stage BST1 to BSTn outputs a clock pulse input as a scan pulse at a timing at which the scan pulse is to be output. At this time, the scan pulse is fed back to maintain its first node Q in a charged state. . Each stage BST1 to BSTn puts its first node Q into a discharge state in response to a clock pulse input after outputting the scan pulse.

In the shift register according to the first embodiment of the present invention configured as described above, each stage may have the following circuit configuration. Here, only the second stage BST2 will be described as an example.

FIG. 8 is a diagram illustrating another circuit configuration of the second stage of FIG. 2.

That is, as shown in FIG. 8, the node controller 400a of the second stage BST2 includes first and second NMOS transistors Tr1 and Tr2.

The first NMOS transistor Tr1 charges the first node Q to the first voltage source VDD in response to the scan pulse from the previous stage. That is, the first NMOS transistor Tr1 of the second stage BST2 sets the first node Q to the first voltage source VDD in response to the first scan pulse Vout1 from the first stage BST1. Charge with. To this end, the gate terminal of the first NMOS transistor Tr1 is connected to the first stage BST1, the source terminal is connected to a power line for transmitting the first voltage source VDD, and the drain terminal is connected to the first node. It is connected to (Q).

The second NMOS transistor Tr2 discharges the first node Q to the second voltage source VSS in response to the scan pulse output from the next stage. That is, in response to the third scan pulse Vout3 from the third stage BST3, the second NMOS transistor Tr2 of the second stage BST2 connects the first node Q to the second voltage source ( VSS). To this end, the gate terminal of the sixth NMOS transistor Tr6 is connected to the third stage BST3, the source terminal is connected to the first node Q, and the drain terminal of the second voltage source VSS. It is connected to the transmitting power line.

The output unit 400b of the second stage BST2 includes the pull-up transistor Tru and the pull-down transistor Trd described above.

The pull-up transistor Tru is delayed by one clock pulse width than the scan pulse applied to the gate terminal of the first NMOS transistor Tr1 in response to the first voltage source VDD charged in the first node Q. The pulses are output as scan pulses. That is, the pull-up transistor Tru of the second stage BST2 outputs the second clock pulse CLK2 delayed by one pulse width from the first scan pulse Vout1 as the second scan pulse Vout2. The output second scan pulse Vout2 is supplied to the gate line connected to the stage to which it belongs, the stage at the previous stage, and the stage at the next stage. That is, the pull-up transistor Tru outputs the second clock pulse CLK2 as a second scan pulse Vout2 for driving a second gate line. The second scan pulse Vout2 is supplied to the second gate line, the first stage BST1, and the third stage BST3. To this end, the gate terminal of the pull-up transistor Tru is connected to the first node Q, the source terminal is connected to the clock line for transmitting the second clock pulse CLK2, and the drain terminal is connected to the second gate. It is commonly connected to the line, the first stage BST1, and the third stage BST3. Here, the second scan pulse Vout2 supplied to the first stage BST1 disables the first stage BST1, and the second scan pulse Vout2 supplied to the third stage BST3 is The third stage BST3 is enabled.

The pull-down transistor Trd outputs the second voltage source VSS in response to the clock pulse charged in the second node QB. Then, the second voltage source VSS is supplied to the gate line connected to the stage to which it belongs, the stage in the previous stage, and the stage in the next stage. That is, the pull-down transistor Trd of the second stage BST2 supplies the second voltage source VSS to the second gate line, the first stage BST1, and the third stage BST3. The second voltage source VSS supplied to the second gate line functions as a signal for deactivating the second gate line. To this end, the gate terminal of the pull-down transistor Trd is connected to the second node QB, and the source terminal is commonly connected to the second gate line, the first stage BST1, and the third stage BST3. The drain terminal is connected to a power line for transmitting the second voltage source VSS.

The discharge unit 400c of the second stage BST2 includes third to fifth NMOS transistors Tr3 to Tr5.

The third NMOS transistor Tr3 supplies the clock pulse to the fourth NMOS transistor Tr4 and the second node in response to the clock pulse supplied to the source terminal of the pull-up transistor Tru. In other words, the third NMOS transistor Tr3 supplies the second clock pulse CLK2 to the gate electrode of the fourth NMOS transistor Tr4 in response to the second clock pulse CLK2. Turn on Tr4). The third NMOS transistor Tr3 charges the second node QB by supplying the second clock pulse CLK2 to the second node QB. To this end, the gate terminal of the third NMOS transistor Tr3 is connected to the clock line for transmitting the second clock pulse CLK2, and the source terminal is connected to the clock line for transmitting the second clock pulse CLK2. The drain terminal is connected to the gate terminal of the fourth NMOS transistor Tr4 and the second node QB.

The fourth NMOS transistor Tr4 discharges the first node Q to the second voltage source VSS in response to a clock pulse supplied through the third NMOS transistor Tr3. That is, the fourth NMOS transistor Tr4 transfers the first node Q to the second voltage source VSS in response to the second clock pulse CLK2 supplied through the third NMOS transistor Tr3. Discharge. To this end, the gate terminal of the fourth NMOS transistor Tr4 is connected to the drain terminal of the third NMOS transistor Tr3, the source terminal is connected to the first node Q, and the drain terminal is connected to the second node. It is connected to a power supply line that transmits a voltage source VSS.

The fifth NMOS transistor Tr5 turns off the fourth NMOS transistor Tr4 in response to a clock pulse synchronized with the scan pulse output from the next stage. That is, the fifth NMOS transistor Tr5 of the second stage BST2 responds to the third clock pulse CLK3 synchronized with the third scan pulse Vout3 from the third stage BST3. The fourth NMOS transistor Tr4 is turned off by supplying the second voltage source VSS to the gate terminal of the NMOS transistor Tr4. For this purpose, the gate terminal of the fifth NMOS transistor Tr5 is connected to the third stage BST3, the source terminal is connected to the gate terminal of the fourth NMOS transistor Tr4, and the drain terminal of the second voltage source. It is connected to the power line which transmits (VSS).

On the other hand, the discharge unit 400c may be configured only of the fourth NMOS transistor Tr4. At this time, the fourth NMOS transistor Tr4 discharges the first node Q to the second voltage source VSS in response to a clock pulse supplied to the source terminal of the pull-up transistor Tru. That is, the fourth NMOS transistor Tr8 discharges the first node Q to the second voltage source VSS in response to the second clock pulse CLK2. For this purpose, the gate terminal of the fourth NMOS transistor Tr4 is connected to the clock line for transmitting the second clock pulse CLK2, the source terminal is connected to the first node Q, and the drain terminal is It is connected to the power supply line which supplies the 2nd voltage source VSS.

In addition, the discharge part 400c may be configured only with the fourth and fifth NMOS transistors Tr4 and Tr5. In addition, the discharge part 400c may be constituted only with the third and fourth NMOS transistors Tr3 and Tr4.

The blocking unit 400d of the second stage BST2 includes the sixth NMOS transistor Tr6.

The sixth NMOS transistor Tr6 turns off the fourth NMOS transistor Tr4 of the discharge unit 400c in response to a scan pulse output from a stage to which the sixth NMOS transistor Tr6 operates to operate the discharge unit 400c. Turn it off. That is, the sixth NMOS transistor Tr6 is provided to the gate terminal of the fourth NMOS transistor Tr4 of the discharge part 400c in response to the second scan pulse Vout2 output from the second stage BST2. The fourth NMOS transistor Tr4 is turned off by supplying a second voltage source VSS. To this end, the gate terminal of the sixth NMOS transistor Tr6 is an output terminal of the output unit 400b of the second stage BST2 (that is, a drain terminal of the pull-up transistor Tru), and the pull-down transistor Trd Terminal connected to the source terminal), the source terminal is connected to the gate terminal of the fourth NMOS transistor Tr4, and the drain terminal is connected to the power supply line for transmitting the second voltage source VSS.

In the circuit configured as described above, the third to sixth NMOS transistors Tr3 to Tr6 are the same as the seventh to tenth NMOS transistors Tr7 to Tr10 described above with reference to FIG. 5.

Hereinafter, the shift register according to the second embodiment of the present invention will be described in detail.

9 is a diagram illustrating a shift register according to a second embodiment of the present invention.

As illustrated in FIG. 9, the shift register according to the second embodiment of the present invention includes n stages CST1 to CSTn and one dummy stage CSTn + 1 connected to each other. Here, each of the stages CST1 to CSTn + 1 outputs one scan pulse Vout1 to Voutn + 1, and in this case, the scan pulse Vout1 is sequentially performed from the first stage CST1 to the dummy stage CSTn + 1. To Voutn + 1). In this case, scan pulses Vout1 to Voutn output from the stages CST1 to CSTn except the dummy stage CSTn + 1 are sequentially supplied to gate lines of the liquid crystal panel (not shown). The gate lines are sequentially scanned.

That is, first, the first stage CST1 outputs the first scan pulse Vout1, and then the second stage CST2 outputs the second scan pulse Vout2, and then, the third stage CST3. ) Outputs the third scan pulse Vout3, ..., and finally, the nth stage CSTn outputs the nth scan pulse Voutn. Meanwhile, after the nth stage CSTn outputs the nth scan pulse Voutn, the dummy stage CSTn + 1 outputs the n + 1th scan pulse Voutn + 1, wherein the dummy stage The n + 1th scan pulse Voutn + 1 output from (CSTn + 1) is not supplied to the gate line, but only to the nth stage CSTn.

On the other hand, the entire stages CST1 to CSTn of the shift registers configured as described above are the first to fourth voltage sources VDD, VSS, VDD3, and VDD4 and the first to fourth clock pulses CLK1 to cyclic with sequential phase differences. One clock pulse of CLK4) is applied. Here, the first voltage source VDD refers to a positive DC voltage source, and the second voltage source VSS refers to a negative voltage source. The third voltage source VDD3 and the fourth voltage source VDD4 are AC voltage sources having polarities inverted for each frame. In this case, the third voltage source VDD3 has an inverted phase with respect to the fourth voltage source VDD4. That is, the third voltage source VDD3 and the fourth voltage source VDD4 have different polarities within the same frame.

Here, the first stage CST1 positioned at the uppermost side of the stages CST1 to CSTn may include the first to fourth voltage sources VDD, VSS, VDD3, and VDD4, and the first to fourth clock pulses. In addition to the two clock pulses (CLK1 to CLK4), the start pulse SP is supplied.

On the other hand, as described above, the first to fourth clock pulses (CLK1 to CLK4) are phase-delayed by one pulse width each other and output. That is, the second clock pulse CLK2 is output by being phase-delayed by one pulse width than the first clock pulse CLK1, and the third clock pulse CLK3 is one pulse than the second clock pulse CLK2. Phase delayed by a width is output, the fourth clock pulse (CLK4) is phase-delayed by one pulse width than the third clock pulse (CLK3) and output, and the first clock pulse (CLK1) is the fourth clock pulse Phase delayed by one pulse width from (CLK4) is output.

Meanwhile, the start pulse SP applied to the first stage CST1 among the stages CST1 to CSTn + 1 is output before the clock pulses CLK1 to CLK4. That is, the start pulse SP is output by one clock pulse width ahead of the first clock pulse CLK1. In addition, the start pulse SP is output only once in one frame. That is, after the start pulse SP is output first in every frame, the first to fourth clock pulses CLK1 to CLK4 are sequentially output. At this time, the first to fourth clock pulses CLK1 to CLK4 are sequentially output, and are also output while circulating. That is, after the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output, the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output. Therefore, the first clock pulse CLK1 is output in a period corresponding to the fourth clock pulse CLK4 and the second clock pulse CLK2. The fourth clock pulse CLK4 and the start pulse SP may be output in synchronization with each other. In this case, the fourth clock pulse CLK4 is first outputted among the first to fourth clock pulses CLK1 to CLK4.

Meanwhile, the shift register according to the present invention may use two or more clock pulses. That is, the shift register according to the present invention may use only the first and second clock pulses CLK1 and CLK2 among the first to fourth clock pulses CLK1 to CLK4, and the first to third clock pulses CLK1 to CLK4. You can also use only CLK3). In addition, the shift register according to the present invention may use four or more clock pulses sequentially output.

Herein, the configuration of each stage included in the shift register according to the second embodiment of the present invention will be described in more detail. Here, since the configurations of the second to nth stages CSTn are all the same, only the second stage CST2 will be representatively described.

FIG. 10 is a detailed configuration diagram of the second stage of FIG. 9.

As illustrated in FIG. 10, the second stage CST2 includes a node controller 900a for controlling charging and discharging of the first, second, and third nodes Q, QB1, and QB2, and the first stage. And are turned on according to the charge / discharge states of the second and third nodes Q, QB1, and QB2 to selectively output a scan pulse or a second voltage source VSS to the second gate line of the liquid crystal panel. An output unit 900b to supply, a discharge unit 900c for discharging the first node Q, and a blocking unit 900d for interrupting the operation of the discharge unit 900c.

Here, the first, second, and third nodes Q, QB1, and QB2 are selectively charged and discharged. Specifically, when the first node Q is in a charged state, the second node QB1 is charged. And both the third node QB2 maintains a discharge state, and when the first node Q is in a discharge state, any one of the second node QB1 and the third node QB2 maintains a discharge state. . That is, in the odd-numbered frame, when the first node Q is in the discharged state, the second node QB1 is charged, the third node QB2 is discharged, and in the even-numbered frame, the first node is discharged. When Q is in the discharged state, the second node QB1 is discharged and the third node QB2 is charged. As described above, when the first node Q is in the discharged state, the voltage sources VDD3 and VDD4 having different polarities are applied (charged and discharged) to the second node QB1 and the third node QB2 for each frame. The reason is to prevent deterioration of the switching device having the gate terminal connected to the second node QB1 and the third node QB2. The charge and discharge states of the first, second, and third nodes Q, QB1, and QB2 are controlled by a plurality of switching elements (not shown) provided in the node controller 900a.

The output unit 900b includes a pull-up transistor Tru and first and second pull-down transistors Trd1 and Trd2. The pull-up transistor Tru receives a clock pulse that is periodically output through its source terminal. At this time, the pull-up transistor Tru outputs a clock pulse supplied at a timing when the first node Q is charged as a scan pulse.

The first and second pull-down transistors Trd1 and Trd2 receive the second voltage source VSS through their drain terminals. In this case, the first and second pull-down transistors Trd1 and Trd2 output a second voltage source VSS when the second and third nodes QB1 and QB2 are in a charged state. Meanwhile, since the second and third nodes QB1 and QB2 are alternately charged with each frame, the first pulldown transistor Trd and the second pulldown transistor Trd are alternately turned every frame. Is on. Therefore, the first pull-down transistor Trd1 and the second pull-down transistor Trd2 alternately supply the second voltage source VSS every frame.

The discharge unit 900c discharges the first node Q whenever the clock pulse is supplied.

The blocking unit 900d receives the scan pulse output from the stage to which the blocking unit 900d belongs, and blocks the operation of the discharge unit 900c. That is, the blocking unit 900d stops the operation of the discharge unit 900c in response to the scan pulse output from the stage to which the blocking unit 900d belongs so that the discharge of the first node Q no longer proceeds. . In other words, the blocking unit 900d plays a role of maintaining the first node Q in a charged state at a time point of being output to any one of the clock pulses corresponding to the scan pulses.

Although not illustrated, the first stage CST1, the third to nth stages CST3 to CSTn, and the dummy stage CSTn + 1 also have the same configuration as the second stage CST2 shown in FIG. 9. Have

That is, through the discharge unit 900c and the blocking unit 900d, each stage CST1 to CSTn + 1 maintains its first node Q in a charged state at a timing to output a scan pulse. Scan pulse is outputted normally. On the other hand, in each of the stages, the first node Q is discharged periodically according to the clock pulse in the remaining period except for the period in which the scan pulse is output. Prevents charging to a predetermined voltage. At this time, each stage CST1 to CSTn + 1 outputs its own scan pulse, and then periodically discharges its first node Q according to the clock pulse.

Here, the circuit configurations of the node control unit 900a, the output unit 900b, and the discharge unit 900c of the second stage CST2 will be described in detail.

FIG. 11 is a diagram illustrating a circuit configuration of the second stage illustrated in FIG. 10.

In other words, the node controller 900a of the second stage CST2 includes first to twelfth NMOS transistors Tr1 to Tr12.

The first NMOS transistor Tr1 charges the first node Q to the first voltage source VDD in response to the scan pulse from the previous stage. That is, in response to the first scan pulse Vout1 from the first stage CST1, the first NMOS transistor Tr1 of the second stage CST2 may turn the first node Q to the first voltage source VDD. Charge with. To this end, the gate terminal of the first NMOS transistor Tr1 is connected to the first stage CST1, the source terminal is connected to a power line for transmitting the first voltage source VDD, and the drain terminal is connected to the first node. It is connected to (Q).

The second NMOS transistor Tr2 discharges the second node QB1 to the second voltage source VSS in response to the scan pulse from the previous stage. That is, the second NMOS transistor Tr2 of the second stage CST2 sets the second node QB1 to the second voltage source VSS in response to the first scan pulse Vout1 from the first stage CST1. To discharge. To this end, the gate terminal of the second NMOS transistor Tr2 is connected to the first stage CST1, the source terminal is connected to the second node QB1, and the drain terminal transmits the second voltage source VSS. Is connected to the power supply line.

The third NMOS transistor Tr3 discharges the third node QB2 to the second voltage source VSS in response to the scan pulse from the previous stage. That is, in response to the first scan pulse Vout1 from the first stage CST1, the third NMOS transistor Tr3 of the second stage BST2 connects the third node QB2 to a second voltage source ( VSS). To this end, the gate terminal of the third NMOS transistor Tr3 is connected to the first stage CST1, the source terminal is connected to the second node QB1, and the drain terminal transmits the second voltage source VSS. It is connected to the power line.

The fourth NMOS transistor Tr4 is turned on or turned off in response to the third voltage source VDD3, and charges the second node QB1 to the third voltage source VDD3 at turn-on. For this purpose, the gate terminal of the fourth NMOS transistor Tr4 is connected to a power line for transmitting the third voltage source VDD3, the source terminal is connected to a power line for transmitting the third voltage source VDD3, and the drain The terminal is connected to the second node QB1. The third voltage source VDD3 is an AC voltage having alternating positive and negative polarities every frame. That is, the third voltage source VDD3 has positive polarity in odd frames and negative polarity in even frames.

The fifth NMOS transistor Tr5 discharges the third node QB2 to the second voltage source VSS in response to the third voltage source VDD3. To this end, the gate terminal of the fifth NMOS transistor Tr5 is connected to a power line for transmitting the third voltage source VDD3, the source terminal is connected to a third node QB2, and the drain terminal is connected to the second voltage source. It is connected to the power line to transmit.

The sixth NMOS transistor Tr6 is turned on or off in response to the fourth voltage source VDD4, and charges the third node QB2 to the fourth voltage source VDD4 when turned on. To this end, the gate terminal of the sixth NMOS transistor Tr6 is connected to a power line for transmitting the fourth voltage source VDD4, and the source terminal is connected to a power line for transmitting the fourth voltage source VDD4. The drain terminal is connected to the third node QB2. Here, the fourth voltage source VDD4 is an AC voltage having alternating positive and negative polarities every frame. In this case, the fourth voltage source VDD4 has an inverted phase with the third voltage source VDD3. That is, the third voltage source VDD3 has negative polarity in odd frames and positive polarity in even frames.

The seventh NMOS transistor Tr7 discharges the second node QB1 to the second voltage source VSS in response to the fourth voltage source VDD4. To this end, a gate terminal of the seventh NMOS transistor Tr7 is connected to a power line for transmitting the fourth voltage source VDD4, a source terminal is connected to the second node QB1, and a drain terminal is connected to the second terminal QB1. 2 is connected to the power supply line for transmitting the voltage source (VSS).

The eighth NMOS transistor Tr8 discharges the second node QB1 to the second voltage source VSS in response to the first voltage source VDD charged in the first node Q. To this end, the gate terminal of the eighth NMOS transistor Tr8 is connected to the first node Q, the source terminal is connected to the second node QB1, and the drain terminal is connected to the second voltage source VSS. It is connected to the power line to transmit.

The ninth NMOS transistor Tr9 discharges the third node QB2 to the second voltage source VSS in response to the first voltage source VDD charged in the first node Q. To this end, the gate terminal of the ninth NMOS transistor Tr9 is connected to the first node Q, the source terminal is connected to the third node QB2, and the drain terminal transmits the second voltage source VSS. Is connected to the power supply line.

The tenth NMOS transistor Tr10 discharges the first node Q to the second voltage source VSS in response to the third voltage source VDD3 charged in the second node QB1. To this end, a gate terminal of the tenth NMOS transistor Tr10 is connected to the second node QB1, a source terminal is connected to the first node Q, and a drain terminal of the second voltage source VSS is connected. It is connected to the transmitting power line.

The eleventh NMOS transistor Tr11 discharges the first node Q to the second voltage source VSS in response to the fourth voltage source VDD4 charged in the third node QB2. To this end, a gate terminal of the eleventh NMOS transistor Tr11 is connected to the third node QB2, a source terminal is connected to the first node Q, and a drain terminal of the second voltage source VSS is connected. It is connected to the transmitting power line.

The twelfth NMOS transistor Tr12 discharges the first node Q to the second voltage source VSS in response to the scan pulse from the next stage. That is, the twelfth NMOS transistor Tr12 of the second stage CST2 responds to the third scan pulse Vout3 from the third stage CST3, and transmits the first node Q to the second voltage source VSS. To discharge). To this end, the gate terminal of the twelfth NMOS transistor Tr12 is connected to the third stage CST3, the source terminal is connected to the first node Q, and the drain terminal transmits the second voltage source VSS. It is connected to the power line.

The output 900b of the second stage CST2 includes the pull-up transistor Tru and the first and second pull-down transistors Trd1 and Trd2.

 The pull-up transistor Tru outputs a clock pulse as a scan pulse to the gate line in response to the first voltage source VDD charged in the first node Q. In addition, this scan pulse is supplied to both the previous stage and the next stage. Here, the clock pulse is a phase delayed signal by one pulse width from the scan pulse input from the previous stage. That is, in response to the first voltage source VDD charged in the first node Q, the pull-up transistor Tru of the second stage CST2 receives the first scan pulse input from the first stage CST1. Outputs a second clock pulse CLK2 that is phase-delayed by one clock pulse width than Vout1 (this first scan pulse Vout1 is a signal synchronized with the first clock pulse CLK1). The second clock pulse CLK2 functions as a second scan pulse Vout2 for driving the second gate line. The second scan pulse Vout2 is supplied to the first stage CST1 and the third stage CST3. To this end, the gate terminal of the pull-up transistor Tru is connected to the first node Q, the source terminal is connected to the clock line for transmitting the second clock pulse CLK2, and the drain terminal is connected to the second gate line; Gate terminals of the twelfth NMOS transistor Tr12 provided in the first stage CST1, and gates of the first, second, and third NMOS transistors Tr1, Tr2, and Tr3 provided in the third stage CST3. Connected to the terminal.

The first pull-down transistor Trd1 supplies the second voltage source VSS to the gate line in response to the first voltage source VDD charged in the second node QB1. That is, the first pull-down transistor Trd1 supplies the second voltage source VSS to the second gate line in response to the first voltage source VDD charged in the second node QB1. To this end, the gate terminal of the first pull-down transistor Trd1 is connected to the second node QB1, the source terminal is connected to the second gate line, and the drain terminal is a power line for transmitting the second voltage source VSS. Is connected to. Here, the source terminal of the first pull-down transistor Trd1 is connected to the gate terminal of the twelfth NMOS transistor Tr12 provided in the previous stage, that is, the first stage CST1, and the next stage, that is, the third terminal. The gate terminals of the first, second, and third NMOS transistors Tr1, Tr2, and Tr3 included in the stage CST3 are connected.

The second pull-down transistor Trd2 supplies the second voltage source VSS to the gate line in response to the first voltage source VDD charged in the third node QB2. That is, the second pull-down transistor Trd2 supplies the second voltage source VSS to the second gate line in response to the first voltage source VDD charged in the third node QB2. To this end, the gate terminal of the second pull-down transistor Trd2 is connected to the third node QB2, the source terminal is connected to the second gate line, and the drain terminal is a power line for transmitting the second voltage source VSS. Is connected to. Here, the source terminal of the second pull-down transistor Trd2 is connected to the gate terminal of the twelfth NMOS transistor Tr12 provided in the previous stage, that is, the first stage CST1, and the next stage, that is, the third terminal. The gate terminals of the first, second, and third NMOS transistors Tr1, Tr2, and Tr3 included in the stage CST3 are connected.

The discharge part 900c of the second stage CST2 includes thirteenth to fifteenth NMOS transistors Tr13 to Tr15.

The thirteenth NMOS transistor Tr13 supplies the clock pulse to the fourteenth NMOS transistor Tr14 in response to a clock pulse supplied to the source terminal of the pull-up transistor Tru. That is, the thirteenth NMOS transistor Tr13 supplies the second clock pulse CLK2 to the fourteenth NMOS transistor Tr14 in response to the second clock pulse CLK2. To this end, the gate terminal of the thirteenth NMOS transistor Tr13 is connected to the clock line for transmitting the second clock pulse CLK2, the source terminal is connected to the clock line for transmitting the clock pulse, and the drain terminal is It is connected to the gate terminal of the fourteenth NMOS transistor Tr14.

The fourteenth NMOS transistor Tr14 discharges the first node Q to the second voltage source VSS in response to a clock pulse supplied through the thirteenth NMOS transistor Tr13. That is, the 14th NMOS transistor Tr14 transfers the first node Q to the second voltage source VSS in response to the second clock pulse CLK2 supplied through the thirteenth NMOS transistor Tr13. Discharge. For this purpose, the gate terminal of the fourteenth NMOS transistor Tr14 is connected to the drain terminal of the thirteenth NMOS transistor Tr13, the source terminal is connected to the first node Q, and the drain terminal is connected to the second node. It is connected to a power supply line that transmits a voltage source VSS.

The fifteenth NMOS transistor Tr15 turns off the fourteenth NMOS transistor Tr14 in response to a clock pulse synchronized with the scan pulse output from the next stage. That is, the fifteenth NMOS transistor Tr15 of the second stage CST2 responds to the third clock pulse CLK3 synchronized with the third scan pulse Vout3 from the third stage CST3. The 14th NMOS transistor Tr14 is turned off by supplying a second voltage source VSS to the gate terminal of the NMOS transistor Tr14. For this purpose, the gate terminal of the fifteenth NMOS transistor Tr15 is connected to the third stage CST3, the source terminal is connected to the gate terminal of the fourteenth NMOS transistor Tr14, and the drain terminal of the second voltage source. It is connected to the power line which transmits (VSS).

The discharge unit 900c may be configured of only the fourteenth NMOS transistor Tr14. At this time, the fourteenth NMOS transistor Tr14 discharges the first node Q to the second voltage source VSS in response to a clock pulse supplied to the source terminal of the pull-up transistor Tru. That is, the 14th NMOS transistor Tr14 discharges the first node Q to the second voltage source VSS in response to the second clock pulse CLK2. To this end, the gate terminal of the fourteenth NMOS transistor Tr14 is connected to a clock line that transmits the second clock pulse CLK2.

In addition, the discharge unit 900c may be configured of only the fourteenth and fifteenth NMOS transistors Tr14 and Tr15. In addition, the discharge unit 900c may be configured of only the thirteenth and fourteenth NMOS transistors Tr13 and Tr14.

The blocking unit 900d of the second stage CST2 includes the sixteenth NMOS transistor Tr16.

The sixteenth NMOS transistor Tr16 turns off the fourteenth NMOS transistor Tr14 of the discharge unit 900c in response to a scan pulse output from a stage to which the sixteenth NMOS transistor Tr16 belongs to operates the discharge unit 900c. Turn it off. That is, the sixteenth NMOS transistor Tr16 of the second stage CST2 responds to the second scan pulse Vout2 output from the second stage CST2, and thus the fourteenth NMOS transistor T1 of the discharge unit 900c ( The 14th NMOS transistor Tr14 is turned off by supplying the second voltage source VSS to the gate terminal of the Tr14. To this end, the gate terminal of the sixteenth NMOS transistor Tr16 is an output terminal of the output unit 900b of the second stage CST2 (that is, a drain terminal of the pull-up transistor Tru), and the first and second pull-downs. Is connected to the source terminal of the transistors Trd1 and Trd2, the source terminal is connected to the gate terminal of the fourteenth NMOS transistor Tr14, and the drain terminal is connected to a power line for transmitting the second voltage source VSS. Connected.

On the other hand, the first stage CST1, the third to nth stages CST3 to CSTn, and the dummy stage CSTn + 1 also have the above-described configuration.

However, since there is no stage before the first stage CST1, the first, second, and third NMOS transistors Tr1, Tr2, and Tr3 included in the first stage CST1 may be timing controllers. The start pulse SP is supplied from. That is, the first NMOS transistor Tr1 included in the first stage CST1 charges the first node Q to the first voltage source VDD in response to the start pulse SP from the timing controller. Let's do it. The second NMOS transistor Tr2 provided in the first stage CST1 discharges the second node QB1 to the second voltage source VSS in response to the start pulse SP from the timing controller. Let's do it. The third NMOS transistor Tr3 included in the first stage CST1 transfers the third node QB2 to the second voltage source VSS in response to the start pulse SP from the timing controller. Discharge.

In addition, for the same reason as described above, the drain terminal of the pull-up transistor Tru provided in the first stage CST1 is commonly connected to the first gate line and the second stage CST2, and the first stage CST1. ) And the source terminals of the first and second pull-down transistors Trd1 and Trd2 are commonly connected to the first gate line and the second stage CST2.

There is no stage next to the dummy stage CSTn + 1. In addition, the dummy stage CSTn + 1 does not supply scan pulses to the gate lines, and the stage (i.e., the nth stage CSTn) of the previous stage is transferred from the n + 1th scan pulse Voutn + 1 outputted from the dummy stage CSTn + 1. ) To disable the nth stage CSTn. Therefore, the drain terminals of the pull-up transistor Tru provided in the dummy stage CSTn + 1 and the source terminals of the first and second pull-down transistors Trd1 and Trd2 are commonly connected to the nth stage CSTn. .

The operation of the shift register according to the second embodiment of the present invention configured as described above will be described in detail as follows.

FIG. 12 is a diagram illustrating the first to third stages of FIG. 9. FIG. 13 is a timing diagram of various signals supplied to the stage of FIG. 12 and scan pulses output from the stage.

Here, it is assumed that the third voltage source VDD3 is maintained at the positive voltage during the first frame, and the fourth voltage source VDD4 is maintained at the negative voltage, and the third voltage source VDD3 is maintained during the second frame. It is assumed that the voltage is maintained at the negative polarity, and the fourth voltage source VDD4 is maintained at the positive voltage. That is, it is assumed that the third voltage source VDD3 is maintained as the positive polarity during the odd frame, and the fourth voltage source VDD4 is maintained as the negative polarity, and the third voltage source VDD3 is negative as the negative frame during the even frame. It is assumed that the fourth voltage source VDD4 remains positive.

First, the operation during the enable period T0 of the first frame will be described.

During the enable period T0, only the start pulse SP remains high as shown in FIG.

The start pulse SP is applied to the gate terminal of the first NMOS transistor Tr1, the gate terminal of the second NMOS transistor Tr2, and the gate terminal of the third NMOS transistor Tr3. The second and third NMOS transistors Tr1, Tr2, and Tr3 are turned on.

Then, the first voltage source VDD is supplied to the first node Q through the turned-on first NMOS transistor Tr1. In this case, as the first node Q is charged with the first voltage source VDD, pull-up transistors Tru, eighth, and ninth transistors Tr8 having gate terminals connected to the first node Q, respectively. , Tr9) are turned on at the same time. Here, the second voltage source VSS is supplied to the second node QB1 through the turned-on eighth NMOS transistor Tr8 and the second NMOS transistor Tr2. Accordingly, the second node QB1 is maintained in a discharged state, and the tenth NMOS transistor Tr10 and the first pull-down transistors Tr10 and Trd1 having a gate terminal connected to the second node QB1 are turned off. do.

The second voltage source VSS is supplied to the third node QB2 through the turned-on third and ninth NMOS transistors Tr3 and Tr9. In this case, as the third node QB2 is discharged to the second voltage source VSS, an eleventh NMOS transistor Tr11 and a second pull-down transistor Tr11 having a gate terminal connected to the third node QB2, Trd2) is turned off.

In addition, the fourth NMOS transistor Tr4 is turned on as the third voltage source VDD3 is applied to its gate terminal. Since the third voltage source VDD3 is always in a positive state during the first frame, the fourth NMOS transistor Tr4 is always turned on during the first frame. Here, the third voltage source VDD3 is supplied to the second node QB1 through the turned-on fourth NMOS transistor Tr4. As a result, the second voltage source VSS and the third voltage source VDD3 are simultaneously supplied to the second node QB1. However, the channel widths of the second and eighth NMOS transistors Tr2 and Tr8 supplying the second voltage source VSS are greater than the channel widths of the fourth NMOS transistor Tr4 supplying the third voltage source VDD3. Since it is larger, the second node QB1 is maintained as the second voltage source VSS. As a result, the second node QB1 maintains a discharge state during the enable period T0. Therefore, the first pull-down transistor Trd and the tenth NMOS transistor Tr10 having the gate terminal connected to the second node QB1 are turned off during this enable period T0.

The third voltage source VDD3 is also supplied to the gate terminal of the fifth NMOS transistor Tr5. Accordingly, the fifth NMOS transistor Tr5 is also always turned on during the first frame. The second voltage source VSS is supplied to the third node QB2 through the turned-on fifth NMOS transistor Tr5. As a result, the third node QB2 is maintained in the discharge state by the third, fifth and ninth NMOS transistors Tr3, Tr5, and Tr9. Therefore, the second pull-down transistor Trd and the eleventh NMOS transistor Tr11 having the gate terminal connected to the third node QB2 in common are turned off.

The sixth NMOS transistor Tr6 is turned off by the fourth voltage source VDD4 applied to its gate terminal. In this case, since the fourth voltage source VDD4 is negatively maintained during the first frame, the sixth NMOS transistor Tr6 is always turned off during the first frame.

In addition, since the fourth voltage source VDD4 is also applied to the gate terminal of the seventh NMOS transistor Tr7, the seventh NMOS transistor Tr7 is always turned off during the first frame.

As such, during the enable period T0, as illustrated in FIG. 12, the first node Q of the first stage CST1 is charged to the first voltage source VDD, and the second and second voltages are charged. Since the three nodes QB1 and QB2 are discharged to the second voltage source VSS, the first stage CST1 is enabled.

Next, the operation during the first period T1 will be described.

During the first period T1, as shown in FIG. 13, only the first clock pulse CLK1 remains high and the remaining clock pulses remain low. Accordingly, the first, second, and third NMOS transistors Tr1, Tr2, and Tr3 of the first stage CST1 are turned off in response to the low state start pulse SP. The first node Q of one stage CST1 is maintained in a floating state.

Meanwhile, as the first node Q of the first stage CST1 is continuously maintained as the first voltage source VDD applied during the enable period T0, the pull-up transistor of the first stage CST1 Tru) remains turned on. At this time, as the first clock pulse CLK1 is applied to the source terminal of the turned-on pull-up transistor Tru, the first node Q of the first stage CST1 as shown in FIG. 12. The first voltage source VDD charged to is amplified by bootstrapping. Thus, the first pull-up transistor Tru is almost completely turned on. Accordingly, the first clock pulse CLK1 applied to the source terminal of the pull-up transistor Tru of the first stage CST1 is stably output through the drain terminal of the pull-up transistor Tru. In this case, as illustrated in FIG. 13, the output first clock pulse CLK1 is applied to the first gate line to serve as a first scan pulse Vout1 driving the first gate line. The first scan pulse Vout1 is supplied to the blocking unit 900d of the first stage CST1. Specifically, the first scan pulse Vout1 is input to the gate terminal of the sixteenth NMOS transistor Tr16 provided in the blocking unit 900d of the first stage CST1, and thus, the first scan pulse Vout1 is input to the gate terminal of the blocking unit 900d. 16 Turn on the NMOS transistor Tr16. Then, the second voltage source VSS is supplied to the discharge unit 900c provided in the first stage CST1 through the turned-on sixteenth NMOS transistor Tr16. Specifically, the second voltage source VSS is applied to the gate terminal of the fourteenth NMOS transistor Tr14 provided in the discharge unit 900c of the first stage CST1.

On the other hand, the first clock pulse CLK1 is also supplied to the discharge unit 900c of the first stage CST1. Specifically, the first clock pulse CLK1 is supplied to the gate terminal and the source terminal of the thirteenth NMOS transistor Tr13 included in the discharge unit 900c of the first stage CST1. Therefore, the first clock pulse CLK1 is supplied to the gate terminal of the fourteenth NMOS transistor Tr14 through the turned-on thirteenth NMOS transistor Tr13.

As such, the first clock pulse CLK1 and the second voltage source VSS are simultaneously applied to the gate terminal of the fourteenth NMOS transistor Tr14 included in the discharge unit 900c of the first stage CST1. . At this time, the channel width of the sixteenth NMOS transistor Tr16, which supplies the second voltage source VSS to the gate terminal of the fourteenth NMOS transistor Tr14, has a first clock at the gate terminal of the fourteenth NMOS transistor Tr14. The second voltage source VSS is applied to the gate terminal of the fourteenth NMOS transistor Tr14 because it is larger than the channel width of the thirteenth NMOS transistor Tr13 that supplies the pulse CLK1. Therefore, the fourteenth NMOS transistor Tr14 of the first stage CST1 is turned off. That is, the discharge unit 900c of the first stage CST1 does not drive. Therefore, the first node Q of the first stage CST1 maintains the state charged with the first voltage source VDD supplied during the enable period T0. Accordingly, the pull-up transistor Tru connected to the first node Q of the first stage CST1 maintains a turn-on state, thereby supplying it to the pull-up transistor Tru in the first period T1. The first clock pulse CLK1 is normally supplied to the first gate line as the first scan pulse Vout1.

In other words, when the first period T1, that is, the timing at which the first stage CST1 outputs the first clock pulse CLK1 as the first scan pulse Vout1, the blocking unit 900d operates. As a result, the discharge unit 900c does not operate. Accordingly, the first node Q of the first stage CST1 maintains a charging state, and thus, the first stage CST1 normally sets the first clock pulse CLK1 as the first scan pulse Vout1. Output

On the other hand, the first scan pulse Vout1 output from the first stage CST1 in the first period T1 is also input to the second stage CST2. Specifically, as illustrated in FIG. 11, the first scan pulse Vout1 may be a gate terminal of the first NMOS transistor Tr1 and a gate of the second NMOS transistor Tr2 provided in the second stage CST2. A terminal is input to the gate terminal of the third NMOS transistor Tr3. Here, the first scan pulse Vout1 supplied to the second stage CST2 plays the same role as the start pulse SP supplied to the first stage CST1 and the first scan pulse Vout1. In response, the first NMOS transistor Tr1 of the second stage CST2 charges the first node Q of the second stage CST2 to the first voltage source VDD, and the second stage CST2. The second NMOS transistor Tr2 of FIG. 2 discharges the second node QB1 of the second stage CST2, and the third NMOS transistor Tr3 of the second stage CST2 is the second stage CST2. Discharges the third node QB2.

As a result, in the first period T1, the first stage CST1 outputs a first scan pulse Vout1, and the second stage CST2 responds to the first scan pulse Vout1. Is enabled.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in FIG. 13, only the second clock pulses CLK2 and CLK4 remain high and the remaining clock pulses remain low.

Accordingly, the first scan pulse Vout1 (that is, the first clock pulse CLK1) from the first stage CST1, which was applied in the first period T1, becomes low in the second period T2. As a result, the first, second, and third NMOS transistors Tr1, Tr2, and Tr3 of the second stage, which are applied through the gate terminal, are turned off, and thus the first stage of the second stage CST2 is turned off. One node Q is kept in a floating state. In this case, as the second clock pulse CLK2 is applied to the source terminal of the pull-up transistor Tru of the second stage CST2, the first charge of the first node Q of the second stage CST2 is performed. One voltage source VDD is amplified by bootstrapping.

Therefore, the second clock pulse CLK2 applied to the source terminal of the pull-up transistor Tru of the second stage CST2 is stably output through the drain terminal of the pull-up transistor Tru. In this case, as shown in FIG. 13, the second clock pulse CLK2 output from the second stage CST2 is applied to a second gate line to drive the second gate pulse Vout2. Acts as).

On the other hand, in the second period T2, the second stage CST2 uses the second scan pulse Vout2 outputted from itself, similarly to the above-described first stage CST1, and has its own blocking unit 900d. ) Is turned on, and the discharge unit 900c is turned off. Therefore, in the second period T2, the first node Q of the second stage CST2 is kept in a charged state, thereby stably supplying the second scan pulse Vout2 to the second gate line. .

In this case, the second scan pulse Vout2 output from the second stage CST2 is also input to the first stage CST1. Specifically, as shown in FIG. 11, the second scan pulse Vout2 is input to the gate terminal of the twelfth NMOS transistor Tr12 provided in the first stage CST1. Here, as the twelfth NMOS transistor Tr12 of the first stage CST1 is turned on by the second scan pulse Vout2, the twelfth NMOS transistor whose second voltage source VSS is turned on It is supplied to the first node Q of the first stage CST1 through Tr12. Therefore, as shown in FIG. 13, the first node Q of the first stage CST1 is discharged by the second voltage source VSS. Then, the pull-up transistor Tru having the gate terminal commonly connected to the first node Q of the first stage CST1 and the eighth and ninth NMOS transistors Tr8 and Tr9 are turned off.

Meanwhile, since the second and eighth NMOS transistors Tr2 and Tr8 of the first stage CST1 are turned off during the second period T2, the first stage (T2) during the second period T2. The second node QB1 of CST1 is charged with the first voltage source VDD supplied through the fourth NMOS transistor Tr4. Therefore, both the first pull-down transistor Trd1 and the tenth NMOS transistor Tr10 having the gate terminal commonly connected to the second node QB1 of the first stage CST1 are turned on. At this time, the second voltage source VSS is supplied to the first gate line through the turned-on first pull-down transistor Trd1.

Meanwhile, a second voltage source VSS is supplied to the first node Q through the turned-on tenth NMOS transistor Tr10. As a result, the first node Q is discharged by the tenth and twelfth NMOS transistors Tr10 and Tr12 during the second period T2.

In addition, the second clock pulse CLK2 output in the second period T2 is supplied to the discharge unit 900c provided in the first stage CST1. Specifically, the second clock pulse CLK2 is input to the gate terminal of the fifteenth NMOS transistor Tr15 provided in the discharge unit 900c of the first stage CST1. Therefore, the fifteenth NMOS transistor Tr15 of the first stage CST1 is turned on. Therefore, the second voltage source VSS is provided to the gate terminal of the fourteenth NMOS transistor Tr14 provided in the discharge unit 900c of the first stage CST1 through the turned-on fifteenth NMOS transistor Tr15. Is approved. The fifteenth NMOS transistor Tr15 included in the discharge unit 900c is a switching device for preventing deterioration of the fourteenth NMOS transistor Tr14. That is, as the first clock pulse CLK1 is periodically output, the second voltage source VSS is provided at the gate terminal of the fourteenth NMOS transistor Tr14 provided in the discharge unit 900c of the first stage CST1. Rather than the first clock pulse CLK1 is applied for more time. Accordingly, characteristics of the threshold voltage of the fourteenth NMOS transistor Tr14 may change. In order to prevent this, the fifteenth NMOS transistor Tr15 is synchronized with the next stage (ie, the third stage CST3) when it outputs the scan pulse (ie, the third scan pulse Vout3). The second voltage source VSS is supplied to the gate terminal of the fourteenth NMOS transistor Tr14 included in the discharge unit 900c by receiving the third clock pulse CLK3. In this way, the second voltage source VSS may be supplied to the gate terminal of the fourteenth NMOS transistor Tr14 for a longer time.

In addition, during the second period T2, the second scan pulse Vout2 output from the second stage CST2 is also input to the third stage CST3. In detail, as illustrated in FIG. 11, the second scan pulse Vout2 may include gates of the first, second, and third NMOS transistors Tr1, Tr2, and Tr3 provided in the third stage CST3. It is input to the terminal. Therefore, in the second period T2, all of the first, second, and third NMOS transistors Tr3 of the third stage CST3 are turned on. Therefore, in the second period T2, the third stage CST3 is enabled. That is, in the second period T2, the first node Q of the third stage CST3 is charged, and the second and third nodes QB1 and QB2 are discharged.

In summary, in the second period T2, the second scan pulse Vout2 is output from the second stage CST2. This second scan pulse Vout2 drives the second gate line. In addition, the second scan pulse Vout2 discharges the first node Q of the first stage CST1 and disables the first stage CST1 by charging the second node QB1. In addition, the second scan pulse Vout2 charges the first node Q of the third stage CST3 and discharges the second and third nodes QB1 and QB2 to discharge the third stage CST3. Enable.

In this manner, in the third period T3, the third scan pulse Vout3 is output from the third stage CST3. This third scan pulse Vout3 drives the third gate line. In addition, the third scan pulse Vout3 discharges the first node Q of the second stage CST2 and disables the second stage CST2 by charging the second node QB1. In addition, the third scan pulse Vout3 is supplied to the discharge unit 900c of the second stage CST2 to prevent deterioration of the fourteenth NMOS transistor Tr14. In addition, the third scan pulse Vout3 charges the first node Q of the fourth stage CST4 and discharges the second and third nodes QB1 and QB2 to discharge the fourth stage CST4. Enable.

In the fourth period T4, the fourth scan pulse Vout4 is output from the fourth stage CST4. This fourth scan pulse Vout4 drives the fourth gate line. In addition, the fourth scan pulse Vout4 discharges the first node Q of the third stage CST3 and disables the third stage CST3 by charging the second node QB1. In addition, the fourth scan pulse Vout4 is supplied to the discharge unit 900c of the first stage CST1 to prevent deterioration of the fourteenth NMOS transistor Tr14. In addition, the fourth scan pulse Vout4 charges the first node Q of the fifth stage and enables the fifth stage by discharging the second and third nodes QB1 and QB2.

Next, the operation during the fifth period T5 will be described.

In this fifth period T5, a fifth scan pulse is output from the fifth stage. This fifth scan pulse drives the fifth gate line. Meanwhile, the first clock pulse CLK1 is output again in the fifth period T5. That is, in the fifth period T5, the first clock pulse CLK1 remains high again. Therefore, in the fifth period T5, the fifth stage outputs the first clock pulse CLK1 as a fifth scan pulse. At this time, the first clock pulse CLK1 output in the fifth period T5 is supplied not only to the fifth stage but also to the first stage CST1. Specifically, the first clock pulse CLK1 output in the fifth period T5 is provided with a source terminal of the pull-up transistor Tru provided in the fifth stage, and provided in the first stage CST1. It is supplied together to the source terminal of the pull-up transistor Tru. In the fifth period T5, the first node Q of the first stage CST1 is in a discharge state, and the first node Q of the fifth stage is in a charged state, so that only the fifth stage is The first clock pulse CLK1 may be output as the fifth scan pulse.

However, as the first clock pulse CLK1 is applied to the source terminal of the pull-up transistor Tru of the first stage CST1, the first node Q and the first stage of the first stage CST1 are applied. Coupling occurs between the source terminals of the pull-up transistor Tru to which the clock pulse CLK1 is applied. By this coupling phenomenon, the first node Q of the first stage CST1 may be charged to a predetermined voltage. The first node Q of the first stage CST1 is charged to a larger voltage as the first clock pulse CLK1 is continuously applied, thereby charging the first node QST1 of the first stage CST1. Q may be charged to a voltage that is large enough to turn on the pull-up transistor Tru of the first stage CST1. Then, a problem occurs in which scan pulses are simultaneously output from two stages, that is, the first and fifth stages, in the fifth period T5. Here, the scan pulse output from the fifth stage in the fifth period T5 is a correct output. However, the scan pulse output from the first stage CST1 is an incorrect output. As a result, the first stage CST1 may generate two or more outputs during one frame. That is, the first stage CST1 may generate an output in the first and fifth periods T1 and T5. Of course, not only the first stage CST1 but also the remaining stages may generate two or more multi-outputs as described above.

In order to prevent the multiple output due to such a coupling phenomenon, the discharge unit 900c of each stage CST1 to CSTn + 1 operates in a period other than its own output. If this is explained in more detail as follows.

As described above, the first clock pulse CLK1 is output in the fifth period T5. The first clock pulse CLK1 output in the fifth period T5 has a time difference corresponding to four clock pulse widths from the first clock pulse CLK1 output in the first period T1. The first clock pulse CLK1 output in the fifth period T5 is supplied to the discharge unit 900c of the first stage CST1 to operate the discharge unit 900c. That is, the first clock pulse CLK1 is applied to the gate terminal of the thirteenth NMOS transistor Tr13 included in the first stage CST1 to turn on the thirteenth NMOS transistor Tr13. Then, the first clock pulse CLK1 is applied to the gate terminal of the fourteenth NMOS transistor Tr14 through the turned-on thirteenth NMOS transistor Tr13. Therefore, the fourteenth NMOS transistor Tr14 included in the first stage CST1 is turned on. Then, the second voltage source VSS is supplied to the first node Q of the first stage CST1 through the turned-on eighth NMOS transistor Tr8. Therefore, the first node Q of the first stage CST1 is discharged. In this case, since the scan pulse from the first stage CST1 is not generated, the blocking unit 900d provided in the first stage CST1 does not operate. Consequently, even if a predetermined voltage is charged to the first node Q of the first stage CST1 during the fifth period T5 by the coupling phenomenon, the voltage is provided to the first stage CST1. By the discharge unit 900c.

As such, when the first clock pulse CLK1 corresponding to the output timing of the first scan pulse Vout1 is applied to the first stage CST1, the first stage CST1 again outputs the first scan pulse Vout1 output from the first stage CST1. It receives the feedback and keeps its first node Q in a charged state. On the other hand, when the first clock pulse CLK1 is applied to the first clock pulse CLK1 applied to a period other than the output timing of the first scan pulse Vout1, the first stage CST1 is applied. Each time, the first node Q is discharged in response. That is, each of the stages CST1 to CSTn + 1 receives feedback of the scan pulses output from the stages, thereby confirming whether the scan pulses are output. Then, each stage CST1 to CSTn + 1 operates the breaker 900d when there is an output, and operates the discharge unit 900c when there is no output.

As a result, the first stage CST1 outputs the first clock pulse CLK1 input in the first period T1 in one frame as the first scan pulse Vout1, and to the first scan pulse Vout1. In response, keeps its first node Q in a charged state and is input to the fifth, ninth, ....., and kth periods T5, T9, ..., Tk. In response to the pulse CLK1, the first node Q is brought into a discharge state.

In this manner, the second stage CST2 outputs the second clock pulse CLK2 input in the second period T2 in one frame as the second scan pulse Vout2, and the second scan pulse Vout2. ) Keeps its first node Q charged. The second stage CST2 includes sixth, tenth, ..., and k + 1th periods T6, T10, ..., Tk + in one frame except the second period T2. In response to the second clock pulse CLK2 input to 1), the first node Q is brought into a discharge state.

In addition, the third stage CST3 outputs the third clock pulse CLK3 input in the third period T3 in one frame as the third scan pulse Vout3, and responds to the third scan pulse Vout3. To keep its first node Q in a charged state. The third stage CST3 includes the seventh, eleventh, ..., and k + 2th periods T7, T11, ..., Tk + in one frame except the third period T3. In response to the third clock pulse CLK3 input to 2), the first node Q is brought into a discharge state.

In addition, the fourth stage CST4 outputs the fourth clock pulse inputted in the fourth period T4 in one frame as the fourth scan pulse Vout4 and in response to the fourth scan pulse Vout4. 1 Keep node Q charged. The fourth stage CST4 includes the eighth, twelfth, ..., and k + 3th periods T8, T12, ..., Tk + in one frame except the fourth period T4. In response to the fourth clock pulse CLK4 input to 3), the first node Q is brought into a discharge state.

In addition, the fifth stage outputs the first clock pulse CLK1 input in the fifth period T5 in one frame as a fifth scan pulse, and in response to the fifth scan pulse, its first node Q. Keep it charged. The fifth stage is a first input unit for the ninth, thirteenth, ..., and kth periods T9, T13, ..., Tk in one frame except for the fifth period T5. In response to the clock pulse CLK1, the first node Q is brought into a discharge state.

The remaining sixth to nth stages CSTn and the dummy stage CSTn + 1 also operate in the same manner as described above.

As a result, each stage outputs a clock pulse input as a scan pulse at a timing to output the scan pulse, and at this time receives the scan pulse and maintains its first node Q in a charged state. Then, each stage puts its first node Q into a discharge state in response to a clock pulse input after the scan pulse is output.

On the other hand, when all the stages output one scan pulse during the first frame, the second frame starts. That is, the first stage CST1 operates again.

During this second frame, as described above, the third voltage is maintained at negative polarity and the fourth voltage is maintained at positive polarity.

Therefore, during this second frame, the fourth NMOS transistor Tr4 of each stage is always turned off, and the sixth NMOS transistor Tr6 of each stage is always turned on.

Therefore, during the second frame, when each stage CST1 to CSTn + 1 is disabled, its second node QB1 is kept in a discharged state and the third node QB2 is kept in a charged state. That is, during the odd-numbered frames, when each stage CST1 to CSTn + 1 is disabled, it charges its own second node QB1 and discharges its own third node QB2. When the stages CST1 to CSTn + 1 are disabled, the second node QB1 is discharged and the third node QB2 is charged. As a result, every frame, the second node QB1 and the third node QB2 of each stage CST1 to CSTn + 1 alternately maintain charge and discharge states. Accordingly, deterioration of the switching element located in the output unit 900b can be prevented. That is, as the second and third nodes QB1 and QB2 are alternately charged and discharged at intervals of the frame, the first and second pull-down transistors Trd1 and Trd2 positioned in the output unit 900b also change the frame. It is turned on and off alternately in cycles. Therefore, it is possible to prevent the threshold voltages of the first and second pull-down transistors Trd1 and Trd2 included in the output unit 900b from increasing to one side.

Hereinafter, the shift register according to the third embodiment of the present invention will be described in detail.

14 is a diagram illustrating a shift register according to a third embodiment of the present invention.

As illustrated in FIG. 14, the shift register according to the third embodiment of the present invention includes n stages DST1 to DSTn and one dummy stage DSTn + 1 connected to each other. Here, each of the stages DST1 to DSTn + 1 outputs one scan pulse Vout1 to Voutn + 1, and in this case, the scan pulse Vout1 is sequentially performed from the first stage DST1 to the dummy stage DSTn + 1. To Voutn + 1). In this case, scan pulses Vout1 to Voutn output from the stages DST1 to DSTn except the dummy stage DSTn + 1 are sequentially supplied to gate lines of the liquid crystal panel (not shown). The gate lines are sequentially scanned.

Since these stages DST1 to DSTn + 1 are the same as those of FIG. 3, description thereof will be omitted.

A circuit configured in the second stage DST2 among the stages DST1 to DSTn + 1 will be described in detail as follows.

FIG. 15 is a circuit diagram illustrating the second stage of FIG. 14.

That is, as illustrated in FIG. 15, the node controller 140a of the second stage DST2 includes first and second NMOS transistors Tr1 and Tr2.

Since the first to second NMOS transistors Tr1 and Tr2 are the same as the first and second NMOS transistors Tr1 and Tr2 illustrated in FIG. 8, description thereof will be omitted.

The output unit 140b of the second stage DST2 includes the pull-up transistor Tru and the pull-down transistor Trd described above.

The pull-up transistor Tru is delayed by one clock pulse width than the scan pulse applied to the gate terminal of the first NMOS transistor Tr1 in response to the first voltage source VDD charged in the first node Q. Output clock pulses as scan pulses. That is, the pull-up transistor Tru of the second stage DST2 outputs the second clock pulse CLK2 delayed by one pulse width from the first scan pulse Vout1 as the second scan pulse Vout2. The output second scan pulse Vout2 is supplied to the gate line connected to the stage to which it belongs, the stage at the previous stage, and the stage at the next stage. That is, the pull-up transistor Tru outputs the second scan pulse Vout2 as the second scan pulse Vout2 for driving the second gate line. The second scan pulse Vout2 is also supplied to the second gate line, the first stage DST1, and the third stage DST3.

Here, the second scan pulse Vout2 supplied to the first stage DST1 disables the first stage DST1, and the second scan pulse Vout2 supplied to the third stage DST3 is The third stage DST3 is enabled. To this end, the gate terminal of the pull-up transistor Tru is connected to the first node Q, the source terminal is connected to the clock line for transmitting the second clock pulse CLK2, and the drain terminal is connected to the second gate. The line, the first stage DST1, and the third stage DST3 are commonly connected.

The pull-down transistor Trd outputs the second voltage source VSS in response to the first voltage source VDD charged in the second node QB. Then, the second voltage source VSS is supplied to the gate line connected to the stage to which it belongs, the stage in the previous stage, and the stage in the next stage. That is, the pull-down transistor Trd of the second stage DST2 supplies the second voltage source VSS to the second gate line, the first stage DST1, and the third stage DST3. The second voltage source VSS supplied to the second gate line functions as a signal for deactivating the second gate line. To this end, the gate terminal of the pull-down transistor Trd is connected to the second node QB, and the source terminal is commonly connected to the second gate line, the first stage DST1, and the third stage DST3. The drain terminal is connected to a power line for transmitting the second voltage source VSS.

The discharge unit 140c of the second stage DST2 includes third to fifth NMOS transistors Tr3 to Tr5.

The third NMOS transistor Tr3 outputs the clock pulse in response to the clock pulse synchronized with the scan pulse output from the next stage. To this end, the gate terminal of the third NMOS transistor Tr3 is connected to the clock line for transmitting the fourth clock pulse CLK4, and the source terminal is connected to the clock line for transmitting the fourth clock pulse CLK4. do.

The fourth NMOS transistor Tr4 discharges the first node Q to the second voltage source VSS in response to a clock pulse supplied through the third NMOS transistor Tr3. That is, the fourth NMOS transistor Tr4 transfers the first node Q to the second voltage source VSS in response to the fourth clock pulse CLK4 supplied through the third NMOS transistor Tr3. Discharge. To this end, the gate terminal of the fourth NMOS transistor Tr4 is connected to the drain terminal of the third NMOS transistor Tr3, the source terminal is connected to the first node Q, and the drain terminal is connected to the second node. It is connected to a power supply line that transmits a voltage source VSS.

The fifth NMOS transistor Tr5 turns off the fourth NMOS transistor Tr4 in response to a clock pulse synchronized with the scan pulse output from the next stage. That is, the fifth NMOS transistor Tr5 of the second stage DST2 is in response to the third clock pulse CLK3 synchronized with the third scan pulse Vout3 from the third stage DST3. The fourth NMOS transistor Tr4 is turned off by supplying the second voltage source VSS to the gate terminal of the NMOS transistor Tr4. To this end, the gate terminal of the fifth NMOS transistor Tr5 is connected to the third stage DST3, the source terminal is connected to the gate terminal of the fourth NMOS transistor Tr4, and the drain terminal of the second voltage source. It is connected to the power line which transmits (VSS).

The interrupter 140d includes a sixth NMOS transistor Tr6.

The sixth NMOS transistor Tr6 turns off the operation of the discharge unit 140c by turning off the fourth NMOS transistor Tr4 of the discharge unit 140c in response to the scan pulse from the previous stage. Let's do it. That is, the sixth NMOS transistor Tr6 is provided to the gate terminal of the fourth NMOS transistor Tr4 of the discharge unit 140c in response to the first scan pulse Vout2 output from the first stage DST1. The fourth NMOS transistor Tr4 is turned off by supplying a second voltage source VSS. To this end, the gate terminal of the sixth NMOS transistor Tr6 is an output terminal of the output unit 140b of the second stage DST2 (that is, a drain terminal of the pull-up transistor Tru), and the pull-down transistor Trd of the Terminal connected to the source terminal), the source terminal is connected to the gate terminal of the fourth NMOS transistor Tr4, and the drain terminal is connected to the power supply line for transmitting the second voltage source VSS.

On the other hand, the first stage DST1, the third to nth stages DSTn, and the dummy stage DSTn + 1 also have the above configuration.

However, since there is no stage before the first stage DST1, the first NMOS and sixth NMOS transistors Tr1 and Tr6 included in the first stage DST1 may have a start pulse (Tr1, Tr6). SP). That is, the first NMOS transistor Tr1 included in the first stage DST1 charges the first node Q to the first voltage source VDD in response to the start pulse SP from the timing controller. Let's do it. The sixth NMOS transistor Tr3 is connected to the gate terminal of the fourth NMOS transistor Tr4 of the discharge part 140c in response to the start pulse SP from the timing controller. The fourth NMOS transistor Tr4 is turned off by supplying.

The operation of the shift register with a stage having the circuit configuration as described above is as follows.

First, the start pulse SP output in the enable period is supplied to the first stage DST1 to enable the first stage DST1.

Thereafter, the first scan pulse Vout1 output from the first stage DST1 is supplied to the second stage DST2 in the first period. Specifically, the first scan pulse Vout1 is supplied to the gate terminals of the first and sixth NMOS transistors Tr1 and Tr6 provided in the second stage DST2. Then, the first and sixth NMOS transistors Tr1 and Tr6 of the first stage DST1 are turned on.

In this case, a first voltage source VDD is supplied to the first node Q of the second stage DST2 through the turned-on first NMOS transistor Tr1, and thus the first node Q is provided. Is charged. The pull-up transistor Tru having a gate terminal connected to the charged first node Q is turned on. The second voltage source VSS is supplied to the gate terminal of the fourth NMOS transistor Tr4 through the turned-on sixth NMOS transistor Tr6. As a result, the fourth NMOS transistor Tr4 is turned off. That is, since the sixth NMOS transistor Tr6 of the blocking unit 140d operates, the fourth NMOS transistor Tr4 of the discharge unit 140c is turned off. In other words, during the first period during which the first node Q is charged, the fourth NMOS transistor Tr4 is turned off. Thus, the first node Q is stably charged.

Thereafter, when the second clock pulse CLK2 is supplied to the source terminal of the turned-up pull-up transistor Tru in the second period, the pull-up transistor Tru receives the second clock pulse CLK2 as a second scan pulse. Output as (Vout2). The output second scan pulse Vout2 is supplied to the second gate line, the first stage DST1, and the third stage DST3.

During the second period, the third stage DST3 supplied with the second scan pulse Vout2 charges its first node Q in the same manner as the second stage DST2. Thereafter, in the third period, the third stage DST3 outputs the third clock pulse CLK3 as the third scan pulse Vout3. The output third scan pulse Vout3 is supplied to the third gate line, the second stage DST2, and the first stage DST1.

Meanwhile, the third clock pulse CLK3 output in the third period is also supplied to the second stage DST2. Specifically, the third clock pulse CLK3 is supplied to the gate terminal of the fifth NMOS transistor Tr5 provided in the second stage DST2. Therefore, in the third period, the fifth NMOS transistor Tr5 of the second stage DST2 is turned on. The second voltage source VSS is supplied to the gate terminal of the fourth NMOS transistor Tr4 through the turned-on fifth NMOS transistor Tr5. Then, the fourth NMOS transistor Tr4 provided in the second stage DST2 is turned off.

On the other hand, the third scan pulse Vout3 output from the third stage DST3 in the third period is also supplied to the second NMOS transistor Tr2 of the second stage DST2. Then, the second NMOS transistor Tr2 of the second stage DST2 is turned on. The second voltage source VSS is supplied to the first node Q of the second stage DST2 through the turned-on second NMOS transistor Tr2. Therefore, in the third period, the first node Q of the second stage DST1 is discharged.

That is, in the third period, the first node Q of the second stage DST2 is discharged, and the fourth NMOS transistor Tr4 of the second stage DST2 is turned off.

Next, in the fourth period, the fourth stage DST4 outputs the fourth clock pulse CLK4 as the fourth scan pulse Vout4. The fourth scan pulse Vout4 is supplied to the fourth gate line, the third stage DST3, and the fifth stage. The fourth clock pulse CLK4 output in this fourth period is also supplied to the second stage DST2. Specifically, the fourth clock pulse CLK4 output in the fourth period is supplied to the gate terminal and the source terminal of the third NMOS transistor Tr3 provided in the second stage DST2. Then, the third NMOS transistor Tr3 of the second stage DST2 is turned on. The fourth clock pulse CLK4 is supplied with the gate terminal of the fourth NMOS transistor Tr4 of the second stage DST2 through the turned-on third NMOS transistor Tr4. Then, the fourth NMOS transistor Tr4 is turned on. Through this turned-on fourth NMOS transistor Tr4, the second voltage source VSS is supplied to the first node Q of the second stage DST2, and thus, the first of the second stage DST2. Node Q is discharged. As a result, the first node Q of the second stage DST2 is discharged whenever the fourth clock pulse CLK4 is output. In this case, the sixth NMOS transistor Tr6 of the blocking unit 140d may be charged with the fourth NMOS transistor Tr4 at a time point (first period) at which the first node Q of the first stage DST1 is charged. By turning off, the first node Q is prevented from being discharged. Therefore, the pull-up transistor Tru of the second stage DST2 can stably output the second scan pulse Vout2 in its output period (ie, the second period). After this output period, as described above, the first node Q of the second stage DST2 is periodically discharged by the fourth clock pulse CLK4.

On the other hand, in the shift register according to the third embodiment of the present invention configured as described above, each stage may have the following circuit configuration. Here, only the second stage DST2 will be described as an example.

FIG. 16 is a diagram illustrating another circuit configuration of the second stage of FIG. 14.

That is, as shown in FIG. 16, the node controller 140a of the second stage DST2 includes first to fifth NMOS transistors Tr1 to Tr5. Here, since the first to fifth NMOS transistors Tr1 to Tr5 illustrated in FIG. 16 are the same as the first to fifth NMOS transistors Tr1 to Tr5 illustrated in FIG. 5, description thereof will be omitted. .

The output unit 140b of the second stage DST2 includes a pull-up transistor Tru and a pull-down transistor Trd.

The pull-up transistor Tru is delayed by one clock pulse width than the scan pulse applied to the gate terminal of the first NMOS transistor Tr1 in response to the first voltage source VDD charged in the first node Q. Output clock pulses as scan pulses. That is, the pull-up transistor Tru of the second stage DST2 outputs the second clock pulse CLK2 delayed by one pulse width from the first scan pulse Vout1 as a scan pulse. The output scan pulse is supplied to the gate line connected to the stage to which the output scan pulse belongs, the stage before the stage, and the stage after the stage. That is, the pull-up transistor Tru outputs the second clock pulse CLK2 as a second scan pulse Vout2 for driving a second gate line. The second scan pulse Vout2 is supplied to the second gate line, the first stage DST1, and the third stage DST3. To this end, the gate terminal of the pull-up transistor Tru is connected to the first node Q, the source terminal is connected to the clock line for transmitting the second clock pulse CLK2, and the drain terminal is connected to the second gate. The line, the first stage DST1, and the third stage DST3 are commonly connected.

Here, the second scan pulse Vout2 supplied to the first stage DST1 disables the first stage DST1, and the second scan pulse Vout2 supplied to the third stage DST3 is The third stage DST3 is enabled.

The pull-down transistor Trd outputs the second voltage source VSS in response to the first voltage source VDD charged in the second node QB. Then, the second voltage source VSS is supplied to the gate line connected to the stage to which it belongs, the stage in the previous stage, and the stage in the next stage. That is, the pull-down transistor Trd of the second stage DST2 supplies the second voltage source VSS to the second gate line, the first stage DST1, and the third stage DST3. The second voltage source VSS supplied to the second gate line functions as a signal for deactivating the second gate line. To this end, the gate terminal of the pull-down transistor Trd is connected to the second node QB, and the source terminal is commonly connected to the second gate line, the first stage DST1, and the third stage DST3. The drain terminal is connected to a power line for transmitting the second voltage source VSS.

The discharge part 140c of the second stage DST2 includes seventh to ninth NMOS transistors Tr7 and Tr9.

The seventh NMOS transistor Tr7 outputs the clock pulse in response to a clock pulse synchronized with the scan pulse output from the next stage. To this end, the gate terminal of the seventh NMOS transistor Tr7 is connected to the clock line for transmitting the fourth clock pulse CLK4, and the source terminal is connected to the clock line for transmitting the fourth clock pulse CLK4. do.

The eighth NMOS transistor Tr8 discharges the first node Q to the second voltage source VSS in response to a clock pulse supplied through the seventh NMOS transistor Tr7. That is, the eighth NMOS transistor Tr8 transfers the first node Q to the second voltage source VSS in response to the fourth clock pulse CLK4 supplied through the seventh NMOS transistor Tr7. Discharge. To this end, the gate terminal of the eighth NMOS transistor Tr8 is connected to the drain terminal of the seventh NMOS transistor Tr7, the source terminal is connected to the first node Q, and the drain terminal is connected to the second node. It is connected to a power supply line that transmits a voltage source VSS.

The ninth NMOS transistor Tr9 turns off the eighth NMOS transistor Tr8 in response to a clock pulse synchronized with the scan pulse output from the next stage. That is, the ninth NMOS transistor Tr9 of the second stage DST2 responds to the third clock pulse CLK3 synchronized with the third scan pulse Vout3 from the third stage DST3. The eighth NMOS transistor Tr8 is turned off by supplying a second voltage source VSS to the gate terminal of the NMOS transistor Tr8. To this end, the gate terminal of the ninth NMOS transistor Tr9 is connected to the third stage DST3, the source terminal is connected to the gate terminal of the eighth NMOS transistor Tr8, and the drain terminal of the second voltage source. It is connected to the power line which transmits (VSS).

The blocking unit 140d includes a tenth NMOS transistor Tr10.

The tenth NMOS transistor Tr10 turns off the operation of the discharge unit 140c by turning off the eighth NMOS transistor Tr8 of the discharge unit 140c in response to the scan pulse from the previous stage. Let's do it. That is, the tenth NMOS transistor Tr10 is formed at the gate terminal of the eighth NMOS transistor Tr8 of the discharge unit 140c in response to the first scan pulse Vout1 output from the first stage DST1. The eighth NMOS transistor Tr8 is turned off by supplying the second voltage source VSS. To this end, the gate terminal of the tenth NMOS transistor Tr10 is an output terminal of the output unit 140b of the second stage DST2 (that is, a drain terminal of the pull-up transistor Tru), and the pull-down transistor Trd Terminal connected to the source terminal), the source terminal is connected to the gate terminal of the eighth NMOS transistor Tr8, and the drain terminal is connected to the power supply line for transmitting the second voltage source VSS.

The operation of the shift register with a stage having such a circuit configuration will now be described in detail.

First, a start pulse output in an enable period is supplied to the first stage DST1 to enable the first stage DST1.

Thereafter, the first scan pulse Vout1 output from the first stage DST1 is supplied to the second stage DST2 in the first period. In detail, the first scan pulse Vout1 is supplied to gate terminals of the first, third, and tenth NMOS transistors Tr1, Tr3, and Tr10 provided in the second stage DST2. Then, the first, third, and tenth NMOS transistors Tr1, Tr3, and Tr10 of the second stage DST2 are turned on.

In this case, a first voltage source VDD is supplied to the first node Q of the second stage DST2 through the turned-on first NMOS transistor Tr1, and thus the first node Q is provided. Is charged. The pull-up transistor Tru having a gate terminal connected to the charged first node Q is turned on.

Meanwhile, the second voltage source VSS is supplied to the second node QB through the turned-on third NMOS transistor Tr3. Therefore, the second node QB of the second stage DST2 is discharged. The fifth NMOS transistor Tr5 and the pull-down transistor Trd having the gate terminal connected to the discharged second node QB are turned off.

The second voltage source VSS is supplied to the gate terminal of the eighth NMOS transistor Tr8 through the turned-on tenth NMOS transistor Tr10. As a result, the eighth NMOS transistor Tr8 is turned off. That is, since the tenth NMOS transistor Tr10 of the blocking unit 140d operates, the eighth NMOS transistor Tr8 of the discharge unit 140c is turned off. In other words, during the first period during which the first node Q is charged, the eighth NMOS transistor Tr8 is turned off. Thus, the first node Q is stably charged.

Thereafter, when the second clock pulse CLK2 is supplied to the source terminal of the turned-up pull-up transistor Tru in the second period, the pull-up transistor Tru receives the second clock pulse CLK2 as a second scan pulse. Output as (Vout2). The output second scan pulse Vout2 is supplied to the second gate line, the first stage DST1, and the third stage DST3.

During the second period, the third stage DST3 supplied with the second scan pulse Vout2 charges its first node Q in the same manner as the second stage DST2. Thereafter, in the third period, the third stage DST3 outputs the third clock pulse CLK3 as the third scan pulse Vout3. The output third scan pulse Vout3 is supplied to the third gate line, the second stage DST2, and the first stage DST1.

Meanwhile, the third clock pulse CLK3 output in the third period is also supplied to the second stage DST2. Specifically, the third clock pulse CLK3 is supplied to the gate terminals of the fourth and ninth NMOS transistors Tr4 and Tr9 provided in the second stage DST2, respectively. Therefore, in the third period, the fourth and ninth NMOS transistors Tr4 and Tr9 of the second stage DST2 are turned on. Through the turned-on fourth NMOS transistor Tr4, the first voltage source VDD is supplied to the second node QB of the second stage DST2. Therefore, the second node QB of the second stage DST1 is charged with the first voltage source VDD. The fifth NMOS transistor Tr5 and the pull-down transistor Trd having the gate terminal connected to the charged second node QB are turned on. At this time, the second voltage source VSS is supplied to the first node Q through the turned-on fifth NMOS transistor Tr5 to discharge the first node Q of the second stage DST2. . The second voltage source VSS is supplied to the second gate line through the turned-on pull-down transistor Trd.

Meanwhile, the second voltage source VSS is supplied to the gate terminal of the eighth NMOS transistor Tr8 through the turned-on ninth NMOS transistor Tr9. Then, the eighth NMOS transistor Tr8 provided in the second stage DST2 is turned off.

Meanwhile, the third scan pulse Vout3 output from the third stage DST3 in the third period is also supplied to the sixth NMOS transistor Tr6 of the second stage DST2. Then, the sixth NMOS transistor Tr6 of the second stage DST2 is turned on. The second voltage source VSS is supplied to the first node Q of the second stage DST2 through the turned-on sixth NMOS transistor Tr6. Therefore, in the third period, the first node Q of the second stage DST2 is discharged.

That is, in the third period, the first node Q of the second stage DST2 is discharged, and the eighth NMOS transistor Tr8 of the second stage DST2 is turned off.

Next, in the fourth period, the fourth stage DST4 outputs the fourth clock pulse CLK4 as the fourth scan pulse Vout4. The fourth scan pulse Vout4 is supplied to the fourth gate line, the third stage DST3, and the fifth stage. The fourth clock pulse CLK4 output in this fourth period is also supplied to the second stage DST2. Specifically, the fourth clock pulse CLK4 output in the fourth period is supplied to the gate terminal of the seventh NMOS transistor Tr7 provided in the second stage DST2. Then, the seventh NMOS transistor Tr7 of the second stage DST2 is turned on. The fourth clock pulse CLK4 is supplied to the gate terminal of the eighth NMOS transistor Tr8 provided in the second stage DST2 through the turned-on seventh NMOS transistor Tr7. Then, the eighth NMOS transistor Tr8 is turned on. Through this turned-on eighth NMOS transistor Tr8, the second voltage source VSS is supplied to the first node Q of the second stage DST2, and thus, the first of the second stage DST2. Node Q is discharged. As a result, the first node Q of the second stage DST2 is discharged whenever the fourth clock pulse CLK4 is output. In this case, the tenth NMOS transistor Tr10 of the blocking unit 140d may be charged with the fourth NMOS transistor Tr4 at a time point (first period) at which the first node Q of the second stage DST2 is charged. By turning off, the first node Q is prevented from being discharged. Therefore, the pull-up transistor Tru of the second stage DST2 can stably output the second scan pulse Vout2 in its output period (ie, the second period). After this output period, as described above, the first node Q of the second stage DST2 is periodically discharged by the fourth clock pulse CLK4.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The shift register according to the present invention as described above has the following effects.

The shift register according to the present invention charges the first node by interrupting the operation of the discharge unit in response to a scan pulse output from the pull-up switching element and a discharge unit for discharging the first node of each stage every clock pulse. It is configured to include a blocking unit for maintaining in a state. That is, each stage included in the shift register according to the present invention receives a scan pulse outputted from itself and maintains its first node in a charged state. On the other hand, each stage prevents the coupling phenomenon by discharging its first node every time the clock pulse is input to the clock pulse inputted in a period not corresponding to the timing at which the scan pulse is output.

Claims (30)

And sequentially supplying scan pulses to sequentially activate gate lines of the liquid crystal panel, and supplying a first voltage source to the remaining periods except for when the scan pulses are supplied, and deactivating the gate lines. Each of the stages includes: a node controller configured to control charge and discharge states of the first node and the second node; A pull-up switching device configured to receive first clock pulses periodically supplied and output a first clock pulse supplied at a timing at which the first node is charged as the scan pulse; A pull-down switching element configured to output an input first voltage source in response to a state of charge of the second node; A discharge unit configured to discharge the first node to the first voltage source at every first clock pulse; And, And a blocking unit for holding the first node in a charged state by interrupting an operation of the discharge unit in response to a scan pulse output from the pull-up switching element. The method of claim 1, Node control unit of each stage, A first switching element for charging the first node with a second voltage source in response to a start pulse or a scan pulse from a previous stage; A second switching element for discharging the second node to the first voltage source in response to the first voltage source charged in the first node; A third switching element configured to discharge the second node to a first voltage source in response to the start pulse or a scan pulse from a previous stage; A fourth switching device for charging the second node with a second voltage source in response to a second clock pulse synchronized with a scan pulse output from a next stage; A fifth switching device configured to discharge the first node to a first voltage source in response to a second voltage source charged in the second node; And, And a sixth switching element for discharging said first node to a first voltage source in response to a scan pulse from a next stage. The method of claim 2, The discharge section of each stage, And a seventh switching device for discharging the first node to the first voltage source in response to the first clock pulse. The method of claim 3, wherein The discharge unit, And an eighth switching device which turns on the seventh switching device by supplying the first clock pulse to the gate terminal of the seventh switching device in response to the first clock pulse. register. The method of claim 4, wherein The discharge unit, And a ninth switching device for turning off the seventh switching device by supplying a first voltage source to the gate terminal of the seventh switching device in response to a clock pulse synchronized with a scan pulse from a next stage. A shift register characterized in that. The method of claim 5, The blocking unit, And a tenth switching device for turning off the seventh switching device by supplying a first voltage source to the gate terminal of the seventh switching device in response to the scan pulse output from the pull-up switching device. Shift register. The method of claim 1, Node control unit of each stage, A first switching element for charging the first node with a second voltage source in response to the scan pulse from the previous stage; And, And a second switching element for discharging the first node to a first voltage source in response to a scan pulse output from a next stage. The method of claim 7, wherein The discharge section of each stage, And a third switching device for discharging a first node to a first voltage source in response to the first clock pulse. The method of claim 8, The discharge unit, And a fourth switching device which turns on the third switching device by supplying the first clock pulse to the gate terminal of the third switching device in response to the first clock pulse. register. The method of claim 9, The discharge unit, In response to the second clock pulse synchronized with the scan pulse from the next stage, a fifth switching device for turning off the third switching device by supplying a first voltage source to the gate terminal of the third switching device. Shift registers, characterized in that configured to include. The method of claim 10, The blocking unit, And a sixth switching device which turns off the third switching device by supplying a first voltage source to the gate terminal of the third switching device in response to the scan pulse output from the pull-up switching device. Shift register. And sequentially supplying scan pulses to sequentially activate gate lines of the liquid crystal panel, and supplying a first voltage source to the remaining periods except for when the scan pulses are supplied, and deactivating the gate lines. A node control unit configured to control the charge / discharge states of the first node, the second node, and the third node; A pull-up switching device configured to receive first clock pulses periodically supplied and output a first clock pulse supplied at a timing at which the first node is charged as the scan pulse; A first pull-down switching device configured to output a first voltage source input in response to a charging state of the second node; A second pull-down switching device configured to output a first voltage source input in response to a charging state of the third node; A discharge unit configured to discharge the first node to the first voltage source at every first clock pulse; And, And a blocking unit which maintains the first node in a charged state by interrupting an operation of the discharge unit in response to a first clock pulse corresponding to a scan pulse to be currently output among the first clock pulses. Shift register. The method of claim 12, Node control unit of each stage, A first switching device for charging the first node to a second voltage in response to a start pulse or a scan pulse from a previous stage; A second switching element for discharging the second node to a first voltage source in response to the start pulse or a scan pulse from a previous stage; A third switching element for discharging the third node to a first voltage source in response to the start pulse or a scan pulse from a previous stage; A fourth switching element configured to charge or discharge the second node to the third voltage source in response to a third voltage source having a different polarity every frame; A fifth switching element configured to discharge the third node to the first voltage source in response to the positive third voltage source; A sixth switching element configured to discharge or charge the third node to the fourth voltage source in response to a fourth voltage source having a phase inverted from the third voltage source; A seventh switching element configured to discharge the second node to the second voltage source in response to the positive fourth voltage source; An eighth switching element configured to discharge the second node to the first voltage source in response to the second voltage source applied to the first node; A ninth switching element configured to discharge the third node to the first voltage source in response to the second voltage source applied to the first node; A tenth switching element discharging the first node to a first voltage source in response to a third voltage source charged in the second node; An eleventh switching element discharging the first node to a first voltage source in response to a fourth voltage source charged to the third node; And, And a twelfth switching element for discharging said first node to a first voltage source in response to a scan pulse from a next stage. The method of claim 13, The discharge section of each stage, And a thirteenth switching device discharging a first node to a first voltage source in response to the first clock pulse. The method of claim 14, The discharge unit, And a fourteenth switching device configured to turn on the thirteenth switching device by supplying the first clock pulse to the gate terminal of the thirteenth switching device in response to the first clock pulse. register. The method of claim 15, The discharge unit, And a fourteenth switching device that turns off the thirteenth switching device by supplying a first voltage source to the gate terminal of the thirteenth switching device in response to a second clock pulse synchronized with a scan pulse from a next stage. The shift register, characterized in that configured. The method of claim 16, The blocking unit, And a fifteenth switching device which turns off the thirteenth switching device by supplying a first voltage source to the gate terminal of the thirteenth switching device in response to a scan pulse output from the pull-up switching device. Shift register. And sequentially supplying scan pulses to sequentially activate gate lines of the liquid crystal panel, and supplying a first voltage source to the remaining periods except for when the scan pulses are supplied, and deactivating the gate lines. Each of the stages includes: a node controller configured to control charge and discharge states of the first node and the second node; A pull-up switching device configured to receive first clock pulses periodically supplied and output a first clock pulse supplied at a timing at which the first node is charged as the scan pulse; A pull-down switching element configured to output an input first voltage source in response to a state of charge of the second node; A discharge unit configured to discharge the first node to the first voltage source at every first clock pulse; And, And a blocking unit for holding the first node in a charged state by shutting off an operation of the discharge unit in response to a second clock pulse output before the first clock pulse. The method of claim 18, Node control unit of each stage, A first switching element for charging the first node with a second voltage source in response to the scan pulse from the previous stage; And, And a second switching element for discharging the first node to a first voltage source in response to a scan pulse output from a next stage. The method of claim 19, The discharge section of each stage, And a third switching element for discharging the first node to a first voltage source in response to a third clock pulse that is phase delayed by at least two clock pulse widths than the first clock pulse. The method of claim 20, The discharge unit, And a fourth switching device which turns on the third switching device by supplying the third clock pulse to the gate terminal of the third switching device in response to the third clock pulse. register. The method of claim 21, The discharge unit, In response to the fourth clock pulse synchronized with the scan pulse from the next stage, a fifth switching device for turning off the third switching device by supplying a first voltage source to the gate terminal of the third switching device is further included. Shift registers, characterized in that configured to include. The method of claim 22, The blocking unit, And a sixth switching device which turns off the third switching device by supplying a first voltage source to the gate terminal of the third switching device in response to the scan pulse output from the pull-up switching device. Shift register. The method of claim 18, Node control unit of each stage, A first switching element for charging the first node with a second voltage source in response to a start pulse or a scan pulse from a previous stage; A second switching element for discharging the second node to the first voltage source in response to the first voltage source charged in the first node; A third switching element configured to discharge the second node to a first voltage source in response to the start pulse or a scan pulse from a previous stage; A fourth switching device for charging the second node with a second voltage source in response to a second clock pulse synchronized with a scan pulse output from a next stage; A fifth switching device configured to discharge the first node to a first voltage source in response to a second voltage source charged in the second node; And, And a sixth switching element for discharging said first node to a first voltage source in response to a scan pulse from a next stage. The method of claim 24, The discharge section of each stage, And a seventh switching element for discharging the first node to the first voltage source in response to the third clock pulse having a phase delay of at least two clock pulse widths than the first clock pulse. The method of claim 25, The discharge section of each stage, And an eighth switching element which turns on the seventh switching element by supplying the third clock pulse to the gate terminal of the seventh switching element in response to the third clock pulse. register. The method of claim 26, The discharge section of each stage, And a ninth switching device that turns off the seventh switching device by supplying a first voltage source to the gate terminal of the seventh switching device in response to the fourth clock pulse synchronized with the scan pulse from the next stage. The shift register, characterized in that configured. The method of claim 27, The blocking unit of each stage, And a tenth switching device for turning off the seventh switching device by supplying a first voltage source to the gate terminal of the seventh switching device in response to the scan pulse output from the pull-up switching device. Shift register. And sequentially supplying scan pulses to sequentially activate the gate lines of the liquid crystal panel, and supplying a first voltage source for a period other than the time when the scan pulses are supplied to deactivate the gate lines. The stage receives a node controller for controlling charge and discharge states of the first node and the second node, and clock pulses periodically supplied, and scans the clock pulses supplied at a timing when the first node is in a charged state. In the driving method of the shift register comprising a pull-up switching device for outputting a pulse and a pull-down switching device for outputting a first voltage source input in response to the state of charge of the second node, The first node is discharged whenever the clock pulse is applied to the pull-up switching device, and the first node is kept in a charged state when the clock pulse is outputted as a scan pulse through the pull-up switching device. Shift register drive method. And sequentially supplying scan pulses to sequentially activate the gate lines of the liquid crystal panel, and supplying a first voltage source for a period other than the time when the scan pulses are supplied to deactivate the gate lines. The stage receives a node control unit for controlling the charge / discharge states of the first node, the second node, and the third node, and first clock pulses that are periodically supplied, and is supplied at a timing when the first node is in a charged state. A pull-up switching element for outputting a first clock pulse to be used as the scan pulse, a first pull-down switching element for outputting a first voltage source input in response to a state of charge of the second node, and a state of charge of the third node In response to, driving a shift register configured to include a second pull-down switching element for outputting an input first voltage source. In law, The first node is discharged whenever the clock pulse is applied to the pull-up switching device, and the first node is kept in a charged state when the clock pulse is outputted as a scan pulse through the pull-up switching device. Shift register drive method.

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