KR101535820B1 - Shift register - Google Patents

Abstract

The present invention relates to a shift register capable of preventing an image quality deterioration due to a variation of a polling time between scan pulses, and more particularly, to a shift register in which scan pulses The polling time can be kept the same.

Shift register, liquid crystal display, scan pulse, stage, AC voltage, polling time

Description

SHIFT REGISTER {SHIFT REGISTER}

The present invention relates to a shift register, and more particularly, to a shift register capable of preventing image quality deterioration due to a variation in polling time between scan pulses.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged in an intersecting manner, and a pixel region is located in an area defined by vertically intersecting the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed on the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) as a switching element. The thin film transistor is turned on by a scan pulse applied to a gate terminal via the gate line so that a data signal of the data line is charged to the pixel voltage.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, And a power supply unit for supplying various driving voltages used in the plasma display apparatus.

The gate driver includes a shift register for sequentially supplying scan pulses to the gate lines to sequentially drive the pixels on the liquid crystal panel by one line. The shift register includes a plurality of stages for outputting scan pulses.

On the other hand, in a shift register structure having a structure sharing a node, there is a problem that a deviation occurs between an output waveform of a scan pulse output from an odd-numbered stage and an output waveform of a scan pulse output from an even-numbered stage. This will be described in more detail as follows.

1 is a diagram showing a voltage waveform and a scan pulse waveform of an enable node in an odd-numbered stage, a voltage waveform of an enable node in an even-numbered stage, and a waveform of a scan pulse, The waveforms of the scan pulses output from the odd-numbered stages and the output characteristics of the scan pulses output from the even-numbered stages are compared.

1 (a) shows the voltage waveform of the enable node and the waveform of the scan pulse in the odd-numbered stages. As shown in Fig. 1 (a), when the scan pulse is changed from a high voltage to a low voltage The voltage of the enable node is not changed to the low voltage at one time and is discharged at the low voltage twice. Therefore, since this enable node is not rapidly discharged, there is a sufficient time for the scan pulse to transition from a high voltage to a low voltage. Therefore, as shown in FIG. 2, the polling time of the scan pulse O output from the odd-numbered stage is statistically short.

On the other hand, FIG. 1 (b) shows the voltage waveform of the enable node and the waveform of the scan pulse in the even-numbered stages. As shown in FIG. 1 (b) The voltage of the enable node changes directly from the high voltage to the low voltage at the point of time when the voltage is changed to the low voltage so that the scan pulse does not have enough time to transit from the high voltage to the low voltage. Therefore, as shown in FIG. 2, the polling time of the scan pulse E outputted from the even-numbered stage rotor is relatively long.

On the other hand, FIG. 1 (c) shows the voltage state of the disable node, and the disable node is held at the low voltage while the enable node is maintained at the high voltage.

In this way, in the conventional shift register, a difference occurs between the output characteristics of the scan pulse output from the odd-numbered stages and the output characteristics of the scan pulses outputted to the even-numbered stage rotors, and the odd- The voltage deviation between the even-numbered gate lines connected to the first stage is generated. This results in an image quality difference between the pixels connected to the odd gate lines and the pixels connected to the even gate lines, resulting in image quality deterioration.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a method of driving gate lines by using two shift registers, The present invention provides a shift register that can maintain the same polling time of scan pulses.

According to an aspect of the present invention, there is provided a shift register including: a first shift register for sequentially supplying scan pulses to one side of gate lines; A second shift register for sequentially supplying scan pulses to the other side of the gate lines; At least one A stage provided in the first shift register comprises an enable node; A pull-up switching element for outputting the scan pulse according to a logic state of the enable node; At least two disable nodes; At least two pulldown switching elements connected to each of the disable nodes for outputting an off voltage according to a logic state of each disable node; And a node control unit for controlling the logical states of the enable node and the disable nodes provided in the node and the logic state of the disable node provided in the other node, At least one B stage provided in the second shift register comprises an enable node; A pull-up switching element for outputting the scan pulse according to a logic state of the enable node; At least two disable nodes; At least two pulldown switching elements connected to each of the disable nodes for outputting an off voltage according to a logic state of each disable node; And a node control unit for controlling the logical states of the enable node and the disable nodes provided in the node and the logic state of the disable node provided in the other node, The node controller provided in the A stage of the first shift register connected to the arbitrary gate line uses the first AC voltage to set the logic states of the enable node and the disable node provided in the node, Controls a logic state of a disable node included in the node; The node controller provided in the B stage of the second shift register connected to the arbitrary gate line uses the second AC voltage to compare the logic states of the enable node and the disable node provided in the B stage, Controlling a logic state of a disable node provided in the stage together; The first AC voltage has an inverted phase with respect to the second AC voltage.

Numbered stage A of the first shift register connected to the odd-numbered gate lines uses the first AC voltage to set the logical states of the enable node and the disable nodes provided in the node, Controlling a logic state of a disable node provided in the stage together; The node controller included in the even-numbered stage A of the first shift register connected to the even-numbered gate line uses the second AC voltage to set the logical states of the enable node and the disable node provided therein, Controlling a logic state of a disable node provided in the stage together; Numbered B stages of the second shift register connected to odd-numbered gate lines uses the second AC voltage to set the logic states of the enable node and the disable node provided therein and the logic states of the enable node and the disable node, Controlling a logic state of a disable node provided in the stage together; The node controller included in the even-numbered stage B of the second shift register connected to the even-numbered gate line uses the first AC voltage to compare the logic state of the enable node and the disable nodes provided in the node, And a logic state of a disable node provided in another stage.

Each of the A stages provided in the first shift register includes a first disable node, a first pull-down switching element connected to the first disable node, a second disable node, and a second disable node And a second pull-down switching element connected to the second pull-down switching element; The 2n-3 (n is a natural number equal to or greater than 2) th stage A node control unit controls the logical states of the enable node and the first disable node included in the 2n-3th A stage, Controlling a logic state of a first disable node provided in a second A stage; The node controller included in the (2n-2) th stage A controls the logical states of the enable node and the second disable node included in the (2n-2) th stage, Controlling a logic state of a provided second disable node; Each B stage included in the second shift register includes a first disable node, a first pull-down switching element connected to the first disable node, a second disable node, and a second disable node And a second pull-down switching element connected to the second node; 2n-3 (n is a natural number of 2 or more) B stages controls the logical state of the enable node and the first disable node provided in the (2n-3) th B stage, Controlling a logic state of a first disable node provided in a second B stage; The node controller included in the (2n-2) th B stage controls the logic states of the enable node and the second disable node provided in the (2n-2) th B stage, And controls the logical state of the provided second disable node.

The first disable node provided in the (2n-3) th stage and the first disable node provided in the (2n-2) th A stage are electrically connected to each other; The second disable node provided in the (2n-2) th stage and the second disable node provided in the (2n-3) th A stage are electrically connected to each other; The first disable node provided in the (2n-3) th B stage and the first disable node provided in the (2n-2) th B stage are electrically connected to each other; The second disable node provided in the (2n-2) th B stage and the second disable node provided in the (2n-3) th B stage are electrically connected to each other.

Wherein the node controller provided in the (2n-3) th stage includes a logic state of the first disable node provided in the (2n-3) th stage and a logic state of the first disable node provided in the Controlling a logic state to the first alternating-current voltage; Wherein the node controller provided in the (2n-2) th stage further includes a logic state of the second disable node provided in the (2n-2) th stage and the second disable node provided in the Controlling the second AC voltage; The node controller included in the (2n-3) th B stage may include a logic state of the first disable node provided in the (2n-3) th B stage and a first disable Controlling the logic state of the second node to the second AC voltage; The node control unit provided in the (2n-2) th B-stage may set the logical state of the second disable node provided in the (2n-2) th B stage and the second disable node provided in the And the second AC voltage is controlled by the first AC voltage.

The 2n-1 st stage and the 2n th A stage are enabled in response to a scan pulse from the (2n-3) th stage and are disabled in response to a scan pulse from the (2n + 2) th stage; The (2n-3) th stage and the (2n-2) th A stage are disabled in response to a scan pulse from the 2n-th stage; The (2n + 1) th stage and the (2n + 2) th A stage are enabled in response to the scan pulse from the (2n-1) th stage; The 2n-1 th B stage and the 2n th B stage are enabled in response to the scan pulse from the (2n-3) th B stage and are disabled in response to the scan pulse from the (2n + 2) th B stage; The 2n-3 th B stage and the 2n-2 th B stage are disabled in response to the scan pulse from the 2n th B stage; The (2n + 1) th B stage and the (2n + 2) th B stage are enabled in response to the scan pulse from the (2n-1) th B stage.

The node control unit provided in the (2n-1) -th stage includes a first switching device for charging the enable node with the first dc voltage in response to the scan pulse from the (2n-3) th stage; A second switching element for discharging the enable node to a second direct current voltage in response to a first alternating voltage supplied to the first disable node; Stage A stage to the second DC voltage in response to the second AC voltage supplied to the second disable node of the (2n-1) th stage through the 2n-th stage A A third switching element; A fourth switching element for discharging the enable node to a second DC voltage in response to a scan pulse from the (2n + 2) th stage; A fifth switching device that turns on or off in response to the first AC voltage and charges the common node with the first AC voltage upon turning on; A sixth switching element for discharging the common node to a second direct-current voltage in response to a first direct-current voltage charged in the enable node; And a seventh node for charging the first disable node of the 2n-1 st stage and the first disable node of the 2n th A stage with the first alternating voltage in response to the first alternating voltage supplied to the common node, A switching element; Stage A stage and the first disable node of the 2 < n > A-stage to the second DC voltage in response to the scan pulse from the (2n-3) device; And a node for discharging the first disable node of the 2n-1 st stage and the first disable node of the 2n th A stage to a second dc voltage in response to the first dc voltage charged to the enable node, The ninth switching element; The node control unit provided in the (2n-1) th B stage includes a first switching device for charging the enable node with the first dc voltage in response to the scan pulse from the (2n-3) th B stage; A second switching element for discharging the enable node to a second DC voltage in response to a first AC voltage supplied to the first disable node; And discharging the enable node of the (2n-1) th B stage to the second DC voltage in response to the second AC voltage supplied to the second disable node of the (2n-1) th B stage through the 2n th B stage A third switching element; A fourth switching element for discharging the enable node to a second DC voltage in response to a scan pulse from the (2n + 2) th B stage; A fifth switching device that turns on or off in response to the first AC voltage and charges the common node with the first AC voltage upon turning on; A sixth switching element for discharging the common node to a second direct-current voltage in response to a first direct-current voltage charged in the enable node; Stage B stage and the first disable node of the 2 < n > B stage in response to the first alternating-current voltage supplied to the common node, A switching element; The eighth switching for discharging the first disable node of the (2n-1) th B stage and the first disable node of the (2n) th B stage to the second DC voltage in response to the scan pulse from the (2n-3) device; And a node for discharging the first disable node of the 2n-1th B stage and the first disable node of the 2n th B stage to the second DC voltage in response to the first DC voltage charged to the enable node, The ninth switching element.

The 2n-1st A stages among the A stages provided in the first shift register are supplied with the first AC voltage, the 2nth A stages receive the second AC voltage; The 2n-1th B stages among the B stages provided in the second shift register are supplied with the first AC voltage, the 2nth B stages receive the second AC voltage;

A 2n-th stage of the first shift register supplies a scan pulse to one side of an n-th gate line; And, the (2n-1) th B stage of the second shift register supplies a scan pulse to the other side of the nth gate line.

A scan pulse from the first A stage and a scan pulse from the last B stage among the A stages are not supplied to the gate line.

A shift register for sequentially supplying a scan pulse to one side of the gate lines; At least one stage provided in the shift register comprises an enable node; A pull-up switching element for outputting the scan pulse according to a logic state of the enable node; At least two disable nodes; At least two pulldown switching elements connected to each of the disable nodes for outputting an off voltage according to a logic state of each disable node; And a node control unit for controlling the logical states of the enable node and the disable nodes provided in the node and the logic state of the disable node provided in the other node, A node controller provided in a stage connected to an arbitrary gate line may use any one of the first AC voltage and the second AC voltage to set the logic state of the enable node and the disable node provided in the node, Controlling a logic state of a disable node provided in another stage together; The first AC voltage having an inverted phase relative to the second AC voltage; The first AC voltage and the second AC voltage are supplied to each stage at random, and AC voltages different from each other are supplied to the 2n-1st stage and the 2nth stage.

The shift register according to the present invention has the following effects.

The shift register according to the present invention supplies an opposite AC voltage to the A stage for supplying a scan pulse to one side of one gate line and the B stage for supplying a scan pulse to the other side of the gate line, Keep the polling time of the pulse the same. Thus, it is possible to prevent deterioration of image quality.

FIG. 3 is a diagram illustrating a shift register according to a first embodiment of the present invention. FIG. 4 is a diagram illustrating the configuration of stages provided in the first shift register SR1 of FIG. 3. FIG. 2 shift register SR2 according to an embodiment of the present invention. 6 is a diagram showing waveforms of an input signal supplied to each stage of FIG. 4 and an output signal output from each stage.

As shown in FIG. 3, the shift register according to the first embodiment of the present invention is located at one side of the gate lines GL1, GL2, GL3, A first shift register SR1 for sequentially supplying scan pulses to one side of each of the gate lines GL1, GL2, GL3, ..., And a second shift register SR2 for sequentially supplying scan pulses to the other sides of the scan lines GL1, GL2, GL3,.

The first shift register SR1 is connected to one side of the gate lines GL1, GL2, GL3, ... and sequentially scans one side of the gate lines GL1, GL2, GL3, (AST1, AST2, AST3, ...) for supplying pulses. The second shift register SR2 is connected to the other side of the gate lines GL1, GL2, GL3, ... and sequentially connects the other side of the gate lines GL1, GL2, GL3, And a plurality of B stages for supplying scan pulses to the scan electrodes.

Particularly, the A stage and the B stage connected to the same gate line are supplied with an AC voltage which is opposite to each other. For example, the first A stage connected to one side of the first gate line GL1 is supplied with the first AC voltage Vac1, while the first B stage connected to the other side of the first gate line GL1, Is supplied with the second AC voltage (Vac2). The first AC voltage and the second AC voltage (Vac1, Vac2) are AC signals having a positive polarity or a negative polarity in a p frame period (p is a natural number) Has a phase inverted by 180 degrees with respect to the second AC voltage (Vac2).

At least each A stage included in the first shift register SR1 includes an enable node Q, as shown in FIG. 4; A pull-up switching element (Tru) for outputting the scan pulse according to a logic state of the enable node (Q); At least two disable nodes (QB1, QB2); At least two pulldown switching elements (Trd1, Trd2) connected to each of the disable nodes (QB1, QB2) for outputting an off voltage according to a logic state of each of the disable nodes (QB1, QB2); The node control unit 205 for controlling both the logic state of the enable node Q and the disable nodes QB1 and QB2 provided in the node A and the logic state of the disable node included in itself and the other A stage ).

At least one B stage included in the second shift register SR2 includes an enable node Q, as shown in FIG. 5; A pull-up switching element (Tru) for outputting the scan pulse according to a logic state of the enable node (Q); At least two disable nodes (QB1, QB2); At least two pulldown switching elements (Trd1, Trd2) connected to each of the disable nodes (QB1, QB2) for outputting an off voltage according to a logic state of each of the disable nodes (QB1, QB2); A node control unit 205 for controlling the logic state of the enable node Q and the disable nodes QB1 and QB2 provided in the node B and the logic state of the disable node provided in the other B stage, ).

At this time, the node controller 205 provided in the odd-numbered stage A of the first shift register SR1 connected to the odd-numbered gate lines uses the first AC voltage Vac1 to enable the enable node Q ) And the nodes for disable (QB1, QB2) and the logic state of the node for disable provided in the other stages. The node controller 205 included in the even-numbered stage A of the first shift register SR1 connected to the even-numbered gate line uses the second AC voltage Vac2 to set the enable node Q ) And the nodes for disable (QB1, QB2) and the logic state of the node for disable provided in the other stages.

On the other hand, the node controller 205 provided in the odd-numbered stage B of the second shift register SR2 connected to the odd-numbered gate lines uses the second AC voltage Vac2 to enable the enable Q- The logic state of the node and the nodes for disable QB1 and QB2 and the logic state of the disable node provided for itself and another stage are controlled. The node controller 205 included in the even-numbered stage B of the second shift register SR2 connected to the even-numbered gate line uses the first AC voltage Vac1 to control the enable node Q ) And the nodes for disable (QB1, QB2) and the logic state of the node for disable provided in the other stages.

Here, the A stages provided in the first shift register SR1 will be described in detail.

Each of the A stages AST1, AST2, AST3, ... has an enable node Q, a pull-up switching element Tru connected to the enable node Q, a first disable node QB1, A first pull-down switching element Trd1 connected to the first disable node QB1, a second disable node QB2 and a second disable node QB2 connected to the second disable node QB2. Down switching element Trd2.

The node controller 205 included in the (2n-3) th stage (n is a natural number of 2 or more) of the (n-2) th stage is configured to charge the enable node Q and the first disable node QB1 / Discharging state and controls the charge / discharge state of the first disable node QB1 provided in the 2n-2 < th > stage.

The node control unit 205 provided in the second n-2 A stage sets the charge / discharge state of the enable node Q and the second disable node QB2 provided in the second n- And controls the charge / discharge state of the second disable node QB2 provided in the second n-3 < th > stage.

To this end, the first disable node QB1 of the second n-3 A stage and the first disable node QB1 of the second n-2 A stage are connected to each other, and the second n- The second disable node QB2 of the second n-2 < th > stage is electrically connected to the second disable node QB2 of the second n-2 &

For example, the node controller 205 included in the third A-stage AST3 may charge the enable node Q and the first disable node QB1 provided in the third A-stage AST3, / Discharge state and controls the charge / discharge state of the first disable node QB1 provided in the fourth A-stage AST4.

The node controller 205 included in the fourth A-stage AST4 may control the charging / discharging of the enable node Q and the second disable node QB2 provided in the fourth A-stage AST4, And controls the charge / discharge state of the second disable node QB2 provided in the third A-stage AST3.

To this end, the first disable node QB1 of the third A stage AST3 and the first disable node QB1 of the fourth A stage AST4 are connected to each other, and the fourth A The second disable node QB2 of the stage AST4 and the second disable node QB2 of the third A stage AST3 are electrically connected to each other.

Particularly, the node controller 205 included in the 2n-3 A stage can control the charging / discharging state of the first disable node QB1 provided in the 2 < n > -3 A stage and the charge / The charge / discharge state of the provided first disable node QB1 is controlled to the first AC voltage.

The node controller 205 included in the second n-2 A stage is connected to the second disable node QB2 provided in the second n-2 A stage and the second disable node QB2 provided in the second n- And the charge / discharge state of the node for disable QB2 is controlled to the second AC voltage.

That is, each node controller 205 included in the odd-numbered A stages AST1, AST3, AST5, ... among the A stages AST1, AST2, AST3, And each node controller 205 provided in the even-numbered A stages AST2, AST4, AST6, ... receives the second AC voltage Vac2.

Here, the first AC voltage (Vac1) and the second AC voltage (Vac2) are AC voltages whose voltages change in frames, and the first AC voltage (Vac1) is 180 degrees with respect to the second AC voltage Phase inverted form.

The A stages AST1, AST2, AST3, ... receive the first DC voltage Vdc1 and charge the enable node Q of their own, and supply the second DC voltage Vdc2 And outputs it as an off voltage.

Instead of the first DC voltage Vdc1, each of the A stages AST1, AST2, AST3, ... may be supplied with a scan pulse from the previous stage A to charge its enable node Q have.

Here, the first direct-current voltage Vdc1 denotes a positive polarity voltage, and the second direct-current voltage Vdc2 denotes a negative polarity voltage.

Each of the A stages AST1, AST2, AST3, ... thus configured is supplied with one of the first to fifth clock pulses CLK1 to CLK5, and supplies the supplied clock pulse as a scan pulse Output.

6, the first to fifth clock pulses CLK1 to CLK1 to CLK5 are delayed in phase by one pulse width to output the second clock pulse CLK2. The third clock pulse CLK3 is delayed by one pulse width from the second clock pulse CLK2 to be output, and the fourth clock pulse CLK2 is output with a phase delay of one pulse width from the first clock pulse CLK1, The third clock pulse CLK4 is delayed by one pulse width from the third clock pulse CLK3 and the fifth clock pulse CLK5 is output after being delayed by one pulse width from the fourth clock pulse CLK4 , The first clock pulse CLK1 is delayed by one pulse width from the fifth clock pulse CLK5 and output.

At this time, the first to fifth clock pulses CLK1 to CLK5 are sequentially output and are circulated. That is, the signals are sequentially output from the first clock pulse CLK1 to the fifth clock pulse CLK5, and then sequentially output from the first clock pulse CLK1 to the fifth clock pulse CLK5. Accordingly, the first clock pulse CLK1 is output in a period corresponding to the fifth clock pulse CLK5 and the second clock pulse CLK2.

Each of the first to fifth clock pulses CLK1 to CLK5 is continuously output with a constant period. Accordingly, when five clock pulses are used as described above, the first to fifth A stages AST1 to AST5 output the first to fifth clock pulses CLK1 to CLK5 as scan pulses.

Since the first to fifth clock pulses CLK1 to CLK5 are phase-delayed by one clock pulse as described above, the first to fifth clock pulses CLK1 to CLK5 are delayed by the first to fifth A- The scan pulses Von1 to Von5 are also delayed by one pulse width and output.

That is, the scan pulses Von1 to Von5 are sequentially output. Then, the sixth A-stage AST6 again outputs the first clock pulse CLK1 as the sixth scan pulse Vout6. At this time, the first clock pulse CLK1 outputted from the sixth A stage AST6 is a one-period delayed pulse from the first clock pulse CLK1 outputted from the first A stage AST1.

On the other hand, in order for each of the A-stages AST1, AST2, AST3, ... to output the scan pulse as described above, each of the A-stages AST1, AST2, AST3, , And each of the A stages AST1, AST2, AST3, ... must be in a disabled state in order to output an off voltage.

To this end, each of the A stages AST1, AST2, AST3, ... is enabled in response to a scan pulse from the previous stage A stage and disabled in response to a scan pulse from the subsequent stage A stage.

Specifically, the 2n-1 A stage and the 2n A stage are simultaneously enabled in response to the 2 < n > scan pulse from the 2 < n & Are simultaneously disabled in response to pulses.

The second n + 1 stage outputs the second n-1 scan pulse and supplies the second n + 1 scan pulse to the (2n + 1) th and (2n + 2) And the 2 < n + 2 > A stage simultaneously.

The enabled second n A stage outputs a second n scan pulse and supplies the second n scan pulse to the second n-3 and the second n-2 A stages, so that the second n-3 and the second n- A stage is simultaneously disabled.

For example, the third A stage AST3 and the fourth A stage AST4 are enabled simultaneously in response to the first scan pulse Vout1 from the first A stage AST1, AST6 in response to the sixth scan pulse Vout6.

The enabled third A stage AST3 outputs a third scan pulse Vout3 and supplies the third scan pulse Vout3 to the fifth and sixth A stages AST5 and AST6, The fifth and sixth A stages AST5 and AST6 are enabled at the same time.

The enabled fourth A stage AST4 outputs a fourth scan pulse Vout4 and supplies the fourth scan pulse Vout4 to the first and second A stages AST1 and AST2, The first and second A stages AST1 and AST2 are simultaneously disabled.

On the other hand, since the A stage does not exist in the first front stage of the first A stage AST1 and the second front stage of the second A stage AST2, the first and second A stages AST1 and AST2 are connected to the timing controller And is enabled in response to the start pulse VAST. For this reason, the second scan pulse Vout2 from the second A stage AST2 is supplied only to the second gate line GL2.

On the other hand, the start pulse VAST is output before the first clock pulse CLK1. That is, the start pulse VAST is output two clock pulses earlier than the first clock pulse CLK1. Also, the start pulse (VAST) is output only once in one frame. That is, the start pulse VAST is output first for every frame, and then the first to fifth clock pulses CLK1 to CLK5 are sequentially output.

The reason why the time difference between the start pulse VAST and the first clock pulse CLK1 is set to the two pulse widths is to match the output characteristics of all the A stages equally.

In other words, the odd-numbered A stages AST1, AST3, AST5, ... are enabled by the scan pulse from the A stage located second in front of the odd-numbered A stages AST2, AST4, AST6, ... ) Is enabled by the scan pulse from the A-stage located at the third preceding stage from itself. By controlling the start pulse (VAST) and the first clock pulse (CLK1) to be output with a time difference of two pulse widths, The first stage AST1 can be operated as if it is enabled by the scan pulse from the second stage A stage and the second stage AST2 can be operated as a scan pulse from the stage A at the third preceding stage Lt; / RTI >

Of course, although not shown in the drawing, the start pulse VAST and the first clock pulse CLK1 may be adjusted to be output with a time difference of one pulse width.

Since the B stages included in the second shift register SR2 have the same configuration as the A stages described above, their description will be omitted. That is, when the alphabet 'A stage' is changed to 'B stage' in the description of the A stages described above, the description is made for the B stages.

The circuit configuration of the A stages provided in the first shift register SR1 will now be described.

7 is a diagram showing a circuit configuration of a node control unit provided in the third and fourth A stages of the first shift register SR1 of FIG.

The second odd numbered stages AST2, AST4, AST6, ... and the odd numbered A stages (second n-1 st stages AST1, AST3, AST5, Have different configurations.

First, the node control unit 205 provided in the odd-numbered A stages (AST1, AST3, AST5, ...) has first to ninth switching elements Tr1 to Tr9 as shown in Fig. .

That is, the first switching device Tr1 provided in the (2n-1) th stage is connected to the enable node Q of the (2n-1) th stage in response to the scan pulse from the And charged with the DC voltage Vdc1.

For example, the first switching element Tr1 provided in the third A-stage AST3 of FIG. 7 is turned on in response to the first scan pulse Vout1 from the first A-stage AST1, AST3 is charged with the first DC voltage Vdc1.

To this end, the gate terminal of the first switching device Tr1 provided in the third A-stage AST3 is connected to the first A-stage AST1, and the drain terminal is connected to the first DC voltage Vdc1 And the source terminal is connected to the enable node Q of the third A stage AST3.

The second switching device Tr2 provided in the second n-1 A stage is turned on in response to the first AC voltage Vac1 supplied to the first disable node QB1 of the second n- -1 Discharge the enable node Q of the A stage to the second DC voltage Vdc2.

For example, the second switching device Tr2 provided in the third A stage (AST3) of FIG. 7 is connected to the first AC node (QB1) of the third A stage (AST3) (Q1) of the third A stage (AST3) to the second DC voltage (Vdc2) in response to the first DC voltage (Vac1).

To this end, the gate terminal of the second switching device Tr2 provided in the third A-stage AST3 is connected to the first disable node QB1 of the third A-stage AST3, Is connected to the enable node (Q) of the third A-stage (AST3), and the source terminal is connected to a power supply line for transmitting the second DC voltage (Vdc2).

The third switching device Tr3 provided in the second n-1 A stage is connected to the second AC voltage Vac2 supplied to the second disable node QB2 of the second n-1 A stage through the second nA stage (Q) of the second n-1 < th > stage to the second DC voltage (Vdc2) in response to the second DC voltage (Vdc2).

In other words, the third switching device Tr3 provided in the 2 < n > 1A stage responds to the second AC voltage Vac2 supplied to the second disable node QB2 of the 2 < The state of the second disable node QB2 provided in the second n-1 A stage is controlled by the second DC voltage Vdc2, And is controlled by the node control section 205 of the second nA stage.

For example, the third switching device Tr3 provided in the third A-stage AST3 of FIG. 7 is connected to the second disable node (AST3) of the third A-stage AST3 via the fourth A- (Q2) of the third A stage (AST3) to the second DC voltage (Vdc2) in response to the second AC voltage (Vac2) supplied to the second A stage (QB2).

To this end, the gate terminal of the third switching device Tr3 provided in the third A-stage AST3 is connected to the second disable node QB2 of the third A-stage AST3, Is connected to the enable node (Q) of the third A stage (AST3), and the source terminal is connected to a power supply line for transmitting the second DC voltage (Vdc2).

The fourth switching device Tr4 provided in the 2 < n > -1 A stage is connected to the enable node Q of the 2 < n > -1 A stage in response to the scan pulse from the 2 & And discharges to the voltage Vdc2.

For example, the fourth switching device Tr4 provided in the third A-stage AST3 of FIG. 7 is turned on in response to the sixth scan pulse Vout6 from the sixth A-stage AST6, AST3) to the second direct-current voltage (Vdc2).

To this end, the gate terminal of the fourth switching device Tr4 provided in the third A-stage AST3 is connected to the sixth A-stage AST6, and the drain terminal is connected to the drain of the third A- And the source terminal is connected to a power supply line for transmitting the second direct-current voltage Vdc2.

The fifth switching device Tr5 provided in the second n-1 A stage is turned on or off in response to the first AC voltage Vac1, (N) to the first AC voltage (Vac1).

For example, the fifth switching device Tr5 provided in the third A-stage AST3 of FIG. 7 is turned on or off in response to the first AC voltage Vac1, The common node N of the A stage AST3 is charged with the first AC voltage Vac1.

To this end, the gate terminal and the drain terminal of the fifth switching device Tr5 provided in the third A-stage AST3 are connected to the power source line for transmitting the first AC voltage (Vac1) 3A is connected to the common node N of the stage AST3.

The sixth switching device Tr6 provided in the second n-1 A stage is responsive to the first DC voltage Vdc1 charged in the enable node Q of the second n-1 A stage, And discharges the common node N of the 1 A stage to the second direct-current voltage Vdc2.

For example, the sixth switching device Tr6 provided in the third A-stage AST3 of FIG. 7 is connected to the first DC voltage Vdc1 charged in the enable node Q of the third A-stage AST3 ) Discharges the common node N of the third A stage AST3 to the second DC voltage Vdc2.

To this end, the gate terminal of the sixth switching device Tr6 provided in the third A-stage AST3 is connected to the enable node Q of the third A-stage AST3, Is connected to the common node N of the 3A stage (AST3), and the source terminal is connected to a power supply line for transmitting the second DC voltage (Vdc2).

The seventh switching device Tr7 provided in the second n-1 A stage is connected to the second n-1 A stage in response to the first AC voltage Vac1 supplied to the common node N of the second n- The first disable node QB1 of the stage and the first disable node QB1 of the second nA stage are charged with the first AC voltage Vac1.

That is, the seventh switching device Tr7 provided in the 2 < n > -1 A stage is in a state of the first disable node QB1 provided in the 2 < And controls the state of the disable node QB1 together.

For example, the seventh switching device Tr7 provided in the third A stage AST3 of FIG. 7 is connected to the first AC voltage Vac1 supplied to the common node N of the third A stage AST3 , The first disable node QB1 of the third A stage AST3 and the first disable node QB1 of the fourth A stage AST4 are charged with the first AC voltage Vac1 .

To this end, the gate terminal of the seventh switching device Tr7 provided in the third A-stage AST3 is connected to the common node N of the third A-stage AST3, and the drain terminal is connected to the first- Is connected to the power supply line for transmitting the voltage Vac1 and the source terminal is connected to the first disable node QB1 of the third A stage AST3.

The eighth switching device Tr8 provided in the 2 < n > -1 A stage is turned on in response to the scan pulse from the 2 < n > -3 A stage by the first disable node QB1 of the second n- And discharges the first disable node QB1 of the 2nA stage to the second DC voltage Vdc2.

That is, the eighth switching device Tr8 provided in the 2 < n > 1A stage is in a state of the first disable node QB1 provided in the 2 < And controls the state of the disable node QB1 together.

For example, the eighth switching device Tr8 provided in the third A stage AST3 of FIG. 7 is turned on in response to the first scan pulse Vout1 from the first A stage AST1, AST3 and the first disable node QB1 of the fourth A stage AST4 to the second DC voltage Vdc2.

To this end, the gate terminal of the eighth switching device Tr8 provided in the third A-stage AST3 is connected to the first A-stage AST1, and the drain terminal is connected to the gate of the third A- 1 disable node QB1, and the source terminal is connected to the power supply line for transmitting the second direct-current voltage Vdc2.

The ninth switching device Tr9 provided in the second n-1 A stage is responsive to the first DC voltage Vdc1 charged in the enable node Q of the second n-1 A stage, The first disable node QB1 of the 1 A stage and the first disable node QB1 of the second nA stage are discharged to the second DC voltage Vdc2.

That is, the ninth switching device Tr9 provided in the 2 < n > -1 A stage is in a state of the first disable node QB1 provided in the 2 < And the state of the node 1 for the disablement QB1.

For example, the ninth switching element Tr9 provided in the third A stage AST3 of FIG. 7 is connected to the first DC voltage Vdc1 charged in the enable node Q of the third A stage AST3 ) Discharges the first disable node QB1 of the third A stage AST3 and the first disable node QB1 of the fourth A stage AST4 to the second DC voltage Vdc2, .

To this end, the gate terminal of the ninth switching device Tr9 provided in the third A-stage AST3 is connected to the enabling node Q of the third A-stage AST3, Is connected to the first disable node QB1 of the 3A stage (AST3), and the source terminal is connected to the power supply line for transmitting the second DC voltage (Vdc2).

The pull-up switching device Tru provided in the (2n-1) -th stage responds to the first DC voltage (Vdc1) charged in the enable node (Q) of the second n- And outputs it as a (2n-1) th scan pulse. Then, this second (n-1) th scan pulse is supplied to the second (n-1) th gate line, the (2n + 1) th and the (2n + 2) th stages.

Here, the second n-1 scan pulse output from the 2 < n > -1 A stage drives the second n-1 gate line and simultaneously enables the 2n + 1 and 2n + 2 A stages.

For example, the pull-up switching element Tru provided in the third A-stage AST3 of FIG. 7 is connected to the first DC voltage Vdc1 charged in the enable node Q of the third A-stage AST3, And outputs the third clock pulse CLK3 as the third scan pulse Vout3 in response to the third clock pulse CLK3. The third scan pulse Vout3 is supplied to the third gate line GL3, the fifth A stage AST5, and the sixth A stage AST6.

To this end, the gate terminal of the pull-up switching device Tru provided in the third A-stage AST3 is connected to the enable node Q of the third A-stage AST3, 3 clock pulse CLK3 and the source terminal is connected to the third gate line GL3, the fifth A stage AST5 and the sixth A stage AST6.

The first pull-down switching device Trd1 provided in the second n-1 A stage is responsive to the first alternating-current voltage Vac1 charged in the first disable node QB1 of the second n- 2 DC voltage Vdc2 as an off voltage. Then, this off-voltage is supplied to the (2n-1) th gate line, the (2n + 1) th, and the (2n + 2)

For example, the first pull-down switching device Trd1 provided in the third A-stage AST3 of FIG. 7 is connected to the first AC voltage Vb1 charged in the first disable node QB1 of the third A- And supplies the off voltage to the third gate line GL3, the fifth A stage AST5, and the sixth A stage AST6 in response to the first DC voltage Vdc2, do.

To this end, the gate terminal of the first pull-down switching device Trd1 provided in the third A-stage AST3 is connected to the first disable node QB1 of the third A-stage AST3, Is connected to the power supply line for transmitting the second DC voltage Vdc2 and the drain terminal is connected to the third gate line GL3, the fifth A stage AST5 and the sixth A stage AST6.

The second pull-down switching device Trd2 provided in the second n-1 A stage is connected to the second AC voltage Vac2 charged in the second disable node QB2 of the second n- And outputs the second direct-current voltage Vdc2 as an off-voltage. Then, this off-voltage is supplied to the (2n-1) th gate line, the (2n + 1) th, and the (2n + 2)

That is, the second pull-down switching device Trd2 provided in the second n-1 A stage responds to the second alternating voltage Vac2 supplied to the second disable node QB2 of the second n- And the second DC voltage Vdc2 is output as an off voltage. At this time, the state of the second disable node QB2 provided in the second n-1 < th > stage is supplied to the node controller 205 of the second nA stage .

For example, the second pull-down switching device Trd2 provided in the third A-stage AST3 of Fig. 7 is connected to the second AC voltage V2 charged in the second disable node QB2 of the third A- The second DC voltage Vdc2 is output as a turn-off voltage in response to the second control signal Vac2 and the turn-off voltage is applied to the third gate line GL3, the fifth A stage AST5 and the sixth A stage AST6 Supply.

To this end, the gate terminal of the second pull-down switching device Trd2 provided in the third A-stage AST3 is connected to the second disable node QB2 of the third A-stage AST3, Is connected to the power supply line for transmitting the second DC voltage Vdc2 and the drain terminal is connected to the third gate line GL3, the fifth A stage AST5 and the sixth A stage AST6.

However, since the A stage does not exist in the first front stage of the first A stage AST1, the first and eighth switching devices Tr1 and Tr8 provided in the first A stage AST1 are connected to the timing controller And operates in response to the start pulse VAST.

On the other hand, the node control section 205 provided in the even-numbered A stages AST2, AST4, AST6, ... has first to ninth switching elements Tr1 to Tr9 as shown in Fig. 7 .

That is, the first switching device Tr1 provided in the second nA stage outputs the enable node Q of the second nA stage in response to the scan pulse from the second n-3A stage to the first direct-current voltage Vdc1 ).

For example, the first switching device Tr1 provided in the fourth A stage (AST4) of FIG. 7 is turned on in response to the first scan pulse (Vout1) from the first A stage (AST1) AST4) with the first DC voltage (Vdc1).

To this end, the gate terminal of the first switching device Tr1 provided in the fourth A-stage AST4 is connected to the first A-stage AST1, and the drain terminal thereof transmits the first DC voltage Vdc1 And the source terminal is connected to the enable node Q of the fourth A stage (AST4).

The second switching device Tr2 provided in the second nA stage is responsive to the first alternating voltage Vac1 supplied to the first disable node QB1 of the second nA stage through the second n- And discharges the enable node Q of the second nA stage to the second direct-current voltage Vdc2.

That is, the second switching device Tr2 provided in the second nA stage is turned on in response to the first alternating-current voltage Vac1 supplied to the first disable node QB1 of the second nA stage, The state of the first disable node QB1 provided in the second nA stage is the same as the state of the second n-1A stage And is controlled by the node control unit 205.

For example, the second switching device Tr2 provided in the fourth A stage AST4 of FIG. 7 is connected to the first disable node (AST4) of the fourth A stage AST4 via the third A stage AST3 Discharges the enable node Q of the fourth A stage AST4 to the second DC voltage Vdc2 in response to the first AC voltage Vac1 supplied to the first A stage QB1.

To this end, the gate terminal of the second switching device Tr2 provided in the fourth A-stage AST4 is connected to the first disable node QB1 of the fourth A-stage AST4, Is connected to an enable node (Q) of the fourth A stage (AST4), and a source terminal is connected to a power supply line for transmitting the second direct current voltage (Vdc2).

The third switching device Tr3 provided in the second nA stage is responsive to the second AC voltage Vac2 supplied to the second disable node QB2 of the second nA stage, And discharges the enable node Q to the second direct-current voltage Vdc2.

For example, the third switching element Tr3 provided in the fourth A stage AST4 of FIG. 7 is connected to the second AC voltage V2 supplied to the second disable node QB2 of the fourth A stage AST4, (Q2) of the fourth A stage (AST4) to the second DC voltage (Vdc2) in response to the second DC voltage (Vac2).

To this end, the gate terminal of the third switching device Tr3 provided in the fourth A stage AST4 is connected to the second disable node QB2 of the fourth A stage AST4, Is connected to the enable node (Q) of the fourth A stage (AST4), and the source terminal is connected to the power supply line for transmitting the second DC voltage (Vdc2).

The fourth switching device Tr4 provided in the second nA stage discharges the enable node Q to the second direct-current voltage Vdc2 in response to the scan pulse from the second (n + 2) th stage.

For example, the fourth switching device Tr4 provided in the fourth A stage (AST4) of FIG. 7 is turned on in response to the sixth scan pulse (Vout6) from the sixth A stage (AST6) AST4 to the second DC voltage Vdc2.

To this end, the gate terminal of the fourth switching device Tr4 provided in the fourth A stage AST4 is connected to the sixth A stage AST6, and the drain terminal is connected to the drain terminal of the fourth A stage AST4. And the source terminal is connected to a power supply line for transmitting the second direct-current voltage Vdc2.

The fifth switching device Tr5 provided in the second nA stage is turned on or off in response to the second AC voltage Vac2 and is turned on when the common node N of the second nA stage is turned on And is charged with the second AC voltage (Vac2).

For example, the fifth switching device Tr5 provided in the fourth A-stage AST4 of FIG. 7 is turned on or off in response to the second AC voltage Vac2, The common node N of the A stage AST4 is charged with the second AC voltage Vac2.

To this end, the gate terminal and the drain terminal of the fifth switching device Tr5 provided in the fourth A stage (AST4) are connected to the power source line for transmitting the second AC voltage (Vac2) Is connected to the common node N of the fourth A stage (AST4).

The sixth switching device Tr6 provided in the second nA stage is responsive to the first direct-current voltage Vdc1 charged in the enable node Q of the second nA stage, (N) to the second direct-current voltage (Vdc2).

For example, the sixth switching element Tr6 provided in the fourth A stage AST4 of FIG. 7 is connected to the first DC voltage Vdc1 charged in the enable node Q of the fourth A stage AST4 ) Discharges the common node N of the fourth A stage AST4 to the second DC voltage Vdc2.

To this end, the gate terminal of the sixth switching device Tr6 provided in the fourth A stage AST4 is connected to the enable node Q of the fourth A stage AST4, Is connected to the common node N of the 4A stage AST4, and the source terminal is connected to the power supply line for transmitting the second DC voltage Vdc2.

The seventh switching device Tr7 provided in the second nA stage is responsive to a second AC voltage Vac2 supplied to the common node N of the second nA stage to generate a second disable And the node QB2 for the second n-1 stage and the node QB2 for the second disable of the second n-1 stage are charged with the second alternating voltage Vac2.

That is, the seventh switching device Tr7 provided in the second nA stage is controlled by the state of the second disable node QB2 provided in the second nA stage and the state of the second disable node QB2 provided in the second n- And controls the state of the node for abuse QB2.

For example, the seventh switching device Tr7 provided in the fourth A stage AST4 of FIG. 7 is connected to the second AC voltage Vac2 supplied to the common node N of the fourth A stage AST4 The second disable node QB2 of the fourth A stage AST4 and the second disable node QB2 of the third A stage AST3 are charged with the second AC voltage Vac2 in response .

To this end, the gate terminal of the seventh switching device Tr7 provided in the fourth A-stage AST4 is connected to the common node N of the fourth A-stage AST4, and the drain terminal is connected to the second AC Is connected to the power supply line for transmitting the voltage Vac2 and the source terminal is connected to the second disable node QB2 of the fourth A stage AST4.

The eighth switch Tr8 provided in the second nA stage is responsive to the scan pulse from the second n-3 A stage to drive the second disable node QB2 and the second n-1 A And discharges the second disable node QB2 of the stage to the second direct-current voltage Vdc2.

That is, the eighth switching device Tr8 provided in the second nA stage is in the state of the second disable node QB2 provided in the second nA stage and the second disable node QB2 provided in the second n- And controls the state of the node for abuse QB2.

For example, the eighth switching element Tr8 provided in the fourth A stage AST4 of FIG. 7 is turned on in response to the first scan pulse Vout1 from the first A stage AST1, The second disable node QB2 of the third AST4 and the second disable node QB2 of the third A stage AST3 to the second DC voltage Vdc2.

To this end, the gate terminal of the eighth switching device Tr8 provided in the fourth A stage AST4 is connected to the first A stage AST1, and the drain terminal is connected to the gate of the third A stage AST3 2 disable node QB2, and the source terminal thereof is connected to the power supply line for transmitting the second direct-current voltage Vdc2.

The ninth switching device Tr9 provided in the second nA stage is responsive to the first direct-current voltage Vdc1 charged in the enable node Q of the second nA stage, And discharges the node for disable QB2 and the node for second disable QB2 of the second n-1 < th > stage to second DC voltage Vdc2.

That is, the ninth switching device Tr9 provided in the second nA stage is controlled by the state of the second disable node QB2 provided in the second nA stage and the second disable node QB2 provided in the second n- And controls the state of the node for disable QB2 together.

For example, the ninth switching element Tr9 provided in the fourth A stage AST4 of FIG. 7 is connected to the first DC voltage Vdc1 charged in the enable node Q of the fourth A stage AST4 ) Discharges the second disable node QB2 of the fourth A stage AST4 and the second disable node QB2 of the third A stage AST3 to the second DC voltage Vdc2, .

To this end, the gate terminal of the ninth switching device Tr9 provided in the fourth A-stage AST4 is connected to the enabling node Q of the fourth A-stage AST4, Stage AST4 is connected to the second disable node QB2 of the 4A stage AST4, and the source terminal is connected to the power supply line for transmitting the second DC voltage Vdc2.

The pull-up switching element Tru provided in the second nA stage receives the clock pulse in response to the first DC voltage Vdc1 charged in the enable node Q of the second nA stage, . Then, this second 2n scan pulse is supplied to the 2n-th gate line, the 2n-3, and the 2n-2A stages.

Here, the second n scan pulse output from the second n A stage drives the second n-gate line and simultaneously disables the second n-3 and the second n-2 A stages.

For example, the pull-up switching element Tru provided in the fourth A-stage AST4 of FIG. 7 has the first DC voltage Vdc1 charged in the enable node Q of the fourth A-stage AST4, And outputs the fourth clock pulse CLK4 as the fourth scan pulse Vout4 in response to the fourth clock pulse CLK4. Then, the fourth scan pulse Vout4 is supplied to the fourth gate line GL4, the first A stage AST1, and the second A stage AST2.

To this end, the gate terminal of the pull-up switching device Tru included in the fourth A stage AST4 is connected to the enable node Q of the fourth A stage AST4, Is connected to the clock transmission line for transmitting the clock pulse CLK4 and the source terminal is connected to the fourth gate line GL4, the first A stage AST1 and the second A stage AST2.

The first pull-down switching device Trd1 provided in the second nA stage is connected to the first AC voltage Vac1 charged in the first disable node QB1 of the second nA stage through the second n- And outputs the second direct-current voltage Vdc2 as a turn-off voltage in response. Then, this off-voltage is supplied to the 2n-th gate line, the 2n-3, and the 2n-2 A stages.

That is, the first pull-down switching device Trd1 provided in the second nA stage is responsive to the first AC voltage Vac1 supplied to the first disable node QB1 of the second nA stage, The state of the first disable node QB1 provided in the second nA stage is controlled by the node controller 205 of the second n-1 A stage.

For example, the first pull-down switching device Trd1 provided in the fourth A-stage AST4 of FIG. 7 is connected to the first AC voltage Vb1 charged in the first disable node QB1 of the fourth A- (AST1) and the second A stage (AST2) in response to the first direct current (Vac1), and outputs the second direct-current voltage (Vdc2) as an off-state voltage to the fourth gate line GL4, the first A- Supply.

To this end, the gate terminal of the first pull-down switching device Trd1 provided in the fourth A stage AST4 is connected to the first disable node QB1 of the fourth A stage AST4, Is connected to the power supply line for transmitting the second DC voltage Vdc2 and the drain terminal is connected to the fourth gate line GL4, the first A stage AST1 and the second A stage AST2.

The second pull-down switching device Trd2 provided in the second nA stage responds to the second AC voltage Vac2 charged in the second disable node QB2 of the second nA stage, Vdc2 as a turn-off voltage. Then, this off-voltage is supplied to the 2n-th gate line, the 2n-3, and the 2n-2 A stages.

For example, the second pull-down switching device Trd2 provided in the fourth A-stage AST4 of Fig. 7 is connected to the second AC voltage V2 charged in the second disable node QB2 of the fourth A- (AST1) and the second A stage (AST2) in response to the first direct current (Vac2) and outputs the second DC voltage (Vdc2) as an off voltage, Supply.

To this end, the gate terminal of the second pull-down switching device Trd2 provided in the fourth A stage AST4 is connected to the second disable node QB2 of the fourth A stage AST4, Is connected to the power supply line for transmitting the second DC voltage Vdc2 and the drain terminal is connected to the fourth gate line GL4, the first A stage AST1 and the second A stage AST2.

However, since the A stage does not exist in the second preceding stage of the second A stage AST2, the first and eighth switching devices Tr and Tr8 provided in the second A stage AST2 are connected to the timing controller And operates in response to the start pulse VAST.

8 is a diagram showing a circuit configuration of a node control unit provided in the third and fourth B stages of the second shift register SR2 of FIG.

The circuit configuration of the B stages included in the second shift register SR2 has the same circuit configuration as that of the A stages provided in the first shift register SR1 described above, and a description thereof will be omitted. That is, if the alphabet A stage is changed to the B stage in the description of the A stages described above, the description will be made of the B stages.

The operation of the first shift register SR1 according to the present invention will now be described.

The description will be made with reference to Figs. 6 and 7. Fig.

First, the operation of the first initial period T0A in the first frame will be described as follows.

During the first frame, the first AC voltage (Vac1) shows positive polarity and the second AC voltage (Vac2) shows negative polarity.

During the first initial period T0A, as shown in FIG. 3, only the start pulse VAST output from the timing controller is maintained in the high state, and the remaining clock pulses are held in the low state.

The start pulse VAST output from the timing controller is input to the first and second A stages AST1 and AST2.

That is, the start pulse VAST is supplied to the gate terminal of the first switching device Tr1 provided in the first A stage AST1 and the gate terminal of the eighth switching device Tr8.

The first and eighth switching elements Tr1 and Tr8 are turned on and the first DC voltage Vdc1 is supplied to the enable node Q via the first switching element Tr1 turned on, . Thus, the pull-up switching element Tru, the sixth switching element Tr6, and the ninth switching element Tr2, which are charged with the enable node Q and whose gate terminals are connected to the charged enable node Q, The element Tr9 is turned on.

Here, the second DC voltage Vdc2 is supplied to the first disable node QB1 through the turn-on eighth and ninth switching elements Tr8 and Tr9. The second switching element Tr2 discharges the first disable node QB1 by the second DC voltage Vdc2 and the gate terminal is connected to the first disable node QB1, The first pull-down switching element Trd1 is turned off.

Meanwhile, since the first AC voltage Vac1 is maintained in the positive polarity during the first frame, the fifth switching device Tr5 of the first A-stage AST1, which receives the first AC voltage Vac1, And maintains the turn-on state for one frame. The first AC voltage Vac1 is supplied to the common node N of the first A stage AST1 through the turn-on fifth switching element Tr5. Also, the second DC voltage Vdc2 output through the sixth switching element Tr6 turned on is also supplied to the common node N of the first A-stage AST1. That is, a positive first AC voltage (Vac1) and a negative second DC voltage (Vdc2) are simultaneously supplied to the common node (N) of the first A stage (AST1).

The channel width of the sixth switching element Tr6 for supplying the second DC voltage Vdc2 is set to be larger than the channel width of the fifth switching element Tr5 for supplying the first AC voltage Vac1 , The common node N of the first A stage AST1 is maintained at the second DC voltage Vdc2. Thus, the common node N is discharged, and the seventh switching device Tr7 of the first A stage AST1, to which the gate terminal is connected to the discharged common node N, is turned off.

Thus, the first A-stage AST1 charges its enable node Q in response to the start pulse VAST and discharges its first disable node QB1. That is, the first A stage AST1 is enabled.

Meanwhile, in the first initial period T0A, the second A stage AST2 is also supplied with the start pulse VAST. This will be described in more detail as follows.

That is, the start pulse VAST is supplied to the gate terminal of the first switching device Tr1 and the gate terminal of the eighth switching device Tr8 provided in the second A stage AST2.

The first and eighth switching elements Tr1 and Tr8 are turned on and the first DC voltage Vdc1 is applied to the second A stage AST2 through the first switching element Tr1 turned on. To the enable node Q of the node Q. Thus, the pull-up switching element Tru, the sixth switching element Tr6, and the ninth switching element Tr2, which are charged with the enable node Q and whose gate terminals are connected to the charged enable node Q, The element Tr9 is turned on.

The second DC voltage Vdc2 is supplied to the second disable node QB2 of the second A stage AST2 through the turn-on eighth and ninth switching elements Tr8 and Tr9. Therefore, the third switching device Tr3, in which the second disable node QB2 is discharged by the second DC voltage Vdc2 and the gate terminal is connected to the second disable node QB2, The second pull-down switching element Trd2 is turned off.

Meanwhile, since the second AC voltage (Vac2) is kept negative during the first frame, the fifth switching element (Tr5) of the second A stage (AST2) receiving the second AC voltage (Vac2) And maintains the turn-off state for one frame.

The second DC voltage Vdc2 outputted through the sixth switching element Tr6 turned on is supplied to the common node N of the second A stage AST2. Accordingly, the common node N of the second A stage AST2 is discharged by the second direct-current voltage Vdc2. Thus, the seventh switching device Tr7 of the second A stage AST2 to which the gate terminal is connected to the discharged common node N is turned off.

In this manner, in the first initial period T0A, the second A stage AST2 charges the enable node Q of its own in response to the start pulse VAST, And discharges the node QB2.

At this time, the first and second disable nodes QB1 and QB2 of the first A stage AST1 and the first and second disable nodes QB1 and QB2 of the second A stage AST2 are turned off The second disable node QB2 of the first A stage AST1 is in the same state as the second disable node QB2 of the second A stage AST2 because they are electrically connected to each other , The first disable node QB1 of the second A stage AST2 shows the same state as the first disable node QB1 of the first A stage AST1.

That is, the second disable node QB2 of the first A stage AST1 is connected to the second DC voltage Vdc2 supplied to the second disable node QB2 of the second A stage AST2 To indicate the discharge state. The first disable node QB1 of the second A stage AST2 is connected to the second DC voltage Vdc2 supplied to the first disable node QB1 of the first A stage AST1 To indicate the discharge state.

In other words, in the first initial period T0A, the first A stage AST1 charges its enable node Q and supplies its own first disable node QB1 and the second A stage < RTI ID = 0.0 > And discharges the first disable node QB1 of the second node AST2. In the first initial period T0A, the second A stage AST2 charges its enable node Q and supplies its own second disable node QB2 and the first A stage AST1 to the second disable node QB2.

Next, the operation during the second initial period T0B will be described as follows.

In the second initial period T0B, the start pulse VAST and all the clock pulses remain in the low state.

Therefore, during the second initial period T0B, the first and second A stages AST2 maintain the enabled state. On the other hand, since the start pulse VAST is changed to the low state in the second initial period T0B, the first and eighth switching elements Tr1 and Tr8 of the first and second A stages AST2 are turned off Turn-off state, whereby each enable node Q of the first and second A-stages AST2 is kept in a floating state. Therefore, the first DC voltage Vdc1 supplied to each enable node Q of the first and second A stages AST1 and AST2 in the first initial period T0A is supplied to each of the enable nodes Q).

The operation during the first period T1 will now be described.

In the first period T1, only the first clock pulse CLK1 is in the high state and the remaining clock pulses are in the low state.

Here, as the enable node Q of the first A-stage AST1 is kept in the constantly charged state by the first DC voltage Vdc1 applied during the first initial period T0A, the first A- The pull-up switching element Tru of the stage AST1 maintains the turn-on state. At this time, as the first clock pulse CLK1 is applied to the drain terminal of the turn-on pull-up switching device Tru, the first clock pulse CLK1 is applied to the enable node Q of the first A- The DC voltage Vdc1 is amplified by bootstrapping.

Therefore, the first clock pulse CLK1 applied to the drain terminal of the pull-up switching element Tru of the first A-stage AST1 is stably outputted through the source terminal of the pull-up switching element Tru. At this time, the output first clock pulse CLK1 is applied to the first gate line GL1 to function as a first scan pulse Vout1 for driving the first gate line GL1.

The first scan pulse Vout1 output from the first A stage AST1 in the first period T1 is also input to the third and fourth A stages AST3 and AST4. 4, the first scan pulse Vout1 is applied to the gate terminals of the first and eighth switching elements Tr1 and Tr8 provided in the third A stage AST3, Is input to the gate terminals of the first and eighth switching devices Tr1 and Tr8 provided in the A stage AST4.

Therefore, the third and fourth A stages AST3 and AST4 are simultaneously enabled in the first period T1. At this time, the third A stage AST3 operates in the same manner as the first A stage AST1 during the first initial period T0A described above, and the fourth A stage AST4 operates in the same manner as the first initial stage (AST2) for the second A stage (AST2) during the first time (T0A).

That is, the third A stage AST3 charges its enable node Q and supplies its first disable node QB1 and the first disable node AST4 of the fourth A stage AST4, (QB1). The fourth A stage AST4 charges the enable node Q of its own and supplies the second disable node QB2 of its own and the second disable node QST of the third A stage AST3, (QB2).

Next, the operation during the second period T2 will be described as follows.

During the second period T2, only the second clock pulse CLK2 remains high and the remaining clock pulses remain low, as shown in Fig.

This second clock pulse CLK2 is supplied to the enabled second A stage AST2. Specifically, the second clock pulse CLK2 is supplied to the drain terminal of the pull-up switching element Tru provided in the second A stage AST2. Therefore, the pull-up switching element Tru provided in the second A stage AST2 outputs the second clock pulse CLK2 as the second scan pulse Vout2. Then, the second scan pulse Vout2 is supplied to the second gate line GL2 to drive the second gate line GL2.

Next, the operation during the third period T3 will be described as follows.

During the third period T3, as shown in FIG. 3, only the third clock pulse CLK3 remains high and the remaining clock pulses remain low.

This third clock pulse CLK3 is supplied to the enabled third A stage AST3. Specifically, the third clock pulse CLK3 is supplied to the drain terminal of the pull-up switching element Tru provided in the third A-stage AST3. Therefore, the pull-up switching element Tru provided in the third A-stage AST3 outputs the third clock pulse CLK3 as the third scan pulse Vout3. The third scan pulse Vout3 is supplied to the third gate line GL3, the fifth A stage AST5, and the sixth A stage AST6.

That is, the third scan pulse Vout3 drives the third gate line GL3 and simultaneously enables the fifth and sixth A-stages AST6.

Next, the operation during the fourth period T4 will be described as follows.

During the fourth period T4, as shown in FIG. 4, only the fourth clock pulse CLK4 remains high and the remaining clock pulses remain low.

This fourth clock pulse CLK4 is supplied to the enabled fourth A stage AST4. Specifically, the fourth clock pulse CLK4 is supplied to the drain terminal of the pull-up switching element Tru provided in the fourth A stage AST4. Accordingly, the pull-up switching element Tru provided in the fourth A-stage AST4 outputs the fourth clock pulse CLK4 as the fourth scan pulse Vout4. Then, the fourth scan pulse Vout4 is supplied to the fourth gate line GL4, the first A stage AST1, and the second A stage AST2.

That is, the fourth scan pulse Vout4 drives the fourth gate line GL4 and simultaneously disables the first and second A stages AST2. This disable operation will be described in more detail as follows.

That is, the fourth scan pulse Vout4 output from the fourth A stage AST4 in the fourth period T4 is supplied to the first A stage AST1. Specifically, the fourth scan pulse Vout4 is supplied to the gate terminal of the fourth switching device Tr4 provided in the first A-stage AST1. The fourth switching device Tr4 is turned on and the second DC voltage Vdc2 is applied to the enable node AST1 of the first A stage AST1 through the fourth switching device Tr4, (Q).

Therefore, the enable node Q is discharged, and the pull-up switching element Tru of the first A-stage AST1 whose gate terminal is connected to the discharged enable node Q, the sixth switching element Tr6, and the ninth switching element Tr9 are all turned off.

As the sixth switching element Tr6 is turned off, the first AC voltage Vac1 outputted through the fifth switching element Tr5 is supplied to the common node N of the first A-stage AST1 do. The seventh switching element Tr7 of the first A stage AST1 in which the common node N of the first A stage AST1 is charged and the gate terminal thereof is connected to the charged common node N, Is turned on.

The first AC voltage Vac1 is supplied to the first disable node QB1 of the first A stage AST1 through the turned-on seventh switching device Tr7. Then, the first node AQ1 of the first A stage AST1 is charged and the gate of the first A stage AST1 connected to the first node QB1 is charged. The first pull-down switching device Trd1 and the second switching device Tr2 are turned on. The second switching device Tr2 supplies the second DC voltage Vdc2 to the enable node Q of the first A stage AST1 to further accelerate the discharge of the enable node Q .

Thus, during the fourth period T4, the pull-up switching element Tru of the first A-stage AST1 is turned off and the first pull-down switching element Trd1 is turned on, AST1 outputs the second DC voltage Vdc2 through the turned-on first pull-down switching device Trd1. The second direct-current voltage Vdc2 is supplied to the first gate line GL1 and functions as an off-voltage for inactivating the first gate line GL1.

In summary, the first A stage AST1 discharges its enable node Q in response to the fourth scan pulse Vout4 and charges its first disable node QB1 . That is, the first A stage AST1 is disabled. At this time, the second disable node QB2 of the first A-stage AST1 maintains the discharge state in the first initial period T0A.

Meanwhile, in the fourth period T4, the second A stage AST2 is also disabled by receiving the fourth scan pulse Vout4. This will be described in more detail as follows.

That is, the fourth scan pulse (Vout4) output from the fourth A stage (AST4) in the fourth period (T4) is supplied to the second A stage (AST2). Specifically, the fourth scan pulse Vout4 is supplied to the gate terminal of the fourth switching device Tr4 provided in the second A stage AST2. The fourth switching device Tr4 is turned on and the second DC voltage Vdc2 is applied to the enable node AST2 of the second A stage AST2 through the fourth switching device Tr4 turned on. (Q).

Therefore, the enable node Q is discharged, and the pull-up switching element Tru of the second A stage AST2 whose gate terminal is connected to the discharged enable node Q, the sixth switching element Tr6, and the ninth switching element Tr9 are all turned off.

The fifth switching device Tr5 of the second A stage AST2 receiving the second AC voltage Vac2 maintains the turn-off state.

Since the state of the first disable node QB1 provided in the second A stage AST2 is controlled by the node controller 205 included in the first A stage AST1, The state of the first disable node QB1 provided in the stage AST2 is the same as the state of the first disable node QB1 of the first A stage AST1.

That is, as described above, since the first disable node QB1 of the first A stage AST1 is charged in the fourth period T4, the first disable state of the second A stage AST2 The node QB1 is also charged.

Since the state of the second disable node QB2 provided in the first A stage AST1 is controlled by the node controller 205 included in the second A stage AST2, The state of the second disable node QB2 provided in the stage AST1 is the same as the state of the second disable node QB2 provided in the second A stage AST2.

That is, since the second disable node QB2 of the second A stage AST2 still exhibits the discharge state during the fourth period T4, the first A stage (AST2) The second disable node QB2 of the node AST1 also shows a discharge state.

Therefore, in the fourth period T4, the enable node Q of the first and second A-stages AST1 and AST2 indicates a discharge state, and the first and second A-stages AST1 and AST2 And the second disable node QB2 of the first and second A stages AST1 and AST2 indicate a discharge state.

As a result, in the fourth period T4, the pull-up switching elements Tru of the first and second A-stages AST1 and AST2 are turned off and the first and second A-stages AST1 and AST2 The first pull-down switching device Trd1 of the first and second A stages AST1 and AST2 is turned off and the second pull down switching device Trd2 of the first and second A stages AST1 and AST2 is turned off.

Thus, in the fourth period T4, the first A stage AST1 supplies the second DC voltage Vdc2 to the first gate line GL1 as the off voltage, and the second A stage AST1 supplies the second DC voltage Vdc2 as the off- Supplies the second direct-current voltage Vdc2 as a turn-off voltage to the second gate line GL2.

Thereafter, in the fifth period T5, the enabled fifth A stage AST5 outputs the fifth clock pulse CLK5 as the fifth scan pulse Vout5, and the fifth scan pulse Vout5 is applied to the fifth The gate line GL5, the seventh A stage, and the eighth A stage.

Next, in the sixth period T6, the enabled sixth A stage A6 outputs the sixth clock pulse as the sixth scan pulse Vout6, and the sixth scan pulse Vout6 is applied to the sixth gate line (GL6), the third A stage (AST3), and the fourth A stage (AST4).

In this way, the remaining A stages operate.

Thereafter, in the second frame, since the first AC voltage Vac1 is kept negative and the second AC voltage Vac2 is maintained in the positive polarity, the A stables AST1, AST2, AST3,. The first disable node QB1 is discharged and the second disable node QB2 is charged. That is, in the second frame, the first pull-down switching device Trd1 of each of the A stages AST1, AST2, AST3, ... is turned off and the second pull-down switching device Trd2 is turned on.

Another operation of the shift register according to the first embodiment of the present invention will now be described.

Description will be made with reference to Figs. 3 and 6. Fig.

First, the operation of the first initial period T0A in the first frame will be described as follows.

During the first frame, the first AC voltage (Vac1) shows positive polarity and the second AC voltage (Vac2) shows negative polarity.

During the first initial period T0A, as shown in FIG. 3, only the start pulse VAST output from the timing controller is maintained in the high state, and the remaining clock pulses are held in the low state.

The start pulse VAST output from the timing controller is input to the first and second A stages AST1 and AST2.

That is, the start pulse VAST is supplied to the gate terminal of the first switching device Tr1 provided in the first A stage AST1 and the gate terminal of the sixth switching device Tr6.

The first and sixth switching elements Tr1 and Tr6 are turned on and the first DC voltage Vdc1 is supplied to the enable node Q via the first switching element Tr1, . Accordingly, the enable node Q is charged, and the pull-up switching element Tru and the seventh switching element Tr7, to which the gate terminal is connected to the enabled enable node Q, are turned on .

Here, the second DC voltage Vdc2 is supplied to the first disable node QB1 via the turned-on sixth and seventh switching elements Tr6 and Tr7. The second switching element Tr2 discharges the first disable node QB1 by the second DC voltage Vdc2 and the gate terminal is connected to the first disable node QB1, The first pull-down switching element Trd1 is turned off. The turned-on second switching device Tr2 supplies the second DC voltage Vdc2 to the enable node Q to accelerate the discharge of the enable node Q further.

Meanwhile, since the first AC voltage Vac1 is maintained in the positive polarity during the first frame, the fifth switching device Tr5 of the first A-stage AST1, which receives the first AC voltage Vac1, And maintains the turn-on state for one frame. The first AC voltage Vac1 is supplied to the first disable node QB1 of the first A stage AST1 through the turn-on fifth switching element Tr5.

As described above, the second disable voltage Vdc2 (Vdc2) output through the sixth and seventh switches Tr7 turned on is applied to the first disable node QB1 of the first A-stage AST1, ). That is, a first AC voltage (Vac1) of positive polarity and a second DC voltage (Vdc2) of negative polarity are simultaneously supplied to the first disable node (QB1) of the first A stage (AST1).

Since the number of the switching elements Tr6 and Tr7 for supplying the second DC voltage Vdc2 is larger than the number of the switching elements Tr5 for supplying the first AC voltage Vac1, The first disable node QB1 of the stage AST1 is maintained at the second DC voltage Vdc2. Therefore, the first disable node QB1 is discharged.

Thus, the first A stage AST1 charges its enable node Q in response to the start pulse VAST and discharges its first disable node QB1. That is, the first A stage AST1 is enabled.

Meanwhile, in the first initial period T0A, the second A stage AST2 is also supplied with the start pulse VAST. This will be described in more detail as follows.

That is, the start pulse VAST is supplied to the gate terminal of the first switching device Tr1 provided in the second A stage AST2 and the gate terminal of the sixth switching device Tr6.

The first and sixth switching elements Tr1 and Tr6 are turned on and the first DC voltage Vdc1 is applied to the second A stage AST2 through the first switching element Tr1 turned on. To the enable node Q of the node Q. Accordingly, the enable node Q is charged, and the pull-up switching element Tru and the seventh switching element Tr7, to which the gate terminal is connected to the enabled enable node Q, are turned on .

The second DC voltage Vdc2 is supplied to the second disable node QB2 of the second A stage AST2 through the turn-on sixth and seventh switching elements Tr6 and Tr7. Therefore, the third switching device Tr3, in which the second disable node QB2 is discharged by the second DC voltage Vdc2 and the gate terminal is connected to the second disable node QB2, The second pull-down switching element Trd2 is turned off.

Meanwhile, since the second AC voltage (Vac2) is kept negative during the first frame, the fifth switching element (Tr5) of the second A stage (AST2) receiving the second AC voltage (Vac2) And maintains the turn-off state for one frame.

In this manner, in the first initial period T0A, the second A stage AST2 charges the enable node Q of its own in response to the start pulse VAST, And discharges the node QB2.

At this time, the first and second disable nodes QB1 and QB2 of the first A stage AST1 and the first and second disable nodes QB1 and QB2 of the second A stage AST2 are turned off The second disable node QB2 of the first A stage AST1 is in the same state as the second disable node QB2 of the second A stage AST2 because they are electrically connected to each other , The first disable node QB1 of the second A stage AST2 shows the same state as the first disable node QB1 of the first A stage AST1.

That is, the second disable node QB2 of the first A stage AST1 is connected to the second DC voltage Vdc2 supplied to the second disable node QB2 of the second A stage AST2 To indicate the discharge state. The first disable node QB1 of the second A stage AST2 is connected to the second DC voltage Vdc2 supplied to the first disable node QB1 of the first A stage AST1 To indicate the discharge state.

In other words, in the first initial period T0A, the first A stage AST1 charges its enable node Q and supplies its own first disable node QB1 and the second A stage < RTI ID = 0.0 > And discharges the first disable node QB1 of the second node AST2. In the first initial period T0A, the second A stage AST2 charges its enable node Q and supplies its own second disable node QB2 and the second A stage AST2 of the second node QB2.

Next, the operation during the second initial period T0B will be described as follows.

In the second initial period T0B, the start pulse VAST and all the clock pulses remain in the low state.

Therefore, during the second initial period T0B, the first and second A stages AST2 maintain the enabled state. On the other hand, since the start pulse VAST has changed to the low state in the second initial period T0B, the first and sixth switching elements Tr1 and Tr6 of the first and second A stages AST2 Turn-off state, whereby each enable node Q of the first and second A-stages AST2 is kept in a floating state. Therefore, the first DC voltage Vdc1 supplied to each enable node Q of the first and second A stages AST1 and AST2 in the first initial period T0A is supplied to each of the enable nodes Q).

The operation during the first period T1 will now be described.

In the first period T1, only the first clock pulse CLK1 is in the high state and the remaining clock pulses are in the low state.

Here, as the enable node Q of the first A-stage AST1 is kept in the constantly charged state by the first DC voltage Vdc1 applied during the first initial period T0A, the first A- The pull-up switching element Tru of the stage AST1 maintains the turn-on state. At this time, as the first clock pulse CLK1 is applied to the drain terminal of the turn-on pull-up switching device Tru, the first clock pulse CLK1 is applied to the enable node Q of the first A- The DC voltage Vdc1 is amplified by bootstrapping.

Therefore, the first clock pulse CLK1 applied to the drain terminal of the pull-up switching element Tru of the first A-stage AST1 is stably outputted through the source terminal of the pull-up switching element Tru. At this time, the output first clock pulse CLK1 is applied to the first gate line GL1 to function as a first scan pulse Vout1 for driving the first gate line GL1.

The first scan pulse Vout1 output from the first A stage AST1 in the first period T1 is also input to the third and fourth A stages AST3 and AST4. 6, the first scan pulse Vout1 is applied to the gate terminals of the first and sixth switching elements Tr1 and Tr6 provided in the third A stage AST3, Are input to the gate terminals of the first and sixth switching elements Tr1 and Tr6 provided in the A stage AST4.

Therefore, the third and fourth A stages AST3 and AST4 are simultaneously enabled in the first period T1. At this time, the third A stage AST3 operates in the same manner as the first A stage AST1 during the first initial period T0A described above, and the fourth A stage AST4 operates in the same manner as the first initial stage (AST2) for the second A stage (AST2) during the first time (T0A).

That is, the third A stage AST3 charges its enable node Q and supplies its first disable node QB1 and the first disable node AST4 of the fourth A stage AST4, (QB1). The fourth A stage AST4 charges the enable node Q of its own and supplies the second disable node QB2 of its own and the second disable node QST of the third A stage AST3, (QB2).

Next, the operation during the second period T2 will be described as follows.

During the second period T2, only the second clock pulse CLK2 remains high and the remaining clock pulses remain low, as shown in Fig.

This second clock pulse CLK2 is supplied to the enabled second A stage AST2. Specifically, the second clock pulse CLK2 is supplied to the drain terminal of the pull-up switching element Tru provided in the second A stage AST2. Therefore, the pull-up switching element Tru provided in the second A stage AST2 outputs the second clock pulse CLK2 as the second scan pulse Vout2. Then, the second scan pulse Vout2 is supplied to the second gate line GL2 to drive the second gate line GL2.

Next, the operation during the third period T3 will be described as follows.

During the third period T3, as shown in FIG. 3, only the third clock pulse CLK3 remains high and the remaining clock pulses remain low.

This third clock pulse CLK3 is supplied to the enabled third A stage AST3. Specifically, the third clock pulse CLK3 is supplied to the drain terminal of the pull-up switching element Tru provided in the third A-stage AST3. Therefore, the pull-up switching element Tru provided in the third A-stage AST3 outputs the third clock pulse CLK3 as the third scan pulse Vout3. The third scan pulse Vout3 is supplied to the third gate line GL3, the fifth A stage AST5, and the sixth A stage AST6.

That is, the third scan pulse Vout3 drives the third gate line GL3 and simultaneously enables the fifth and sixth A-stages AST5 and AST6.

Next, the operation during the fourth period T4 will be described as follows.

During the fourth period T4, as shown in FIG. 3, only the fourth clock pulse CLK4 remains high and the remaining clock pulses remain low.

This fourth clock pulse CLK4 is supplied to the enabled fourth A stage AST4. Specifically, the fourth clock pulse CLK4 is supplied to the drain terminal of the pull-up switching element Tru provided in the fourth A stage AST4. Accordingly, the pull-up switching element Tru provided in the fourth A-stage AST4 outputs the fourth clock pulse CLK4 as the fourth scan pulse Vout4. Then, the fourth scan pulse Vout4 is supplied to the fourth gate line GL4, the first A stage AST1, and the second A stage AST2.

That is, the fourth scan pulse Vout4 drives the fourth gate line GL4 and simultaneously disables the first and second A stages AST1 and AST2. This disable operation will be described in more detail as follows.

That is, the fourth scan pulse Vout4 output from the fourth A stage AST4 in the fourth period T4 is supplied to the first A stage AST1. Specifically, the fourth scan pulse Vout4 is supplied to the gate terminal of the fourth switching device Tr4 provided in the first A-stage AST1. The fourth switching device Tr4 is turned on and the second DC voltage Vdc2 is applied to the enable node AST1 of the first A stage AST1 through the fourth switching device Tr4, (Q).

Therefore, the enable node Q is discharged, and the pull-up switching element Tru and the seventh switching element Tru of the first A stage AST1, to which the gate terminal is connected to the discharged enable node Q, Tr7 are all turned off.

On the other hand, the fifth switching element Tr5 of the first A-stage AST1 is kept in the turn-on state for one frame by the first AC voltage Vac1, so that the fifth switching element Tr5 The first AC voltage Vac1 is supplied to the first disable node QB1 of the first A stage AST1. Therefore, the first disable node QB1 of the first A stage AST1 is charged and the first pull-down switch AST1 of the first A stage AST1 connected to the charged first disable node QB1 is charged The switching element Trd1 and the second switching element Tr2 are turned on. The second switching device Tr2 accelerates the discharge of the enable node Q by supplying the second DC voltage Vdc2 to the enable node Q of the first A stage AST1.

Thus, during the fourth period T4, the pull-up switching element Tru of the first A-stage AST1 is turned off and the first pull-down switching element Trd1 is turned on, AST1 outputs the second DC voltage Vdc2 through the turned-on first pull-down switching device Trd1. The second direct-current voltage Vdc2 is supplied to the first gate line GL1 and functions as an off-voltage for inactivating the first gate line GL1.

In other words, the first A-stage AST1 discharges its own enable node Q in response to the fourth scan pulse Vout4 and charges its first disable node QB1 . That is, the first A stage AST1 is disabled. At this time, the second disable node QB2 of the first A-stage AST1 maintains the discharge state in the first initial period T0A.

Meanwhile, in the fourth period T4, the second A stage AST2 is also disabled by receiving the fourth scan pulse Vout4. This will be described in more detail as follows.

That is, the fourth scan pulse (Vout4) output from the fourth A stage (AST4) in the fourth period (T4) is supplied to the second A stage (AST2). Specifically, the fourth scan pulse Vout4 is supplied to the gate terminal of the fourth switching device Tr4 provided in the second A stage AST2. The fourth switching device Tr4 is turned on and the second DC voltage Vdc2 is applied to the enable node AST2 of the second A stage AST2 through the fourth switching device Tr4 turned on. (Q).

Therefore, the enable node Q is discharged, and the pull-up switching element Tru and the seventh switching element Tru of the second A stage AST2, to which the gate terminal is connected to the discharged enable node Q, Tr7 are all turned off.

The fifth switching device Tr5 of the second A stage AST2 receiving the second AC voltage Vac2 maintains the turn-off state.

Since the state of the first disable node QB1 provided in the second A stage AST2 is controlled by the node controller 205 included in the first A stage AST1, The state of the first disable node QB1 provided in the stage AST2 is the same as the state of the first disable node QB1 of the first A stage AST1.

That is, as described above, since the first disable node QB1 of the first A stage AST1 is charged in the fourth period T4, the first disable state of the second A stage AST2 The node QB1 is also charged.

Since the state of the second disable node QB2 provided in the first A stage AST1 is controlled by the node controller 205 included in the second A stage AST2, The state of the second disable node QB2 provided in the stage AST1 is the same as the state of the second disable node QB2 provided in the second A stage AST2.

That is, since the second disable node QB2 of the second A stage AST2 still exhibits the discharge state during the fourth period T4, the first A stage (AST2) The second disable node QB2 of the node AST1 also shows a discharge state.

Therefore, in the fourth period T4, the enable node Q of the first and second A-stages AST2 indicates a discharge state, and the enable node Q of the first and second A-stages AST1 and AST2 The first disable node QB1 indicates a charged state and the second disable node QB2 of the first and second A stages AST1 and AST2 indicates a discharge state.

As a result, in the fourth period T4, the pull-up switching elements Tru of the first and second A-stages AST1 and AST2 are turned off and the first and second A-stages AST1 and AST2 The first pull-down switching device Trd1 of the first and second A stages AST1 and AST2 is turned off and the second pull down switching device Trd2 of the first and second A stages AST1 and AST2 is turned off.

Thus, in the fourth period T4, the first A stage AST1 supplies the second DC voltage Vdc2 to the first gate line GL1 as the off voltage, and the second A stage AST1 supplies the second DC voltage Vdc2 as the off- Supplies the second direct-current voltage Vdc2 as a turn-off voltage to the second gate line GL2.

Thereafter, in the fifth period T5, the enabled fifth A stage AST5 outputs the fifth clock pulse CLK5 as the fifth scan pulse Vout5, and the fifth scan pulse Vout5 is applied to the fifth The gate line GL5, the seventh A stage, and the eighth A stage.

Next, in the sixth period T6, the enabled sixth A stage A6 outputs the sixth clock pulse as the sixth scan pulse Vout6, and the sixth scan pulse Vout6 is applied to the sixth gate line (GL6), the third A stage (AST3), and the fourth A stage (AST4).

In this way, the remaining A stages operate.

Thereafter, in the second frame, since the first AC voltage Vac1 is kept negative and the second AC voltage Vac2 is maintained in the positive polarity, the respective A stages AST1, AST2, AST3, The first disable node QB1 is discharged and the second disable node QB2 is charged. That is, in the second frame, the first pull-down switching device Trd1 of each of the A stages AST1, AST2, AST3, ... is turned off and the second pull-down switching device Trd2 is turned on.

Meanwhile, the operation of the B stages included in the second shift register SR2 is also the same as the operation of the A stages described above.

At this time, since the A-stage and the B-stage connected to the same gate line are supplied with different AC voltages, scan pulses having different output characteristics are simultaneously supplied to one gate line. For example, on one side of the first gate line GL1, a first scan pulse having a relatively fast polling time output from the first A stage is supplied, and on the other side of the first gate line GL1, A composite scan pulse of a form in which scan pulses of two different output characteristics are combined is supplied to the first gate line GL1. At this time, the composite scan pulse has a characteristic that the characteristics of the first scan pulse supplied from the first A stage and the characteristics of the first scan pulse supplied from the first B stage are combined. And the other odd-numbered gate lines are supplied with scan pulses having the same characteristics as the scan pulses supplied to the first gate line GL1.

As another example, a second scan pulse, which is output from the second A stage and has a relatively slow polling timing, is supplied to one side of the second gate line GL2, and a second scan pulse is applied to the other side of the second gate line GL2. Since the second scan pulse outputted from the stage is supplied at a relatively high polling time, the second scan line is supplied with a composite scan pulse in which scan pulses of two different output characteristics are combined. At this time, the composite scan pulse has a characteristic that the characteristics of the second scan pulse supplied from the second A stage and the characteristics of the second scan pulse supplied from the second B stage are combined. And the other even-numbered gate lines are supplied with scan pulses having the same characteristics as the scan pulses supplied to the second gate line GL2 described above.

Since all the other gate lines GL1, GL2, GL3, ... are supplied with two scan pulses having different characteristics, all of the gate lines GL1, GL2, GL3, ... are charged under the same conditions. Therefore, a charge deviation between the gate lines can be prevented.

9 is a view illustrating a shift register according to a second embodiment of the present invention.

9, the shift register according to the second embodiment of the present invention is disposed at one side of the gate lines GL1, GL2, GL3, A first shift register SR1 for sequentially supplying scan pulses to one side of each of the gate lines GL1, GL2, GL3, ..., And a second shift register SR2 for sequentially supplying scan pulses to the other sides of the scan lines GL1, GL2, GL3,.

The first shift register SR1 is connected to one side of the gate lines GL1, GL2, GL3, ... and sequentially scans one side of the gate lines GL1, GL2, GL3, And a plurality of A stages for supplying pulses. The second shift register SR2 is connected to the other side of the gate lines GL1, GL2, GL3, ... and sequentially connects the other side of the gate lines GL1, GL2, GL3, And a plurality of B stages for supplying scan pulses to the scan electrodes.

The 2n-1st A stages among the A stages provided in the first shift register SR1 are supplied with the first AC voltage and the 2nth A stages are supplied with the second AC voltage. The 2n-1th B stages of the B stages provided in the second shift register SR2 are supplied with the first AC voltage and the 2nth B stages are supplied with the second AC voltage. In particular, the (n + 1) th A stage of the first shift register SR1 supplies the scan pulse to one side of the nth gate line, and the nth B stage of the second shift register SR2 supplies the scan pulse to the other side In the second embodiment.

The configuration of each A stage is the same as that in the first embodiment described above, and a description thereof will be omitted.

On the other hand, a scan pulse from the first A stage of the A stages and a scan pulse from the last B stage of the B stages are not supplied to the gate line.

10 is a view illustrating a shift register according to a third embodiment of the present invention.

The shift register according to the third embodiment of the present invention includes a plurality of stages ST1, ST2, ST3, ... as shown in Fig.

At this time, the circuit configuration of each stage ST1, ST2, ST3, ... provided in the shift register is the same as the circuit configuration of the A stage or B stage in the above-described first embodiment.

That is, each of the stages ST1, ST2, ST3, ... has an enable node; A pull-up switching element for outputting the scan pulse according to a logic state of the enable node; At least two disable nodes; At least two pulldown switching elements connected to each of the disable nodes for outputting an off voltage according to a logic state of each disable node; And a node control unit for controlling the logic states of the enable node and the disable nodes provided in the node A and the logic state of the disable node provided in the other A stage.

At this time, a node controller provided in a stage connected to an arbitrary gate line may use any one of the first AC voltage and the second AC voltage to set the logic states of the enable node and the disable node, And also controls the logical state of the disable node provided in the other stage. Particularly, the first feature is that the first AC voltage and the second AC voltage are randomly supplied to the stages ST1, ST2, ST3, ... in the third embodiment. However, the n-th stage and the (n-1) -th stage are supplied with different alternating voltages.

10, the first stage ST1 receives the first AC voltage Vac1, the second stage ST2 receives the second AC voltage Vac2, the third stage ST2 receives the second AC voltage Vac2, The fourth stage ST4 receives the first AC voltage Vac1 and the fifth stage ST5 supplies the first AC voltage Vac1 to the stage ST3. And the sixth stage ST6 receives the second AC voltage Vac2. As described above, by randomly supplying any one of the first and second AC voltages Vac1 and Vac3 to the stages ST1, ST2, ST3, ..., scan pulses having different output characteristics are randomly supplied to the respective gate lines . Accordingly, it is possible to improve the image quality by eliminating the longitudinal dimming phenomenon represented by the specific regularity.

FIG. 11 is a view for explaining the effect of the shift register according to the first embodiment of the present invention, and it can be seen that the polling time of the scan pulse from the shift register according to the first embodiment of the present invention is low .

FIG. 12 is a diagram for explaining the effect of the shift register according to the second embodiment of the present invention, and it can be seen that the polling time of the scan pulse from the shift register according to the second embodiment of the present invention is low.

The output characteristics of the scan pulse supplied from the conventional shift register to the odd gate lines and the output characteristics of the scan pulses supplied to the even gate lines were different from each other. Specifically, the rising time of the scan pulse supplied to the odd-numbered gate lines is about 2.08 usec, and the rising time of the scan pulses supplied to the even-numbered gate lines is about 2.06 usec, The falling time of the scan pulse supplied to the gate line and the polling time of the scan pulse supplied to the even gate line were 4.63 usec and the deviation was considerably high. However, the rising time of the scan pulse supplied to the even-numbered gate line from the shift register according to the first embodiment of the present invention is about 2.09 usec, and the rising time of the scan pulse supplied to the even- The poling time of the scan pulse supplied to the odd-numbered gate lines was 2.21 usec, and the polling time of the scan pulses supplied to the even-numbered gate lines was equal to 2.21 usec.

The rising time of the scan pulse supplied to the even-numbered gate line from the shift register according to the second embodiment of the present invention is about 2.07 usec, and the rising time of the scan pulse supplied to the even-numbered gate line is about 2.07 usec The poling time of the scan pulse supplied to the odd-numbered gate lines was 2.63 usec, and the polling time of the scan pulses supplied to the even-numbered gate lines was 2.63 usec.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

1 is a diagram showing waveforms of a voltage waveform and a scan pulse of an enable node in an odd-numbered stage and a waveform of a voltage waveform and a scan pulse of an enable node in an even-numbered stage;

FIG. 2 is a diagram for comparing the waveforms of the scan pulses output from the odd-numbered stages of FIG. 1 and the output characteristics of the scan pulses output from the even-numbered stages;

3 is a view illustrating a shift register according to the first embodiment of the present invention.

4 is a diagram showing the configuration of stages provided in the first shift register of FIG. 3;

5 is a diagram showing the configuration of stages provided in the second shift register of FIG. 4;

FIG. 6 is a diagram showing waveforms of an input signal supplied to each stage of FIG. 2 and an output signal output from each stage;

7 is a diagram showing a circuit configuration of a node control unit provided in the third and fourth A stages of the first shift register of Fig. 2

8 is a diagram showing a circuit configuration of a node control unit provided in the third and fourth B stages of the second shift register of Fig. 2

9 is a view showing a shift register according to a second embodiment of the present invention

10 is a view illustrating a shift register according to a third embodiment of the present invention.

11 is a view for explaining the effect of the shift register according to the first embodiment of the present invention;

12 is a view for explaining the effect of the shift register according to the second embodiment of the present invention;

Claims (10)

A first shift register disposed at one side of the plurality of gate lines to sequentially supply scan pulses to the gate lines; A second shift register disposed on the other side of the plurality of gate lines to sequentially supply scan pulses to the gate lines; At least one A stage provided in the first shift register comprises an enable node; A pull-up switching element for outputting the scan pulse according to a logic state of the enable node; At least two disable nodes; At least two pulldown switching elements connected to each of the disable nodes for outputting an off voltage according to a logic state of each disable node; And a node control unit for controlling the logical states of the enable node and the disable nodes provided in the node and the logic state of the disable node provided in the other node, At least one B stage provided in the second shift register comprises an enable node; A pull-up switching element for outputting the scan pulse according to a logic state of the enable node; At least two disable nodes; At least two pulldown switching elements connected to each of the disable nodes for outputting an off voltage according to a logic state of each disable node; And a node control unit for controlling the logical states of the enable node and the disable nodes provided in the node and the logic state of the disable node provided in the other node, The node controller provided in the A stage of the first shift register connected to the arbitrary gate line uses the first AC voltage to set the logic states of the enable node and the disable node provided in the node, Controls a logic state of a disable node included in the node; The node controller provided in the B stage of the second shift register connected to the arbitrary gate line uses the second AC voltage to compare the logic states of the enable node and the disable node provided in the B stage, Controlling a logic state of a disable node provided in the stage together; Wherein the first and second shift registers supply scan pulses to the same gate line in synchronization with each other; And, Wherein the first AC voltage has an inverted phase with respect to the second AC voltage. The method according to claim 1, Numbered stage A of the first shift register connected to the odd-numbered gate lines uses the first AC voltage to set the logical states of the enable node and the disable nodes provided in the node, Controlling a logic state of a disable node provided in the stage together; The node controller included in the even-numbered stage A of the first shift register connected to the even-numbered gate line uses the second AC voltage to set the logical states of the enable node and the disable node provided therein, Controlling a logic state of a disable node provided in the stage together; Numbered B stages of the second shift register connected to odd-numbered gate lines uses the second AC voltage to set the logic states of the enable node and the disable node provided therein and the logic states of the enable node and the disable node, Controlling a logic state of a disable node provided in the stage together; And, The node controller included in the even-numbered stage B of the second shift register connected to the even-numbered gate line uses the first AC voltage to set the logic states of the enable node and the disable node provided therein, And the logic state of the disable node provided in the stage is controlled together. The method according to claim 1, Each of the A stages provided in the first shift register includes a first disable node, a first pull-down switching element connected to the first disable node, a second disable node, and a second disable node And a second pull-down switching element connected to the second pull-down switching element; The 2n-3 (n is a natural number equal to or greater than 2) th stage A node control unit controls the logical states of the enable node and the first disable node included in the 2n-3th A stage, Controlling a logic state of a first disable node provided in a second A stage; The node controller included in the (2n-2) th stage A controls the logical states of the enable node and the second disable node included in the (2n-2) th stage, Controlling a logic state of a provided second disable node; And, Each B stage included in the second shift register includes a first disable node, a first pull-down switching element connected to the first disable node, a second disable node, and a second disable node And a second pull-down switching element connected to the second pull-down switching element; 2n-3 (n is a natural number of 2 or more) B stages controls the logical state of the enable node and the first disable node provided in the (2n-3) th B stage, Controlling a logic state of a first disable node provided in a second B stage; The node controller included in the (2n-2) th B stage controls the logic states of the enable node and the second disable node provided in the (2n-2) th B stage, And controls the logic state of the provided second disable node. The method of claim 3, The first disable node provided in the (2n-3) th stage and the first disable node provided in the (2n-2) th A stage are electrically connected to each other; The second disable node provided in the (2n-2) th stage and the second disable node provided in the (2n-3) th A stage are electrically connected to each other; And, The first disable node provided in the (2n-3) th B stage and the first disable node provided in the (2n-2) th B stage are electrically connected to each other; And a second disable node provided in the (2n-2) th B stage and a second disable node provided in the (2n-3) th B stage are electrically connected to each other. The method of claim 3, Wherein the node controller provided in the (2n-3) th stage includes a logic state of the first disable node provided in the (2n-3) th stage and a logic state of the first disable node provided in the Controlling a logic state to the first alternating-current voltage; Wherein the node controller provided in the (2n-2) th stage further includes a logic state of the second disable node provided in the (2n-2) th stage and the second disable node provided in the Controlling the second AC voltage; And, The node controller provided in the (2n-3) th B-stage may be configured to select one of the logic states of the first disable node provided in the (2n-3) Controlling a logic state to the second alternating-current voltage; The node control unit provided in the (2n-2) th B-stage may set the logical state of the second disable node provided in the (2n-2) th B stage and the second disable node provided in the And said second resistor is controlled by said first AC voltage. 6. The method of claim 5, The 2n-1 st stage and the 2n th A stage are enabled in response to a scan pulse from the (2n-3) th stage and are disabled in response to a scan pulse from the (2n + 2) th stage; The (2n-3) th stage and the (2n-2) th A stage are disabled in response to a scan pulse from the 2n-th stage; The (2n + 1) th stage and the (2n + 2) th A stage are enabled in response to the scan pulse from the (2n-1) th stage; And, The 2n-1 th B stage and the 2n th B stage are enabled in response to the scan pulse from the (2n-3) th B stage and disabled in response to the scan pulse from the (2n + 2) th B stage; The 2n-3 th B stage and the 2n-2 th B stage are disabled in response to the scan pulse from the 2n th B stage; And the (2n + 1) th B stage and the (2n + 2) th B stage are enabled in response to the scan pulse from the (2n-1) th B stage. The method according to claim 6, The node control unit provided in the (2n-1) -th stage includes a first switching device for charging the enable node with the first dc voltage in response to the scan pulse from the (2n-3) th stage; A second switching element for discharging the enable node to a second DC voltage in response to a first AC voltage supplied to the first disable node; Stage A stage to the second DC voltage in response to the second AC voltage supplied to the second disable node of the (2n-1) th stage through the 2n-th stage A A third switching element; A fourth switching element for discharging the enable node to a second DC voltage in response to a scan pulse from the (2n + 2) th stage; A fifth switching device that is turned on or off in response to the first AC voltage and charges the common node with the first AC voltage upon turning on; A sixth switching element for discharging the common node to a second direct-current voltage in response to a first direct-current voltage charged in the enable node; And a seventh node for charging the first disable node of the 2n-1 st stage and the first disable node of the 2n th A stage with the first alternating voltage in response to the first alternating voltage supplied to the common node, A switching element; Stage A stage and the first disable node of the 2 < n > A-stage to the second DC voltage in response to the scan pulse from the (2n-3) device; And a node for discharging the first disable node of the 2n-1 st stage and the first disable node of the 2n th A stage to a second dc voltage in response to the first dc voltage charged to the enable node, The ninth switching element; And, The node control unit provided in the (2n-1) -th stage includes a first switching device for charging the enable node with the first DC voltage in response to the scan pulse from the (2n-3) A second switching element for discharging the enable node to a second DC voltage in response to a first AC voltage supplied to the first disable node; And discharging the enable node of the (2n-1) th B stage to the second DC voltage in response to the second AC voltage supplied to the second disable node of the (2n-1) th B stage through the 2n th B stage A third switching element; A fourth switching element for discharging the enable node to a second DC voltage in response to a scan pulse from the (2n + 2) th B stage; A fifth switching device that turns on or off in response to the first AC voltage and charges the common node with the first AC voltage upon turning on; A sixth switching element for discharging the common node to a second direct-current voltage in response to a first direct-current voltage charged in the enable node; Stage B stage and the first disable node of the 2 < n > B stage in response to the first alternating-current voltage supplied to the common node, A switching element; The eighth switching for discharging the first disable node of the (2n-1) th B stage and the first disable node of the (2n) th B stage to the second DC voltage in response to the scan pulse from the (2n-3) device; And a node for discharging the first disable node of the 2n-1th B stage and the first disable node of the 2n th B stage to the second DC voltage in response to the first DC voltage charged to the enable node, Wherein the first and second switching elements are connected in series. The method according to claim 1, The 2n-1th (n is a natural number) A stages of the A stages provided in the first shift register are supplied with a first AC voltage, and the 2nth A stages are supplied with a second AC voltage; The 2n-1th B stages among the B stages provided in the second shift register are supplied with the first AC voltage, the 2nth B stages receive the second AC voltage; The (n + 1) th A stage of the first shift register supplies a scan pulse to one side of the n-th gate line; The nth B stage of the second shift register supplies a scan pulse to the other side of the nth gate line; And, Wherein the (n + 1) th A stage of the first shift register and the nth B stage of the second shift register supply scan pulses to the nth gate line in synchronization with each other. 9. The method of claim 8, Wherein a scan pulse from a first A stage of the A stages and a scan pulse from a last B stage of the B stages are not supplied to the gate line. A shift register for sequentially supplying a scan pulse to one side of the gate lines; At least one stage provided in the shift register comprises an enable node; A pull-up switching element for outputting the scan pulse according to a logic state of the enable node; At least two disable nodes; At least two pulldown switching elements connected to each of the disable nodes for outputting an off voltage according to a logic state of each disable node; And a node control unit for controlling the logical states of the enable node and the disable nodes provided in the node and the logic state of the disable node provided in the other node, A node controller provided in a stage connected to an arbitrary gate line may use any one of the first AC voltage and the second AC voltage to set the logical state of the enable node and the disable node provided in the stage, And a logic state of a disable node provided in another stage; The first AC voltage having an inverted phase relative to the second AC voltage; And, Wherein the first AC voltage and the second AC voltage are randomly supplied to each stage, and a different AC voltage is supplied from the 2n-1st stage to the 2n-th stage.

Images