KR20100065523A - Shift register - Google Patents

Abstract

PURPOSE: A shift register is provided to minimize a discharge time of a gate line with rapidly discharging an output terminal of a stage connected to the gate line using a pull up switching element and a pull down switching element. CONSTITUTION: A node controller controls a logic state of the node according to a scan pulse from a stage. A pull-up switching element(Tu) is turned on/off according to the logic state of a first node and outputs the scan pulse through an output terminal when it is turned on. A first full down switching element(Td1) is switched to the turn-on or turn-off according to the logic state of a fifth node and outputs a voltage for discharging through the output terminal in the turn-on. A second full down switching element(Td2) is switched to the turn-on or turn-off according to the logic state of a sixth node and outputs the voltage for discharging through the output terminal in the turn-on.

Description

Shift register {SHIFT REGISTER}

The present invention relates to a shift register, and more particularly to a shift register that can minimize the discharge time of the gate line.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and a pixel region is positioned in an area defined by vertical crossings of the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed in the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a scan pulse applied to a gate terminal via the gate line, so that the data signal of the data line is charged to the pixel voltage.

The driving circuit may include a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, and a liquid crystal display device. It is provided with a power supply for supplying a variety of driving voltages used in.

The gate driver sequentially supplies scan pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. Here, the gate driver includes a shift register to sequentially output the scan pulses as described above.

The conventional shift register includes a plurality of stages which in turn output a scan signal. A scan pulse is output from the stage, which is supplied to the gate line to charge the gate line for a predetermined time. That is, the gate line is charged by the scan pulse in the high state and discharged by the scan pulse in the low state. In this case, reducing the discharge time of the gate line as much as possible plays an important role in improving the image quality of the liquid crystal display device. As the liquid crystal display device becomes larger in area, the longer the gate line, the longer the discharge time becomes.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the shift register which can minimize the discharge time of the gate line by quickly discharging the output terminal of the stage connected to the gate line using a pull-up switching device and a pull-down switching device The purpose is to provide.

The shift register according to the present invention for achieving the above object comprises a plurality of stages for sequentially outputting a scan pulse; The kth stage may include: a first node controller configured to control logic states of the first to third nodes according to the scan pulse from the k-1th stage and the scan pulse from the k + 2th stage; A second node controller for controlling the logic state of the fourth node according to the logic state of the second node of the kth stage and the scan pulse from the k + 1 stage; A third node controller for controlling the logic state of the fifth node according to the logic state of the third node of the kth stage and the scan pulse from the k + 1 stage; A pull-up switching device which is turned on or turned off according to a logic state of the first node and outputs as a scan pulse through an output terminal at turn-on; A first pull-down switching device that is turned on or turned off according to a logic state of the fifth node, and outputs a discharge voltage through the output terminal when turned on; And a second pull-down switching device which is turned on or turned off according to the logic state of the sixth node, and which outputs a discharge voltage through the output terminal during turn-on.

The first node controller provided in the k-th stage is turned on or off according to the scan pulse from the k-th stage, and is turned on between the output terminal of the k-th stage and the first node. A first switching element for connecting a; A second switching element which is turned on or off according to the scan pulse from the k + 2th stage and connects the discharge power line and the first node to transmit the discharge voltage at turn-on; A third switching element which is turned on or off according to the logic state of the second node and connects between the first node and the discharge power supply line when turned on; A fourth switching element which is turned on or turned off according to the logic state of the third node and connects between the first node and the discharge power supply line when turned on; A fifth switching element which is turned on or off in accordance with a first AC voltage from a first AC power line and connects the first AC power line and the second node when turned on; A sixth switching element which is turned on or turned off according to the logic state of the first node and connects between the second node and a power supply line for discharge when turned on; A seventh switching element which is turned on or turned off according to a second AC voltage from a second AC power line and connects the second AC power line and a discharge power line at turn-on; And an eighth switching device which is turned on or turned off according to the logic state of the first node and connects the third node and the discharge power supply line during turn-on.

The second node controller provided in the k-th stage is turned on or turned off according to the logic state of the third node, and a ninth node connecting the first AC power line and the fourth node at turn-on. Switching element; A tenth switching element which is turned on or off according to the scan pulse from the k + 1th stage and connects the charging power supply line transmitting the charging voltage with the fourth node at turn-on; And an eleventh switching device that is turned on or off according to a second AC voltage from the second AC power line and connects the fourth node to a discharge power line during turn-on. It is done.

The third node controller provided in the n-th stage is turned on or off according to the logic state of the second node, and a twelfth node which connects the first AC power supply line to the fifth node when turned on. Switching element; A thirteenth switching element which is turned on or off according to the scan pulse from the k + 1th stage and connects the charging power supply line transmitting the charging voltage with the fifth node at turn-on; And a fourteenth switching element which is turned on or turned off according to the first AC voltage from the first AC power line and connects the fifth node and the discharge power line when turned on. It is done.

The shift register according to the present invention has the following effects.

The shift register according to the present invention can minimize the discharge time of the gate line connected to the output terminal by quickly discharging the output terminal of the stage by using the pull-up switching device and the pull-down switching device.

1 is a diagram illustrating a shift register according to an exemplary embodiment of the present invention, and FIG. 2 is a diagram illustrating a timing diagram of various signals supplied or output to each stage of FIG. 1.

The shift register according to the embodiment of the present invention includes n stages and two dummy stages STn + 1 and STn + 2, as shown in FIG. 1. Here, each of the stages ST1 to STn including the first and second dummy stages STn + 1 and STn + 2 outputs one scan pulse for one frame period through each output terminal OT. It is fed to stages located at its front and rear ends to control its operation.

The k-th stage receives the scan pulse from the k-1 stage through the set terminal SE, receives the scan pulse from the k + 1 stage through the first reset terminal RE1, and receives the k ++ th stage. The scan pulse from the second stage is supplied through the second reset terminal RE2. In addition, each stage ST1 to STn + 2 receives the corresponding clock pulse through the clock terminal CT and outputs a scan pulse through the output terminal OT.

However, since the stage does not exist in front of the first stage ST1, the first stage ST1 receives the start pulse Vst from the timing controller through the set terminal SE. Meanwhile, the n-1 stage (not shown) receives the first dummy scan pulse Voutn + 1 from the first dummy stage STn + 1 through the second reset terminal RE2. In addition, the n-th stage STn receives the first dummy scan pulse Voutn + 1 from the first dummy stage STn + 1 through the first reset terminal RE1 and the second dummy stage STn. The second dummy scan pulse Voutn + 2 from +2) is supplied through the second reset terminal RE2.

The stages ST1 to STn + 2 output scan pulses in order from the first stage ST1 to the second dummy stage STn + 2. That is, the first stage ST1 outputs the first scan pulse Vout1, and then the second stage ST2 outputs the second scan pulse Vout2, and then the third stage ST3 performs the first stage. Outputs 3 scan pulses Vout3, then kth stage outputs kth scan pulse, first dummy stage STn + 1 outputs k + 1th scan pulse, and finally The second dummy stage STn + 2 outputs the k + 2th scan pulse.

Scan pulses Vout1 to Voutn output from the stages except for the first and second dummy stages STn + 1 and STn + 2 are sequentially supplied to gate lines of a liquid crystal panel (not shown). The gate lines are sequentially scanned.

Such a shift register may be embedded in the liquid crystal panel. That is, the liquid crystal panel has a display portion for displaying an image and a non-display portion surrounding the display portion, and the shift register is embedded in the non-display portion.

The entire stage of the shift register configured as described above is a clock pulse circulating with the sequential phase difference between the charging voltage VDD, the discharging voltage VSS, the first AC voltage VDD_O, the second AC voltage VDD_E, and the sequential phase difference. Any one of CLK1 to CLK4 is authorized. Meanwhile, the first stage ST1 of the stages ST1 to STn + 2 is further supplied with a start pulse Vst.

The charging voltage VDD is provided from a charging power supply line, the discharge voltage VSS is provided from a discharge power supply line, and the first clock pulse CLK1 is provided from a first clock transmission line. The second clock pulse CLK2 is provided from the second clock transmission line, the third clock pulse CLK3 is provided from the third clock transmission line, and the fourth clock pulse CLK4 is the fourth clock transmission line. And the start pulse Vst is provided from the start transmission line.

The charging voltage VDD and the discharging voltage VSS are both DC voltages, and the charging voltage VDD has a potential higher than that of the discharging voltage VSS. For example, the charging voltage VDD may indicate positive polarity, and the discharge voltage VSS may indicate negative polarity. The discharge voltage VSS may be a ground voltage. The discharge voltage VSS is equal to the voltage value of the low state of each clock pulse.

Each of the clock pulses CLK1 to CLK4 is a signal used to generate a scan pulse of each stage, and each of the stages ST1 to STn + 2 generates a scan pulse using any one of these clock pulses. For example, the 4k + 1 stage outputs the scan pulse using the first clock pulse CLK1, and the 4k + 2 stage outputs the scan pulse using the second clock pulse CLK2, and the 4k + 1 stage outputs the scan pulse. The +3 stage outputs the scan pulse using the third clock pulse CLK3, and the 4k + 4 stage outputs the scan pulse using the fourth clock pulse CLK4. K is a natural number including zero.

In the present invention, an example of using four types of clock pulses having different phase differences is shown, but any number of clock pulses can be used.

The first to fourth clock pulses CLK1 to CLK4 are output with phase differences from each other. The second clock pulse CLK2 is output by being phase-delayed by one pulse width than the first clock pulse CLK1, and the third clock pulse CLK3 is output by one pulse width than the second clock pulse CLK2. Phase delayed output, the fourth clock pulse (CLK4) is phase-delayed output by one pulse width than the third clock pulse (CLK3), the first clock pulse (CLK1) is the fourth clock pulse (CLK4) Phase delayed by 1 pulse width than) is output.

The first to fourth clock pulses CLK1 to CLK4 are sequentially output, and are also output in a circular manner. That is, after the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output, the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output. Therefore, the first clock pulse CLK1 is output in a period corresponding to the fourth clock pulse CLK4 and the second clock pulse CLK2. The fourth clock pulse CLK4 and the start pulse Vst may be synchronized with each other and output. As such, when the fourth clock pulse CLK4 and the start pulse Vst are synchronized with each other, the fourth clock pulse CLK4 is first outputted among the first to fourth clock pulses CLK4.

Each of the clock pulses CLK1 to CLK4 is output multiple times during one frame period, but the start pulse Vst is output only once during one frame period. In other words, each clock pulse CLK1 to CLK4 periodically shows several active states (high states) during one frame period, but the start pulse Vst shows only one active state during one frame period.

Each stage ST1 to STn + 2 is supplied with the first and second AC voltages VDD_O and VDD_E. The first and second AC voltages VDD_O and VDD_E are both AC voltages, and the first AC voltage VDD_O has a phase inverted 180 degrees with respect to the second AC voltage VDD_E. Voltage values in the high state of the first and second AC voltages VDD_O and VDD_E may be the same as voltage values of the charging voltage VDD, and the first and second AC voltages VDD_O and VDD_E. The voltage value in the low state may be equal to the voltage value of the discharge voltage VSS. The first and second alternating voltages VDD_O and VDD_E are inverted in their p-frame periods. Where p is a natural number.

The first AC voltage VDD_O is provided from a first AC power line, and the second AC voltage VDD_E is provided from a second AC power line.

3 is a diagram illustrating a configuration of any one stage shown in FIG. 1.

The k-th stage includes the first to fifth nodes Q, QB1, QB2, Gd1, and Gd2, the first to third node controllers NC1 to NC3, the pull-up switching device Tu, and the first pull-down switching device Td1. And a second pull-down switching device Td2.

The first node controller NC1 provided in the k-th stage is configured to perform logic of the first to third nodes Q, QB1, and QB2 according to the scan pulse from the k-1 stage and the scan pulse from the k + 2 stage. Control the state. To this end, the first node controller NC1 of the k-th stage includes first to eighth switching elements Tr1 and Tr8.

The first switching device Tr1 provided in the first node controller NC1 of the kth stage is turned on or turned off according to the scan pulse from the k-1st stage, and when turned on, the k-1th stage The output terminal OT of the stage and the first node Q are connected.

The second switching device Tr2 provided in the first node controller NC1 of the kth stage is turned on or turned off according to the scan pulse from the k + 2th stage, and the discharge voltage ( The discharge power supply line for transmitting VSS is connected to the first node Q.

The third switching device Tr3 provided in the first node controller NC1 of the k-th stage is turned on or turned off according to the logic state of the second node QB1, and when turned on, the first node (Q) and the discharge power supply line are connected.

The fourth switching device Tr4 provided in the first node controller NC1 of the kth stage is turned on or turned off according to the logic state of the third node QB2, and when turned on, the first node ( Q) and the discharge power supply line are connected.

The fifth switching device Tr5 provided in the first node controller NC1 of the k-th stage is turned on or turned off in accordance with the first AC voltage VDD_O from the first AC power line. The first AC power line is connected between the second node QB1.

The sixth switching element Tr6 included in the first node controller NC1 of the kth stage is turned on or turned off according to the logic state of the first node Q, and when turned on, the second node (QB1) is connected between the power supply line for discharge.

The seventh switching element Tr7 included in the first node controller NC1 of the k-th stage is turned on or turned off in accordance with the second AC voltage VDD_E from the second AC power line. The second AC power line and the discharge power line are connected.

The eighth switching device Tr8 provided in the first node controller NC1 of the kth stage is turned on or turned off according to the logic state of the first node Q, and when turned on, the third node ( Connect between QB2) and the power supply line for discharge.

On the other hand, the second node controller NC2 provided in the k-th stage is the logic state of the fourth node Gd1 according to the logic state of the second node QB1 of the k-th stage and the scan pulse from the k + 1th stage. To control. To this end, the second node controller NC2 of the k-th stage includes the ninth to eleventh switching elements Tr9 to Tr11.

The ninth switching element Tr9 provided in the second node controller NC2 of the kth stage is turned on or turned off according to the logic state of the third node QB2, and when turned on, the first AC The power line is connected between the fourth node Gd1.

The tenth switching element Tr10 of the second node controller NC2 of the kth stage is turned on or turned off according to the scan pulse from the k + 1th stage, and the charging voltage VDD is turned on. ) Is connected between the power supply line for charging and the fourth node (Gd1).

The eleventh switching element Tr11 provided in the second node controller NC2 of the k-th stage is turned on or turned off in accordance with the second AC voltage VDD_E from the second AC power line. On, the fourth node Gd1 is connected to the discharge power supply line.

On the other hand, the third node controller NC3 provided in the k-th stage is the logic state of the fifth node Gd2 according to the logic state of the third node QB2 of the k-th stage and the scan pulse from the k + 1th stage. To control. To this end, the third node controller NC3 includes twelfth to fourteenth switching elements Tr12 to Tr14.

The twelfth switching element Tr12 provided in the third node controller NC3 of the k-th stage is turned on or turned off according to the logic state of the second node QB1, and when turned on, the first AC The power line is connected between the fifth node Gd2.

The thirteenth switching element Tr13 included in the third node controller NC3 of the kth stage is turned on or turned off according to the scan pulse from the k + 1th stage, and the charging voltage VDD is turned on. Is connected between the charging power supply line and the fifth node Gd2.

The fourteenth switching element Tr14 included in the third node controller NC3 of the k-th stage is turned on or turned off in accordance with the first AC voltage VDD_O from the first AC power line. On, the fifth node Gd2 is connected to the discharge power supply line.

The pull-up switching device Tu provided in the k-th stage is turned on or turned off according to the logic state of the first node Q, and outputs a scan pulse through the output terminal OT at turn-on. At this time, the pull-up switching device Tu of each stage receives one of the first to fourth clock pulses CLK1 to CLK4 supplied from the outside, and outputs it as a scan pulse.

The first pull-down switching device Td1 provided in the k-th stage is turned on or turned off according to the logic state of the fifth node Gd2, and during turn-on, a discharge voltage is provided through the output terminal OT. Outputs (VSS).

The second pull-down switching device Td2 provided in the k-th stage is turned on or turned off according to the logic state of the sixth node, and during turn-on, the discharge voltage VSS is provided through the output terminal OT. Outputs

The operation of the stage configured as described above will be described with reference to FIGS. 2 and 3.

Since the operation of each stage is the same, the operation of the k-th stage will be described as an example.

First, the operation during the first period t1 will be described.

In the first period t1, a scan pulse in a high state from the k-1 stage is supplied to the gate electrode and the drain electrode of the first switching element Tr1 provided in the k-th stage. Then, the first switching device Tr1 is turned on, and the scan pulse is supplied to the first node Q through the turned-on first switching device Tr1. Then, the first node Q is charged with the size of the VM voltage and connected to the first node Q through the gate electrode, the pull-up switching device Tu, the sixth switching device Tr6 and the eighth switching device. (Tr8) is turned on.

The discharge voltage VSS is supplied to the second node QB1 through the turned-on sixth switching element Tr6. On the other hand, the second node QB1 is also supplied with the first AC voltage VDD_O having a high state passing through the fifth switching element Tr5 which maintains the turn-on state every odd frame period. That is, the discharge voltage VSS in the low state and the first AC voltage VDD_O in the high state are simultaneously applied to the second node QB1, and the area of the sixth switching element Tr6 is the fifth switching element ( Since it is designed to be larger than the area of Tr5, the voltage of the second node QB1 depends on the voltage supplied through the sixth switching element Tr6 having a relatively large area. In other words, the voltage of the second node QB1 in this first period t1 has a logic of low state. Accordingly, the twelfth switching element Tr12 connected to the second node QB1 discharged to have low logic through the gate electrode is turned off.

The discharge voltage VSS is supplied to the second node QB1 through the turned-on eighth switching element Tr8, and the ninth switching element Tr9 connected to the second node QB1 through a gate electrode. ) Is turned off. On the other hand, the eleventh switching element Tr11 maintains the turn-off state by the second AC voltage VDD_E maintained at the low state voltage in every odd-numbered frame period.

In addition, since there are no scan pulses from the k + 1 and k + 2 stages in the first period t1, the second switching element Tr2, the tenth switching element Tr10, and the thirteenth switching element Tr13 are It is turned off. In addition, the fourteenth switching device Tr14 maintains the turned-on state by the first AC voltage VDD_O in the high state, and the discharge voltage VSS is turned on by the fourteenth switching device Tr14 that is turned on. It is supplied to the fifth node Gd2. Accordingly, the fifth node Gd2 is discharged, and the second pull-down switching device Td2 connected to the discharged fifth node Gd2 through the gate electrode is turned off.

On the other hand, since the fourth node Gd1 of the first period t1 is in a discharged state, the first pull-down switching device Td1 connected to the fourth node Gd1 via the gate electrode is in a turn-off state.

The operation during the second period t2 will now be described.

In the second period t2, the first clock pulse CLK1 in the high state is supplied to the drain electrode of the pull-up switching device Tu provided in the first stage ST1. Accordingly, the voltage of the first node Q in the floating state is bootstraped from the VM level to the VH level by a coupling phenomenon caused by the parasitic capacitor Cgd between the gate electrode and the drain electrode of the pull-up switching device Tu. . Accordingly, the pull-up switching device Tu remains almost completely turned on, and the first clock pulse CLK1 in the high state is output as the scan pulse through the turn-on pull-up switching device Tu. ) Stable supply. The scan pulse output from the kth stage is supplied to the gate electrode of the first switching element Tr1 provided in the k + 1th stage. Accordingly, in this second period t2, the k + 1th stage operates in the same manner as the kth stage in the above-described first period t1. In addition, the scan pulse from the k-th stage is supplied to the gate electrodes of the tenth and thirteenth switching elements Tr10 and Tr13 provided in the k-th stage and the second switching provided in the k-2th stage. It is supplied to the gate electrode of the element Tr2.

Next, the operation during the third period t3 will be described.

In the third period t3, the first clock pulse CLK1 is kept low. In the third period t3, since the first node Q of the k-th stage is kept in a charged state, the pull-up switching device Tu connected to the first node Q through the gate terminal is turned on. It is a state. Therefore, in this third period, the pull-up switching device Tu of the kth stage supplies the first clock pulse CLK1 in the low state to the output terminal OT. Accordingly, the voltage of this output terminal OT transitions from the high state to the low state. Meanwhile, in the present invention, in order to further reduce the transition time of the low state from the high state of the output terminal OT, the following operation is further proceeded.

That is, in the third period t3, the second clock pulse CLK2 is supplied to the drain electrode of the pull-up switching device Tu provided in the k + 1 stage. The operation of the k + 1 stage in this third period t3 is the same as the operation of the k stage in the second period t2 described above. The scan pulse output from the k + 1th stage in the third period t3 is supplied to the gate electrodes of the tenth and thirteenth switching elements Tr13 provided in the kth stage. Then, the charging voltage VDD is supplied to the fourth node Gd1 through the turned-on tenth switching element Tr10. Meanwhile, in this period, since the eleventh switching element Tr11 is turned off, the fourth node Gd1 is maintained in a charged state, and the first pull-down connected to the fourth node Gd1 through a gate electrode is provided. The switching element Td1 is turned on. Then, the discharge voltage VSS is supplied to the output terminal OT through the turned-on first pull-down switching device Td1. As a result, the output terminal OT of the k-th stage includes the first clock pulse CLK1 in the low state from the pull-up switching device Tu described above and the discharge voltage from the first pull-down switching device Td1 described above. Since VSS) is supplied together, the voltage of this output terminal OT can be discharged faster than the existing circuit.

Meanwhile, although the charging voltage VDD is supplied to the fifth node Gd2 through the turned-on thirteenth switching element Tr13, the fifth node Gd2 is larger than the thirteenth switching element Tr13. The discharge is performed by the discharge voltage VSS supplied from the fourteenth switching element Tr14 having an area. Therefore, in the third period t3, the second pull-down switching device Td2 connected to the fifth node Gd2 via the gate electrode maintains the turn-off state.

Next, the operation during the fourth period t4 will be described.

In the fourth period t4, the scan pulse is output from the k + 2th stage, and the scan pulse from the k + 2th stage is supplied to the gate electrode of the second switching element Tr2 provided in the kth stage. The discharge voltage VSS is supplied to the first node Q through the turned-on second switching element Tr2. Then, the first node Q is discharged, and the pull-up switching device Tu, the sixth switching device Tr6 and the eighth switching device are connected to the discharged first node Q through the gate electrode. Tr8) is turned off.

As the sixth switching device Tr6 is turned off, the second node QB1 of the k-th stage is charged by the first AC voltage VDD_O of the high state from the fifth switching device Tr5. As a result, the twelfth switching element Tr12 connected to the second node QB1 through the gate electrode is turned on. The first AC voltage VDD_O in a high state is supplied to the fifth node Gd2 through the turned-on twelfth switching element Tr12. On the other hand, since the twelfth switching element Tr12 has a larger area than the fourteenth switching element Tr14, the fourteenth switching element Tr14 is turned on in the fourth period t4. The fifth node Gd2 remains charged. Accordingly, the second pull-down switching device Td2 connected to the charged fifth node Gd2 through the gate electrode is turned on. Then, the discharge voltage VSS is supplied to the output terminal OT through the turned-on second pull-down switching device Td2.

Each stage also operates in the same manner as the k-th stage described above.

On the other hand, as the first AC voltage VDD_O is kept low in the even-numbered frame period and the second AC voltage VDD_E is kept high, in the even-numbered frame period, instead of the fourth node Gd1, the first AC voltage VDD_O is kept low. Five nodes Gd2 are charged. Specifically, in the even-numbered frame period, when the kth stage receives the scan pulse from the k + 1th stage, the second pull-down switching device Td2 is operated by the third node controller NC3. In addition, in the even-numbered frame period, when the kth stage receives the scan pulse from the k + 2th stage, the first pulldown switching element Td1 operates instead of the second pulldown switching element Td2. As described above, as the first and second pull-down switching devices Td1 and Td2 operate alternately for each frame period, deterioration of the first and second pull-down switching devices Td1 and Td2 may be prevented.

On the other hand, the start pulse Vst is supplied to the gate electrode of the second switching element Tr2 provided in the first dummy stage STn + 1. The start pulse Vst is also supplied to the gate electrodes of the second, tenth, and thirteenth switching elements Tr2, Tr10, and Tr13 provided in the second dummy stage STn + 2.

4 is a timing diagram of various types of signals supplied or output to each stage of FIG. 1.

As shown in FIG. 4, the first to fourth clock pulses CLK1 to CLK4 are output in a form in which they are overlapped for a predetermined period. The shift register according to the present invention may use the first to fourth clock pulses CLK1 to CLK4 as shown in FIG. 4 instead of the first to fourth clock pulses CLK1 to CLK4 shown in FIG. 2. When the first to fourth clock pulses CLK1 to CLK4 as shown in FIG. 4 are used, the k-th stage sets the scan pulses from the k-2 stage instead of the k-1st stage to the set terminal SE. Received through The first start pulse Vst1 is supplied to the set terminal SE of the first stage ST1, and the second start pulse Vst2 is supplied to the set terminal SE of the second stage ST2.

5 is a diagram illustrating voltage states of first, second, and fourth nodes Q, QB1, and Gd1 of an arbitrary stage included in the shift register and scan pulses output from the k-th stage. It is a figure which shows a waveform.

6 is a view for comparing the waveform of the scan pulse output from any stage provided in the conventional shift register and the waveform of the scan pulse output from any stage provided in the shift register according to an embodiment of the present invention. As shown in FIG. 6, it can be seen that the transition time from the high state to the low state of the scan pulse is shorter than the transition time from the high state to the low state of the conventional scan pulse.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 illustrates a shift register according to an embodiment of the present invention.

FIG. 2 is a timing diagram of various signals supplied or output to each stage of FIG. 1. FIG.

3 is a diagram showing the configuration of any one stage shown in FIG.

4 is a timing diagram of various types of signals supplied or output to each stage of FIG. 1.

FIG. 5 is a view illustrating voltage states of first, second, and fourth nodes of a stage provided in a shift register and waveforms of scan pulses output from a k-th stage according to an embodiment of the present invention; FIG.

6 is a view for comparing the waveform of the scan pulse output from any stage provided in the conventional shift register with the waveform of the scan pulse output from any stage provided in the shift register according to an embodiment of the present invention.

Claims (4)

A plurality of stages that sequentially output scan pulses; K stage, A first node controller configured to control logic states of the first to third nodes according to the scan pulse from the k-1th stage and the scan pulse from the k + 2th stage; A second node controller for controlling the logic state of the fourth node according to the logic state of the second node of the kth stage and the scan pulse from the k + 1 stage; A third node controller for controlling the logic state of the fifth node according to the logic state of the third node of the kth stage and the scan pulse from the k + 1 stage A pull-up switching device which is turned on or turned off according to a logic state of the first node and outputs as a scan pulse through an output terminal at turn-on; A first pull-down switching device that is turned on or turned off according to a logic state of the fifth node, and outputs a discharge voltage through the output terminal when turned on; And, And a second pull-down switching device which is turned on or turned off according to the logic state of the sixth node, and outputs a discharge voltage through the output terminal when turned on. The method of claim 1, The first node controller provided in the k-th stage is A first switching device which is turned on or off according to a scan pulse from the k-1th stage and connects an output terminal of the k-1th stage and the first node when turned on; A second switching element which is turned on or off according to the scan pulse from the k + 2th stage and connects the discharge power supply line to the first node for transmitting the discharge voltage at turn-on; A third switching element which is turned on or off according to the logic state of the second node and connects between the first node and the discharge power supply line when turned on; A fourth switching element which is turned on or turned off according to the logic state of the third node and connects between the first node and the discharge power supply line when turned on; A fifth switching element which is turned on or off in accordance with a first AC voltage from a first AC power line and connects the first AC power line and the second node when turned on; A sixth switching element which is turned on or turned off according to the logic state of the first node and connects between the second node and a power supply line for discharge when turned on; A seventh switching element which is turned on or turned off according to a second AC voltage from a second AC power line and connects the second AC power line and a discharge power line at turn-on; And, And an eighth switching element which is turned on or turned off according to the logic state of the first node and connects the third node and the power supply line for discharge when turned on. The method of claim 2, The second node controller provided in the k-th stage is A ninth switching element turned on or off according to a logic state of the third node, and connected between the first AC power line and a fourth node when turned on; A tenth switching element which is turned on or off according to the scan pulse from the k + 1th stage and connects the charging power supply line transmitting the charging voltage with the fourth node at turn-on; And, And an eleventh switching element which is turned on or off according to a second AC voltage from the second AC power line and connects the fourth node to a discharge power line during turn-on. Shift register. The method of claim 3, wherein The third node controller provided in the n th stage is A twelfth switching element which is turned on or turned off according to a logic state of the second node and connects between the first AC power line and a fifth node when turned on; A thirteenth switching element which is turned on or off according to the scan pulse from the k + 1th stage and connects the charging power supply line transmitting the charging voltage with the fifth node at turn-on; And, And a fourteenth switching element which is turned on or off according to a first AC voltage from the first AC power line and connects the fifth node to a discharge power line when turned on. Shift register.

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