KR101232152B1 - A gate driver and a method for driving the same - Google Patents

Abstract

The present invention relates to a gate driving circuit capable of preventing deterioration of a pull-down switching device and a driving method thereof, comprising: a plurality of first stages connected to one side of each gate line; And a plurality of second stages connected to the other side of each gate line, wherein the first stage and the second stage connected to the same gate line simultaneously output the gate on voltage, and alternately output the gate off voltage. It is characterized by.

Shift register, stage, gate on voltage, gate off voltage

Description

A gate driver and a method for driving the same {A gate driver and a method for driving the same}

1 is a view showing a conventional gate driving circuit

2 illustrates a gate driving circuit according to a first embodiment of the present invention.

3 is a diagram illustrating waveforms of a clock pulse supplied to the first and second shift registers of FIG. 2 and a gate on voltage output from the first and second shift registers.

4 shows waveforms for first and second AC voltage sources supplied to the first and second shift registers of FIG.

5 is a diagram for describing an operation of a first stage provided in the first shift register and a first stage provided in the second shift register of FIG. 2.

FIG. 6 is a diagram illustrating a configuration of a first stage provided in the first and second shift registers of FIG. 2. FIG.

7 is a diagram illustrating a circuit configuration of a second stage provided in the first shift register of FIG. 2.

8 is a diagram illustrating a circuit configuration of a second stage provided in the second shift register of FIG. 2.

FIG. 9 is a diagram illustrating a circuit configuration of the first to third stages of FIG. 2.

FIG. 10 is a diagram illustrating another circuit configuration of a second stage provided in the first shift register of FIG. 2.

FIG. 11 is a diagram illustrating another circuit configuration of a second stage included in the second shift register of FIG. 2.

FIG. 12 is a diagram illustrating another circuit configuration of a second stage provided in the first shift register of FIG. 2.

FIG. 13 is a diagram illustrating another circuit configuration of a second stage provided in the second shift register of FIG. 2.

14 is a view illustrating another circuit configuration of the first to third stages of FIG.

FIG. 15 is a view showing another circuit configuration of the first switching device shown in FIGS. 7, 8, 10, 11, and 12;

16 illustrates a gate driving circuit according to a second embodiment of the present invention.

17 illustrates a gate driving circuit according to a third embodiment of the present invention.

18 illustrates a gate driving circuit according to a fourth embodiment of the present invention.

19 illustrates a gate driving circuit according to a fifth embodiment of the present invention.

20 is a diagram illustrating a circuit configuration of a third stage included in the first shift register of FIG. 19.

FIG. 21 is a diagram illustrating a circuit configuration of a second stage included in the second shift register of FIG. 19.

FIG. 22 is a diagram illustrating a circuit configuration of the first to third stages of FIG. 19.

* Explanation of symbols on the main parts of the drawings

CLK: Clock Pulse ST: Stage

Von: Gate On Voltage SR: Shift Register

Vdc: DC voltage source Vac: AC voltage source

Vst: Start Pulse GL: Gate Line

The present invention relates to a gate driving circuit, and more particularly, to a gate driving circuit and a driving method thereof capable of preventing deterioration of a pull-down switching device.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged in an intersecting manner, and a pixel region is located in an area defined by vertically intersecting the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed on the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a scan pulse applied to a gate terminal via the gate line so that a data signal of the data line is charged to the pixel voltage.

The driving circuit may include a gate driving circuit for driving the gate lines, a data driving circuit for driving the data lines, a timing controller for supplying a control signal for controlling the gate driving circuit and the data driving circuit; And a power supply unit supplying various driving voltages used in the liquid crystal display.

The gate driving circuit sequentially supplies the gate-on voltage to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driving circuit supplies a pixel voltage signal to each of the data lines whenever a scan pulse is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Here, the gate driving circuit includes a shift register to sequentially output the gate on voltage as described above. Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a view showing a conventional gate driving circuit.

The conventional gate driving circuit is connected to one side of the gate lines GL1 to GLm as shown in FIG. 1 to sequentially apply gate-on voltages Von1 to Vonm to the gate lines GL1 to GLm. A second shift register 10a to be supplied and a second to be connected to the other side of the gate lines GL1 to GLm to sequentially supply gate on voltages Von1 to Vonm to the gate lines GL1 to GLm. A shift register 10b.

The first shift register 10a includes first to mth stages ST1_L to STm_L connected to each other independently. The first to mth stages ST1_L to STm_L sequentially output the first to mth gate on voltages Von1 to Vonm, and gate off in a period except for a period during which the gate on voltages Von1 to Vonm are output. Output voltage.

The second shift register 10b also includes first to mth stages ST1_R to STm_R connected to each other independently. The first to m th stages ST1_R to STm_R sequentially output the first to m th gate on voltages Von1 to Vonm, and gate off in a period except for a period during which the gate on voltages Von1 to Vonm are output. Output voltage.

Here, the stages ST1_L to STm_L of the first shift register 10a and the stages ST1_R to STm_R of the second shift register 10b corresponding to the gate on voltages Von1 to Vonm are simultaneously connected to each other. And a gate off voltage.

For example, the first stage ST1_L of the first shift register 10a connected to one side of the first gate line GL1 and the second shift register 10b connected to the other side of the first gate line GL1. First stage ST1_R simultaneously outputs the first gate on voltage Von1 to the first gate line GL1 in the enable period, and simultaneously outputs the gate off voltage in the disable period to the first stage ST1_R. Supply to gate line GL1.

For this operation, each of the stages ST1_L to STm_L and ST1_R to STm_R includes a node controller for controlling charging and discharging of the first node and charging and discharging of the second node, and a gate according to the state of the first node. A pull-up switching device for outputting an on voltage, and a pull-down switching device for outputting a gate-off voltage according to the state of the second node.

On the other hand, since each of the stages ST1_L to STm_L and ST1_R to STm_R outputs a gate-off voltage for the remaining period except one horizontal period 1H of one frame, the time for which the second node is kept in the charged state is It will inevitably be much longer than the time the first node remains charged. Accordingly, the pull-down switching device connected to the second node remains on for much longer than the pull-up switching device. This causes a problem that the pull-down switching device is easily degraded.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and by charging each of the second nodes of the stages connected to both sides of the same gate line alternately with each other, the degradation of the pull-down switching device connected to the second node is prevented. It is an object of the present invention to provide a gate driving circuit and a driving method thereof.

According to another aspect of the present invention, a gate driving circuit includes: a plurality of first stages connected to one side of each gate line; And a plurality of second stages connected to the other side of each gate line, wherein the first stage and the second stage connected to the same gate line simultaneously output the gate on voltage, and alternately output the gate off voltage. It is characterized by that.

In addition, a method of driving a gate driving circuit according to the present invention for achieving the above object includes a plurality of first stages connected to one side of each gate line and a plurality of first stages connected to the other side of each gate line. A method of driving a gate driving circuit comprising two stages, comprising: simultaneously supplying gate-on voltages from a first stage and a second stage connected to the same gate line to the gate line; And supplying a gate off voltage from one of the first stage and the second stage to the gate line.

Hereinafter, a gate driving circuit according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a diagram illustrating a gate driving circuit according to a first embodiment of the present invention, and FIG. 3 is a clock pulse supplied to the first and second shift registers of FIG. 2 and output from the first and second shift registers. A waveform showing a gate on voltage.

As shown in FIG. 2, the gate driving circuit according to the first embodiment of the present invention includes a first shift register connected to one end of gate lines GL1 to GLm, and the gate lines GL1 to GLm. And a second shift register SR2 connected to the other end of the.

The first shift register SR1 outputs a gate on voltage at predetermined intervals, and sequentially supplies the output gate on voltage to the m-th gate line GLm from the first gate line GL1. In addition, the first shift register SR1 outputs a gate off voltage Voff in a period other than the output period of the gate on voltage and supplies the gate off voltage Voff to the gate lines GL1 to GLm.

The gate on voltages Von1 to Vonm are voltages for charging the gate lines GL1 to GLm, and are connected to the gate lines GL1 to GLm by the gate on voltages Von1 to Vonm. The thin film transistor of the pixel cell is turned on. At this time, each pixel cell receives a data voltage from a data line to display an image.

The gate off voltage Voff is a voltage for discharging the gate lines GL1 to GLm, and is a thin film of a pixel cell connected to the gate lines GL1 to GLm by the gate off voltage Voff. The transistor is turned off. At this time, each pixel cell displays and holds an image for one frame by maintaining the supplied data voltage until the gate-on voltage is supplied to the next frame.

For this function, as illustrated in FIG. 2, the first shift register SR1 includes m stages ST1_L to STm_L and one dummy stage STm + 1_L that are dependently connected to each other. The first to m th stages ST1_L to STm_L are connected to one end of the first to m th gate lines GL1 to GLm, and the dummy stage STm + 1_L is not connected to any gate line. .

As illustrated in FIG. 3, each stage ST1_L to STm + 1_L provided in the first shift register SR1 may include a first DC voltage source Vdc1, a second DC voltage source Vdc2, and a start pulse. Vst) and one of the clock pulses CLK1 to CLK4 is supplied.

Here, each of the stages ST1_L to STm + 1_L outputs one gate on voltage Von1 to Vonm + 1 in one frame, and in this case, the first stage ST1_L to the dummy stage STm + 1_L in order. The gate on voltages Von1 to Vonm + 1 are output. Here, the gate on voltages Von1 to Vonm output from the remaining stages ST1_L to STm_L except for the dummy stage STm + 1_L are sequentially supplied to the gate lines GL1 to GLm, thereby providing the gate. The lines GL1 to GLm are sequentially scanned.

That is, firstly, the first stage ST1_L outputs the first gate on voltage Von1, and then the second stage ST2_L outputs the second gate on voltage Von2, and then, the third stage ST1_L. ST3_L outputs the third gate-on voltage Von3, and the m-th stage STm_L outputs the m-th gate-on voltage Vonm. Meanwhile, after the m-th stage STm_L outputs the m-th gate on voltage Vonm, the dummy stage STm + 1_L outputs the m + 1 gate on voltage, wherein the dummy stage STm + The m + 1 gate-on voltage output from 1_L is not supplied to the gate line, but only to the m-th stage STm_L.

The second shift register SR2 also has first to mth stages ST1_R to STm_R and one dummy stage STm + 1_R. The first to m th stages ST1_R to STm_R included in the second shift register SR2 are connected to the other ends of the first to m th gate lines GL1 to GLm. The dummy stage STm + 1_R is not connected to any gate line.

In addition, each stage ST1_R to STm + 1_R included in the second shift register SR2 also includes the first DC voltage source Vdc1, the second DC voltage source Vdc2, the start pulse Vst, and the clock pulse. One of the clock pulses CLK1 to CLK4 is supplied.

On the other hand, the stages ST1_L to STm + 1_L provided in the first shift register SR1 and the stages ST1_R to STm + 1_R provided in the second shift register SR2 may use different AC voltage sources. To be supplied.

4 is a diagram illustrating waveforms of first and second AC voltage sources supplied to the first and second shift registers of FIG. 2.

The stages ST1_L to STm + 1_L provided in the first shift register SR1 are commonly supplied with the first AC voltage source Vac1 as shown in FIG. 4. The stages ST1_R to STm + 1_R provided in the second shift register SR2 are commonly supplied with a second AC voltage source Vac2 as illustrated in FIG. 4.

As shown in FIG. 4, the first and second alternating voltage sources Vac1 and Vac2 alternate between the high voltage source Vh and the low voltage source Vl at regular intervals. In this case, the first AC voltage source Vac1 has a phase inverted by 180 degrees with respect to the second AC voltage source Vac2. Therefore, in the same period, the first AC voltage source Vac1 and the second AC voltage source Vac2 have voltage values of different polarities.

That is, the high voltage source Vh may be a positive voltage source and may have the same voltage as the first DC voltage source Vdc1, and the low voltage source V1 may be a negative voltage source and the second DC voltage source Vdc2. May have the same voltage.

The first and second alternating current voltage sources Vac1 and Vac2 are preferably changed in a fixed period, that is, in units of frames. For example, in the odd-numbered frame, the first AC voltage source Vac1 may have a low voltage source Vl, and the second AC voltage source Vac2 may have a high voltage source Vh. The first AC voltage source Vac1 may have a high voltage source Vh, and the second AC voltage source Vac2 may have a low voltage source Vl.

In addition, the first AC voltage source Vac1 may have a low voltage source Vl and the second AC voltage source Vac2 may have a high voltage source Vl for several consecutive frames. The first AC voltage source Vac1 may have a high voltage source Vh and the second AC voltage source Vac2 may have a low voltage source Vl for several frames.

As such, the first and second phases in which the stages ST1_L to STm + 1_L of the first shift register SR1 and the stages ST1_R to STm + 1_R of the second shift register SR2 are inverted in phase with each other Since the AC voltage sources Vac1 and Vac2 are supplied, the stages ST1_L to STm + 1_L of the first shift register SR1 and the stages ST1_R to STm + 1_R of the second shift register SR2 It is driven as follows.

That is, the stages ST1_L to STm + 1_L of the first shift register SR1 and the stages ST1_R to STm + 1_R of the second shift register SR2 are simultaneously gate-on voltages Von1 to Vonm + 1. ) And the gate-off voltage Voff are alternately outputted.

FIG. 5 is a diagram for describing an operation of a first stage provided in the first shift register of FIG. 2 and a first stage provided in the second shift register.

For example, as illustrated in FIG. 5A, the first stage ST1_L and the first gate line GL1 of the first shift register SR1 connected to one end of the first gate line GL1. The first stage ST1_R of the second shift register SR2 connected to the other end of the output terminal simultaneously outputs a first gate-on voltage Von1 and simultaneously supplies the same to the first gate line GL1. After the output of the first gate on voltage Von1, as shown in FIG. 5B or FIG. 5C, any one of the first stages ST1_L and ST1_R corresponds to the first stage. The gate off voltage Voff is output to one gate line GL1.

Therefore, in the period of outputting the gate off voltage Voff, any one of the first stages ST1_L and ST1_R has a rest period in which no output occurs.

The remaining stages of the pair also operate in the same manner as the pair of first stages ST1_L and ST1_R.

Here, the configuration of each stage provided in the first and second shift registers SR1 and SR2 will be described in more detail as follows.

Since all stages have the same configuration, only the first stages ST1_L and ST1_R of the first and second shift registers SR1 and SR2 will be described as an example.

FIG. 6 is a diagram illustrating a configuration of a first stage provided in the first and second shift registers of FIG. 2.

The first stage ST1_L of the first shift register includes a node controller 401 for controlling charging and discharging of the first node Q, and charging and discharging of the second node QB, and the first node (1). A pull-up switching device Trpu for outputting a gate-on voltage in accordance with the state of Q), and a pull-down switching device Trpd for outputting a gate-off voltage in accordance with the state of the second node QB.

Here, the node controller 601 included in the first shift register SR1 controls the first and second nodes QB as follows.

First, in the enable period, the node controller 601 charges the first node Q and discharges the second node QB. In the disable period, the node controller 601 performs one of the first operation and the second operation. That is, the node controller 601 discharges the first node Q and charges the second node QB, and the second operation discharges both the first and second nodes QB. Perform any of the operations.

At this time, the node controller 601 selects one of the first operation and the second operation according to the polarity of the first AC voltage source Vac1 described above. For example, when the first AC voltage source Vac1 is the high voltage source Vh, the node controller 601 discharges the first node Q and charges the second node QB during the disable period. Let's do it. On the contrary, when the first AC voltage source Vac1 is the low voltage source V1, the node controller 601 discharges both the first and second nodes Q and QB during the disable period.

Meanwhile, the first stage ST1_R of the second shift register SR2 also has the same configuration as the first stage ST1_L of the first shift register SR1.

However, the node control unit 601 included in the first stage ST1_R of the second shift register SR2 next follows the first node Q and the second node QB of the first stage ST1_R. Control it together.

That is, the node controller 601 of the second shift register SR2 selects one of the first operation and the second operation according to the polarity of the second AC voltage source Vac2 described above. In this case, since the first AC voltage source Vac1 and the second AC voltage source Vac2 have opposite phases, the node control unit 601 and the right first stage of the left first stage ST1_L during the disable period. The node controller 601 of ST1_R performs different operations.

That is, in the same disable period, the node controller 601 of the left first stage ST1_L performs a first operation, and the node controller 601 of the right first stage ST1_R performs a second operation. . Therefore, in the same disable period, the first node Q of the left first stage ST1_L is in a discharge state and the second node QB is in a charged state. In contrast, both the first and second nodes Q and QB of the right first stage ST1_R are in a discharge state.

As a result, in the disable period, the pull-up switching device Trpu of the left first stage ST1_L is turned off and the pull-down switching device Trpd is turned on, so that the left first stage ST1_L is turned on. The gate-off voltage Voff is output to the first gate line GL1 through the on pull-down switching element Trpd. On the contrary, during the disable period, both the pull-up switching device Trpu and the pull-down switching device Trpd of the right first stage ST1_R are turned off so that the right first stage ST1_R generates no output. Don't let that happen.

In other words, since the second node QB of the right first stage ST1_R is in a discharged state during the disable period, a pull-down switching device Trpd having a gate terminal connected to the second node QB in the discharged state. Has a rest period. Similarly, since the second node QB of the left first stage ST1_L is in a discharged state in a next disable period, a pull-down switching device Trpd having a gate terminal connected to the second node QB in the discharged state. Has a rest period.

As described above, the pull-down switching element Trpd of the left stages ST1_L to STm + 1_L and the pull-down switching elements Trpd of the right stages ST1_R to STm + 1_R are alternately driven so that the present invention pulls down the pull-down switching element Trpd. Deterioration of the switching element Trpd can be prevented.

Here, a circuit configuration provided in each of the stages ST1_L to STm + 1_L and ST1_R to STm + 1_R of the first and second shift registers SR1 and SR2 will be described below.

FIG. 7 is a diagram illustrating a circuit configuration of a second stage included in the first shift register of FIG. 2.

The stages ST1_L to STm_L and the dummy stages STm + 1_L provided in the first shift register SR1 may include first to ninth switching elements Tr1 to Tr9, and first and second capacitors C1 and C2. Has

The first switching device Tr1 provided in each of the stages ST1_L to STm + 1_L receives the first node Q of the stage to which it belongs in response to the gate-on voltage from the first front end stage. Charge to Vdc1).

For example, the first switching device Tr1 included in the second stage ST2_L of FIG. 7 may respond to the first gate on voltage Von1 from the first stage ST1_L. Charges the first node (Q) of the first DC voltage source (Vdc1). To this end, the gate terminal of the first switching device Tr1 provided in the second stage ST2_L is connected to the first stage ST1_L, and the drain terminal is a power source for transmitting the first DC voltage source Vdc1. It is connected to the line, and the source terminal is connected to the first node (Q).

The second switching device Tr2 provided in each of the stages ST1_L to STm + 1_L has a response to the first AC voltage source Vac1 charged to the second node QB of the stage to which the stage belongs. The first node Q is discharged to the second DC voltage source Vdc2.

For example, the second switching device Tr2 provided in the second stage ST2_L of FIG. 7 responds to the first AC voltage source Vac1 charged in the second node QB of the second stage ST2_L. As a result, the first node Q of the second stage ST2_L is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the second switching element Tr2 provided in the second stage ST2_L is connected to the second node QB of the second stage ST2_L, and the drain terminal of the second DC voltage source. It is connected to the power line for transmitting (Vdc2), the source terminal is connected to the first node (Q) of the second stage (ST2_L).

The third switching device Tr3 included in each of the stages ST1_L to STm + 1_L transmits the first node Q of the stage to which it belongs to the second DC voltage source in response to the gate-on voltage from the first next stage. Discharge at (Vdc2).

For example, the third switching device Tr3 included in the second stage ST2_L of FIG. 7 may respond to the third gate on voltage Von3 from the third stage ST3_L. The first node (Q) of D is discharged to the second DC voltage source (Vdc2). To this end, the gate terminal of the third switching device Tr3 provided in the second stage ST2_L is connected to the third stage ST3_L, and the drain terminal thereof is the first node Q of the second stage ST2_L. Is connected to the power supply line for transmitting the second DC voltage source Vdc2.

The fourth switching device Tr4 included in each of the stages ST1_L to STm + 1_L outputs the second DC voltage source Vdc2 in response to the start pulse Vst from the timing controller, and this is the stage to which it belongs. To the common node (N).

For example, the fourth switching device Tr4 provided in the second stage ST2_L of FIG. 7 outputs the second DC voltage source Vdc2 in response to the start pulse Vst from the timing controller. The common node N of the second stage ST2_L is supplied. To this end, the gate terminal of the fourth switching device Tr4 provided in the second stage ST2_L is connected to the timing controller, and the drain terminal is connected to the common node N of the second stage ST2_L. The source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The fifth switching device Tr5 provided in each stage ST1_L to STm + 1_L is configured to respond to the second DC voltage source Vdc1 in response to the first DC voltage source Vdc1 charged in the first node Q of the stage to which it belongs. Outputs Vdc2) and supplies it to the common node (N) of the stage to which it belongs.

For example, the fifth switching device Tr5 provided in the second stage ST2_L of FIG. 7 responds to the first DC voltage source Vdc1 charged in the first node Q of the second stage ST2_L. To output a second DC voltage source Vdc2 and supply it to the common node N of the second stage ST2_L. To this end, the gate terminal of the fifth switching device Tr5 provided in the second stage ST2_L is connected to the first node Q of the second stage ST2_L, and the drain terminal of the second stage ST2_L It is connected to the common node N of ST2_L, and the source terminal is connected to the power supply line which transmits the said 2nd DC voltage source Vdc2.

The sixth switching device Tr6 included in each of the stages ST1_L to STm + 1_L is turned on or turned off in response to a first AC voltage source Vac1, and when turned on, the first AC voltage source Vac1 is turned on. ) Is supplied to the common node (N) of the stage to which it belongs.

For example, the sixth switching device Tr6 included in the second stage ST2_L of FIG. 7 is turned on or turned off in response to the first AC voltage source Vac1, and when turned on, the first switching element Tr6 is turned on. The AC voltage source Vac1 is supplied to the common node N of the second stage ST2_L. To this end, the gate terminal and the drain terminal of the sixth switching device Tr6 provided in the second stage ST2_L are connected to a power line for transmitting the first AC voltage source Vac1, and the source terminal of the second stage ST2_L is connected to the power line. It is connected to the common node N of the stage ST2_L.

The seventh switching element Tr7 included in each stage ST1_L to STm + 1_L is connected to the second DC voltage source Vdc2 and the first AC voltage source Vac1 supplied to the common node N of the stage to which the stage belongs. In response, it is turned on or turned off, and when turned on, the second node QB of the stage to which it belongs is charged or discharged to the first AC voltage source Vac1.

For example, the seventh switching device Tr7 included in the second stage ST2_L of FIG. 7 includes the second DC voltage source Vdc2 and the second DC voltage supplied to the common node N of the second stage ST2_L. It is turned on or turned off in response to the first AC voltage source Vac1, and charges or discharges the second node QB of the second stage ST2_L to the first AC voltage source Vac1 during turn-on. To this end, the gate terminal of the seventh switching element Tr7 provided in the second stage ST2_L is connected to the common node N of the second stage ST2_L, and the drain terminal of the first AC voltage source ( Vac1) is connected to the power supply line, and the source terminal is connected to the second node QB of the second stage ST2_L.

The eighth switching device Tr8 included in each of the stages ST1_L to STm + 1_L includes the stage of the stage to which the eighth switching element Tr8 belongs in response to the first DC voltage source Vdc1 charged to the first node Q of the stage. The second node QB is discharged to the second DC voltage source Vdc2.

For example, the eighth switching device Tr8 included in the second stage ST2_L of FIG. 7 is connected to the first DC voltage source Vdc1 charged in the first node Q of the second stage ST2_L. In response, the second node QB of the second stage ST2_L is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the eighth switching element Tr8 provided in the second stage ST2_L is connected to the first node Q of the second stage ST2_L, and the drain terminal of the second stage ST2_L It is connected to the second node QB of ST2_L, and the source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The ninth switching device Tr9 provided in each of the stages ST1_L to STm + 1_L receives the second node QB of the stage to which it belongs in response to the gate-on voltage from the first front stage. Discharge to Vdc2).

For example, the ninth switching device Tr9 included in the second stage ST2_L of FIG. 7 may respond to the first gate on voltage Von1 from the first stage ST1_L. Discharges the second node QB to the second DC voltage source Vdc2. To this end, the gate terminal of the ninth switching element Tr9 provided in the second stage ST2_L is connected to the first stage ST1_L, and the drain terminal thereof is the second node QB of the second stage ST2_L. Is connected to the power supply line for transmitting the second DC voltage source Vdc2.

The pull-up switching device Trpu outputs the clock pulse as a gate on voltage in response to the first DC voltage source Vdc1 charged to the first node Q of the stage to which the pull-up switching device Trpu belongs, and outputs the gate on voltage to the corresponding gate. It is supplied to a line, a front stage, and a next stage. At this time, the gate on voltage output to the front stage serves as a signal for disabling the front stage, and the gate on voltage output to the next stage is a start pulse Vst for enabling the next stage. Function as.

For example, the pull-up switching device Trpu provided in the second stage ST2_L of FIG. 7 receives the second clock pulse CLK2 in response to the first DC voltage source Vdc1 charged in the first node Q. The second gate on voltage Von2 is output as the second gate on voltage Von2, and the second gate on voltage Von2 is supplied to the second gate line GL2, the first stage ST1_L, and the third stage ST3_L. To this end, the gate terminal of the pull-up switching device Trpu provided in the second stage ST2_L is connected to the first node Q of the second stage ST2_L, and the drain terminal of the second clock pulse It is connected to a clock transmission line for transmitting CLK2, and a source terminal is connected to the second gate line GL2, the first stage ST1_L, and the third stage ST3_L.

The pull-down switching device Trpd outputs the second DC voltage source Vdc2 as the gate-off voltage Voff in response to the first AC voltage source Vac1 charged in the second node QB of the stage to which the pull-down switching device Trpd belongs. The gate off voltage Voff is supplied to the corresponding gate line, the front stage, and the next stage.

For example, the pull-down switching device Trpd included in the second stage ST2_L of FIG. 7 may respond to the first AC voltage source Vac1 charged in the second node QB of the second stage ST2_L. The second DC voltage source Vdc2 is output as the gate off voltage Voff, and the gate off voltage Voff is supplied to the second gate line GL2, the first stage ST1_L, and the third stage ST3_L. do. To this end, the gate terminal of the pull-down switching device (Trpd) provided in the second stage (ST2_L) is connected to the second node (QB) of the second stage (ST2_L), the source terminal of the second DC voltage source ( Vdc2) is connected to the power supply line, and the drain terminal is connected to the second gate line GL2, the first stage ST1_L, and the third stage ST3_L.

The first capacitor C1 is connected between the gate terminal and the source terminal of the pull-up switching device Trpu to facilitate a bootstrapping operation of the pull-up switching device Trpu.

The second capacitor C2 is connected between the gate terminal and the drain terminal of the pull-down switching device Trpd to facilitate the bootstrapping operation of the pull-down switching device Trpd.

Each switching device provided in the first stage ST1_L, the third to mth stages ST3_L to STm_L, and the dummy stage STm + 1_L also operates in the same manner as described above.

However, since the stage does not exist in the first front end of the first stage ST1_L, the first and ninth switching elements Tr1 and Tr9 included in the first stage ST1_L may have a start pulse (T1) from the timing controller. It operates by receiving Vst). That is, the first stage ST1_L is enabled by the start pulse Vst.

In addition, since the stage does not exist at the first stage after the dummy stage STm + 1_L, the third switching device Tr3 included in the dummy stage STm + 1_L has a start pulse from the timing controller. It operates by receiving Vst). That is, the dummy stage STm + 1_L is disabled by the start pulse Vst.

Next, a circuit configuration of the stages ST1_R to STm_R and the dummy stage STm + 1_R included in the second shift register SR2 will be described.

8 is a diagram illustrating a circuit configuration of a second stage provided in the second shift register of FIG. 2.

The circuit configuration of each stage ST1_R to STm + 1_R provided in the second shift register SR2 is the same as that of each stage ST1_L to STm + 1_L provided in the first shift register SR1 described above. Do. However, the second AC voltage source Vac2 is supplied to the sixth and seventh switching elements Tr6 and Tr7 of each stage ST1_R to STm + 1_R.

For example, as illustrated in FIG. 8, a second alternating current is provided to the gate terminal and the drain terminal of the sixth switching device Tr6 and the drain terminal of the seventh switching device Tr7 provided in the second stage ST2_R. The voltage source Vac2 is supplied.

The operation of the gate driving circuit according to the first embodiment of the present invention configured as described above will be described in detail as follows.

Here, the operation of the first shift register SR1 will be described for each period as follows.

FIG. 9 is a diagram illustrating a circuit configuration of the first to third stages of FIG. 2.

First, the operation of the start period in the first frame will be described.

During the initial period, as shown in FIG. 3, only the start pulse Vst output from the timing controller is kept high and the remaining clock pulses are kept low.

The start pulse Vst output from the timing controller is input to the first stage ST1_L. Specifically, as shown in FIG. 9, the start pulse Vst includes the gate terminal of the first switching element Tr1 and the gate terminal of the fourth switching element Tr4 provided in the first stage ST1_L. And the gate terminal of the ninth switching element Tr9.

Then, the first, fourth, and ninth switching elements Tr9 are turned on, and at this time, the first DC voltage source Vdc1 is connected to the first node through the turned-on first switching elements Tr1. Is applied to Q). Accordingly, the first node Q is charged, and the pull-up switching device Trpu, the fifth switching device Tr5, and the eighth switching device having a gate terminal connected to the charged first node Q are connected. Tr8) are all turned on.

Here, the second DC voltage source Vdc2 is supplied to the second node QB through the turned-on eighth switching device Tr8 and the ninth switching device Tr9. Accordingly, the second node QB is discharged by the second DC voltage source Vdc2, and the pull-down switching device Trpd having a gate terminal connected to the second node QB is turned off.

In addition, a second DC voltage source Vdc2 is applied to the common node N through the turned-on fourth and fifth switching devices Tr4 and Tr5. Accordingly, the common node N is discharged, and the seventh switching element Tr7 having a gate terminal connected to the common node N is turned off. As the seventh switching element Tr7 is turned off, the supply of the first AC voltage source Vac1 to the second node QB is blocked.

As such, during the initial period, as illustrated in FIG. 9, the first node Q of the first stage ST1_L is charged with the first DC voltage source Vdc1, and the second node QB is charged. The first stage ST1_L is enabled by discharging to the second DC voltage source Vdc2.

On the other hand, the start pulse Vst output in the initial period is also applied to each of the fourth switching elements Tr4 provided in the second to mth stages ST2_L to STm_L and the dummy stage STm + 1_L. The common node N of the stages ST2_L to STm_L and STm + 1_L is discharged. Since the start pulse Vst is output once in one frame, the common node N of all the stages ST1_L to STm + 1_L is discharged in the initial period of every frame.

Next, the operation during the first period will be described.

During the first period, as shown in FIG. 6, only the first clock pulse CLK1 remains high and the remaining clock pulses remain low. Accordingly, the first, fourth, and ninth switching elements Tr1, Tr4, and Tr9 of the first stage ST1_L are turned off in response to the low state start pulse Vst, thereby turning off the first. The first node Q of the stage ST1_L remains in a floating state.

Meanwhile, as the first node Q of the first stage ST1_L is continuously maintained as the first DC voltage source Vdc1 applied during the initial period, the pull-up switching device Trpu of the first stage ST1_L is maintained. Remains turned on. In this case, as the first clock pulse CLK1 is applied to the drain terminal of the turned-on pull-up switching device Trpu, the first DC voltage source charged in the first node Q of the first stage ST1_L. Vdc1 is amplified by bootstrapping.

Therefore, the first clock pulse CLK1 applied to the drain terminal of the pull-up switching device Trpu of the first stage ST1_L is stably output through the source terminal of the pull-up switching device Trpu. In this case, the output first clock pulse CLK1 is applied to the first gate line GL1 and functions as a first gate on voltage Von1 for driving the first gate line GL1.

The first gate on voltage Von1 output from the first stage ST1_L in the first period is also input to the second stage ST2_L. In detail, as illustrated in FIG. 9, the first gate on voltage Von1 may include a gate terminal of the first switching device Tr1 provided in the second stage ST2_L, and a ninth switching device Tr9. Is input to the gate terminal of. Here, the first gate on voltage Von1 supplied to the second stage ST2_L plays the same role as the start pulse Vst supplied to the first stage ST1_L. In response to Von1, the second stage ST2_L is enabled.

That is, the first node Q of the second stage ST2_L is charged to the first DC voltage source Vdc1 by the first gate on voltage Von1, and the second node QB is charged to the second DC voltage source. Discharged to (Vdc2).

In summary, the first gate-on voltage Von1 output from the first stage ST1_L during the first period drives the first gate line GL1 and at the same time the first node of the second stage ST2_L. The second stage ST2_L is enabled by charging Q and discharging the second node QB.

Next, the operation during the second period will be described.

During the second period, as shown in FIG. 6, only the second clock pulse CLK2 remains high and the remaining clock pulses remain low.

During this second period, the enabled second stage ST2_L receives the second clock pulse CLK2 and outputs it as the second gate on voltage Von2. The second gate on voltage Von2 is supplied to the second gate line GL2, the first stage ST1_L, and the third stage ST3_L.

That is, the operation of the second stage ST2_L during the second period is the same as the operation of the first stage ST1_L during the first period. However, the second gate on voltage Von2 output from the second stage ST2_L during the second period is supplied to the first stage ST1_L to disable the first stage ST1_L. If this is explained in more detail as follows.

In the second period, the second gate-on voltage Von2 output from the second stage ST2_L is supplied to the third switching device Tr3 of the first stage ST1_L. Specifically, the second gate on voltage Von2 is supplied to the gate terminal of the third switching element Tr3. Then, the third switching device Tr3 is turned on, and the second DC voltage source Vdc2 is turned on through the turned-on third switching device Tr3 to the first node Q of the first stage ST1_L. Is supplied. Accordingly, the first node Q is discharged and the pull-up switching device Trpu, the fifth switching device Tr5, and the eighth switching device Tr8 having a gate terminal connected to the discharged first node Q. ) Are all turned off. In addition, since the start pulse Vst is low in this second period, the fourth switching element Tr4 of the first stage ST1_L to which the start pulse Vst of this low state is supplied is also turned off.

In addition, since the first AC voltage source Vac1 supplied to the first stage ST1_L during the first frame has a high voltage source Vh, the first stage ST1_L supplied with the first AC voltage source Vac1. The sixth switching device Tr6 of) maintains a turn-on state.

As a result, the fourth and fifth switching devices Tr4 and Tr5 of the first stage ST1_L are turned off and the sixth switching device Tr6 is turned on during the second period. The common node N of the first stage ST1_L is charged with the first AC voltage source Vac1 supplied through the sixth switching element Tr6. Accordingly, the seventh switching device Tr7 having the gate terminal connected to the common node N is turned on, and the first AC voltage source Vac1 is turned on through the turned-on seventh switching device Tr7. It is supplied to the second node QB. On the other hand, as described above, since the eighth switching device Tr8 is turned off, only the first AC voltage source Vac1 is supplied to the second node QB.

Accordingly, the pull-down switching device Trpd having the gate terminal connected to the charged second node QB is turned on.

As such, the pull-up switching device Trpu of the first stage ST1_L is turned off and the pull-down switching device Trpd is turned on during the second period, so that the first stage ST1_L is turned on. The second DC voltage source Vdc2 is output through the pull-down switching device Trpd. The second DC voltage source Vdc2 is supplied to the first gate line GL1 and functions as a gate off voltage Voff for deactivating the first gate line GL1.

In summary, the first node Q of the first stage ST1_L is discharged and the second node QB is charged during the second period, so that the pull-up switching device Trpu is turned off and the pull-down switching is performed. Device Trpd is turned on. In other words, the first stage ST1_L is disabled by performing a first operation during the second period.

In the same manner, the remaining stages ST2_L to STm + 1_L are enabled according to the gate-on voltage from the first front stage from themselves, and are supplied with the corresponding clock pulses in the enabled state and output as the gate-on voltage. And is disabled by performing the first operation according to the gate on voltage from the first next stage from itself.

Next, the operation of the second shift register SR2 will be described.

In the above-described start period and the first period, the first stage ST1_R of the second shift register SR2 operates the same as the first stage ST1_R of the first shift register SR1. However, the second AC voltage source Vac2 is supplied to the first stage ST1_R provided in the second shift register SR2, and the second AC voltage source Vac2 is supplied to the low voltage source Vl during the first frame. Since it is maintained, the sixth switching device Tr6 of the first stage ST1_R is always turned off.

Meanwhile, in the second period, the first stage ST1_R of the second shift register SR2 operates differently from the first stage ST1_R of the first shift register SR1. If this is explained in more detail as follows.

The second period is a period in which the first stages ST1_L and ST1_R of the first and second shift registers SR1 and SR2 are disabled, and the first period of the first shift register SR1 in the second period. The stage ST1_L is disabled by performing a first operation while the first stage ST1_R of the second shift register SR2 is disabled by performing a second operation.

That is, in the second period, the first stage ST1_R of the second shift register SR2 is disabled according to the second gate on voltage Von2 from the second stage ST2_R. In detail, the second gate on voltage Von2 is supplied to the gate terminal of the third switching device Tr3 provided in the first stage ST1_R. Then, the third switching device Tr3 is turned on, and the second DC voltage source Vdc2 is turned on through the turned-on third switching device Tr3 to the first node Q of the first stage ST1_L. Is supplied. Accordingly, the first node Q is discharged and the pull-up switching device Trpu, the fifth switching device Tr5, and the eighth switching device Tr8 having a gate terminal connected to the discharged first node Q. ) Are all turned off. In addition, since the start pulse Vst is low in this second period, the fourth switching element Tr4 of the first stage ST1_R, which is supplied with the start pulse Vst in this low state, is also turned off.

In addition, since the second AC voltage source Vac2 supplied to the first stage ST1_R during the first frame has a low voltage source Vl, the first stage ST1_L supplied with the second AC voltage source Vac2. The sixth switching element Tr6 of) maintains a turn-off state.

As a result, since the fourth, fifth, and sixth switching elements Tr4, Tr5, and Tr6 of the first stage ST1_R are turned off during the second period, the common node of the first stage ST1_R is turned off. (N) maintains the discharge state in the first period. Therefore, the seventh switching element Tr7 having the gate terminal connected to the discharged common node N is turned off. As the seventh switching element Tr7 maintains the turn-off state, no voltage is supplied to the second node QB. Accordingly, the second node QB of the first stage ST1_R maintains a discharge state in a first period, and a pull-down switching device Trpd having a gate terminal connected to the second node QB in this discharge state. Remains turned off.

As such, the pull-up switching device Trpu and the pull-down switching device Trpd of the first stage ST1_L are turned on during the second period, so that the first stage ST1_R outputs any output during the second period. Also does not occur.

In summary, both the first node Q and the second node QB of the first stage ST1_L are discharged during the second period, so that both the pull-up switching device Trpu and the pull-down switching device Trpd are discharged. Turn off. In other words, the first stage ST1_L is disabled by performing the second operation during the second period.

In the same manner, the remaining stages ST2_R to STm + 1_R are enabled according to the gate-on voltage from the first front stage from themselves, and are supplied with the corresponding clock pulses in the enabled state and output as the gate-on voltage. And is disabled by performing the second operation in accordance with the gate on voltage from the first next stage from itself.

In conclusion, each stage ST1_L to STm + 1_L provided in the first shift register SR1 outputs a gate-off voltage Voff, and each stage provided in the second shift register SR2 is included in the first frame. ST1_R to STm + 1_R do not output the gate off voltage Voff. Therefore, in the first frame, the pull-down switching device Trpd of each stage ST1_R to STm + 1_R of the second shift register SR2 has a rest period.

In the second frame, the first shift register SR1 and the second as the first AC voltage source Vac1 is changed to the low voltage source Vl and the second AC voltage source Vac2 is changed to the high voltage source Vh. The shift register SR2 operates opposite to each other. That is, in this second frame, each stage ST1_R to STm + 1_R provided in the second shift register SR2 outputs a gate off voltage Voff, and each stage provided in the first shift register SR1. (ST1_L to STm + 1_L) produces no output. Therefore, in the second frame, the pull-down switching device Trpd of each stage ST1_L to STm + 1_L of the first shift register SR1 has a rest period.

In the above-described embodiment, an example in which the first and second AC voltage sources Vac1 and Vac2 are changed in units of one frame has been described. The first and second AC voltage sources Vac1 and Vac2 are p (p is 2). The above natural number) may be changed in units of frames.

The stages ST1_L to STm + 1_L and ST1_R to STm + 1_R provided in the first and second shift registers SR1 and SR2 may have the following circuit configurations.

FIG. 10 is a diagram illustrating another circuit configuration of the second stage provided in the first shift register of FIG. 2, and FIG. 11 is another circuit configuration of the second stage provided in the second shift register SR2 of FIG. 2. It is a diagram showing.

As shown in FIG. 10, the second stage ST2_L provided in the first shift register SR1 includes the first to tenth switching elements Tr1 to Tr10, and the first and second capacitors C1 and C2. Has

Here, since the first to ninth switching elements Tr1 to Tr9 are the same as those in FIG. 7, description thereof will be omitted.

The tenth switching element Tr10 is supplied with an alternating voltage source 180 degrees out of phase with respect to an alternating voltage source supplied to the sixth and seventh switching elements Tr6 and Tr7 of the stage to which the tenth switching element Tr10 belongs. Then, in response to the AC voltage source, it is turned on or off and discharges the second node QB of the stage to which it belongs to the second DC voltage source Vdc2.

For example, the tenth switching element Tr10 of the second stage ST2_L of the first shift register SR1 illustrated in FIG. 10 is turned on or turned in response to the second AC voltage source Vac2. When turned off, the second node QB of the second stage ST2_L is discharged to the second DC voltage source Vdc2 at turn-on.

The tenth switching element Tr10 included in the second stage ST2_R of the second shift register SR2 shown in FIG. 11 is turned on or turned off in response to the first AC voltage source Vac1. In operation, the second node QB of the second stage ST2_L is discharged to the second DC voltage source Vdc2.

As described above, an AC voltage source supplied to the sixth and seventh switching elements Tr6 and Tr7 of each stage ST1_L to STm + 1_L and ST1_R to STm + 1_R and an AC voltage source supplied to the tenth switching element Tr10. Since the phases are inverted from each other, the tenth switching element Tr10 is always turned off at a time when the stages ST1_L to STm + 1_L and ST1_R to STm + 1_R are disabled by performing the first operation. Therefore, the tenth switching element Tr10 does not affect the second node QB in the first operation. However, since the tenth switching element Tr10 is always turned on at the time when each stage ST1_L to STm + 1_L and ST1_R to STm + 1_R are disabled by performing the second operation, the tenth switching element Tr10 is always turned on. The switching element Tr10 maintains the second node QB in the discharge state more reliably.

The stages ST1_L to STm + 1_L and ST1_R to STm + 1_R provided in the first and second shift registers SR1 and SR2 may have the following circuit configurations.

FIG. 12 is a diagram illustrating another circuit configuration of the second stage ST2_L included in the first shift register of FIG. 2.

The first to m th stages ST1_L to STm_L and the dummy stage STm + 1_L provided in the first shift register SR1 are the first to eighth switching elements Tr1 to Tr8, and the first and second stages. It has capacitors C1 and C2.

The first switching device Tr1 provided in each of the stages ST1_L to STm + 1_L receives the first node Q of the stage to which it belongs in response to the gate-on voltage from the first front end stage. Charge to Vdc1).

For example, the first switching device Tr1 provided in the second stage ST2_L of FIG. 12 has its first node Q in response to the first gate on voltage Von1 from the first stage ST1_L. ) Is charged to the first DC voltage source Vdc1. To this end, the gate terminal of the first switching device Tr1 provided in the second stage ST2_L is connected to the first stage ST1_L, and the drain terminal is a power source for transmitting the first DC voltage source Vdc1. It is connected to the line, and the source terminal is connected to the first node (Q).

The second switching device Tr2 provided in each of the stages ST1_L to STm + 1_L has a response to the first AC voltage source Vac1 charged to the second node QB of the stage to which the stage belongs. The first node Q is discharged to the second DC voltage source Vdc2.

For example, the second switching device Tr2 included in the second stage ST2_L of FIG. 12 responds to the first AC voltage source Vac1 charged in the second node QB of the second stage ST2_L. As a result, the first node Q of the second stage ST2_L is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the second switching element Tr2 provided in the second stage ST2_L is connected to the second node QB of the second stage ST2_L, and the drain terminal of the second DC voltage source. It is connected to the power line for transmitting (Vdc2), the source terminal is connected to the first node (Q) of the second stage (ST2_L).

The third switching device Tr3 included in each of the stages ST1_L to STm + 1_L transmits the first node Q of the stage to which it belongs to the second DC voltage source in response to the gate-on voltage from the first next stage. Discharge at (Vdc2).

For example, the third switching device Tr3 included in the second stage ST2_L of FIG. 12 may respond to the third gate on voltage Von3 from the third stage ST3_L. The first node (Q) of D is discharged to the second DC voltage source (Vdc2). To this end, the gate terminal of the third switching device Tr3 provided in the second stage ST2_L is connected to the third stage ST3_L, and the drain terminal thereof is the first node Q of the second stage ST2_L. Is connected to the power supply line for transmitting the second DC voltage source Vdc2.

The fourth switching device Tr4 provided in each of the stages ST1_L to STm + 1_L is turned on or turned off in response to the first AC voltage source Vac1, and when turned on, the second switching element Tr4 is turned on. The node QB is charged with the first AC voltage source Vac1.

For example, the fourth switching device Tr4 included in the second stage ST2_L of FIG. 12 is turned on or turned off in response to the first AC voltage source Vac1, and when turned on, the second switching element Tr4 is turned on. The second node QB of the stage ST2_L is charged with the first AC voltage source Vac1. To this end, the gate terminal and the drain terminal of the fourth switching device Tr4 provided in the second stage ST2_L are connected to a power line for transmitting the first AC voltage source Vac1, and the source terminal is connected to the first terminal. It is connected to the 2nd node QB of 2 stage ST2_L.

The fifth switching device Tr5 provided in each of the stages ST1_L to STm + 1_L exchanges the second node QB of the stage to which the stage belongs to the first AC in response to the gate-on voltage from the first next stage. Charge or discharge to the voltage source (Vac1).

For example, the fifth switching device Tr5 included in the second stage ST2_L of FIG. 12 may respond to the second gate ST2_L in response to the third gate on voltage Von3 from the third stage ST3_L. Charge or discharge the second node QB of FIG. 1 to the first AC voltage source Vac1. To this end, the gate terminal of the fifth switching device Tr5 provided in the second stage ST2_L is connected to the third stage ST3_L, and the drain terminal is a power line for transmitting the first AC voltage source Vac1. The source terminal is connected to the second node QB of the second stage ST2_L.

The sixth switching device Tr6 included in each of the stages ST1_L to STm + 1_L may be connected to the first DC voltage source Vdc1 charged in the first node Q of the stage to which the stage belongs. The second node QB is discharged to the second DC voltage source Vdc2.

For example, the sixth switching device Tr6 included in the second stage ST2_L of FIG. 12 is connected to the first DC voltage source Vdc1 charged in the first node Q of the second stage ST2_L. In response, the second node QB of the second stage ST2_L is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the sixth switching element Tr6 provided in the second stage ST2_L is connected to the first node Q of the second stage ST2_L, and the drain terminal of the second stage ST2_L It is connected to the second node QB of ST2_L, and the source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The seventh switching element Tr7 included in each of the stages ST1_L to STm + 1_L receives the second node QB of the stage to which it belongs in response to the gate-on voltage from the first front stage. Discharge to Vdc2).

For example, the seventh switching device Tr7 included in the second stage ST2_L of FIG. 12 may respond to the first gate on voltage Von1 from the first stage ST1_L. Discharges the second node QB to the second DC voltage source Vdc2. To this end, the gate terminal of the seventh switching element Tr7 provided in the second stage ST2_L is connected to the first stage ST1_L, and the drain terminal thereof is the second node QB of the second stage ST2_L. Is connected to the power supply line for transmitting the second DC voltage source Vdc2.

The eighth switching device Tr8 included in each stage ST1_L to STm + 1_L is turned on or turned off in response to the second AC voltage source Vac2, and when turned on, the second node of the stage to which it belongs QB is discharged to the second DC voltage source Vdc2.

For example, the eighth switching device Tr8 provided in the second stage ST2_L of FIG. 12 is turned on or turned off in response to a second AC voltage source Vac2, and when turned on, the second stage The second node QB of ST2_L is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the eighth switching device Tr8 provided in the second stage ST2_L is connected to a power line for transmitting the second AC voltage source Vac2, and the drain terminal of the second stage ST2_L Is connected to a second node QB, and a source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The pull-up switching device Trpu provided in each stage ST1_L to STm + 1_L gates the clock pulse in response to the first DC voltage source Vdc1 charged in the first node Q of the stage to which it belongs. It outputs as a voltage and supplies this gate-on voltage to the said gate line, the front stage, and the next stage. At this time, the gate on voltage output to the front stage serves as a signal for disabling the front stage, and the gate on voltage output to the next stage is a start pulse Vst for enabling the next stage. Function as.

For example, the pull-up switching device Trpu provided in the second stage ST2_L of FIG. 12 receives the second clock pulse CLK2 in response to the first DC voltage source Vdc1 charged in the first node Q. The second gate on voltage Von2 is output as the second gate on voltage Von2, and the second gate on voltage Von2 is supplied to the second gate line GL2, the first stage ST1_L, and the third stage ST3_L. To this end, the gate terminal of the pull-up switching device Trpu provided in the second stage ST2_L is connected to the first node Q of the second stage ST2_L, and the drain terminal of the second clock pulse It is connected to a clock transmission line for transmitting CLK2, and a source terminal is connected to the second gate line GL2.

The pull-down switching device Trpd provided in each of the stages ST1_L to STm + 1_L has a second DC voltage source Vdc2 in response to the first AC voltage source Vac1 charged in the second node QB of the stage to which it belongs. ) Is output as the gate off voltage Voff, and the gate off voltage Voff is supplied to the gate line, the front stage, and the next stage.

For example, the pull-down switching device Trpd of the second stage ST2_L of FIG. 12 may respond to the first AC voltage source Vac1 charged in the second node QB of the second stage ST2_L. The second DC voltage source Vdc2 is output as the gate off voltage Voff, and the gate off voltage Voff is supplied to the second gate line GL2, the first stage ST1_L, and the third stage ST3_L. do. For this purpose, the gate terminal of the pull-down switching device Trpd provided in the second stage ST2_L is connected to the second node QB of the second stage ST2_L, and the drain terminal of the second gate line GL2), and a source terminal is connected to a power line for transmitting the second DC voltage source Vdc2.

The first capacitor C1 is connected between the gate terminal and the source terminal of the pull-up switching device Trpu to facilitate a bootstrapping operation of the pull-up switching device Trpu.

The second capacitor C2 is connected between the gate terminal and the drain terminal of the pull-down switching device Trpd to facilitate the bootstrapping operation of the pull-down switching device Trpd.

Each of the switching elements provided in the second to mth stages ST2_L to STm_L and the dummy stage STm + 1_L also operates in the manner described above.

However, since the stage does not exist in the first front end of the first stage ST1_L, the first and ninth switching elements Tr1 and Tr9 included in the first stage ST1_L may have a start pulse (T1) from the timing controller. It operates by receiving Vst). That is, the first stage ST1_L is enabled by the start pulse Vst.

In addition, since the stage does not exist at the first stage after the dummy stage STm + 1_L, the third switching device Tr3 included in the dummy stage STm + 1_L has a start pulse from the timing controller. It operates by receiving Vst). That is, the dummy stage STm + 1_L is disabled by the start pulse Vst.

Next, a circuit configuration of the first to m th stages ST1_R to STm_R and the dummy stage STm + 1_L included in the second shift register SR2 will be described.

FIG. 13 is a diagram illustrating another circuit configuration of the second stage included in the second shift register of FIG. 2.

The circuit configuration of each stage provided in the second shift register SR2 is the same as the circuit configuration of each stage provided in the first shift register SR1 described above. However, the second AC voltage source Vac2 is supplied to the fourth and fifth switching elements Tr4 and Tr5 of each stage ST1_R to STm + 1_R.

For example, as illustrated in FIG. 13, a second alternating current is provided to the gate terminal and the drain terminal of the fourth switching device Tr4 and the drain terminal of the fifth switching device Tr5 provided in the second stage ST2_R. The voltage source Vac2 is supplied.

The first AC voltage source Vac1 is supplied to the gate terminal of the eighth switching device Tr8 of each stage ST1_R to STm + 1_R.

For example, as illustrated in FIG. 13, the first AC voltage source Vac1 is supplied to the gate terminal of the eighth switching device Tr8 provided in the second stage ST2_L.

12 and 13 will be described in detail with reference to the operation of the gate driving circuit according to the present invention.

First, the operation of the initial period in the first frame will be described.

FIG. 14 is a diagram illustrating still another circuit configuration of the first to third stages ST3_L of FIG. 2.

During the initial period, as shown in FIG. 3, only the start pulse Vst output from the timing controller remains high, and the remaining clock pulses Vst remain low.

The start pulse Vst output from the timing controller is input to the first stage ST1_L. In detail, the start pulse Vst is supplied to the gate terminal of the first switching element Tr1 and the gate terminal of the seventh switching element Tr7 provided in the first stage ST1_L.

Then, the first and seventh switching elements Tr1 and Tr7 are turned on, and at this time, the first DC voltage source Vdc1 is turned on by the first node Q through the turned-on first switching element Tr1. Is applied to. Accordingly, the first node Q is charged, and the pull-up switching device Trpu and the sixth switching device Tr6 having a gate terminal connected to the charged first node Q are turned on.

Here, the second DC voltage source Vdc2 is supplied to the second node QB through the turned-on sixth and seventh switching elements Tr6 and Tr7. Accordingly, the second node QB is discharged by the second DC voltage source Vdc2, and the second switching element Tr2 and the pull-down switching element Trpd having the gate terminal connected to the second node QB. Is turned off. The turned-on second switching device Tr2 further accelerates the discharge of the second node QB by supplying a second DC voltage source Vdc2 to the second node QB.

As such, during the initial period, the first node Q of the first stage ST1_L is charged with the first DC voltage source Vdc1, and the second node QB is charged with the second DC voltage source Vdc2. By discharging, the first stage ST1_L is enabled.

In addition, the eighth switching device Tr8 of the first stage ST1_L is always turned off by the second AC voltage source Vac2. The second AC voltage source Vac2 is in the low voltage source Vl state during the first frame.

Next, the operation during the first period will be described.

During the first period, as shown in FIG. 3, only the first clock pulse CLK1 remains high and the remaining clock pulses remain low. Accordingly, the first and seventh switching elements Tr1 and Tr7 of the first stage ST1_L are turned off in response to the low state start pulse Vst, thereby turning off the first stage ST1_L. The first node Q is kept in a floating state.

Meanwhile, as the first node Q of the first stage ST1_L is continuously maintained as the first DC voltage source Vdc1 applied during the initial period, the pull-up switching device Trpu of the first stage ST1_L is maintained. Remains turned on. In this case, as the first clock pulse CLK1 is applied to the drain terminal of the turned-on pull-up switching device Trpu, the first DC voltage source charged in the first node Q of the first stage ST1_L. Vdc1 is amplified by bootstrapping.

Therefore, the first clock pulse CLK1 applied to the drain terminal of the pull-up switching device Trpu of the first stage ST1_L is stably output through the source terminal of the pull-up switching device Trpu. In this case, the output first clock pulse CLK1 is applied to the first gate line GL1 and functions as a first gate on voltage Von1 for driving the first gate line GL1.

The first gate on voltage Von1 output from the first stage ST1_L in the first period is also input to the second stage ST2_L. In detail, as illustrated in FIG. 14, the first gate on voltage Von1 may include a gate terminal of the first switching device Tr1 provided in the second stage ST2_L, and a seventh switching device Tr7. Is input to the gate terminal of. Here, the first gate on voltage Von1 supplied to the second stage ST2_L plays the same role as the start pulse Vst supplied to the first stage ST1_L. In response to Von1, the second stage ST2_L is enabled.

That is, the first node Q of the second stage ST2_L is charged to the first DC voltage source Vdc1 by the first gate on voltage Von1, and the second node QB is charged to the second DC voltage source. Discharged to (Vdc2).

In summary, the first gate-on voltage Von1 output from the first stage ST1_L during the first period drives the first gate line GL1 and at the same time the first node of the second stage ST2_L. The second stage ST2_L is enabled by charging Q and discharging the second node QB.

Next, the operation during the second period will be described.

During the second period, as shown in FIG. 3, only the second clock pulse CLK2 remains high and the remaining clock pulses remain low.

During this second period, the enabled second stage ST2_L receives the second clock pulse CLK2 and outputs it as the second gate on voltage Von2. The second gate on voltage Von2 is supplied to the second gate line GL2, the first stage ST1_L, and the third stage ST3_L.

That is, the operation of the second stage ST2_L during the second period is the same as the operation of the first stage ST1_L during the first period. However, the second gate on voltage Von2 output from the second stage ST2_L during the second period is supplied to the first stage ST1_L to disable the first stage ST1_L. If this is explained in more detail as follows.

The second gate on voltage Von2 output from the second stage ST2_L in the second period is supplied to the third and fifth switching devices Tr3 and Tr5 of the first stage ST1_L. In detail, the second gate on voltage Von2 is supplied to the gate terminal of the third switching element Tr3 and the gate terminal of the fifth switching element Tr5. Then, the third switching device Tr3 is turned on, and the second DC voltage source Vdc2 is turned on through the turned-on third switching device Tr3 to the first node Q of the first stage ST1_L. Is supplied. Accordingly, the first node Q is discharged, and both the pull-up switching device Trpu and the sixth switching device Tr6 having a gate terminal connected to the discharged first node Q are turned off.

Meanwhile, as the first AC voltage source Vac1 is maintained as the high voltage source Vh during the first frame, the fourth switching device Tr4 supplied with the first AC voltage source Vac1 is turned on. Then, the first AC voltage source Vac1 is supplied to the second node QB through the turned-on fourth switching device Tr4. In addition, the first AC voltage source Vac1 is supplied to the second node QB through the turned-on fifth switching device Tr5. Accordingly, the second node QB is charged with the first AC voltage source Vac1 and the pull-down switching device Trpd and the second switching device Tr2 having the gate terminal connected to the charged second node QB. ) Are all turned on.

Here, the second DC voltage source Vdc2 is supplied to the first node Q through the turned-on second switching device Tr2. Therefore, the discharge of the first node Q is further accelerated.

As such, the pull-up switching device Trpu of the first stage ST1_L is turned off and the pull-down switching device Trpd is turned on during the second period, so that the first stage ST1_L is turned on. The second DC voltage source Vdc2 is output through the pull-down switching device Trpd. The second DC voltage source Vdc2 is supplied to the first gate line GL1 and functions as a gate off voltage Voff for deactivating the first gate line GL1.

In summary, the first node Q of the first stage ST1_L is discharged and the second node QB is charged during the second period, so that the pull-up switching device Trpu is turned on and the pull-down switching is performed. Element Trpd is turned off. In other words, the first stage ST1_L is disabled by performing a first operation during the second period.

In the same manner, the remaining stages ST2_L to STm + 1_L are enabled according to the gate-on voltage from the first front stage from themselves, and are supplied with the corresponding clock pulses in the enabled state and output as the gate-on voltage. And is disabled by performing the first operation according to the gate on voltage from the first next stage from itself.

Next, the operation of the second shift register SR2 will be described.

In the above-described start period and the first period, the first stage ST1_R of the second shift register SR2 operates in the same manner as the first stage ST1_L of the first shift register SR1.

However, the second AC voltage source Vac2 is supplied to the fourth and fifth switching devices Tr4 and Tr5 provided in the first stage ST1_R of the second shift register SR2, and the second AC voltage source Vac2 is supplied. ) Is maintained as the low voltage source Vl during the first frame, so that the fourth switching device Tr4 of the first stage ST1_R is always turned off. In addition, since the first AC voltage source Vac1 is maintained as the high voltage source Vh during the first frame, the eighth switching device Tr8 of the first stage ST1_R is always turned on.

Meanwhile, in the second period, the first stage ST1_R of the second shift register SR2 operates differently from the first stage ST1_L of the first shift register SR1. If this is explained in more detail as follows.

The second period is a period during which the first stage ST1_L of the first and second shift registers SR1 and SR2 is disabled. In this second period, the first stage of the first shift register SR1 ( ST1_1 is disabled by performing a first operation, while the first stage ST1_R of the second shift register SR2 is disabled by performing a second operation.

That is, in the second period, the first stage ST1_R of the second shift register SR2 is disabled according to the second gate on voltage Von2 from the second stage ST2_R. Specifically, the second gate on voltage Von2 output from the second stage ST2_R in the second period is supplied to the third and fifth switching devices Tr3 and Tr5 of the first stage ST1_R. . In detail, the second gate on voltage Von2 is supplied to the gate terminal of the third switching element Tr3 and the gate terminal of the fifth switching element Tr5. Then, the third switching device Tr3 is turned on, and the second DC voltage source Vdc2 is turned on by the first node Q1 of the first stage ST1_R through the turned-on third switching device Tr3. Is supplied. Accordingly, the first node Q is discharged, and both the pull-up switching device Trpu and the sixth switching device Tr6 having a gate terminal connected to the discharged first node Q are turned off.

Meanwhile, as the second AC voltage source Vac2 is maintained as the low voltage source Vl during the first frame, the fourth switching device Tr9 of the first stage ST1_R receives the second AC voltage source Vac1. Is turned off. The second AC voltage source Vac2 is supplied to the second node QB through the turned-on fifth switching device Tr5. Accordingly, the second node QB is discharged to the second AC voltage source Vac2, and the pull-down switching device Trpd and the second switching device Tr2 having the gate terminal connected to the discharged second node QB. ) Are all turned off.

In addition, the eighth switching device Tr8 of the first stage ST1_R supplied with the first AC voltage source Vac1 is turned on. The second DC voltage source Vdc2 is supplied to the second node QB through the turned-on eighth switching device Tr8. Accordingly, the discharge of the second node QB is accelerated.

As such, the pull-up switching device Trpu and the pull-down switching device Trpd of the first stage ST1_R are turned off during the second period, so that the first stage ST1_L outputs any output during the second period. Also does not occur.

In summary, both the first node Q and the second node QB of the first stage ST1_R are discharged during the second period, so that both the pull-up switching device Trpu and the pull-down switching device Trpd are discharged. Turn off. In other words, during the second period, the first stage ST1_R is disabled by performing a second operation.

In the same manner, the remaining stages ST2_R to STm + 1_R are enabled according to the gate-on voltage from the first front stage from themselves, and are supplied with the corresponding clock pulses in the enabled state and output as the gate-on voltage. And is disabled by performing the second operation in accordance with the gate on voltage from the first next stage from itself.

In conclusion, each stage ST1_R to STm + 1_R provided in the first shift register SR1 outputs a gate-off voltage Voff in the first frame, and each stage provided in the second shift register SR2. (ST1_L to STm + 1_L) produces no output. Therefore, in the first frame, the pull-down switching device Trpd of each stage ST1_R to STm + 1_R of the second shift register SR2 has a rest period.

In the second frame, the first shift register SR1 and the second as the first AC voltage source Vac1 is changed to the low voltage source Vl and the second AC voltage source Vac2 is changed to the high voltage source Vh. The shift register SR2 operates opposite to each other. That is, in this second frame, each stage ST1_R to STm + 1_R provided in the second shift register SR2 outputs a gate off voltage Voff, and each stage provided in the first shift register SR1. (ST1_L to STm + 1_L) produces no output. Therefore, in the second frame, the pull-down switching device Trpd of each stage ST1_L to STm + 1_L of the first shift register SR1 has a rest period.

In the above-described embodiment, an example in which the first and second AC voltage sources Vac1 and Vac2 are changed in units of one frame has been described. The first and second AC voltage sources Vac1 and Vac2 are k (k is 2). The above natural number) may be changed in units of frames.

Meanwhile, the first switching device Tr1 illustrated in FIGS. 7, 8, 10, 11, and 12 may be changed as follows.

FIG. 15 is a diagram illustrating another circuit configuration of the first switching device Tr1 illustrated in FIGS. 7, 8, 10, 11, and 12.

First, the first switching device Tr1 illustrated in FIGS. 7, 8, 10, 11, and 12 may have a diode configuration, as shown in FIG. 15A. The first switching device Tr1 configured as described above may turn the first node Q into the start pulse Vst or the gate on in response to the start pulse Vst from the timing controller or the gate on voltage from the first front stage. Charge to voltage.

The first terminal 511 shown in FIG. 15A has a gate terminal of the ninth switching element Tr9 shown in FIG. 7 (or a gate terminal of the seventh switching element Tr7 shown in FIG. 10). Is connected to the first node (Q). In such a configuration, the first DC voltage source Vdc1 is not necessary in the present invention.

7, the first switching elements Tr1 shown in Figs. 7, 8, 10, 11, and 12 are the first and second A and B connected in series, as shown in Fig. 15B. It may be composed of the switching elements (TrA, TrB).

The A switching element TrA has the diode configuration described above, and the drain terminal of the B switching element TrB is connected to the source terminal of the A switching element TrA.

The gate terminal and the drain terminal of the A switching element TrA are supplied with the start pulse Vst from the timing controller or the gate on voltage from the first front stage. The clock terminal synchronized with the start pulse Vst or the gate on voltage supplied to the A switching device TrA is supplied to the gate terminal of the B switching device TrB.

The first switching device Tr1 configured as described above charges the first node Q to the start pulse Vst or the gate on voltage in response to the start pulse Vst and the clock pulse, or the gate on voltage and the clock pulse. . The first terminal 521 shown in FIG. 15B has a gate terminal of the ninth switching element Tr9 shown in FIG. 7 (or a gate terminal of the seventh switching element Tr7 shown in FIG. 10). The second terminal 522 is connected to the first node Q. In such a configuration, the first DC voltage source Vdc1 is not necessary in the present invention. Instead of the first terminal 521, a third terminal 523 may be connected to the gate terminal of the ninth switching element Tr7 (or the gate terminal of the seventh switching element Tr7).

7, the first switching elements Tr1 shown in FIGS. 7, 8, 10, 11, and 12 are the first and second connected Bs in parallel, as shown in Fig. 15C. It may be composed of the switching elements (TrA, TrB).

Here, the A switching device TrA outputs the first DC voltage source Vdc1 in response to the start pulse Vst from the timing controller or the gate-on voltage from the first front stage. The B switching device TrB outputs the first DC voltage source Vdc1 in response to a clock pulse. The drain terminal of the A switching element TrA is connected to the drain terminal of the B switching element TrB, and the source terminal of the A switching element TrA is the source terminal of the B switching element TrB. And are connected to each other. The clock pulse is synchronized with the start pulse Vst or the gate on voltage.

The first terminal 531 shown in FIG. 15C has a gate terminal of the ninth switching element Tr9 shown in FIG. 7 (or a gate terminal of the seventh switching element Tr7 shown in FIG. 10). The second terminal 532 is connected to the first node Q. In such a configuration, the first DC voltage source Vdc1 is not necessary in the present invention. Instead of the first terminal 531, a third terminal 533 may be connected to the gate terminal of the ninth switching element Tr9 (or the gate terminal of the seventh switching element Tr7).

Hereinafter, the gate driving circuit according to the second embodiment of the present invention will be described in detail.

16 is a diagram illustrating a gate driving circuit according to a second embodiment of the present invention.

The gate driving circuit according to the second embodiment of the present invention is the same as the gate driving circuit according to the first embodiment of the present invention. As illustrated in FIG. 16, the odd stages ST1_L, ST3_L, ..., STm + 1_L of the stages ST1_L to STm + 1_L included in the first shift register SR1 are the first. The AC voltage source Vac1 is supplied, and the even-numbered stages ST2_L, ST4_L, ..., STm_L are supplied with the second AC voltage source Vac2.

The odd stages ST1_R, ST3_R, ..., STm + 1_R of the stages provided in the second shift register SR2 are supplied with the second AC voltage source Vac2 and the even-numbered stages ST2_R. , ST4_R, ..., STm_R are supplied with the first AC voltage source Vac1.

As a result, the odd stages ST1_L, ST3_L, ..., STm + 1_L of the first shift register SR1 and the even stages ST2_R, ST4_R, ..., of the second shift register SR2. STm_R operates in the same manner as each stage ST1_L to STm + 1_L of the first shift register SR1 described in the first embodiment.

The even-numbered stages ST2_L, ST4_L, ..., STm_L of the first shift register SR1 and the odd-numbered stages ST1_R, ST3_R, ..., STm + 1_R of the second shift register SR2. ) Operates in the same manner for each stage ST1_R to STm + 1_R of the second shift register SR2 described in the first embodiment.

Therefore, the odd-numbered stages ST1_L, ST3_L, ..., STm + 1_L of the first shift register SR1 and the even-numbered stages ST2_R, ST4_R, of the second shift register SR2 are included in the first frame. STm_R outputs the gate-off voltage Voff, and in the second frame, the even-numbered stages ST2_L, ST4_L, ..., STm_L and the second shift register of the first shift register SR1. The odd stages ST1_R, ST3_R, ..., STm + 1_R of SR2 output the gate-off voltage Voff.

As a result, in the first frame, the pull-down switching element Trpd provided in the even-numbered stages ST2_L, ST4_L, ..., STm_L of the first shift register SR1, and the odd-numbered number of the second shift register SR2. The pull-down switching device Trpd provided in the stages ST1_R, ST3_R, ..., STm + 1_R has a rest period. On the contrary, in the second frame, the pull-down switching element Trpd and the second shift register SR2 provided in the odd stages ST1_L, ST3_L, ..., STm + 1_L of the first shift register SR1 are provided. The pull-down switching device Trpd provided in the even-numbered stages ST2_R, ST4_R, ..., STm_R has a rest period.

Each stage provided in the gate driving circuit according to the second embodiment of the present invention may have the circuit configuration described in the first embodiment.

Hereinafter, a gate driving circuit according to a third embodiment of the present invention will be described in detail.

17 is a diagram illustrating a gate driving circuit according to a third embodiment of the present invention.

The gate driving circuit according to the third embodiment of the present invention is the same as the gate driving circuit according to the second embodiment of the present invention.

However, as shown in FIG. 17, the first stage outputting the gate-on voltage first among the odd stages ST1_L, ST3_L, ..., STm + 1_L included in the first shift register SR1 ( ST1_L is enabled by the first start pulse Vst1, and the second stage ST2_L, which outputs the gate-on voltage first among the even-numbered stages ST2_L, ST4_L, ..., STm + 2_L, Enabled by two start pulses Vst2.

Similarly, the first stage ST1_R that outputs the gate-on voltage first among the odd stages ST1_R, ST3_R, ..., STm + 1_L included in the second shift register SR2 is the first start. The second stage ST2_R, which is enabled by the pulse Vst1 and outputs the gate-on voltage first among the even-numbered stages ST2_R, ST4_R, ..., STm + 2_R, is the second start pulse Vst2. Enabled by

Here, each of the stages ST1_L to STm + 2_L provided in the first shift register SR1 sequentially outputs gate-on voltages Von1 to Vonm + 2.

Each stage ST1_L to STm + 2_L supplies the gate-on voltages Von1 to Vonm + 2 as a start pulse from itself to the second next stage and as a disable signal to the second front stage. Thus, each stage ST1_L to STm + 2_L is enabled in response to the gate on voltage from the second next stage and is disabled according to the gate on voltage from the second front stage.

For example, the third stage ST3_L is enabled in response to the first gate on voltage Von1 from the first stage ST1_L and is disabled in response to the fifth gate on voltage from the fifth stage. The fourth stage ST4_L is enabled in response to the second gate on voltage Von2 from the second stage ST2_L and is disabled in response to the sixth gate on voltage from the sixth stage.

However, since no stage exists in the second front end of the first stage ST1_L, the first stage ST1_L is enabled by the first start pulse Vst from the timing controller. In addition, since there is no stage in the second front end of the second stage ST2_L, the second stage ST2_L is enabled by the second start pulse Vst2 from the timing controller.

In addition, since the stage does not exist in the second next stage of the first dummy stage STm + 1_L, the first dummy stage STm + 1_L is disconnected by the first start pulse Vst1 from the timing controller. Is enabled.

In addition, since there is no stage in the second next stage of the second dummy stage STm + 2_L, the second dummy stage STm + 2_L is applied to the second start pulse Vst2 from the timing controller. Is disabled.

As such, the odd-numbered stages ST1_L, ST3_L, ..., STm + 1_L and the even-numbered stages ST2_L, ST4_L, ..., STm + 2_L provided in the first shift register SR1 are The start pulses Vst1 and Vst2 are independent of each other and driven independently of each other. That is, the odd stages ST1_L, ST3_L, ..., STm + 1_L in the first shift register SR1 output the outputs of the odd stages ST1_L, ST3_L, ..., STm + 1_L to each other. Send and receive is enabled and disabled. In the first shift register SR1, even-numbered stages ST2_L, ST4_L, ..., STm + 2_L output outputs of even-numbered stages ST2_L, ST4_L, ..., STm + 2_L to each other. Send and receive is enabled and disabled.

Of course, the stages ST1_R to STm + 2_R provided in the second shift register SR2 also have the same configuration as the stages ST1_L to STm + 2_L provided in the first shift register SR1. At this time, the odd stages ST1_L, ST3_L, ..., STm + 1_L of the first shift register SR1 and the even stages ST2_R, ST4_R, which are provided in the second shift register SR2. STm + 2_R is supplied with the same AC voltage source (first AC voltage source Vac1), and the even-numbered stages ST2_L, ST4_L, ..., STm + 2_L of the first shift register SR1. And the odd-numbered stages ST1_R, ST3_R, ..., STm + 1_R provided in the second shift register SR2 are supplied with the same AC voltage source (second AC voltage source Vac2).

As a result, the odd stages ST1_L, ST3_L, ..., STm + 1_L of the first shift register SR1 and the even stages ST2_R, ST4_R, ..., of the second shift register SR2. STm + 2_R operates in the same manner as the stages ST1_L to STm + 1_L of the first shift register SR1 described in the first embodiment. The even-numbered stages ST2_L, ST4_L, ..., STm + 2_L of the first shift register SR1 and the odd-numbered stages ST1_R, ST3_R, ..., STm of the second shift register SR2. + 1_R operates in the same manner as the stages ST1_R to STm + 1_R of the second shift register SR2 described above in the first embodiment.

Therefore, the odd-numbered stages ST1_L, ST3_L, ..., STm + 1_L of the first shift register SR1 and the even-numbered stages ST2_R, ST4_R, of the second shift register SR2 are included in the first frame. STm + 2_R outputs the gate-off voltage Voff, and in the second frame, even-numbered stages ST2_R, ST4_R, ..., STm + 2_R of the first shift register SR1, and The odd stages ST1_R, ST3_R, ..., STm + 1_R of the second shift register SR2 output the gate off voltage Voff.

As a result, the first frame includes the pull-down switching element Trpd and the second shift register SR2 provided in the even-numbered stages ST2_L, ST4_L, ..., STm + 2_L of the first shift register SR1. The pull-down switching device Trpd provided in the odd stages ST1_R, ST3_R, ..., STm + 1_R has a rest period. On the contrary, in the second frame, the pull-down switching element Trpd and the second shift register SR2 provided in the odd stages ST1_L, ST3_L, ..., STm + 1_L of the first shift register SR1 are provided. The pull-down switching device Trpd provided in the even-numbered stages ST2_R, ST4_R, ..., STm + 2_R has a rest period.

Each stage included in the gate driving circuit according to the third exemplary embodiment of the present invention may have the circuit configuration shown in FIGS. 7, 8, 10, 11, 12, and 13.

However, when the circuit configuration of FIGS. 7 and 8 is applied to the stages of the third embodiment of the present invention, the first and ninth switching elements Tr9 provided in each of the stages of FIGS. 7 and 8 are separated from the timing controller. The first start pulse Vst (or the second start pulse Vst) or the gate-on voltage from the shear stage are turned on. The third and fourth switching devices Tr4 included in each stage are turned on according to the gate on voltage from the next stage.

On the other hand, when the circuit configuration of Figs. 10 and 11 is applied to the stages of the third embodiment of the present invention, the first and ninth switching elements Tr9 provided in each stage of the third embodiment are the first from the timing controller. It is turned on according to the start pulse Vst (or the second start pulse Vst) or the gate on voltage from the shear stage. Then, the third switching device Tr3 provided in each stage of the third embodiment is turned on according to the gate on voltage from the next stage.

On the other hand, when the circuit configuration of Figs. 12 and 13 is applied to the stages of the third embodiment of the present invention, the first and seventh switching elements Tr7 provided in each stage of the third embodiment are made from the timing controller. It is turned on in accordance with one start pulse Vst (or second start pulse Vst) or the gate on voltage from the shear stage. Then, the third and fifth switching devices Tr5 provided in each stage of the third embodiment are turned on according to the gate on voltage from the next stage.

Hereinafter, a gate driving circuit according to a fourth embodiment of the present invention will be described in detail.

18 is a diagram illustrating a gate driving circuit according to a fourth embodiment of the present invention.

The gate driving circuit according to the fourth embodiment of the present invention is the same as the gate driving circuit of the third embodiment described above. As shown in FIG. 18, the first AC voltage source Vac1 and the second AC voltage source Vac2 are included in the odd stages ST1_L, ST3_L, ..., STm + 1_L of the first shift register SR1. ) Is supplied. Specifically, the first AC voltage source Vac1 is supplied to odd-numbered stages and the second AC voltage source Vac2 is supplied to even-numbered stages.

The first AC voltage source Vac1 and the second AC voltage source Vac2 are also supplied to even-numbered stages of the first shift register SR1. Specifically, the first AC voltage source Vac1 is supplied to odd-numbered stages and the second AC voltage source Vac2 is supplied to even-numbered stages among even-numbered stages ST2_L, ST4_L, ..., STm + 2_L. do.

In other words, the first AC voltage source Vac1 is supplied to the 4k + 1 stage and the 4k + 2 stage, and the second AC voltage source Vac2 is supplied to the 4k-1 stage and the 4k-4 stage.

Here, k represents a natural number including zero.

For example, the first AC voltage source Vac1 is supplied to the first stage ST1_L, the fifth stage, the ninth stage, and the like, and to the second stage ST2_L, the sixth stage, the tenth stage, and the like.

In addition, since the -4, -1, and 0th stages do not exist, the second AC voltage source Vac2 is supplied to the third stage ST3_L, the seventh stage, the eleventh stage, and the like, and the fourth stage ST4_L. ), The eighth stage, the twelfth stage and the like.

Similarly, the first AC voltage source Vac1 and the second AC voltage source Vac2 are also supplied to the odd stages ST1_R, ST3_R, ..., STm + 1_R of the second shift register SR2. Specifically, the second AC voltage source Vac2 is supplied to odd-numbered stages of the odd stages ST1_R, ST3_R, ..., STm + 1_R, and the first AC voltage source Vac1 is supplied to even-numbered stages. do.

The first AC voltage source Vac1 and the second AC voltage source Vac2 are also supplied to even-numbered stages ST2_R, ST4_R, ..., STm + 2_R of the second shift register SR2. Specifically, the second AC voltage source Vac2 is supplied to odd-numbered stages among the even-numbered stages ST2_R, ST4_R, ..., STm + 2_R, and the first AC voltage source Vac1 is supplied to even-numbered stages. do.

In other words, the second AC voltage source Vac2 is supplied to the 4k + 1 stage and the 4k + 2 stage, and the first AC voltage source Vac1 is supplied to the 4k-1 stage and the 4k-4 stage.

Here, k represents a natural number including zero.

For example, the second AC voltage source Vac2 is supplied to the first stage ST1_R, the fifth stage, the ninth stage, and the like, and to the second stage ST2_R, the sixth stage, the tenth stage, and the like.

In addition, since the -4, -1, and 0th stages do not exist, the first AC voltage source Vac1 is supplied to the third stage ST3_R, the seventh stage, the eleventh stage, and the fourth stage ST4_R. ), The eighth stage, the twelfth stage and the like.

Thus, the 4k + 1 stages of the first shift register SR1, the 4k + 2 stages of the first shift register ST1, and the 4k-1 stages of the second shift register SR2. And the 4k-4 stages of the second shift register SR2 operate in the same manner as the respective stages ST1_L to STm + 1_L of the first shift register SR1 described in the first embodiment.

And 4k + 1 stages of the second shift register SR1, 4k + 2 stages of the second shift register SR2, and 4k-1 stages of the first shift register SR1. In addition, the 4k-4 stages of the first shift register SR1 operate the same as the stages ST1_R to STm + 1_R of the second shift register SR2 described above in the first embodiment.

Accordingly, the first frame includes 4k + 1 stages of the first shift register SR1, 4k + 2 stages of the first shift register SR1, and 4k of the second shift register SR2. -1 stages and the 4k-4 stages of the second shift register SR2 output the gate off voltage Voff.

The second frame includes 4k + 1 stages of the second shift register SR2, 4k + 2 stages of the second shift register SR2, and 4k− of the first shift register SR1. One stage and the fourth k-4 stages of the first shift register SR1 output a gate off voltage.

As a result, the first frame includes 4k + 1 stages of the second shift register SR2, 4k + 2 stages of the second shift register SR2, and 4k− of the first shift register SR1. The pull-down switching device Trpd provided in one stage and the fourth k-4 stages of the first shift register SR1 has a rest period.

The second frame includes 4k + 1 stages of the first shift register SR1, 4k + 2 stages of the first shift register SR1, and 4k− of the second shift register SR2. The pull-down switching device Trpd provided in the first stages and the fourth k-4 stages of the second shift register SR2 has a rest period.

Each stage ST1_L to STm + 2_L and (ST1_R to STm + 2_R) of the gate driving circuit according to the fourth embodiment of the present invention are illustrated in FIGS. 7, 8, 10, 11, 12, And the circuit configuration shown in FIG.

However, when the circuit configuration of FIGS. 7 and 8 is applied to the stages ST1_L to STm + 2_L and (ST1_R to STm + 2_R) of the fourth embodiment of the present invention, each stage ST1_L to FIG. 7 and FIG. The first and ninth switching elements Tr1 and Tr9 provided at STm + 1_L and (ST1_R to STm + 1_R) may have a first start pulse Vst1 (or a second start pulse Vst2) from a timing controller, or It is turned on according to the gate-on voltage from the second front stage, and the third and fourth switching devices Tr3 and Tr4 provided in each of the stages ST1_L to STm + 1_L and (ST1_R to STm + 1_R) It is turned on according to the gate on voltage from the second next stage.

On the other hand, when the circuit configuration of Figs. 10 and 11 is applied to the stages of the fourth embodiment of the present invention, the first and the provided in each stage (ST1_L to STm + 2_L, (ST1_R to STm + 2_R) of the fourth embodiment The ninth switching elements Tr1 and Tr9 are turned on in response to the first start pulse Vst1 (or the second start pulse Vst2) from the timing controller or the gate on voltage from the second front stage. The third switching device Tr3 provided in each stage of the fourth embodiment is turned on according to the gate on voltage from the second next stage.

On the other hand, when the circuit configuration of Figs. 12 and 13 is applied to the stages of the fourth embodiment of the present invention, each of the stages ST1_L to STm + 2_L and (ST1_R to STm + 2_R) of the fourth embodiment is provided. And the seventh switching elements Tr1 and Tr7 are turned on in accordance with the first start pulse Vst1 (or the second start pulse Vst2) from the timing controller or the gate on voltage from the second front stage. The third and fifth switching elements Tr3 and Tr5 provided in each of the stages ST1_L to STm + 2_L and ST1_R to STm + 2_R of the fourth embodiment are turned on in accordance with the gate-on voltage from the second next stage. -On.

Hereinafter, a gate driving circuit according to a fifth embodiment of the present invention will be described in detail.

19 is a diagram illustrating a gate driving circuit according to a fifth embodiment of the present invention.

The gate driving circuit according to the fifth embodiment of the present invention includes first and second shift registers SR1 and SR2 as shown in FIG. 19.

The first and second shift registers SR1 and SR2 include first to mth stages ST1_L to STm_L and dummy stages STm + 1_L, respectively.

Each stage ST1_L to STm + 1_L provided in the first shift register SR1 sequentially outputs gate-on voltages Von1 to Vonm + 1. In addition, each stage ST1_L to STm + 1_L supplies the gate on voltages Von1 to Vonm + 1 as a start pulse Vst to the first next stage and the second next stage, and to the first front stage. It is supplied as a disable signal.

Thus, each stage ST1_L to STm + 1_L is enabled in response to the gate on voltages from the first and second front stages, and disabled in response to the gate on voltages from the first next stage.

However, since there are no stages in the first and second front ends of the first stage ST1_L, the first stage ST1_L is enabled by the start pulse Vst from the timing controller.

Since the stage does not exist in the second front end of the second stage ST2_L, the second stage ST2_L is enabled by the start pulse Vst from the timing controller.

In addition, since there is no stage in the first next stage of the dummy stage STm + 1_L, the dummy stage STm + 1_L is disabled by the start pulse Vst from the timing controller.

Meanwhile, the node controller 601 of each stage controls the voltage of the second node QB of the stage to which it belongs according to the voltage supplied to the second node QB of the first next stage.

The second shift register SR2 also has the same configuration as the first shift register SR1.

As described above, a circuit configuration of the stages ST1_L to STm + 1_L and ST1_R to STm + 1_R provided in the first and second shift registers SR1 and SR2 will be described in detail.

20 is a diagram illustrating a circuit configuration of a third stage included in the first shift register of FIG. 19.

The first to m th stages ST1_L to STm_L and the dummy stage STm + 1_L provided in the first shift register SR1 are the first to tenth switching elements Tr1 to Tr10 and the pull-up switching element Trpu. And a pull-down switching device Trpd.

The first switching device Tr1 included in each stage charges the first node Q to the first DC voltage source Vdc1 in response to the gate-on voltage from the first front end stage.

For example, the first switching device Tr1 included in the third stage ST3_L of FIG. 20 may respond to the second gate on voltage Vom2 from the second stage ST2_L. Charges the first node (Q) of the first DC voltage source (Vdc1). To this end, the gate terminal of the first switching device Tr1 provided in the third stage ST3_L is connected to the second stage ST2_L, and the drain terminal is a power source for transmitting the first DC voltage source Vdc1. The source terminal is connected to the first node Q of the third stage ST3_L.

The second switching device Tr2 provided in each stage discharges the first node Q of the stage to which it belongs to the second DC voltage source Vdc2 in response to the gate-on voltage from the first next stage.

For example, the second switching device Tr2 included in the third stage ST3_L of FIG. 20 may respond to the fourth gate on voltage Vom4 from the fourth stage ST4_L. The first node (Q) of D is discharged to the second DC voltage source (Vdc2).

The third switching device Tr3 provided in each stage is turned on or turned off in response to the first AC voltage source Vac1 (or the second AC voltage source Vac2), and the stage to which the third switching element Tr3 belongs is included. The second node QB is charged with the first AC voltage source Vac1 (or the second AC voltage source Vac2).

For example, the third switching device Tr3 included in the third stage ST3_L of FIG. 20 is turned on or turned off in response to the first AC voltage source Vac1, and when turned on, the third stage The second node QB of ST3_L is charged with the first AC voltage source Vac1. To this end, the gate terminal and the drain terminal of the third switching device Tr3 provided in the third stage ST3_L are connected to a power line for transmitting the first AC voltage source Vac1, and the source terminal is connected to the third terminal ST3_L. It is connected to the second node QB of the stage ST3_L.

The fourth switching device Tr4 provided in each stage is turned in response to the first AC voltage source Vac1 (or the second AC voltage source Vac2) charged in the second node QB of the first next stage. It is turned on or turned off, and when turned on, discharges the first node Q of the stage to which it belongs to the second DC voltage source Vdc2.

For example, the fourth switching device Tr4 included in the third stage ST3_L of FIG. 20 responds to the first AC voltage source Vac1 charged in the second node QB of the fourth stage ST4_L. It is turned on or turned off and discharges the first node Q of the third stage ST3_L to the second DC voltage source Vdc2 during turn-on. To this end, the gate terminal of the fourth switching device Tr4 provided in the third stage ST3_L is connected to the second node QB of the fourth stage ST4_L, and the drain terminal of the second DC voltage source ( It is connected to the power supply line for transmitting Vdc2), the source terminal is connected to the first node (Q) of the third stage (ST3_L).

The fifth switching device Tr5 provided in each stage is itself in response to the first AC voltage source Vac1 (or the second AC voltage source Vac2) charged in the second node QB of the stage to which it belongs. The first node Q of the belonging stage is discharged to the second DC voltage source Vdc2.

For example, the fifth switching device Tr5 of the third stage ST3_L of FIG. 20 responds to the first AC voltage source Vac1 charged in the second node QB of the third stage ST3_L. As a result, the first node Q of the third stage ST3_L is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the fifth switching device Tr5 provided in the third stage ST3_L is connected to the second node QB of the third stage ST3_L, and the drain terminal thereof is the second DC voltage source. It is connected to the power line for transmitting (Vdc2), the source terminal is connected to the first node (Q).

The sixth switching device Tr6 included in each stage may move the second node QB of the stage to which it belongs to the first AC voltage source Vac1 (or the second) in response to the gate-on voltage from the first next stage. Charge or discharge with AC voltage source (Vac2).

For example, the sixth switching device Tr6 included in the third stage ST3_L of FIG. 20 may respond to the fourth gate on voltage Vom4 from the fourth stage ST4_L. The second node QB is charged or discharged by the first AC voltage source Vac1. To this end, the gate terminal of the sixth switching device Tr6 provided in the third stage ST3_L is connected to the fourth stage ST4_L, and the drain terminal of the power line transmits the first AC voltage source Vac1. The source terminal is connected to the second node QB of the third stage ST3_L.

The seventh switching element Tr7 included in each stage may turn the second node QB of the stage to which it belongs to the second DC voltage source in response to the second AC voltage source Vac2 (or the first AC voltage source Vac1). Discharge at (Vdc2).

For example, the seventh switching device Tr7 provided in the third stage ST3_L of FIG. 20 may perform the second node QB of the third stage ST3_L in response to the second AC voltage source Vac2. 2 Discharge to DC voltage source (Vdc2). To this end, a gate terminal of the seventh switching element Tr7 provided in the third stage ST3_L is connected to a power line for transmitting the second AC voltage source Vac2, and a drain terminal thereof is connected to the second DC voltage source ( It is connected to the power line for transmitting Vdc2), the source terminal is connected to the second node (QB) of the third stage (ST3_L).

The eighth switching element Tr8 included in each stage may receive the second node QB of the stage to which it belongs in response to the first DC voltage source Vdc1 charged in the first node Q of the stage to which it belongs. Discharge to the second DC voltage source Vdc2.

For example, the eighth switching device Tr8 included in the third stage ST3_L of FIG. 20 is connected to the first DC voltage source Vdc1 charged in the first node Q of the third stage ST3_L. In response, the second node QB of the third stage ST3_L is discharged to the second DC voltage source Vdc2. To this end, the gate terminal of the eighth switching device Tr8 provided in the third stage ST3_L is connected to the first node Q of the third stage ST3_L, and the drain terminal of the second DC voltage source. It is connected to the power line for transmitting (Vdc2), the source terminal is connected to the second node (QB) of the third stage (ST3_L).

The ninth switching element Tr9 provided in each stage discharges the second node QB of the stage to which it belongs to the second DC voltage source Vdc2 in response to the gate-on voltage from the first front end stage.

For example, the ninth switching device Tr9 included in the third stage ST3_L of FIG. 20 may respond to the second gate on voltage Vom2 from the second stage ST2_L. Discharges the second node QB to the second DC voltage source Vdc2. To this end, the gate terminal of the ninth switching device Tr9 provided in the third stage ST3_L is connected to the second stage ST2_L, and the drain terminal of the power supply line transmits the second DC voltage source Vdc2. The source terminal is connected to the second node QB of the third stage ST3_L.

The tenth switching device Tr10 provided in each stage discharges the second node QB of the stage to which it belongs to the second DC voltage source Vdc2 in response to the gate-on voltage from the second front stage.

For example, the tenth switching device Tr10 included in the third stage ST3_L of FIG. 20 may respond to the first gate on voltage Vom1 from the first stage ST1_L and may correspond to the third stage ST3_L. Discharges the second node QB to the second DC voltage source Vdc2. To this end, the gate terminal of the ninth switching device Tr9 provided in the third stage ST3_L is connected to the first stage ST1_L, and the drain terminal of the power supply line transmits the second DC voltage source Vdc2. The source terminal is connected to the second node QB of the third stage ST3_L.

The pull-up switching device Trpu provided in each stage outputs the corresponding clock pulse as a gate-on voltage in response to the first DC voltage source Vdc1 charged in the first node Q of the stage to which the stage belongs. The on voltage is supplied to the corresponding gate line, the first front stage, the first next stage, and the second next stage. In this case, the gate on voltage output to the first front stage serves as a signal for disabling the first front stage, and the gate on voltage output to the first next stage enables the first next stage. And a gate on voltage outputted to the second next stage stage as a disable signal for disabling the second next stage stage.

For example, the pull-up switching device Trpu provided in the third stage ST3_L of FIG. 20 receives the third clock pulse CLK3 in response to the first DC voltage source Vdc1 charged in the first node Q. The third gate on voltage Vom3 is output, and the third gate on voltage Vom3 is output to the third gate line GL3, the second stage ST2_L, the fourth stage ST4_L, and the fifth stage ST5_L. Supplies). To this end, the gate terminal of the pull-up switching device Trpu provided in the third stage ST3_L is connected to the first node Q of the third stage ST3_L, and the drain terminal of the third clock pulse It is connected to a clock transmission line for transmitting CLK3, and a source terminal is connected to the third gate line GL3, the second stage ST2_L, the fourth stage ST4_L, and the fifth stage ST5_L.

The pull-down switching device Trpd included in each stage may turn off the second DC voltage source Vdc2 in response to the first AC voltage source Vac1 charged in the second node QB of the stage to which the stage belongs. The off voltage source Voff is supplied to the corresponding gate line, the first front stage, the first next stage, and the second next stage.

For example, the pull-down switching device Trpd included in the third stage ST3_L of FIG. 20 may respond to the first AC voltage source Vac1 charged in the second node QB of the third stage ST3_L. The second DC voltage source Vdc2 is output as the off voltage source Voff, and the off voltage source Voff is output to the third gate line GL3, the second stage ST2_L, the fourth stage ST4_L, and the fifth stage. Supply to (ST5_L). To this end, the gate terminal of the pull-down switching device (Trpd) provided in the third stage (ST3_L) is connected to the second node (QB) of the third stage (ST3_L), the source terminal of the second DC voltage source ( Vdc2) is connected to the power supply line, and the drain terminal is connected to the third gate line GL3, the second stage ST2_L, the fourth stage ST4_L, and the fifth stage ST5_L.

Each switching element provided in the first and second stages ST1_L and ST2_L, the fourth to mth stages ST4_L to STm_L, and the dummy stage STm + 1_L also operates in the same manner as described above.

However, since there are no stages in the first and second front stages of the first stage ST1_L, the first, ninth, and tenth switching elements Tr1, Tr9, Tr10 is supplied with a start pulse Vst from the timing controller. That is, the first stage ST1_L is enabled by the start pulse Vst from the timing controller. Here, the tenth switching element Tr10 may not be provided in the first stage ST1_L.

In addition, since the stage does not exist in the second front end of the second stage ST2_L, the tenth switching element Tr1 included in the second stage ST2_L supplies the start pulse Vst from the timing controller. Receive. That is, the first stage ST1_L is enabled by the start pulse Vst from the timing controller.

In addition, since the stage does not exist at the first stage after the dummy stage STm + 1_L, the second switching element Tr2 and the sixth switching element Tr6 included in the dummy stage STm + 1_L are timingd. The start pulse Vst is supplied from the controller. That is, the dummy stage STm + 1_L is disabled by the start pulse Vst from the timing controller.

In addition, the third and sixth switching elements Tr3 and Tr6 included in the odd stages ST1_L, ST3_L, ..., STm + 1_L of the stages ST1_L to STm + 1_L may have a first AC voltage source. Vac1 is supplied, and the seventh switching element Tr7 is supplied with a second AC voltage source Vac2.

In addition, the third and sixth switching elements Tr3 and Tr6 included in the even-numbered stages ST2_L, ST4_L, ..., STm_L of the stages ST1_L to STm + 1_L may have a second AC voltage source Vac2. ) Is supplied, and the seventh switching device Tr7 is supplied with the first AC voltage source Vac1.

Next, a circuit configuration of the first to m th stages ST1_R to STm_R and the dummy stage STm + 1_R included in the second shift register SR2 will be described.

FIG. 21 is a diagram illustrating a circuit configuration of a third stage included in the second shift register of FIG. 19.

The circuit configuration of each stage ST1_R to STm + 1_R provided in the second shift register SR2 is the same as that of each stage ST1_L to STm + 1_L provided in the first shift register SR1 described above. Do.

However, the third and sixth switching elements Tr3 and Tr6 included in the odd stages ST1_R, ST3_R, ..., STm + 1_R of the stages ST1_R to STm + 1_R may be a second AC voltage source. Vac2 is supplied, and the seventh switching element Tr7 is supplied with the first AC voltage source Vac1.

In addition, the third and sixth switching elements Tr3 and Tr6 included in the even-numbered stages ST2_R, ST4_R, ..., STm_R of the stages ST1_R to STm + 1_R may have a first AC voltage source Vac1. ) Is supplied, and the seventh switching device Tr7 receives the second AC voltage source Vac2.

The operation of the gate driving circuit according to the fifth embodiment of the present invention configured as described above will be described in detail as follows.

Here, the operation of the first shift register SR1 will be described for each period as follows.

FIG. 22 is a diagram illustrating a circuit configuration of the first to third stages included in the first shift register of FIG. 19.

First, the operation of the initial period T0 in the first frame will be described.

Here, it is assumed that the first AC voltage source Vac1 is maintained as the high voltage source Vh and the second AC voltage source Vac2 is maintained as the low voltage source Vl during the first frame, and the second AC voltage source Vac1 is maintained as the low voltage source Vl during the second frame. Assume that the first AC voltage source Vac1 is maintained as the low voltage source Vl and the second AC voltage source Vac2 is maintained as the high voltage source Vh.

Therefore, during the first frame, the third switching device Tr3 provided in the odd stages ST1_L, ST3_L, ..., STm + 1_L of the first shift register SR1 maintains a turn-on state and is excellent. The third switching device Tr3 provided in the first stages ST2_L, ST4_L, ..., STm_L maintains a turn-off state. During the first frame, the seventh switching device Tr7 provided in the odd stages ST1_L, ST3_L, ..., STm + 1_L of the first shift register SR1 maintains a turn-off state. The seventh switching element Tr7 provided in the even-numbered stages ST2_L, ST4_L, ..., STm_L maintains a turn-on state.

On the contrary, during the first frame, the third switching device Tr3 provided in the odd stages ST1_R, ST3_R, ..., STm + 1_R of the second shift register SR2 maintains a turn-off state. The third switching device Tr3 provided in the even-numbered stages ST2_R, ST4_R, ..., STm_R maintains a turn-on state. During the first frame, the seventh switching device Tr7 provided in the odd stages ST1_R, ST3_R, ..., STm + 1_R of the second shift register SR2 maintains a turn-on state. The seventh switching device Tr7 provided in the even-numbered stages ST2_R, ST4_R, ..., STm_R maintains a turn-off state.

As the polarity of the first and second AC voltage sources Vac1 and Vac2 is changed in the second frame, the above-described third and seventh switching elements Tr3 and Tr7 operate in reverse.

During the initial period TO, as shown in FIG. 3, only the start pulse Vst output from the timing controller is kept high, and the remaining start pulses Vst are kept low.

The start pulse Vst output from the timing controller is supplied to the first stage ST1_L and the second stage ST2_L.

Specifically, the start pulse Vst may include a gate terminal of the first switching device Tr1 provided in the first stage ST1_L, a gate terminal of the ninth switching device Tr9, and a tenth switching device Tr10. Is supplied to the gate terminal.

Then, the first, ninth, and tenth switching elements Tr1, Tr9, and Tr10 are turned on, and the first DC voltage source Vdc1 is turned on through the turned-on first switching element Tr1. Is applied to the first node (Q). Accordingly, the first node Q is charged, and both the pull-up switching device Trpu and the eighth switching device Tr8 having the gate terminal connected to the charged first node Q are turned on.

Here, the second DC voltage source Vdc2 is supplied to the second node QB through the turned-on eighth, ninth, and tenth switching elements Tr8, Tr9, and Tr10.

As described above, since the first AC voltage source Vac1 is maintained as the high voltage source Vh during the first frame, the third switching device receives the first AC voltage source Vac1 through the gate terminal and the source terminal. Tr3) is turned on. Then, the first AC voltage source Vac1 is supplied to the second node QB through the turned-on third switching device Tr3. Therefore, the first AC voltage source Vac1 and the second DC voltage source Vdc2 are simultaneously supplied to the second node QB. At this time, the switching device (the eighth, which discharges the second node QB to the second DC voltage source Vdc2 than the number of switching devices (third switching device (Tr3)) for charging the first AC voltage source (Vac1) Since the number of the ninth and tenth switching elements Tr8, Tr9 and Tr10 is larger, the second node QB is maintained in a discharged state. As a result, the pull-down switching device Trpd and the fifth switching device Tr5 having the gate terminal connected to the discharged second node QB are turned off.

As described above, since the second AC voltage source Vac2 is maintained as the low voltage source Vl during the first frame, the seventh switching element Tr7 receiving the second AC voltage source Vac2 through the gate terminal is It is turned off.

In addition, since there is no output from the second stage ST2_L in this initial period T0, the second and sixth switching elements Tr2 and Tr6 of the first stage ST1_L are turned off.

In particular, in order to maintain the state of charge of the first node Q of the first stage ST1_L during this initial period T0, the fourth switching element Tr4 of the first stage ST1_L is turned off. State must be maintained. The fourth switching device Tr4 is turned on or off according to the voltage supplied to the first next stage, that is, the second node QB of the second stage ST2_L. Therefore, it is necessary to keep the second node QB of the second stage ST2_L in the discharge state in this initial period T0. To this end, the start pulse Vst output in this initial period T0 discharges the second node QB of the second stage ST2_L. If this is explained in more detail as follows.

That is, the start pulse Vst is supplied to the gate terminal of the tenth switching element Tr10 provided in the second stage ST2_L.

Then, the tenth switching element Tr10 of the second stage ST2_L is turned on. At this time, the second DC voltage source Vdc2 is turned on through the turned-on tenth switching element Tr10. Is applied to the second node QB of ST2_L.

As a result, the fourth switching device Tr4 of the first stage having the gate terminal connected to the second node QB of the second stage is turned off.

In summary, in the initial period T0, the first node Q of the first stage ST1_L is charged, and the second node QB of the first stage ST1_L is discharged. In addition, the second node QB of the second stage ST2_L is discharged. That is, the first stage ST1_L is enabled in the initial period T0.

Next, the operation of the first period T1 will be described.

During the first period T1, as shown in FIG. 3, only the first clock pulse CLK1 remains high and the remaining clock pulses remain low. Accordingly, the first, ninth, and tenth switching elements Tr1, Tr9, and Tr10 and the second stage ST2_L provided in the first stage ST1_L in response to the low state start pulse Vst. The tenth switching element Tr10 provided in the is turned off. Accordingly, the first node Q of the first stage ST1_L is maintained in a floating state.

Meanwhile, as the first node Q of the first stage ST1_L is continuously maintained as the first DC voltage source Vdc1 applied during the initial period T0, the pull-up switching device of the first stage ST1_L is maintained. Trpu remains turned on. In this case, as the first clock pulse CLK1 is applied to the drain terminal of the turned-on pull-up switching device Trpu of the first stage ST1_L, the first node Q of the first stage ST1_L The first DC voltage source Vdc1 charged in) is amplified by bootstrapping.

Therefore, the first clock pulse CLK1 applied to the drain terminal of the pull-up switching device Trpu of the first stage ST1_L is stably output through the source terminal of the pull-up switching device Trpu. In this case, the output first clock pulse CLK1 is applied to the first gate line GL1 and functions as a first gate on voltage Vom1 for driving the first gate line GL1.

The first gate-on voltage Vom1 output from the first stage ST1_L in the first period T1 is also input to the second stage ST2_L. In detail, as illustrated in FIG. 22, the first gate on voltage Vom1 may include the gate terminal of the first switching element Tr1 and the ninth switching element Tr9 of the second stage ST2_L. It is input to the gate terminal and the gate terminal of the tenth switching element Tr10. Here, the first gate on voltage Vom1 supplied to the second stage ST2_L plays the same role as the start pulse Vst supplied to the first stage ST1_L. In response to Vom1, the second stage ST2_L is enabled.

In addition, the first gate-on voltage Vom1 output from the first stage ST1_L in the first period T1 is also input to the third stage ST3_L. That is, the second node QB of the third stage ST3_L is discharged in response to the first gate on voltage Vom1. Here, since the second node QB of the third stage ST3_L is in a discharged state in the first period T1, the second terminal connected to the gate terminal of the second node QB of the third stage ST3_L is discharged. The fourth switching device Tr4 of the stage ST2_L is turned off.

In summary, during the first period T1, the first stage ST1_L outputs a first gate-on voltage Vom1, the second stage ST2_L is enabled, and the third stage ST2_L and ST3_L. Is discharged.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in FIG. 3, only the second clock pulse CLK2 remains high and the remaining clock pulses remain low.

Therefore, the second stage ST2_L receiving the second clock pulse CLK2 outputs the second gate on voltage Vom2 and supplies it to the second gate line GL2. In addition, the second gate on voltage Vom2 output from the second stage ST2_L enables the third stage ST3_L and discharges the second node QB of the fourth stage ST4_L. In addition, the second gate on voltage Vom2 output from the second stage ST2_L is supplied to the first stage ST1_L to disable the first stage ST1_L. If this is explained in more detail as follows.

The second gate on voltage Vom2 output from the second stage ST2_L is supplied to the second and sixth switching elements Tr2 and Tr6 of the first stage ST1_L. That is, the second gate on voltage Vom2 is supplied to the gate terminal of the second switching element Tr2 and the gate terminal of the sixth switching element Tr6. Then, the second and sixth switching elements Tr2 and Tr6 are turned on. The second DC voltage source Vdc2 is supplied to the first node Q of the first stage ST1_L through the turned-on second switching element Tr2. Accordingly, the first node Q of the first stage ST1_L is discharged, and the pull-up switching device Trpu and the eighth switching device Tr8 having the gate terminal connected to the discharged first node Q. ) Is turned off.

As a result, switching elements (the seventh, eighth, ninth, and tenth switching elements Tr7 and Tr8 for discharging the second node QB of the first stage ST1_L in the second period T2). , Tr9 and Tr10) are all turned off. In addition, since the third switching device Tr3 of the first stage ST1_L is turned on, the second node QB of the first stage ST1_L is turned on of the third switching device Tr3. It is charged with the first DC voltage source Vdc1 applied through. Accordingly, the pull-down switching device Trpd and the fifth switching device Tr5 connected to the charged second node QB are turned on. The second DC voltage source Vdc2 is supplied to the first node Q of the first stage ST1_L through the turned-on fifth switching element Tr5, so that the discharge rate of the first node Q is increased. Is accelerated.

The second DC voltage source Vdc2 is supplied to the first gate line GL1 as an off voltage source Voff through the turned-on pull-down switching device Trpd. Here, the first stage ST1_L is disabled by performing a first operation. That is, in the disable period, the first node Q of the first stage ST1_L is discharged and the second node QB is charged.

In summary, during the second period T2, the first stage ST1_L is disabled (first operation) to output an off voltage source Voff, and the second stage ST2_L receives a second gate on voltage Vom2. ), The third stage ST3_L is enabled, and the fourth stage ST4_L discharges its second node QB by the third gate on voltage Vom2.

Subsequently, in the third period T3, the third stage ST3_L outputs the third gate on voltage Vom3, and the fourth stage ST4_L is enabled in response to the third gate on voltage Vom3. And the second node QB of the fifth stage ST4_L is discharged. In addition, the second stage ST2_L is disabled in response to the third gate on voltage Vom3.

In this case, the second stage ST2_L, which is the even-numbered stage, is disabled in a different manner from the first stage ST1_L, which is the odd-numbered stage. That is, the second stage ST2_L is disabled by performing the second operation. If this is explained in more detail as follows.

That is, since the second stage ST2_L is the even-numbered stage, the seventh switching element Tr7 of the second stage ST2_L is turned on during the first frame and the second stage ST2_L of the second stage ST2_L The third switching device Tr3 is turned off during the first frame. Therefore, in the third period T3, the first node Q of the second stage ST2_L maintains the discharge state by the above-described operation, and also the second node of the second stage ST2_L. QB also maintains a discharge state by the second DC voltage source Vdc2 applied through the turned-on seventh switching device Tr7. As a result, the second stage ST2_L disabled by the second operation in the third period T3 does not generate any output.

In the same manner, the remaining stages ST1_L to STm + 1_L are enabled according to the gate-on voltage from the first front stage from the stage, and are supplied with the corresponding clock pulses as the gate-on voltage. Output Then, it is disabled according to the gate on voltage from the first next stage stage from itself.

At this time, the odd stages ST1_L, ST3_L, ..., STm + 1_L are disabled by performing the first operation, and the even-numbered stages ST2_L, ST4_L, ..., STm_L perform the second operation. To disable.

As a result, the pull-down switching device Trpd provided in the even-numbered stages ST2_L, ST4_L, ..., STm_L of the first shift register SR1 has a rest period in the first frame period.

Next, the operation of the second shift register SR2 will be described.

As described above, the third switching device Tr3 provided in the odd stages ST1_R, ST3_R, ..., STm + 1_R of the second shift register SR2 is turned off during the first frame. Is maintained, and the seventh switching device Tr7 is kept turned on. During the first frame, the third switching device Tr3 provided in the even-numbered stages ST2_R, ST4_R, ..., STm_R of the second shift register SR2 maintains a turn-on state. The seventh switching device Tr7 maintains a turn-off state.

Therefore, the odd stages ST1_R, ST3_R, ..., STm + 1_R of the second shift register SR2 are the even-numbered stages ST2_R, ST4_R,... Of the first shift register SR1. .., STm_R). In addition, even-numbered stages ST2_R, ST4_R, ..., STm_R of the second shift register SR2 are the odd-numbered stages ST1_L, ST3_L, ... of the first shift register SR1 described above. , STm + 1_L).

That is, the operation during the initial period T0 will be described below.

The start pulse Vst output from the timing controller is supplied to the first stage ST1_R and the second stage ST2_R.

In detail, the start pulse Vst includes the gate terminal of the first switching element Tr1, the gate terminal of the ninth switching element Tr9, and the tenth switching element Tr10 provided in the first stage ST1_R. It is supplied to the gate terminal of.

Then, the first, ninth, and tenth switching elements Tr1, Tr9, and Tr10 are turned on, and the first DC voltage source Vdc1 is turned on through the turned-on first switching element Tr1. Applied to one node (Q). Accordingly, the first node Q is charged, and both the pull-up switching device Trpu and the eighth switching device Tr8 having the gate terminal connected to the charged first node Q are turned on.

Here, the second DC voltage source Vdc2 is supplied to the second node QB through the turned-on eighth and ninth switching elements Tr8 and Tr9. Accordingly, the second node QB is discharged, and the pull-down switching device Trpd and the fifth switching device Tr5 connected to the discharged second node QB are turned off.

As described above, since the second AC voltage source Vac2 is maintained as the low voltage source Vl during the first frame, the third switching receives the second AC voltage source Vac2 through the gate terminal and the source terminal. Element Tr3 is turned off.

In addition, as described above, since the first AC voltage source Vac1 is maintained as the high voltage source Vh during the first frame, the seventh switching element Tr7 receiving the first AC voltage source Vac1 through the gate terminal. ) Is turned on. The second DC voltage source Vdc2 is supplied to the second node QB through the turned-on seventh switching element Tr7 to accelerate the discharge of the second node QB.

In addition, since there is no output from the second stage ST2_L in this initial period T0, the second and sixth switching elements Tr6 of the first stage ST1_L are turned off.

In particular, in order to maintain the state of charge of the first node Q of the first stage ST1_R during this initial period T0, the fourth switching element Tr4 of the first stage ST1_R is turned off. State must be maintained. The fourth switching device Tr4 is turned on or off according to the voltage supplied to the first next stage, that is, the second node QB of the second stage ST2_R. Therefore, it is necessary to keep the second node QB of the second stage ST2_R in the discharged state in this initial period T0. To this end, the start pulse Vst output in this initial period T0 discharges the second node QB of the second stage ST2_R. If this is explained in more detail as follows.

That is, the start pulse Vst is supplied to the gate terminal of the tenth switching element Tr10 provided in the second stage ST2_R.

Then, the tenth switching device Tr10 of the second stage ST2_R is turned on, and at this time, the second DC voltage source Vdc2 is turned on through the turned-on tenth switching device Tr1 to the second stage ( Is applied to the second node QB of ST2_R.

Accordingly, the fourth switching device Tr4 of the first stage ST1_R having the gate terminal connected to the second node QB of the second stage ST2_R is turned off.

Thereafter, the first stage ST1_R outputs the first gate-on voltage Vom1 in the first period T1, and no output occurs in the second period T2. In the second period T2, the second stage ST2_L outputs the second gate on voltage Vom2, and in the third period T3, the second stage ST2_L supplies the off voltage source Voff. Output

In the same manner, each of the remaining stages ST2_R to STm + 1_R is enabled according to the gate on voltage from the first front end stage from the stage, and is supplied with the corresponding clock pulse in the enabled state as the gate on voltage. Output Then, it is disabled according to the gate on voltage from the first next stage stage from itself.

At this time, the odd stages ST1_R, ST3_R, ..., STm + 1_R are disabled by performing the second operation, and the even-numbered stages ST2_R, ST4_R, ..., STm_R perform the first operation. To disable.

Therefore, in the first frame period, the pull-down switching device Trpd provided in the odd stages ST1_R, ST3_R, ..., STm + 1_R of the second shift register SR2 has a rest period.

As described above, in the first frame, even-numbered stages ST1_L, ST3_L, ..., STm + 1_L of the first shift register SR1 and even-numbered stages ST2_R, ST4_R of the second shift register SR2. , ..., STm_R outputs the off voltage source Voff, and in the second frame, the even-numbered stages ST2_L, ST4_L, ..., STm_L and the second shift register of the first shift register SR1. The odd-numbered stages ST1_R, ST3_R, ..., STm + 1_R of SR2 output the off voltage source Voff.

As a result, in the first frame, the odd-numbered stages ST2_L, ST4_L, ..., STm_L of the first shift register SR1 and the odd-numbered stage of the second shift register SR2 are provided. The pull-down switching devices Trpd provided in the fields ST1_R, ST3_R, ..., STm + 1_R have a rest period, and the odd stages ST1_L and ST3_L of the first shift register SR1 are provided in the second frame. , Pull down switching element Trpd provided in STm + 1_L and pulldown switching element Trpd provided in even-numbered stages ST2_R, ST4_R, ..., STm_R of second shift register SR2. ) Has a rest period.

In the above-described embodiment, an example in which the first and second AC voltage sources Vac1 and Vac2 are changed in units of one frame has been described. The first and second AC voltage sources Vac1 and Vac2 are p (p is 2). The above natural number) may be changed in units of frames.

In each of the above-described embodiments, each switching element may use either an NMOS transistor or a PMOS transistor.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The gate driving circuit according to the present invention as described above has the following effects.

The first shift register and the second shift register provided in the gate driving circuit according to the present invention simultaneously output the gate on voltage and alternately output the gate off voltage. Therefore, deterioration of the pull-down switching device provided in each stage of the first and second shift registers can be prevented.

Claims (35)

A plurality of first stages connected to one side of each gate line; And A plurality of second stages connected to the other side of each gate line, And a first stage and a second stage connected to the same gate line simultaneously output a gate on voltage and alternately output a gate off voltage. The method of claim 1, The first and second stages, A pull-up switching device configured to output a gate on voltage when the first node is charged; A pull-down switching device configured to output a gate off voltage when the second node is charged; And A first operation of charging the first node and discharging the second node in an enable period, and discharging the first node and charging the second node in a disable period, and the first and second nodes; And a node controller configured to perform any one of the second operations of discharging all of the gates. The method of claim 2, In the disable period, When the node control unit provided in each first stage performs the first operation, the node control unit provided in each second stage performs the second operation, And the node controller provided in each second stage performs a first operation when the node controller provided in each first stage performs a second operation. The method of claim 3, wherein The node control unit provided in the m (m is a natural number) stage of the first stages, A first switching device for charging the first node with a first DC voltage source in response to a start pulse from an external source or a gate on voltage from an m−1 th stage; A second switching element discharging the first node to a second DC voltage source in response to a first AC voltage source charged in a second node; a third switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from an m + 1 th stage; A fourth switching element outputting a second DC voltage source in response to a start pulse from the outside; A fifth switching device configured to output a second DC voltage source in response to the first DC voltage source charged in the first node; A sixth switching element turned on or off in response to a first alternating current voltage source and outputting the first alternating current voltage source when turned on; It is turned on or off in response to the second DC voltage source and the first AC voltage source output from the fourth, fifth, and sixth switching elements, and when turned on, the second node is turned into the first AC voltage source. A seventh switching element for charging; An eighth switching device discharging the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; And And a ninth switching device for discharging the second node to a second DC voltage source in response to a start pulse from an external source or a gate on voltage from an m-1th stage. 5. The method of claim 4, The node control unit provided in the m (m is a natural number) stage of the first stages, And a tenth switching element which is turned on or turned off in response to a second alternating voltage source and discharges the second node to a second direct current voltage source when turned on. 5. The method of claim 4, The node control unit provided in the m (m is a natural number) stage of the second stages, A first switching device configured to charge a first node to the first DC voltage source in response to a start pulse from an external source or a gate on voltage from an m−1th stage; A second switching element for discharging the first node to a second DC voltage source in response to a second AC voltage source charged in a second node; a third switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from an m + 1 th stage; A fourth switching element outputting a second DC voltage source in response to a start pulse from the outside; A fifth switching device configured to output a second DC voltage source in response to the first DC voltage source charged in the first node; A sixth switching element turned on or off in response to a second alternating current voltage source and outputting the second alternating current voltage source when turned on; It is turned on or off in response to a second DC voltage source and a second AC voltage source output from the fourth, fifth, and sixth switching elements, and when turned on, the second node is turned into the second AC voltage source. A seventh switching element for charging; An eighth switching device discharging the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; And And a ninth switching device for discharging the second node to a second DC voltage source in response to a start pulse from an external source or a gate on voltage from an m-1th stage. The method of claim 6, The node control unit provided in the m (m is a natural number) stage of the second stages, And a tenth switching element which is turned on or off in response to the first alternating current voltage source and discharges the second node to a second direct current voltage source when turned on. The method of claim 3, wherein The node control unit provided in the m (m is a natural number) stage of the first stages, A first switching device for charging the first node with a first DC voltage source in response to a start pulse from an external source or a gate on voltage from an m−1 th stage; A second switching element for discharging the first node to the second DC voltage source in response to the first AC voltage source charged in the second node; a third switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from an m + 1 th stage; A fourth switching element which is turned on or off in response to the first alternating current voltage source and charges the second node with a first alternating current voltage source when turned on; a fifth switching device configured to charge or discharge the second node to the first AC voltage source in response to a gate on voltage from an m + 1 th stage; A sixth switching element configured to discharge the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; a seventh switching element configured to discharge the second node to a second DC voltage source in response to a gate on voltage from an m−1 th stage; And And an eighth switching element which is turned on or off in response to a second alternating current voltage source and discharges the second node to a second direct current voltage source at turn-on time. 9. The method of claim 8, The node controller provided in the m-th stage of the second stages, A first switching device for charging the first node with a first DC voltage source in response to a start pulse from an external source or a gate on voltage from an m−1 th stage; A second switching element for discharging the first node to the second DC voltage source in response to the second AC voltage source charged in the second node; a third switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from an m + 1 th stage; A fourth switching element that is turned on or off in response to the second alternating voltage source and charges the second node with a second alternating voltage source when turned on; a fifth switching device configured to charge or discharge the second node to the second AC voltage source in response to a gate on voltage from an m + 1th stage; A sixth switching element configured to discharge the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; a seventh switching element configured to discharge the second node to a second DC voltage source in response to a gate on voltage from an m−1 th stage; And And an eighth switching element which is turned on or turned off in response to the first alternating current voltage source, and discharges the second node to a second direct current voltage source when turned on. The method of claim 2, In the disable period, When the node controller provided in the 2m-1 (m is a natural number) stage of the first stages and the node controller provided in the 2mth stage of the second stages perform the first operation, the first stage The node controller provided in the 2m-th stage among the second stages and the node controller provided in the 2m-1th stage of the second stages perform the second operation, When the node controller provided in the 2m-1th stage of the first stages and the node controller provided in the 2mth stage of the second stages perform the second operation, the 2mth stage of the first stages is performed. And the node controller provided in the 2m-1th stage of the second stages performs the second operation. 11. The method of claim 10, The node control unit provided in the 2m-1 (m is a natural number) stage of the first stages, A first switching device for charging the first node with a first DC voltage source in response to a start pulse from an external source or a gate on voltage from a 2m-2 < th >stage; A second switching element discharging the first node to a second DC voltage source in response to a first AC voltage source charged in a second node; A third switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from a 2m-th stage; A fourth switching element outputting a second DC voltage source in response to a start pulse from the outside; A fifth switching device configured to output a second DC voltage source in response to the first DC voltage source charged in the first node; A sixth switching element turned on or off in response to a first alternating current voltage source and outputting the first alternating current voltage source when turned on; It is turned on or off in response to the second DC voltage source and the first AC voltage source output from the fourth, fifth, and sixth switching elements, and when turned on, the second node is turned into the first AC voltage source. A seventh switching element for charging; An eighth switching device discharging the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; And And a ninth switching element for discharging the second node to a second DC voltage source in response to a start pulse from an external source or a gate on voltage from a 2m-2th stage. The method of claim 11, The node controller of 2m-1 (m is a natural number) of the first stages, And a tenth switching element which is turned on or turned off in response to a second alternating voltage source and discharges the second node to a second direct current voltage source when turned on. The method of claim 11, The node controller provided in the 2m stage (m is a natural number) of the first stages, A first switching device for charging a first node with the first DC voltage source in response to a gate on voltage from a 2m-1th stage; A second switching element for discharging the first node to a second DC voltage source in response to a second AC voltage source charged in a second node; A third switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from a 2m + 1th stage; A fourth switching element outputting a second DC voltage source in response to a start pulse from the outside; A fifth switching device configured to output a second DC voltage source in response to the first DC voltage source charged in the first node; A sixth switching element turned on or off in response to a second alternating current voltage source and outputting the second alternating current voltage source when turned on; It is turned on or off in response to a second DC voltage source and a second AC voltage source output from the fourth, fifth, and sixth switching elements, and when turned on, the second node is turned into the second AC voltage source. A seventh switching element for charging; An eighth switching device discharging the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; And And a ninth switching element for discharging the second node to a second DC voltage source in response to a gate on voltage from a 2m-1th stage. The method of claim 13, The node controller provided in the 2mth stage of the first stages, And a tenth switching element which is turned on or turned off in response to the first alternating current voltage source, and which, when turned on, discharges the second node to a second direct current voltage source. The method of claim 13, The node control unit provided in the 2m-1 (m is a natural number) stage of the second stages, A first switching device configured to charge a first node to the first DC voltage source in response to a start pulse from an external source or a gate on voltage from a 2m-2nd stage; A second switching element for discharging the first node to a second DC voltage source in response to a second AC voltage source charged in a second node; A third switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from a 2m-th stage; A fourth switching element outputting a second DC voltage source in response to a start pulse from the outside; A fifth switching device configured to output a second DC voltage source in response to the first DC voltage source charged in the first node; A sixth switching element turned on or off in response to a second alternating current voltage source and outputting the second alternating current voltage source when turned on; It is turned on or off in response to a second DC voltage source and a second AC voltage source output from the fourth, fifth, and sixth switching elements, and when turned on, the second node is turned into the second AC voltage source. A seventh switching element for charging; An eighth switching device discharging the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; And And a ninth switching element for discharging the second node to a second DC voltage source in response to a start pulse from an external source or a gate on voltage from a 2m-2th stage. 16. The method of claim 15, The node control unit provided in the 2m-1 (m is a natural number) stage of the second stages, And a tenth switching element which is turned on or off in response to the first alternating current voltage source and discharges the second node to a second direct current voltage source when turned on. 16. The method of claim 15, The node control unit provided in the 2m stage (m is a natural number) of the second stages, A first switching device for charging a first node with the first DC voltage source in response to a gate on voltage from a 2m-1th stage; A second switching element discharging the first node to a second DC voltage source in response to a first AC voltage source charged in a second node; A third switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from a 2m + 1th stage; A fourth switching element outputting a second DC voltage source in response to a start pulse from the outside; A fifth switching device configured to output a second DC voltage source in response to the first DC voltage source charged in the first node; A sixth switching element turned on or off in response to a first alternating current voltage source and outputting the first alternating current voltage source when turned on; It is turned on or off in response to the second DC voltage source and the first AC voltage source output from the fourth, fifth, and sixth switching elements, and when turned on, the second node is turned into the first AC voltage source. A seventh switching element for charging; An eighth switching device discharging the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; And And a ninth switching element for discharging the second node to a second DC voltage source in response to a gate on voltage from a 2m-1th stage. The method of claim 17, The node control unit provided in the 2m stage (m is a natural number) of the second stages, And a tenth switching element which is turned on or turned off in response to a second alternating voltage source and discharges the second node to a second direct current voltage source when turned on. 11. The method of claim 10, The node control unit provided in the 2m-1 (m is a natural number) stage of the first stages, A first switching element for charging the first node with a first DC voltage source in response to a first start pulse from an external source or a gate on voltage from a 2m-3rd stage; A second switching element discharging the first node to a second DC voltage source in response to a first AC voltage source charged in a second node; A third switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from a 2m + 1th stage; A fourth switching element outputting a second DC voltage source in response to the first start pulse from the outside; A fifth switching device configured to output a second DC voltage source in response to the first DC voltage source charged in the first node; A sixth switching element turned on or off in response to a first alternating current voltage source and outputting the first alternating current voltage source when turned on; It is turned on or off in response to the second DC voltage source and the first AC voltage source output from the fourth, fifth, and sixth switching elements, and when turned on, the second node is turned into the first AC voltage source. A seventh switching element for charging; An eighth switching device discharging the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; And And a ninth switching element for discharging the second node to a second DC voltage source in response to a first start pulse from the outside or a gate on voltage from the 2m-3rd stage. 20. The method of claim 19, The node control unit provided in the 2m-1 (m is a natural number) stage of the first stages, And a tenth switching element which is turned on or turned off in response to a second alternating voltage source and discharges the second node to a second direct current voltage source when turned on. 20. The method of claim 19, The node controller provided in the 2m stage (m is a natural number) of the first stages, A first switching device for charging a first node with the first DC voltage source in response to a second start pulse from an external source or a gate-on voltage from a 2m-2nd stage; A second switching element for discharging the first node to a second DC voltage source in response to a second AC voltage source charged in a second node; A third switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from a 2m + 2th stage; A fourth switching device for outputting a second DC voltage source in response to a second start pulse from the outside; A fifth switching device configured to output a second DC voltage source in response to the first DC voltage source charged in the first node; A sixth switching element turned on or off in response to a second alternating current voltage source and outputting the second alternating current voltage source when turned on; It is turned on or off in response to a second DC voltage source and a second AC voltage source output from the fourth, fifth, and sixth switching elements, and when turned on, the second node is turned into the second AC voltage source. A seventh switching element for charging; An eighth switching device discharging the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; And And a ninth switching element for discharging the second node to a second DC voltage source in response to a second start pulse from an external source or a gate on voltage from a 2m-2th stage. 22. The method of claim 21, The node controller provided in the 2m stage (m is a natural number) of the first stages, And a tenth switching element which is turned on or off in response to the first alternating current voltage source and discharges the second node to a second direct current voltage source when turned on. 22. The method of claim 21, The node control unit provided in the 2m-1 (m is a natural number) stage of the second stages, A first switching device for charging a first node with the first DC voltage source in response to a first start pulse from an external source or a gate on voltage from a 2m-3rd stage; A second switching element for discharging the first node to a second DC voltage source in response to a second AC voltage source charged in a second node; A third switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from a 2m + 1th stage; A fourth switching element outputting a second DC voltage source in response to the first start pulse from the outside; A fifth switching device configured to output a second DC voltage source in response to the first DC voltage source charged in the first node; A sixth switching element turned on or off in response to a second alternating current voltage source and outputting the second alternating current voltage source when turned on; It is turned on or off in response to a second DC voltage source and a second AC voltage source output from the fourth, fifth, and sixth switching elements, and when turned on, the second node is turned into the second AC voltage source. A seventh switching element for charging; An eighth switching device discharging the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; And And a ninth switching element for discharging the second node to a second DC voltage source in response to a first start pulse from the outside or a gate on voltage from the 2m-3rd stage. 24. The method of claim 23, The node control unit provided in the 2m-1 (m is a natural number) stage of the second stages, And a tenth switching element which is turned on or off in response to the first alternating current voltage source and discharges the second node to a second direct current voltage source when turned on. 24. The method of claim 23, The node control unit provided in the 2m stage (m is a natural number) of the second stages, A first switching device configured to charge a first node to the first DC voltage source in response to a second start pulse from an external source or a gate on voltage from a 2m-2nd stage; A second switching element discharging the first node to a second DC voltage source in response to a first AC voltage source charged in a second node; A third switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from a 2m + 2th stage; A fourth switching device for outputting a second DC voltage source in response to a second start pulse from the outside; A fifth switching device configured to output a second DC voltage source in response to the first DC voltage source charged in the first node; A sixth switching element turned on or off in response to a first alternating current voltage source and outputting the first alternating current voltage source when turned on; It is turned on or off in response to the second DC voltage source and the first AC voltage source output from the fourth, fifth, and sixth switching elements, and when turned on, the second node is turned into the first AC voltage source. A seventh switching element for charging; An eighth switching device discharging the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; And And a ninth switching element for discharging the second node to a second DC voltage source in response to a second start pulse from an external source or a gate on voltage from a 2m-2th stage. 26. The method of claim 25, The node control unit provided in the 2m stage (m is a natural number) of the second stages, And a tenth switching element which is turned on or turned off in response to a second alternating voltage source and discharges the second node to a second direct current voltage source when turned on. 11. The method of claim 10, The node control unit provided in the 2m-1 (m is a natural number) stage of the first stages, A first switching element for charging the first node with a first DC voltage source in response to a first start pulse from an external source or a gate on voltage from a 2m-3rd stage; A second switching element for discharging the first node to the second DC voltage source in response to the first AC voltage source charged in the second node; A third switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from a 2m + 1th stage; A fourth switching element which is turned on or off in response to the first alternating current voltage source and charges the second node with a first alternating current voltage source when turned on; A fifth switching device configured to charge or discharge the second node to the first AC voltage source in response to a gate on voltage from a 2m + 1th stage; A sixth switching element configured to discharge the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; A seventh switching device configured to discharge the second node to a second DC voltage source in response to a gate on voltage from a 2m-3rd stage; And And an eighth switching element which is turned on or off in response to a second alternating current voltage source and discharges the second node to a second direct current voltage source at turn-on time. 28. The method of claim 27, The node controller provided in the 2m stage (m is a natural number) of the first stages, A first switching device for charging the first node with a first DC voltage source in response to a second start pulse from an external source or a gate on voltage from a 2m-2 < th >stage; A second switching element for discharging the first node to the second DC voltage source in response to the second AC voltage source charged in the second node; A third switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from a 2m + 2th stage; A fourth switching element that is turned on or off in response to the second alternating voltage source and charges the second node with a second alternating voltage source when turned on; A fifth switching device configured to charge or discharge the second node to the second AC voltage source in response to a gate on voltage from a 2m + 2th stage; A sixth switching element configured to discharge the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; A seventh switching device discharging the second node to a second DC voltage source in response to a gate on voltage from a 2m-2 < th >stage; And And an eighth switching element which is turned on or turned off in response to the first alternating current voltage source, and discharges the second node to a second direct current voltage source when turned on. 29. The method of claim 28, The node control unit provided in the 2m-1 (m is a natural number) stage of the second stages, A first switching element for charging the first node with a first DC voltage source in response to a first start pulse from an external source or a gate on voltage from a 2m-3rd stage; A second switching element for discharging the first node to the second DC voltage source in response to the second AC voltage source charged in the second node; A third switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from a 2m + 1th stage; A fourth switching element that is turned on or off in response to the second alternating voltage source and charges the second node with a second alternating voltage source when turned on; A fifth switching device configured to charge or discharge the second node to the second AC voltage source in response to a gate on voltage from a 2m + 1th stage; A sixth switching element configured to discharge the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; A seventh switching device configured to discharge the second node to a second DC voltage source in response to a gate on voltage from a 2m-3rd stage; And And an eighth switching element which is turned on or turned off in response to the first alternating current voltage source, and discharges the second node to a second direct current voltage source when turned on. 30. The method of claim 29, The node control unit provided in the 2m stage (m is a natural number) of the second stages, A first switching device for charging the first node with a first DC voltage source in response to a second start pulse from an external source or a gate on voltage from a 2m-2nd stage; A second switching element for discharging the first node to the second DC voltage source in response to the first AC voltage source charged in the second node; A third switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from a 2m + 2th stage; A fourth switching element which is turned on or off in response to the first alternating current voltage source and charges the second node with a first alternating current voltage source when turned on; A fifth switching device configured to charge or discharge the second node to the first AC voltage source in response to a gate on voltage from a 2m + 2th stage; A sixth switching element configured to discharge the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; A seventh switching device discharging the second node to a second DC voltage source in response to a gate on voltage from a 2m-2 < th >stage; And And an eighth switching element which is turned on or off in response to a second alternating current voltage source and discharges the second node to a second direct current voltage source at turn-on time. 11. The method of claim 10, The node control unit provided in the 2m-1 (m is a natural number) stage of the first stages, A first switching device for charging the first node with a first DC voltage source in response to a start pulse from an external source or a gate on voltage from a 2m-2nd stage and a 2m-3rd stage; A second switching element configured to discharge the first node to a second DC voltage source in response to a gate on voltage from a 2m-th stage; A third switching element configured to discharge the first node to the second DC voltage source in response to a first AC voltage source charged in the second node; A fourth switching element that is turned on or off in response to a first AC voltage source charged in a second node of a 2m-th stage, and discharges the first node to a second DC voltage source when turned on; A fifth switching element turned on or off in response to the first alternating current voltage source and charging the second node with the first alternating current voltage source when turned on; A sixth switching device configured to charge or discharge the second node to the first AC voltage source in response to a gate on voltage from a 2m-th stage; A seventh switching element configured to discharge the second node to a second DC voltage source in response to a second AC voltage source phase-inverted with respect to the first AC voltage source; An eighth switching device discharging the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; And And a ninth switching device configured to discharge the second node to a second DC voltage source in response to a start pulse from an external source or a gate on voltage from a 2m-2nd stage and a 2m-3rd stage. Driving circuit. 32. The method of claim 31, The node controller provided in the 2m stage (m is a natural number) of the first stages, A first switching device for charging the first node with the first DC voltage source in response to a gate on voltage from a 2m-1 st stage and a 2m-2 st stage; A second switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from a 2m + 1th stage; A third switching element configured to discharge the first node to the second DC voltage source in response to a first AC voltage source charged in the second node; A fourth switching element that is turned on or off in response to a second alternating current voltage source charged in a second node of a 2m + 1th stage, and discharges the first node to a second direct current voltage source when turned on; A fifth switching element that is turned on or off in response to the second alternating voltage source and charges the second node with the second alternating voltage source when turned on; A sixth switching device configured to charge or discharge the second node to the second AC voltage source in response to a gate on voltage from a 2m + 1th stage; A seventh switching element configured to discharge the second node to a second DC voltage source in response to the first AC voltage source; An eighth switching device discharging the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; And And a ninth switching element configured to discharge the second node to a second DC voltage source in response to a start pulse from an external source or a gate on voltage from the 2m-1 stage and the 2m-2 stage. Driving circuit. 33. The method of claim 32, The node controller provided in the 2m-1th stage of the second stages, A first switching device for charging the first node with the first DC voltage source in response to a start pulse from an external source or a gate on voltage from a 2m-2nd stage and a 2m-3rd stage; A second switching element configured to discharge the first node to a second DC voltage source in response to a gate on voltage from a 2m-th stage; A third switching element configured to discharge the first node to the second DC voltage source in response to a first AC voltage source charged in the second node; A fourth switching element that is turned on or off in response to a second alternating current voltage source charged in a second node of a 2m-th stage, and discharges the first node to a second DC voltage source when it is turned on; A fifth switching element that is turned on or off in response to the second alternating voltage source and charges the second node with the second alternating voltage source when turned on; A sixth switching device configured to charge or discharge the second node to the second AC voltage source in response to a gate on voltage from a 2m-th stage; A seventh switching element configured to discharge the second node to a second DC voltage source in response to the first AC voltage source; An eighth switching device discharging the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; And And a ninth switching device configured to discharge the second node to a second DC voltage source in response to a start pulse from an external source or a gate on voltage from a 2m-2nd stage and a 2m-3rd stage. Driving circuit. 34. The method of claim 33, The node controller provided in the 2mth stage of the second stages, A first switching device for charging the first node with the first DC voltage source in response to a gate on voltage from a 2m-1 st stage and a 2m-2 st stage; A second switching element for discharging the first node to a second DC voltage source in response to a gate on voltage from a 2m + 1th stage; A third switching element configured to discharge the first node to the second DC voltage source in response to a first AC voltage source charged in the second node; A fourth switching element that is turned on or off in response to a first alternating current voltage source charged in a second node of a 2m + 1th stage, and discharges the first node to a second direct current voltage source when turned on; A fifth switching element turned on or off in response to the first alternating current voltage source and charging the second node with the first alternating current voltage source when turned on; A sixth switching element configured to charge or discharge the second node to the first AC voltage source in response to a gate on voltage from a 2m + 1th stage; A seventh switching element configured to discharge the second node to a second DC voltage source in response to the second AC voltage source; An eighth switching device discharging the second node to a second DC voltage source in response to the first DC voltage source charged in the first node; And And a ninth switching element configured to discharge the second node to a second DC voltage source in response to a start pulse from an external source or a gate on voltage from the 2m-1 stage and the 2m-2 stage. Driving circuit. In a driving method of a gate driving circuit comprising a plurality of first stages connected to one side of each gate line, and a plurality of second stages connected to the other side of each gate line, Simultaneously supplying gate-on voltages from the first and second stages connected to the same gate line to the gate line; And And supplying a gate off voltage from one of the first stage and the second stage to the gate line.

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