JPH09230308A - Display scanning circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce manufacturing cost, to eliminate the necessity of mounting an integrated circuit on a separated substrate and to increase reliabilty by using' a row selecting and driving circuit similar to the shift register. SOLUTION: A row selecting and driving circuit is divided into odd number stages and even number stages, and each stage has eleven transistors. The output r1 of the stage 1 is connected to the input of the stage 2 and also to the first row line ROW1 of the pixel array. The output r2 of the stage 2 is connected to the input of the stage 3 and also to the second row line ROW2 of the pixel array through a stage 240. All odd number atages receive the first, second and third clock signals, S1, o; S2,o; and S3,o respectively. All even number stages receive the fourth, fifth, and sixth clock signals S1,e, S2,e, S3,e respectively. The seventh clock signal S4 is connected to all stages. The eighth SDIN shift of the clock signal is connected to the first stage of the row selecting and driving circuit alone.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for an active matrix display device, and more particularly to a row selection drive circuit for driving a pixel row of a liquid crystal display (LCD) using a thin film transistor (TFT).

[0002]

BACKGROUND OF THE INVENTION Liquid crystal displays (LCDs) or similar devices usually use thin film MOS transistors, usually placed on a substrate, usually glass. Currently, almost all commercially available active matrix liquid crystal displays (AMLCD) are not scanned in that the scan signal is external to and used by the AMLCD.

Unscanned AMLCDs require one external lead for each column and row line. For example, a direct line interface driver for black and white 768 x 1024 XGA computer displays requires 1792 leads. The need for this large number of leads in the display drive is a serious problem that gets worse with increasing display resolution and complexity. Two major challenges are to reduce the number of input leads required and to "integrate" the drive circuitry on the display substrate.

US Pat. No. 5,034,735 discloses a driver using two transistors per pixel row for generating select and deselect signals and then addressing via a control gate. However, the scanning drive circuit and the signal drive circuit are suitable for the ferroelectric liquid crystal display,
Not suitable for T-LCD. U.S. Patent No. 5,157,386 refers to AMLCD
A circuit driven by K-bit video digital data is disclosed. The analog switch receives the video voltage and outputs the video voltage to each column when the analog switch is turned on by the control signal. This is not a circuit that selectively drives the display row.

US Pat. No. 5,113,181 discloses a display in which a data driver is used, but does not disclose a scan driver circuit. U.S. Pat. No. 5,313,222 discloses a selective driving circuit for LCD display which must be subjected to a large amount of electrical stress.

[0006]

It is an object of the present invention to reduce manufacturing costs and to increase reliability by eliminating the need to mount integrated circuits on isolation substrates. Another object of the present invention is to form a novel row select drive circuit which can be integrated directly on the display substrate, thereby providing a peripheral I
To reduce the cost of the mixed set needed for Cs and unscanned AMLCD.

It is another object of the present invention to overcome the long time constant due to the high series resistance of the thin film transistor by forming a new integrated row selection drive circuit in which the selection release time is short and the drive signal is full amplitude. To do. A further object of the invention is to reduce the power consumption of the row select drive circuit.

[0008]

These objects are achieved by using a row select drive circuit similar to a shift register. Each row select drive circuit activates a row of pixels. The row selection drive circuit is disposed on the glass substrate of the pixel. The output of each row select drive circuit is connected to the corresponding pixel row line and to the next row select drive circuit as an active input. These row select drive circuits continuously activate pixel rows. The switching device, which is external to the display device, has leads connected to the row select drive circuit and the number of leads is much less than the number of pixel rows. Each of the row select driver circuits comprises a number of thin film transistors formed on the display substrate and interconnected to provide continuous activation of each pixel row.

The first row select driver circuit stage activates the first pixel row for a first predetermined period. The second adjacent row select drive circuit activates the consecutive pixel rows for the second predetermined period before the end of the first predetermined period so that a longer row select time is provided for each row and the corresponding pixel row. To charge or discharge the pixels. Thus, a faster deselect time is achieved to overcome the slow time constant due to the high series resistance of the thin film transistors.

[0010]

Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiment with reference to the accompanying drawings. The present invention is described by way of example for a 384 × 240 pixel array color TV. FIG. 1 shows the row selection drive circuit of the present invention, which includes the row selection drive circuit of the present invention. The upper block in FIG. 1 shows an external drive system, which comprises, for example, the circuitry, sample and hold of the control logic signal generator for the display. The display device is shown as a block at the bottom of FIG. The block labeled "row select driver" represents the invention and is shown only coupled to the first two rows and the last row of the pixel matrix array.

A first preferred embodiment of the row select drive circuit of the present invention is shown in FIG. 2, where all input and power supply signals are provided by an external drive system from that shown in the upper block of FIG. . The row select driver circuit is shown only on one side of the display device of FIG. 1, but comprises a second identical row select driver circuit connected to the pixel row lines on the opposite side of the display device. Should be noted. This second row select drive circuit provides circuit redundancy and enhances circuit diagnostics when repair is required.

In the row selection drive circuit for this embodiment,
As shown in FIG. 2, there are 240 identical circuit stages. Each drive circuit stage is indicated by a dotted rectangle and is labeled via stage 240 as stage 1, stage 2 and stage 3. All stages are identical except that the input of each stage is connected to the output of the previous stage.

The focus of this embodiment is specifically focused on reducing the number of external lead connections to the row drive circuit from a number such as 240 to 11 in the example used. The circuit has poor performance characteristics such as low mobility, inhomogeneous threshold voltage and threshold voltage shift, and solves the problem of using thin film transistors that can be placed directly on the glass substrate.

As shown in FIG. 2, the row select drive circuit is divided into odd and even stages, each stage having 11 transistors. The output r1 of stage 1 is the input to stage 2 and the first row line ROW1 of the pixel array.
Connected to. The output r2 of stage 2 is connected to the input of the stage and to the second column line ROW2 of the pixel array and via stage 240. All odd stages receive the first, second and third clock signals S1, o, S2, o, S3, o, respectively. All even stages receive the fourth, fifth and sixth clock signals S1, e, S2, e, S3, e, respectively. The seventh clock signal S 4 is connected to all stages. The eighth SDIN shift of the clock signal is connected only to the first stage of the row selection drive circuit. All stages have two common ground (or negative electrode supply) VSS and VSS1 and common positive electrode supply VC
Connected to C. The reason for having two grounds is to separate the output device ground VSS of each stage from the second ground VSS1 to provide noise immunity to the output. Thus 11 input leads, namely S1, o, S2, o, S3, o and S1, e, S2,
e, S3, e, S4, SDIN, VCC, VSS and VSS1 are connected from the external drive system to the row select drive circuit of the display device. 11 control leads have 240 row select drive circuits,
It will be seen that it only needs to be controlled, as described below. If the output interference of each stage is VSS1
And only 10 control leads are required, if not critical due to VSS coupling. Separate power supply lines, VSS and VSS1, are used in this embodiment.

Referring again to FIG. Each driver circuit stage comprises a transistor M1 and a transistor M2, which are connected in series between the power supply VCC and the negative power supply VSS1, with the gate of M1 at the odd stage S1, o clock signal and at the even stage S1. , e connected to the clock signal, and the gate of M2 serves as the input terminal of the special stage.
Transistor M5 and transistor M4 are connected in series between VSS1 and S2, o clock signals of odd stages, and are connected to S2, e of even stages, the gate of M4 is connected to the input terminal, and the gate of M5 is M1 and M2. Is connected to the common node between them, is also connected to the drain and gate of the transistor M3, and the source is connected to VSS1. Transistors M7 and M6 are connected in series between the negative electrode supply VSS and the even stage S3, o clock signals and to the even stage S3, e clock signals, and the gate of M7 is connected to the common node between M1 and M2. The gate of M6 is connected to the common node between M4 and M5, and the common node between M7 and M6 is connected to the low output and input terminal of the next stage. The transistors M11 and M10 are connected in series between the negative power supply VSS1 and the S1, o clocks for the odd stages and to the S1, e clock signals for the even stages, the gate of M11 is connected to the input terminal, and M11 and M10 are connected. The common node of M10 is connected to the gate of transistor M8, and its drain and source are connected in parallel to the drain and source of M7. Transistor M9 has its gate connected between the gate of M10 and the low output of the next stage, and to clock signal S4.

The row select driver circuit is preferably made of a thin film transistor (TFT) on the display substrate to generate the scan signal for the display to turn on and off the select row of the pixel transistor. The waveforms of the control clock signal and the signals at the internal and output nodes are shown in FIG. The clock signals S1, o, S1, e S2, o S2, e S3, o S3, e have a period that is twice as long as the scan line period, and S4 has a scan line period. The input shift of the signal SDIN has a frame period. Using the NTSC system as an example, the scan line time width and frame time width are about 63us and 16.67ms, respectively.
It is. The output of each stage is, as shown in FIG.
Connected to low on display pixel gate line.

Video information (or other means of input signals for display) is provided to the system of FIG. 1 one row at a time. As those skilled in the art will recognize, the low mobility (eg, high resistance) pixel capacitance charge and discharge times of the thin film transistor of FIG. 2 are shown via TFTs, effectively reducing the row select time. To achieve a longer row select period to charge or discharge the pixel capacitance, the next adjacent row is activated before the activation of the previous row is eliminated. However, only one line of information is given in one period. This is because only one pixel row is locked during any given horizontal line period. This operation is called "line preselection". The benefit of the 0-select drive circuit is to reduce the number of external lead selects. In this embodiment, the number of lead connections is reduced from 240 to 11 for the select driver only. This reduction in leads is then significant in simplifying display assembly and packaging. Although the novel circuit of this embodiment requires 11 transistors per stage, the transistors are relatively small and easy to fabricate on a substrate such as glass. As a result, manufacturing costs are reduced due to a significant reduction in lead connections and less external drive chips.

As shown in the timing diagrams of FIGS. 2 and 3, the start of operation extends from t0 to t1. Initialization pulse of S1, o, S1, e clock signal is a transistor in all stages
Turn on M1, which causes all nodes a1, a2, ... a2
40 is charged to a high voltage (logical "1") level around VDD or VCC, where VDD is the positive amplitude of the S1, o and S1, e signal pulses. At this moment, all nodes a1, o, a1, o, ... a2
40 makes all the transistors M5 and M7 conductive, and all the nodes b1,
b2, ... b240 and all output nodes r1, r2 ... r240 have common ground levels VSS1 and VSS (low voltage or logical "0" level)
Until each is discharged. Therefore, all the scan lines for the first row line ROW1 via the last row line ROW240 are discharged to the VSS level at the beginning of the operation. However, these initialization pulses have been shown to be selective.

As long as the output node is at a low voltage level, the voltage variation at node d of the same stage has no effect on the corresponding output because the drain (source) of M8 is in common with the drain (source) of M7. . It is assumed that the positive (negative) amplitude for each black signal is equal to VDD, where VDD is equal or close in magnitude to VCC. Any clock signal pulsing after t1 and before t2 has no effect on the output node because nodes a 1 and b 2 remain high and low, respectively, during this period. At time t2, the SDIN shift of the signal is pulsed high, turning on M2, M4 and M11 of stage 1.
By turning on M2, node a1 is discharged to the VSS1 level, while node a2 via a240 remains at the high voltage level. Node b1 remains at the low voltage level because M4 of stage 1 is conducting and S2, o is at the low voltage level at t2. Node d1 is at a low voltage level at t2 because M11 is on.

At t3, the signal S1, o is pulsed high, turning on M1 of all odd stages. M1 and M2 conduct in stage 1 and node a1 is charged to an intermediate voltage level between VDD and VSS1, depending on the dimensional ratio of the transistors of M1 and M2. Signal S2, o is pulsed high at t4 and node b1 goes to the intermediate voltage level if node a1 (at the intermediate voltage level) at this time is large enough to turn on M5 of stage 1. Be charged. In any event, the potential of node b1 at this point in time has no effect on the operation of the circuit because signal S3, o is at a low voltage level.

At t5, the signals S1, o return to a low voltage level, turning off M1 in stage 1, node a1 is discharged to a low voltage level, turning off M5. Next, node b1 is charged to the high voltage level because M4 is still on and S2, o is at the high voltage level. Thus, node b1 is pulled up at t5 to a logical "1" level. At t6, this signal S3, o
Is raised to VDD level, which causes the output node r1 to be charged to a high voltage level (logical "1"). Node r1
During the period when is at a logical "1" level, all pixel transistors in row 1 of the pixel array in Figure 1 are on. The transistor M11 in stage 1 is connected to the node d1.
, At node d1 at a logical "0" level, is used to hold T6 during the transition of output node r1.

Immediately after r1 is charged to a logical "1" level, M2 and M4 of stage 2 turn on and node a2
Discharged to the VSS1 level, node b2 remains at the low voltage level because S2, e is at the low voltage level. From t3 at t7
After a scan period of 63 us, the signal S1, e is pulsed high, turning on M1 of all even stages. At this moment, M1 and M2 of stage 2 are conducting (because the output node r1 of stage 1 is at a logical "1" level), node a2 is charged to an intermediate voltage level and resembles node a1 at t3. . Signal SDIN
Returns to the low voltage level at t7 and is arbitrarily selected. This is because it is synchronized with the special pulse of S3, e between t2 and t7, as shown in FIG.
And M4 are turned off, nodes a1 and b1 are still at the low and high voltages, respectively, and thus have no effect on output node r1. SDIN falling edge is t6 at any time
, And t9 can be designed to occur without affecting node r1.

At t8, after the scanning period of 63us from t4, signals S2, e
Is pulsed high and node b2 is charged to an intermediate voltage level, similar to node b1 at t4. The signal S2, o returns to the low voltage level at t9 and has no effect on node b1 until M4 is already off at t7. The signals S1, e return to the low voltage level at t10, turning off M1 in stage 2, which causes node a2 to discharge to the low voltage level (because output node r1 is at a logical "1" level), Then turn off the M5 of Stage 2. Node b2 has stage 2 still on,
Since S2, e is at a high voltage level, it can be charged to a high voltage level. b2 is high and Stage 6 M6 turns on at t10.

At t11, the signals S3, e are raised to the VDD level. S3, e is high, M2 of stage 2 is on, and output node r2 is pulled to a logical "1" level. node
During the period when r2 is at the logical "1" level, all pixel transistors in the second row line ROW2 of the pixel array of FIG. 1 are on. M11 on stage 2 is a node
It turns on for the purpose of holding d2 at a logical "0" level at t11 during the transition of output node r2. t1
At 1, both output nodes r1 and r2 are at a logical "1" level, as desired.

At t12, signal S4 is raised to a logical "1" voltage level, turning on M9 in stage 1 and node
c1 is pulled to a high voltage level, while output node r2 is at a high voltage level. Node c1 is high and stage 1 M10 is on. At t13, 126us after t3 (or twice the scan line time), the signal S1, o is re-pulsed high and node d1
Are charged to a logical "1" level, turning on Stage 1 M8. If S1, o is high at t13, M1 of all odd stages will be on. Since M1 and M2 of stage 1 are turned on and off respectively at t13, node a1 is pulled to a logical "1" level, turning on M3, M5 and M7 of stage 1. Turning on M5 of stage 1 discharges node b1 to a low voltage level. The signal S3, o is t1
Can be returned to a low voltage level of 3. Stage 1 M7 and M8
Is turned on at t13, the output node r1 is discharged to VSS level at t13. The high-speed deselection operation for the first row line ROW1 is performed at this moment. M3 is connected to allow an appropriate bias voltage to be applied to M5 and M7 of the same stage during the non-selected period of the corresponding row line.

Immediately after the output node r2 is pulled to the logical "1" level at t11, M2 and M4 of stage 3 are turned on, which causes node a3 to be discharged to VSS1.
b3 remains at the low voltage level because S2, o is at the low voltage level. Similar to stage 1, S1, o is pulsed high to t13 so that M1 turns on while M2 conducts in stage 3, thereby charging node a3 to an intermediate voltage level. The signal S2, o is re-pulsed high at t14, which is 126u (or twice the scan line time) after t4.
B3 is charged to the intermediate voltage level and again resembles the operation that occurs in stage 1 at t4. As output node r1 is pulled to a logical "0" level, M2 and M4 of stage 2 are turned off. At t15, the signal S2, e returns to a low voltage level, and due to M4 of stage 2 there is no effect on node b2,
It is already off at t13.

At t16, the signals S1, o return to the low voltage level,
Turning off M1 in stage 3, this causes node a3 to be discharged to a low voltage level because the output node is at a logical "1". If node a3 is at a logical "0" level, then stage 5 M5 is off, and node b3 is
Since M4 of stage 3 is turned on and S2, o is at the high voltage level, it is charged to the high voltage level. The signal S3, o is
It is raised to VDD level at t17 and 126us after t6. Again, the sequence of operations is similar to that occurring at the output node r1 of stage 1 at t6. Therefore, the output node r3 is shortly after S3, o is pulsed high to t13,
You are drawn to a logical "1" level. During the period when the output node r3 is at the logical "1" level, all pixel transistors in the third row line ROW3 of the pixel array of FIG. 1 are turned on. The high voltage level turns on M11 in stage 3 at output node r2, which causes node d3
At t13, during the changing period of the output node r3, a logical "0" is given.
Hold on level. Both output nodes r2 and r3 are at the high voltage level at t17.

At t13, similar to the selective removal operation for the first row line ROW1, the second and third lines ROW2 and ROW3 are
At t18 and t19, they are selectively removed. As seen so far, the timing sequence of the clock signals S1, e, S2, e and S3, e during the period between t6 and t18 for stage 2 is S1, in stage 1 during the period between t2 and t13.
It has not only the same characteristics as o, S2, o and S3, o, but also the same characteristics as stage 1 (only for one scan line time delay). Similarly, the same operation sequence ha, t11
And t2 and t1 due to stage 3 in the time motion between t19 and t19
Performed as per Stage 1 for a period of 3 (only for 2 scan line time delays).

Each successive row select drive circuit stage operates similarly to the output of the stage prior to providing stage 1 with an equivalent "change" in signal similar to the input signal SDIN. All successive stages remain in the off condition (logical "0" level) until they receive a high output signal from the previous stage. Therefore, the drive circuit and the clock signal during the remaining frame time continuously shift the selection and deselection of the scan line ROW4 via 240 as before.
The dummy stage (not shown) has an output node r241,
It can be added to connect to the drain electrode of M9 in stage 240 without connecting to the pixel array. The drain electrode of M9 of the dummy stage may be connected to VSS1.

As will be appreciated by those skilled in the art, only the first frame of display information after power is turned on is normally ignored because it is pulsed very quickly and does not adversely affect the display output. It should be noted that Therefore, the initialization pulses of S1, o and S1, e are
Since the output nodes are all at low voltage levels and all other nodes are at known stages, just at the end of the first frame, and at the beginning of the first frame, without the S1, o and S1, e initialization pulses. , Not needed. Note that FIG. 3 only shows a timing diagram for the first few scan lines of a frame.

A second preferred embodiment of the invention is shown in FIG. 4, which is an exact copy of the previous embodiment, except that the drain of M1 in each stage is connected to the gate of the same transistor. except. In other words, the drain is S
Depending on the odd or even stage, either the 1, o or S1, e clock signal, the power supply VC as shown in FIG.
Connected instead of C. In this way, one less external lead, i.e. 10 leads, is used in the second embodiment compared to the 11 leads for the previous embodiment, thus simplifying assembly and packaging. Furthermore, the circuit performance is
Whenever M1 is on, it is not sacrificed because the drain of M1 is at a high voltage level and the drain behaves as if it were connected to VCC. Node a is
If M1 is off, it is unaffected by the drain voltage on M1. Therefore, the output waveform produced by the circuit in FIG. 4 will necessarily be the same as that produced by the circuit shown in FIG.

As shown in FIG. 5, according to the third aspect of the present invention.
The row select driver circuit of the preferred embodiment of is divided into odd and even stages, each stage having only six transistors. The output of stage 1, R1 is the stage 2
, And to the first row line ROW1 of the pixel array. The output of stage 2, R2, is connected to the input of stage 3 and to the second row line ROW2 of the pixel array, and via stage 240. All odd stages have first, second and third clock signals S1, o, S2, o, S3, o
Receive each. All even stages receive the fourth, fifth and sixth clock signals S1, e, S2, e, S3, e, respectively. SD
The IN shift-in signal is connected to the first stage only.
All stages are connected to two common ground (or negative power supplies) VSS and VSS1 and a common positive power supply VCC. Thus, unlike the first preferred embodiment, 10 input leads,
That is, S1, o, S2, o, S3, o, S1, e, S2, e, S3, e, SDIN,
Only VCC and VSS1 are from an external system connected to the row select drive circuit of the display. Only these 10 control leads are used to control the 240 row select drive circuit.

Each row select driver circuit stage comprises a transistor M1 and a transistor M2 which are connected in series to a positive power supply VCC and a negative power supply VSS1, the gate of M1 being the S1, o clock signal for the odd stages and Connected to the S1, e clock signals for the even stages, the gate of M2 acts as an input terminal. Transistor M3 and transistor M4 are connected in series between the positive power supply VCC and the input terminal, the gate of M3 is connected to the S1, o clock signal for the odd stages and the S1, e clock signal for the even stages, and the gate of M4 is It is connected to the S2, o clock signal for the odd stages and the S2, e clock signal for the even stages. The transistors M6 and M5 are connected in series between the negative power supply VSS and the odd stage S3, o clock signal and the S3, e clock signal for the even stage,
The gate of M5 is connected to the common node between M3 and M4, the gate of M6 is connected to the common node between M1 and M2, and M5 and M6.
The common node between is connected to the low output and the input terminal of the next stage.

The control clock signals and signals at internal and output nodes are shown in FIG. As with the previous embodiment, the clock signals S1, o, S2, o, S3, o, S1, e, S2, e, S3, e
Has a period that is twice as long as the scan line time, and the shift-in signal SDIN has a period equal to the frame time. As mentioned earlier, the scan line time width and frame time width are each approximately 63us in the NTSC system.
And 16.67ms. The next adjacent row is activated to achieve a longer row selection period to charge or discharge the pixel capacitance before the activation of the previous row is eliminated.

As shown in the timing diagrams of FIGS. 5 and 6, at t0, signal S3, o is pulsed low and signal S1, o is pulsed high to drive all odd stages M1 and M3. Turn on, which causes all odd nodes a1, a2, ... a239 and b1, b
2, ... b239 is charged to a voltage level of approximately VDD-Vt (logical "1"), where VDD is the amplitude of signal S1, o, Vt
Is the threshold voltage of the transistor. At this instant, nodes a and b in all odd stages cause M5 and M6 to conduct, and all odd row scan lines have VSS and VSS1 at S3, o at t0.
Since it is at the same ground level as, it is discharged to the common ground level (logical "0"). It should be noted that the positive swing for each clock signal is assumed to be equal to VDD which can be approximately equal to VCC.

At t1, S2, o is pulsed high to turn on M4 of all odd stages, and the input signal SDIN is at a logical "0" level, which causes node b of all odd stages to VDD and Discharge to an intermediate voltage level between VSS. All odd-numbered stages of M3 are conducting at this moment. The level of the intermediate voltage level depends on the size of the M3 and M4 transistors. Node b in all odd stages returns to the logical “0” level immediately after S1, o returns to the logical “0”,
On the other hand, S2, o remains high.

At t2 delayed by 63us from t0, S1, e is pulsed high and S3, e is pulsed low. At t3, the signal S2, e is pulsed high. These timing sequences for even stages are
Not only the same waveform as the pair of S1, o, S2, o and S3, o, but also
It has the same operation as odd stage in to and t1. From t0 to t3, the change of node b in all stages is that only when node b is high and the corresponding S3, o and S3, e are at ground level, M5 of all stages is only turned on during the period. , Has no logical effect on the output waveform.

At t4, the shift-in signal SDIN is pulsed high, turning on M2 of stage 1, which causes node a1
Is discharged to the VSS1 level which is a logical "0", while a
2, a3, ... a240 remain high. Then, at t5, S1, o is pulsed high to turn on M1 and M3 in all odd stages, pulling node a1 to an intermediate voltage level and node b in all odd stages to a high voltage level. To do.
Since S3, o is a low voltage level at t5, the output nodes R1, R
3, ... R239 remains low.

The odd nodes b3, b5, ... B239 are at an intermediate voltage at t6, both S1, o and S2, o are at a logical "1" level, and the output node of the previous stage is at a ground level. Due to the fact that the odd stages M3 and M4 turn on. However, the M4 on stage 1
Since SDIN is high and bi remains at the high voltage level,
Turn off. At t7, S1, o returns to a logical "0" and then the odd nodes b3, b5, ... B239 return to a low voltage level. This is because M3 is off and M4 is still on in all odd stages, except for stages. At this moment, b1
Remains high because both M3 and M4 in stage 1 turn off, and node a1 returns to a low voltage level due to the coupling effect of turning M1 off and M2 on.

At t8, S3, o is raised to the VDD level, and only node b1 is at the logical "1" level and M5 of stage 1
Can be turned on so that the output node R1 is pulled up all the way to the VDD level, while b2, b3, ... B240 are all at a logical "0" level. During the period when the output node R1 is at the logical "1" level, all pixel transistors in the first row line ROW1 of the pixel array of FIG. 1 are turned on. Immediately after the output node R1 is charged to VDD, the logical "1" level that turns on M2 of stage 2 is discharged to the VSS1 level.

At t9, after a period of t5 to 63us, S1, e is pulsed high to turn on M1 and M3 of all even stages. At this moment, if M1 and M2 of stage 2 conduct (because the output node R1 of stage 1 is still at the logical "1" level), node a2 is charged to the intermediate voltage level. If M3 turns on and M4 turns off in all even stages, node b in all even stages will be charged to a high voltage level (logical "1"). Again, similar to the odd stage at t5, the output nodes of all even stages remain at the low voltage level because M5 of all even stages are turned on and S3, e is at the low voltage level at t9.

The even nodes b4, b6, ... B240 are discharged to the intermediate voltage at t10, due to the fact that S1, e and S2, e are at a logical "1" level, M3 of the even stage. as well as
M4 turns on, while on stage M4 turns off. The output node R1 of stage 1 is at a high voltage level,
Therefore, b2 remains at the high voltage level. At t11, the signals S1 and e return to the logical “0” level, and the nodes b4, b6,
... b240 is discharged at a low voltage level because M3 is off and M4 is still on in all even stages. However, stage 2 is excluded. At this moment node a2 of stage 2 is discharged to VSS1 because M1 is off and M2 is still on due to the high R1. Node b2 remains high as stage 2 M3 and M4 are turned off.

At t12, similar to stage 1, the signal S3, e
Is raised to VDD level. Since only b2 between all even b-nodes is at a logical "1" level, M2 of stage 2 is turned on and the output node R2 is charged to a logical "1" level. The high R2 level then turns on all pixel transistors in the second row line ROW2 of the pixel array of FIG. Note that at t12, the output nodes R1 and R2 are at the desired logical "1".

Immediately after the output node R2 of stage 2 is at the high voltage level, node a3 of stage 3 is discharged to the low voltage level. At t13, and 126us after t5, S1, o is pulsed high again, turning on M1 and M3 of all odd stages.
If all odd stages have M1 turned on, node a1
Is pulled up to a high voltage level because M2 is off in stage 1 and node a3 is charged to an intermediate level because M2 in stage 3 is on and nodes a5, a7 ,.
39 remains at the high voltage level. The sequence of operations that follows in stage 3 is similar to the operation performed in stage 1 126us before.

At t13, signal S3, e is pulsed low, nodes b1 and a1 are at a logical "1" level, and M5 and M6
Turning on, the first row line ROW1 discharges to a logical "0" level, thus deselecting ROW1 at this moment. Similarly, ROW2 is deselected at t14. As with the previous embodiment, each next row select drive circuit stage
It behaves similarly to the output of the stage before applying an equivalent "shift-in" signal to stage 1 which is similar to the signal SDIN. All successive stages remain in the off condition (logical "0" level) until they receive a high output signal from the previous stage. Therefore, the drive circuit and the clock signal during the remaining frame time shift the selection and deselection of the scanning line ROW4 continuously through 240 as described above.

FIG. 7 illustrates a fourth preferred embodiment of the present invention. The additional transistor M7 is connected in parallel with M6. The gate of M7 for each odd stage is connected to S1, o and the gate of M7 for each even stage is connected to S1, e. Transistor M7 is used to pull down the rowline faster if a faster deselect time for the pixel rowline is desired. This is seen at t13 when M7 is added on M5 and M6 and turned on, discharging node R1 faster. Similarly,
Stage 7 M7 helps output node R2 discharge faster due to t14. Each stage in FIG. 7 has seven transistors.

Another concern with the embodiment of FIG. 5 is that when the next stage M4 is turned on by either S2, o or S2, e, the output node goes low by turning M6 on. That is, it is possible to experience a disturbance while being held at the voltage level. This is not desirable because it allows any disturbance on the row select lines to couple to the pixel electrodes. When the noise peak voltage is extreme above the threshold voltage of the pixel transistor, the pixel transistor turns on too early. One way to address this problem is to make the M6 transistor size larger than the M4. However, achieving very large dimensional proportions is sometimes impractical.

A fifth preferred embodiment of the present invention which overcomes this noise problem is shown in FIG. Two or more transistors M8 and M9 are added to the circuit of FIG. Instead of connecting the output row line directly to M2 and M4 of the next stage, the new node c has the same logical waveform as the output node R of the same stage, as shown in FIG. 8
Used to connect to the next stage, as shown in. As seen in FIG. 8, M8 (M9) is a parallel connection of M5 (M6), except that the common node c of M8 and M9 is separated from the common node R of M5 and M6. Therefore, node R can be shielded from noise at node c. In this way, the noise at node c does not affect the pixel electrodes in the row line because node c is not connected to the pixel row. Every stage of the drive circuit shown in FIG. 8 has eight transistors.

FIG. 9 illustrates a sixth preferred embodiment of the present invention, which combines the features of the fourth and fifth embodiments.
Thus, an improved noise immune output with faster deselection time can be obtained for the embodiment of FIG. 9 with 9 transistors. FIG. 10 shows a seventh embodiment of the present invention,
This uses the same input signal to produce an output waveform similar to the circuit shown in FIG. 4th and 7th
The only difference between the examples is the connection of M3 and M4. node
The output produced by the a and the embodiment of FIG. 10 is similar to that of the embodiment of FIG. However, the waveform of the node b at each stage of the embodiment of FIG. 10 deviates from that of the embodiment of FIG. This can be seen in stage 1, as an example. Node b1 is S as described in one of the previous paragraphs
Instead of t5 while 1, o is pulled high, t2 while S2, o is pulled high is pulled high for the circuit of FIG. t13 '
At 126us after t6, node b1 is discharged to a low voltage because SDIN is at a low voltage level and S2, o is pulsed high again at this moment. Since b1 is at the logical "1" level between t6 and t13 ', the output node R1 is
Pulsed high during the time between t8 and t13, which is similar to that described previously. Similarly, stage 2 operates similarly except it is delayed by 63us. Further, stages 3 to 240 are similarly continuously operated.

Transistor M4 at each stage in the embodiment of FIG. 10 is used to hold node b at a logical "0" level so that any coupling effect cannot affect node b. This can be demonstrated using stage 1 again, as an example. Node a1
Outside the period of t4 and t13 ', while node B1 is at the high voltage level that turns on M4, node b1 can be maintained at a low voltage level so that any coupling signal to node b1 will cause an output node
It is possible to affect R1 and it will be deleted. The noise appearing at the output node R when M6 of the current stage and M4 of the next stage are turned on at the same time, as in the embodiment of FIG. 7, is because if the output node is connected to the input of the next stage. For example, it can be eliminated in the circuit of FIG.

FIG. 11 shows an eighth preferred embodiment of the present invention. In this embodiment, transistors M8 and M9 are shown in FIG.
Added to each stage of the circuit to eliminate any disturbance to the output node when at high voltage levels.
This can be demonstrated by the operations described below. t10
Finally, S2, o is pulsed to a high voltage level. This is not preferable because the output node R1 can be disturbed, the node b2 is at a low voltage level, and the output node R1 is at a low voltage level just before t10. Therefore, M8 and
M9 is added to each stage of the circuit to shield the output node from noise.

FIG. 12 will be described. To further improve the performance of the eighth preferred embodiment, the ninth embodiment is proposed. As shown, a special M10 is added to each stage of the circuit shown in FIG. Transistor M10 is
Ensure that node c at each stage can be pulled to VSS1 level under all conditions. M10 is connected in parallel with M9, except that its gate is connected to node c of the stage adjacent to the next stage. In this way, by way of example, node c1 can certainly be pulled to VSS1 when node c3 is pulled to a high voltage level. Similar explanations apply to stages 2 to 240. Two dummy stages (not shown) have nodes 241 and c242 connected to the gates of M10 of stages 239 and 240 and may be added to this embodiment.

In practice, the power supply VCC, the high voltage VDD of the clock signal and the negative power supply (ground line) VSS and VSS1 should all be regulated by the data drive scheme.
For example, if the column reversal scheme is used, the polarity of the data voltage is reversed in alternating frames to produce an alternating current (a
c) When the drive signal is affected, VCC is 10 and 25
It should be selected between volts and the ground line voltage level should be between 0 and -10 volts. All ground lines, VSS and VSS1, are not preferred and are kept isolated from each other to reduce any noise injected by the circuit.

As will be appreciated by those skilled in the art, the pulse widths of different control and clock signals will vary depending on the timing budget of operation, device characteristics and thin film transistor dimensions.
Is determined by TFT dimensions should be optimized to meet performance requirements. The operation of the row select drive circuit of the disclosed embodiment is 63us for a 384 x 240 pixel array display that interferes with the NTSC television system in the above paragraph.
Of scan line time intervals. Other embodiments and timing schemes may be used without departing from the inventive concept. For example, displays other than television or with greater or lesser resolution may be incorporated within the scope of the invention.

Given that all key timing and voltage level clock signals are derived from external ICs, the present invention provides the convenience and flexibility of optimizing the display system. Moreover, because of the simplicity of operation of the present invention, the row select drive circuit integrated on the display substrate should lead to a good production profit. Thus, the present invention is for use in a display device, which comprises a substrate having a first number of pixel columns and a second number of pixel columns.
Contains a number of pixel rows. The present invention comprises a plurality of row select drive circuits, which correspond to the number of pixel rows,
And continuously energize the pixel rows. Row select drive circuits are disposed on the display substrate, and each circuit produces an output that is electrically connected to the corresponding pixel row and to the continuous row select drive circuit as an active input. Each row selection driving circuit includes a plurality of thin film transistors formed on a display substrate, usually glass, and connected to each other to provide continuous activation of each pixel row.

As previously described, the first select driver circuit stage activates the first pixel row for the first predetermined period. The second adjacent row select drive circuit stage provides a longer row precursor time for each row by activating the next pixel row for the second predetermined period before the end of the first predetermined period. Charge or discharge the pixels in the corresponding pixel row.

A novel row select drive circuit for a display device, particularly an LCD display, has been disclosed. This employs a thin film transistor that can be placed as glass on the substrate, along with a display TFT array, and also substantially reduces the number of low drive input leads from some predetermined number, such as 240 in the example given here. Reduce to as low as 10 lines. Thus, the benefit of the disclosed drive circuit is to reduce the number of external lead connections and to significantly solve the display (such as AMLCD) assembly and packaging problems due to connector pitch limitations. Further, the number of the drive ICs for driving the row lines is reduced.

Although the present invention has been described in relation to what is considered to be the most practical and preferred embodiments, it is not limited to the disclosed embodiments but is within the spirit and scope of its broadest interpretation. It is intended to cover a wide variety of configurations and includes all variations and equivalent configurations.

[Brief description of drawings]

FIG. 1 is a block diagram of a display system in which a row selection driving circuit of the present invention is used.

FIG. 2 is a schematic diagram of a first preferred embodiment according to the present invention.

3 is a timing diagram of inputs and outputs to the circuit of FIG.

FIG. 4 is a schematic diagram of a second preferred embodiment of the present invention.

FIG. 5 is a schematic diagram of a third preferred embodiment according to the present invention.

6 is a timing diagram of inputs and outputs of the circuit of FIG.

FIG. 7 is a schematic diagram of a fourth preferred embodiment according to the present invention.

FIG. 8 is a schematic diagram of a fifth preferred embodiment according to the present invention.

FIG. 9 is a schematic diagram of a sixth preferred embodiment according to the present invention.

FIG. 10 is a schematic view of a seventh preferred embodiment according to the present invention.

FIG. 11 is a schematic view of an eighth preferred embodiment according to the present invention.

FIG. 12 is a schematic diagram of a ninth preferred embodiment according to the present invention.

[Explanation of symbols]

 S1, o, S2, o, S3, o, S1, e, S2, e, S3, e ... Clock signal SDIN ... Shift-in clock signal VCC ... Positive power supply VSS, VSS1 ... Ground

Claims (9)

[Claims] 1. A liquid crystal display (LCD) is a picture element (pixel).
A circuit for use in a liquid crystal display (LCD) comprising a matrix of ones arranged on a substrate in a first number of pixel columns and a second number of pixel rows, the pixels corresponding to the number of pixel rows A plurality of row selection drive circuits for electrically energizing rows, the row selection drive circuits being disposed on an LCD display substrate,
Each output of the row select drive circuit is connected to a corresponding one of the pixel rows and to the next one of the row select drive circuits as an active input; external to the LCD display, and Switching means for supply, having leads electrically connected to the row selection drive circuit, and: first three clock signals S1, for all odd rows having a duration of twice the horizontal scanning time of the display. o, S
2, o, S3, o, and second three clock signals S1, e, S2, e, S3, e for all even lows that delay the first three clock signals by the horizontal scanning time, respectively, A shift-in clock signal SDIN coupled to only one first input terminal of the selection driving circuit, the first three clock signals, the second three clock signals and the shift-in clock signal are low-selected. A circuit characterized in that each pixel row is continuously energized by providing an output from each of the drive circuits. 2. The switching means further supplies a clock signal S4 having a period equal to the horizontal scanning time to all the row selection drive circuits.
Circuit. 3. The circuit of claim 1, wherein the number of leads from the switching means is less than the number of pixel rows. 4. The circuit of claim 1, wherein each of the row select drive circuits comprises a plurality of thin film transistors connected together to provide successive activation of each pixel row. 5. A first row select drive stage for activating a first pixel row for a predetermined period; and a longer row select time each for activating a next pixel row for a second predetermined period. The circuit of claim 4, characterized by a second adjacent row select drive stage provided in the pixel row for charging or discharging the pixel of the corresponding pixel row. 6. The substrate is glass,
The circuit according to claim 1. 7. The clock signal S2, o is delayed but partially overlaps, has a wider pulse width than the clock signals S1, o, and the clock signal S3, o is delayed but partially overlaps, and the clock signal S2, o is delayed. characterized by having a wider pulse width than
The circuit according to claim 1. 8. The clock signals S3, o, S3, e are of opposite polarity to the clock signals S1, o, S2, o, S1, e and S2, e. 7. The circuit according to 7. 9. The output signal from each of the row select drive circuits energizes the corresponding pixel row and acts like a shift signal for the next one of the row select drive circuits. The circuit according to 1.