KR101213828B1 - Hybrid Gate Driver for Liquid Crystal Panel - Google Patents

Abstract

A hybrid gate driver suitable for enlarging the display area of a liquid crystal panel while supplying a scan signal of sufficient power to the gate line is disclosed.

In the hybrid gate driver for the liquid crystal panel, the plurality of shift stages are respectively corresponded to the plurality of gate lines on the liquid crystal panel and connected in dependence on the start pulse. Each of the shift stages includes a pull-down transistor that pulls down a voltage on a corresponding gate line; A pull-down transistor that pulls up a voltage on a corresponding gate line and has a shorter channel width than the pull-up transistor; A pull-up driver for driving the pull-up and pull-down transistors in opposition so that a voltage on the corresponding gate line is pulled up in response to a scan signal from a previous shift stage; And a pull-down driver for driving the pull-up and pull-down transistors in opposition so that the voltage on the corresponding gate line is pulled down in response to a scan signal from a next shift stage.

Accordingly, pull-up transistors are formed on the liquid crystal panel in the form of rods, thereby reducing the occupied area of the hybrid gate driver. As a result, the image display area of the liquid crystal panel can be expanded.

 Liquid crystal panel, gate line, shift, driver, channel width, footprint.

Description

Hybrid gate driver for liquid crystal panel

In order to better understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a view schematically illustrating a liquid crystal display including a hybrid gate driver according to an exemplary embodiment of the present invention.

2 is a block diagram schematically illustrating a hybrid gate driver according to an exemplary embodiment of the present invention.

FIG. 3 is a detailed circuit diagram illustrating the shift stage in FIG. 2 in detail.

4 is a waveform diagram illustrating characteristics of a scan signal output by the shift stage of FIG. 3.

DESCRIPTION OF THE REFERENCE NUMERALS to the main parts of the drawings "

10: downloading control module 12: color filter substrate

14 thin film transistor array substrate 20 gate driver

22: pull-up driving unit 24: pull-down driving unit

30: data driver chip 40: printed circuit board

42: timing controller 44: TCP

M1 to M8: transistor

The present invention relates to a driving circuit for driving a liquid crystal panel, and more particularly to a hybrid gate driver for driving a gate line on the liquid crystal panel.

A typical liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal panel. In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area divided by the gate lines and the data lines. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to one of the data lines via a source and a drain of a thin film transistor, which is a switching element, and a gate of the thin film transistor is connected to one of the gate lines. The driving circuit includes a gate driver for driving the gate lines and a data driver for driving the data lines, and the gate driver sequentially supplies the scanning signal to the gate lines to sequentially supply the liquid crystal cells on the liquid crystal panel by one line. Drive. The data driver also supplies a video signal to each of the data lines whenever either of the gate lines is enabled. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the video signal for each liquid crystal cell.

The thin film transistor used in the liquid crystal display device is classified into an amorphous silicon type and a polysilicon type depending on whether amorphous silicon or poly silicon is used as the semiconductor layer. Amorphous silicon type thin film transistors have the advantage that the characteristics of the amorphous silicon film are relatively good and the characteristics are stable. However, the application of the amorphous silicon thin film transistor is difficult in the case of improving the pixel density due to the relatively low charge mobility. In addition, in the case of using an amorphous silicon type thin film transistor, peripheral driving circuits such as the gate driver and the data driver have to be manufactured separately and mounted on the liquid crystal panel, which has a disadvantage in that the manufacturing cost of the liquid crystal display device is high. On the other hand, as the polysilicon thin film transistor has a high charge mobility, there is no difficulty in increasing the pixel density and it is possible to embed peripheral driving circuits in the liquid crystal panel, thereby lowering the manufacturing cost. Accordingly, liquid crystal displays using polysilicon thin film transistors have emerged. In particular, a gate driver is mounted on the liquid crystal panel.

The gate driver mounted on the liquid crystal panel has a plurality of shift stages corresponding to the gate lines and connected in a cascade manner. Each shift stage included in the gate driver should output a scan signal of sufficient power to drive the gate line on the liquid crystal panel. To this end, each shift stage of the gate driver includes a wide pull-up and pull-down transistor of a wide channel. Pull-up and pull-down transistors with wide channel widths occupy large areas to prevent output reduction by reducing the channel width of transistors due to process foreign materials in the form of rods, but they can improve the reduction of the transistor width due to the above problem. Can be formed into a "U" shape. In addition, transistor control circuitry for controlling the drive timing of these pull-up and pull-down transistors is included in the shift stage. Transistors included in this transistor control circuit were also formed in a "U" shape. The shift stage for the gate driver including the pull-up and pull-down transistors and the transistor control circuit for controlling the same serves as a limiting factor of the display area of the liquid crystal panel.

Accordingly, an object of the present invention is to provide a hybrid gate driver suitable for mounting a shift stage in a narrow gate region of a liquid crystal panel at high resolution while supplying a scan signal of sufficient power to a gate line.

The present invention relates to a hybrid gate driver manufactured at the edge of a liquid crystal panel by a process of forming a thin film transistor on an image display region of a liquid crystal panel.

A hybrid gate driver for a liquid crystal panel according to an embodiment of the present invention for achieving the above object includes a plurality of shift stages corresponding to a plurality of gate lines on the liquid crystal panel and connected in dependence on a start pulse. Each of the shift stages includes: a pull-down transistor that pulls down a voltage on a corresponding gate line; A pull-up transistor that pulls up a voltage on a corresponding gate line and has a narrow channel width compared to the pull-down transistor; A pull-up driver for driving the pull-up and pull-down transistors in opposition so that a voltage on the corresponding gate line is pulled up in response to a scan signal from a previous shift stage; And a pull-down driver for driving the pull-up and pull-down transistors in opposition so that the voltage on the corresponding gate line is pulled down in response to a scan signal from a next shift stage.

The pull-down transistor is preferably set to be approximately 10 times wider than the pull-up transistor in channel width.

The pull-up transistor is formed in a rod shape on the liquid crystal panel.

The a-up, pull-down driver transistor "U" shape-up transistors shorter considerably than that of it, and pull-in by the above construction, the hybrid gate driver for a liquid crystal panel is a full channel width of the pull-down transistor of the present invention To form a rod. Accordingly, accordingly, the hybrid gate driver according to the present invention can reduce the occupied area and further expand the image display area of the liquid crystal panel.

Other objects, other advantages and other features of the present invention will become apparent from the detailed description of the preferred embodiments with reference to the accompanying drawings, in addition to the objects of the present invention as described above.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram schematically illustrating a liquid crystal display including a hybrid gate driver according to an exemplary embodiment of the present invention.

The liquid crystal display of FIG. 1 includes a liquid crystal panel 10 including a color filter array substrate 12 and a transistor array substrate 14 bonded together to have an image display portion 12A for displaying an image. Signal lines such as a plurality of data lines DL and a plurality of gate lines GL are formed in the display region of the transistor array substrate 14, that is, the image display portion 12A. In the liquid crystal cell region of the display area of the transistor array substrate 14 defined by the intersection of the data line DL and the gate line GL, a thin film transistor TFT and each thin film transistor TFT are formed. Pixel electrodes (not shown) to be connected are formed. Each of these liquid crystal cells may be equivalently represented by a liquid crystal capacitor Clc, and includes a storage capacitor Cst for maintaining a data signal charged in the liquid crystal capacitor Clc until the next data signal is charged. The thin film transistor TFT switches an image signal to be transmitted from the data line DL toward the pixel electrode of the liquid crystal cell Clc in response to a scan signal (gate pulse) from the gate line GL. In addition, a data pad region connected to the data line DL is formed in the upper non-display area of the transistor array substrate 14. In the left non-display area of the transistor array substrate 14, a gate driver 20 connected to the gate line GL is formed. This gate driver 20 is manufactured by the process of forming the thin film transistor TFT in the image display part 12A.

In the liquid crystal display, a printed circuit board 40 including a gate driver 20 and a timing controller 42 for controlling the plurality of data driver chips 30 and a data driver chip 20 are mounted. In addition, a plurality of tape carrier packages (hereinafter referred to as TCP) 44 connected between the printed circuit board 40 and the liquid crystal panel 10 are included. Each TCP 44 is electrically connected between the printed circuit board 40 and the liquid crystal panel 10 by a tape automated bonding (TAB) method. At this time, the input pads of each TCP 44 are electrically connected to the printed circuit board 40, and the output pads are electrically connected to the liquid crystal panel 10. Each data driver chip 30 receives a control signal and a data signal from the timing controller 42 mounted on the printed circuit board 40 through an input pad of the TCP 44, and uses the input control signal to input the data signal. Is converted into an analog image signal and supplied to the data line DL of the liquid crystal panel 10 through an output pad of the TCP 44. The timing controller 42 arranges the source data supplied from the driving system according to the driving of the liquid crystal panel 10 according to the vertical, horizontal synchronizing signal and the data enable signal supplied from the external driving system so that each data driver chip ( 30). In addition, the timing controller 42 generates a data control signal for controlling the driving timing of each data driver chip 30 by using the vertical and horizontal synchronization signals and the data enable signal supplied from the driving system. It supplies to 30. The timing controller 42 generates a gate control signal for controlling the driving timing of each of the gate driving circuits 20 using the vertical and horizontal synchronizing signals and the data enable signal supplied from the driving system. 20) Supply to each.

FIG. 2 is a block diagram schematically illustrating a hybrid gate driver 20 according to an exemplary embodiment of the present invention included in the liquid crystal display of FIG. 1.

In FIG. 2, the gate driver 20 includes a plurality of cascaded shift stages STE1 to STEn. That is, the scan signal GL generated in each shift stage is connected to the next shift stage STEi + 1 and the previous shift stage STEi-1 and to the corresponding gate line GL. The first shift stage STE1 is set by the pulse start signal STV. Here, the pulse start signal STV is a pulse synchronized with the vertical synchronization signal Vsync. The second to n th shift stages STE2 to STEn are set by the scan signal GLi of the previous shift stage STEi-1, respectively. When n gate lines are provided, the scan signals GL1 to GLn from each of the shift stages STE1 to STEn are supplied to the corresponding gate lines GL1 to GLn.

Also, the first to fourth clocks CKV1 to CKV4 are sequentially applied to the n shift stages STE1 to STEn so as not to overlap each other. The first clock CKV1 is provided to the 4m + 1th shift stages STE1, STE5, ..., STEn-3, and the 4m + 2th shift stages SRC2, SRC6, ..., STEn-2 ) Is provided with the second clock CKVB and the 4m + 3rd shift stages STE3, STE7, ..., STEn-1 is provided with the third clock CKV and the 4mth shift stages STE4, STE8. The fourth clock CKV is applied to STEn. Here, "m" is an integer including "0". For example, a first clock CKV1 is provided to the first shift stages STE1, STE5, ..., STEn-3, and a second shift stages SRC2, SRC6, ..., STEn-2 are provided. The second clock CKV2 is provided, and the third shift stages STE3, STE7, ..., STEn-1 are provided with the third clock CKV3, and the fourth shift stages STE4, STE8, ..., STEn-1. Is applied to the fourth clock CKV4. Stages. Here, the first clock CKV to the fourth clock CKV4 alternately have high logic pulses sequentially shifted by the width without overlapping each other. The first shift stage STE1 in response to the pulse start signal STV outputs a scan signal GL1 synchronized with the first clock CKV1. In this manner, the second to n-th shift stages STE2 to STEn may correspond to any one of the corresponding clocks (that is, the first to fourth clocks CKV1 to CKV4) in response to the output of the previous shift stages STE1 to STEn-1. The scan signals GL2 to GLn synchronized to one) are output.

In other words, each shift stage STE1 to STEn is set by the corresponding scan signal GL of the pulse start signal STV or the scan signals GL1 to GLi-1 of the previous shift stage, and the first clock ( After the scan signal GLi is generated in synchronization with the corresponding clock among the CKV1 to the fourth clocks CKV4, the scan signal GLi + 1 of the next shift stage is reset. Here, "i" is an integer not containing "0".

3 is a diagram illustrating each of the shift stages of FIG. 2 in detail. The shift stage shown in FIG. 3 is an i-th shift stage and responds to the scan signal GLi-1 of the front shift stage STEi-1 and the scan signal GLi + 1 of the rear shift stage STEi + 1. do. In addition, the i-th shift stage STEi may input any one of the first clocks CKV1 to 4th clock CKV4 according to which of the 4 th + 0 th to m + 3 th positions it is.

As shown in FIG. 3, the i-th shift stage STEi is applied to the first transistor M1 and the i-th gate line GLi for applying a pull-up voltage having a high potential to the i-th gate line GLi. And a second transistor M2 which causes the pull-down voltage of the low potential to be induced. The first transistor M1 includes a gate connected to the first node N1, a drain for inputting a clock signal CKV1 to CKV4, and a source connected to the i-th gate line GLi. The first transistor M1 is turned on when a high potential voltage appears on the first node N1 to supply the clock signal CKV1 to CKV4 to the i-th gate line GLi, thereby providing a high potential. A scan signal of a level is generated in the i-th gate line GLi. Similarly, the second transistor M2 also includes a gate connected to the second node N2, a drain connected to the i-th gate line GLi, and a source connected to the low potential line Vss. The second transistor M2 is turned on when the high potential voltage appears on the second node N2 so that the i-th gate line GLi is connected to the low potential line Vss, whereby the i-th gate line ( A scan signal GLi of low potential level is generated on GLi. The second transistor M2 is the first transistor after the high potential period of one of the first to fourth clock signals CKV1 or CKV4 elapses after the first transistor M1 is turned on. It is turned on instead of the transistor M1. As the first and second transistors M1 and M2 are sequentially turned on at regular time intervals, the i-th scan signal GLi having a high potential pulse is generated in the i-th gate line GLi. Accordingly, the thin film transistor TFT for one line connected to the i-th gate line GLi in the image display portion 12A of the liquid crystal panel 10 is driven. In addition, the i-th scan signal GLi is supplied to the previous shift stage STEi-1 and the next shift stage STEi + 1. Then, the previous shift stage STEi-1 is reset at the rising edge of the i-th scan signal GLi, while the next shift stage STEi + 1 is set at the rising edge of the i-th scan signal GLi.

The voltages on the first and second nodes N1 and N2 are driven by the pull-up driver 22 and the pull-down driver 24 to have potentials opposite to each other. The pull-up driving unit 22 receives the first node N1 while the scan signal GLi-1 of the high potential pulse is applied from the i-1 th shift stage STEi-1 from the previous shift stage STEi-1. ) Causes the high potential voltage to be charged while the voltage on the second node N2 is discharged toward the low potential line Vss. To this end, the pull-up driver 22 responds to the third and fourth transistors M3 and M4 having gates connected to the i-1 th scan signal GLi-1 and the voltage on the first node N1. Is composed of a fifth transistor M5. On the other hand, the pull-down driving unit 24 receives the first node while the scan signal GLi + 1 of the high potential pulse is applied from the i + 1 th shift stage STEi + 1 from the next shift stage STEi + 1. The voltage on N1 is discharged toward the low potential line Vss while the high potential voltage VDD is charged from the high potential line VDD on the second node N2. To this end, the pull-down driver 24 responds to the sixth transistor M6 having the gate connected to the i + 1th scan signal GLi + 1 and the high potential voltage VDD on the high potential line VDD. A seventh transistor M7 and an eighth transistor M5 responsive to a voltage on the second node N2.

The clock signal CKV or CKVB supplied to the drain of the first transistor M1 swings wider than the voltage difference between the high potential voltage on the high potential line VDD and the low potential voltage on the low potential line Vss. do. The clock signal having a large swing width is driven by the pull-up and pull-down drivers 22 and 24 to be opposite to each other, so that the first transistor M1 is the second transistor among the first and second transistors M1 and M2. It has a significantly smaller channel width compared to M2. Furthermore, a transistor having a channel width equal to that of the third through eighth transistors M3 through M8 included in the pull-up and pull-down drivers 22 and 24 is used as the first transistor M1. Also in this case, the rising edge of the scan signal GL supplied to the gate line GL has a slope similar to that of the falling edge as shown in FIG. 4. Therefore, the first transistor M1 may have a significantly narrower channel width than the second transistor M2. The ratio in the channel width between the first transistor M1 and the second transistor M2 is preferably about 1:18.

Thus, since the first transistor M1 has a significantly narrower channel width than the second transistor M2, unlike the pull-down second transistor M2, which is inevitably formed in a “U” shape, The first transistor M1 for up may be formed at the edge of the thin film transistor array substrate 14 in the same bar shape as the third to eighth transistors M3 to M8. Accordingly, the hybrid gate driver 20 can reduce its occupied area and further allow the image display portion 12A of the liquid crystal panel 10 to be expanded.

As described above, the hybrid gate driver for the liquid crystal panel according to the present invention significantly reduces the channel width of the pull-down transistor compared to that of the pull-up transistor and “U” the transistors of the pull-up and pull-down drivers. It is shaped like a rod rather than a shape. Accordingly, the hybrid gate driver according to the present invention can reduce the occupied area.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be apparent that various modifications, alterations, and other equivalent embodiments are possible.

Claims (3)

A shift stage corresponding to gate lines on a liquid crystal panel and connected in dependence on a start pulse, wherein each of the shift stages includes: A pull-down transistor each of the shift stages pulls down a voltage on a corresponding gate line; A pull-up transistor that pulls up the voltage on the corresponding gate line and has a longer channel width than the pull-down transistor; A pull-up driver for driving the pull-up and pull-down transistors in opposition so that a voltage on the corresponding gate line is pulled up in response to a scan signal from a previous shift stage; And And a pull-down driver for driving the pull-up and pull-down transistors in opposition so that the voltage on the corresponding gate line pulls down in response to a scan signal from a next shift stage. Hybrid gate driver. The method of claim 1, And the pull-up transistor is 10 times wider than the pull-down transistor in channel width. The method of claim 1, The transistor included in the pull-up and pull-down driver is formed in a rod shape hybrid gate driver for a liquid crystal panel.

Images