JP2004152482A - Shift register and image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a shift register, which is used suitable for a drive circuit of an image display device, which allows a drive circuit to be reduced in size, and which allows the pulse width of an output signal to be changed arbitrarily, and to provide the image display device using the shift register. <P>SOLUTION: This device comprises a shift resister 1, provided with a flip-flop 23 which operates in synchronization with a clock signal. A switching means 21, to be turned on and off according to the output in the pre-stage of each flip-flop 23, is provided. A clock signal is selectively input by the switching means 21, and the selected clock signal is inverted by an inverter 24, and is used as the shift register output of each stage. Moreover, the use of two kinds of clock signals, which have a duty ratio of 50% or lower and of which the respective low level periods do not overlap, allows respective outputs of the shift registers to be prevented from overlapping. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention is suitably used, for example, in a driving circuit of an image display device, and can reduce the size of the driving circuit and arbitrarily change the pulse width of an output signal, and an image display using the shift register. Equipment related.

  Conventionally, in a data signal line driving circuit and a scanning signal line driving circuit of an image display device, in order to take timing when sampling an input video signal or to create a scanning signal to be applied to each scanning signal line. In addition, shift registers are widely used.

  In the data signal line driving circuit, a sampling signal is created in order to write video data obtained from a video signal via a data signal line to each pixel. At this time, if the sampling signal overlaps with the preceding or next sampling signal, the video data greatly fluctuates, and erroneous video data is output to the data signal line. In order to avoid such a problem, the conventional shift register 101 has, for example, a circuit configuration as shown in FIG.

  Referring to FIG. 17, shift register 101 has n stages, and each stage includes a D-type flip-flop 102, a NAND circuit 103, two-stage inverters 104a and 104b, and a NOR circuit 105. The shift register 101 receives two clock signals SCK and SCKB having different phases and a start pulse SSP.

  The clock signals SCK and SCKB are provided at a half cycle for sampling the input video signal, and pulses are sequentially output from each stage of the shift register 101 in synchronization with the clock signals SCK and SCKB. Focusing on the i-th stage (1 ≦ i ≦ n) of the shift register 101, the output Qi-1 of the i-th stage D-type flip-flop 102 and the output Qi of the i-th stage D-type flip-flop 102 are: The signal is input to the i-th stage NAND circuit 103 and an output signal NSOUTi is obtained.

  Further, in order to prevent the i-th sampling signal Si from overlapping with the (i + 1) -th sampling signal Si + 1, if the output signal NSOUTi is only directly input to one input terminal of the i-th NOR circuit 105, Instead, it is also input to a delay circuit composed of two-stage inverters 104a and 104b. By inputting the output of the delay circuit to the other input terminal of the NOR circuit 105, the width of the sampling signal Si output from the i-th NOR circuit 105 can be reduced.

  By performing the same processing as described above in each stage of the shift register 101, sampling signals S1 to Sn that do not overlap each other can be obtained as shown in FIG.

  Next, a conventional shift register 111 provided in a scanning signal line driving circuit will be described with reference to FIGS.

  The scanning signal line driving circuit outputs a scanning signal to each scanning signal line so that video data is sequentially written to pixels arranged in the display unit. At this time, the pulse output of the (i + 1) -th scanning signal is set so as not to overlap with the scanning signal of the i-th day or to perform processing for refreshing the video data on the data signal line which has been written on the i-th day. I have to stop.

  Therefore, the conventional shift register 111 provided in the scanning signal line driving circuit has n stages as shown in FIG. 19, and includes a D-type flip-flop 112, a NAND circuit 113, and a NOR circuit 114 for each stage. Configuration. The shift register 111 receives two clock signals GCK and GCKB having different phases, a start pulse GSP, and a pulse width control signal PWC.

  In the shift register 111, pulses are sequentially output from each stage in synchronization with the clock signals GCK and GCKB. Focusing on the i-th stage (1 ≦ i ≦ n) of the shift register 111, the output Qi-1 of the i-th stage D-type flip-flop 112 and the output Qi of the i-th stage D-type flip-flop 112 are: The signal is input to the i-th stage NAND circuit 113, and an output signal NOUTi is obtained. The output signals NOUT1 to NOUTn of each stage obtained in this way are output at the same cycle as the scanning signals GL1 to GLn, respectively.

  In the shift register 111, the pulse width control signal PWC is further directly input to one input terminal of the NOR circuit 114 in each stage. The output signal NOUTi of the i-th stage NAND circuit 113 is input to the other input terminal of the i-th stage NOR circuit 114. As a result, the scanning signal GLi is output from the i-th NOR circuit 114.

  By performing the same processing as described above in each stage of the shift register 111, scanning signals GL1 to GLn that do not overlap each other can be obtained as shown in FIG. Therefore, the (i + 1) -th scanning signal GLi + 1 does not overlap with the i-th scanning signal GLi, and it is possible to perform processing for refreshing the video data on the data signal line that has been written on the i-th day.

  As shown in FIG. 21, when the signal A is input from the D terminal and two clock signals CK and CKB are input from the other terminals, the D flip-flops 102 and 112 receive the signal B from the Q terminal. Is output.

  However, the above-described conventional shift registers 101 and 111 require circuits as shown in FIGS. 17 and 19, and there is a problem that the driving circuit becomes large.

  In recent years, there has been a demand for an image display device having a wider display screen, higher definition, and a narrower periphery of the display area. Therefore, it is necessary to reduce the area of the drive circuit. In addition, it can be said that there is a high demand for simplification of the circuit configuration of the shift register even when it is used for devices other than the image display device.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has as its object to provide a shift circuit that does not overlap output pulses of each stage, can change the pulse width arbitrarily, and realizes a simplified circuit configuration. It is an object of the present invention to provide a register and an image processing apparatus which realizes a narrow frame by simplifying a driving circuit by using the shift register.

  In order to solve the above problem, a shift register according to the present invention has a plurality of stages of flip-flops to which a clock signal is input and an output signal of the i-th (i is an arbitrary value) stage flip-flop. A plurality of switch means for respectively controlling the input of the clock signal to the flip-flop of the (i + 1) -th stage when the clock signal is turned on or off, wherein M (M ≧ 2) types of clock signals are used as the clock signal. , Is input to the plurality of flip-flops at intervals of (M−1), and when the switching means is turned on by the output signal of the i-th flip-flop, the i + 1 is output via the switching means. While the clock signal is input to the flip-flop of the stage, an output having the same width as the pulse width of the clock signal is generated by the clock signal. And the plurality of flip-flops are set / reset type flip-flops, and the switch controlling input of the clock signal to the (i + k × M) -th (k ≧ 1) flip-flop The output pulse generated by the switching of the input of the means is input to a reset terminal of the i-th flip-flop.

  In order to solve the above problem, a shift register according to the present invention includes a plurality of flip-flops to which a clock signal is input, and an output signal of the i-th (i is an arbitrary value) flip-flop. A plurality of switch means for controlling the input of the clock signal to the flip-flop of the (i + 1) -th stage by being turned on or off in response to the control signal. Is turned on, the clock signal is input to the (i + 1) -th stage flip-flop via the switch means, while the clock signal generates an output pulse having the same width as the pulse width of the clock signal, The plurality of stages of flip-flops are set / reset type flip-flops, and are provided before (i + k × M) th stage (k ≧ 1). The output signal of the flip-up is, is characterized in that the input to the reset terminal of the flip-flop in the i-th stage.

  According to the above configurations, the output of the flip-flop that operates in synchronization with the clock signal controls the clock signal supplied to the next-stage flip-flop via the switch. Further, the controlled clock signal becomes an output of the shift register in the stage, and the output has the same pulse width as the clock signal.

  As a result, conventionally, a logical operation was performed on the output of the preceding flip-flop and the output of the own stage, and a signal having the same pulse width as the clock signal was generated. Do not need. In addition, it is possible to prevent a part of the output of the logical operation unit from overlapping due to a signal delay (delay of a rise or fall of a signal) in the logical operation unit. Furthermore, a special circuit for preventing the output pulses from overlapping and a transmission line for a special signal are not required, so that the shift register can be significantly reduced in size.

  Therefore, it is possible to provide a shift register in which the output pulses of each stage do not overlap, and the circuit configuration is simplified.

  Further, in the shift register of the present invention, M (M is an integer of 2 or more) kinds of clock signals are input to the plurality of flip-flops every (M−1) as the clock signals. With this configuration, a plurality of clock signals are used, and the frequency can be reduced. Therefore, when a clock signal is input from an external circuit, the frequency can be kept low, which helps to reduce the voltage consumption of the external circuit.

  Further, in the shift register according to the present invention, the plurality of flip-flops are set / reset flip-flops, and the input of the clock signal to the (i + k × M) -th (k ≧ 1) flip-flop is performed. The output pulse generated by switching the input of the switch means to be controlled is input to the reset terminal of the i-th flip-flop, whereby the pulse width of the signal output from each flip-flop Can be adjusted for a desired period of time.

  In general, a "set / reset flip-flop" is a circuit that transitions between two stable states each time a signal is applied at a certain timing, and holds that state when the signal is not input. In a set / reset type flip-flop, for example, an output is set to a high state by an input set signal, and the output state is maintained even if the set signal becomes inactive. After that, when the set signal is inactive and the reset signal becomes active, the flip-flop keeps its output low, and keeps the state until the set signal becomes active even if the reset signal becomes inactive.

  Further, in the shift register of the present invention, the flip-flops of the plurality of stages are set / reset flip-flops, and an output signal of the (i + k × M) -th stage (k ≧ 1) is an i-th stage flip-flop. With the configuration in which the signal is input to the reset terminal of the flip-flop, the pulse width of the signal output from each flip-flop can be adjusted to a desired period.

  In the shift register of the present invention, preferably, each of the M types of clock signals has a phase such that high-level periods do not overlap each other or a phase such that low-level periods do not overlap each other. An output signal that does not overlap with an adjacent output signal can be obtained from the stage.

  Further, in the shift register of the present invention, preferably, the duty ratio of each of the M types of clock signals is set to (100 × 1 / M)% or less so that each stage overlaps with an adjacent output signal. It is possible to obtain an output signal that does not need to be changed, and it is possible to arbitrarily change the pulse width.

  Note that the “duty ratio” indicates a temporal ratio between active and inactive signal waveforms. For example, if the signal waveform is High when the signal waveform is active (active is a state in which the signal is acting) and the signal waveform is Low when the signal waveform is low, one cycle of the waveform is assumed. Is the sum of the active time and the inactive time. For example, a duty ratio of 40% indicates that the active time occupies 40% of one cycle. In some circuits, the Low period is active.

  Further, in the shift register of the present invention, preferably, when the switch means is turned off, the switch means is opened by providing input stabilizing means for stabilizing an input to the plurality of flip-flops. Then, the input to the flip-flop becomes a predetermined potential, so that malfunction of the flip-flop can be prevented.

  Further, the shift register of the present invention preferably includes an inverter for inverting a clock signal selectively input by the switch means, and the switch means is turned on by an output signal of the i-th flip-flop. The clock signal is input to the inverter via the switch means, and is output via the inverter, whereby the output pulse is generated.

  According to another embodiment of the present invention, there is provided an image display device, comprising: a display unit including a plurality of pixels provided in a matrix; and video data connected to a plurality of data signal lines and written to the pixels. And a scanning signal line driving circuit connected to a plurality of scanning signal lines and supplying a scanning signal for controlling writing of the video data to the pixels to each scanning signal line. An image display device comprising a shift register according to the present invention is provided in at least one of the data signal line driving circuit and the scanning signal line driving circuit.

  According to the above configuration, by using the shift register of the present invention, it is possible to provide an image processing apparatus in which the circuit scale of the driving circuit is reduced and the frame is narrowed.

  In the image display device of the present invention, preferably, at least one of the data signal line driving circuit and the scanning signal line driving circuit is formed on a substrate on which the pixels are formed. The wiring between the data signal line driving circuit and each pixel or the wiring between the scanning signal line driving circuit and each pixel is provided on the same substrate and does not need to be out of the substrate. As a result, even if the number of data signal lines and the number of scanning signal lines increase, the number of signal lines extending out of the substrate does not change, and there is no need to assemble. In addition to this, it is possible to prevent a reduction in the degree of integration. In addition, labor during manufacturing can be saved.

  Further, in the image display device of the present invention, preferably, a switch element forming at least one of the data signal line driving circuit and the scanning signal line driving circuit is a polycrystalline silicon thin film transistor, so that a display area is Can be easily expanded.

  By the way, the polycrystalline silicon thin film has a larger area than the monocrystalline silicon, while the polycrystalline silicon transistor has inferior transistor characteristics such as mobility and threshold value as compared with the monocrystalline silicon transistor. ing. Therefore, when each circuit is manufactured using a single crystal silicon transistor, it is difficult to increase the display area, and when each circuit is manufactured using a polycrystalline silicon thin film transistor, the driving capability of each circuit is reduced. When both the driving circuits and the pixels are formed on different substrates, it is necessary to connect the two substrates with each signal line, which is troublesome at the time of manufacturing and increases the capacitance of each signal line. .

  Therefore, the display area can be easily enlarged by adopting a configuration including the switching element composed of the polycrystalline silicon thin film transistor. Further, by using the shift register of the present invention, it is possible to realize a narrow frame and a reduction in power consumption by reducing the circuit scale.

  In the image display device of the present invention, preferably, the switch element is formed at a temperature of 600 ° C. or less, so that a normal glass substrate (having a strain point of 600 ° C.) is formed as a substrate on which each switching element is formed. Even when the following glass substrate is used, warping or bending due to a process at or above the strain point does not occur. As a result, an image display device which is easier to mount and has a larger display area can be realized.

  As described above, the shift register according to the present invention is turned on or off in accordance with the plurality of flip-flops to which a clock signal is input and the output signal of the i-th flip-flop (i is an arbitrary value). A plurality of switch means for respectively controlling the input of the clock signal to the flip-flop of the (i + 1) th stage, wherein M (M ≧ 2) kinds of clock signals are provided as the clock signal. (M-1) flip-flops, and when the switch means is turned on by the output signal of the i-th flip-flop, the (i + 1) -th flip-flop is passed through the switch means. While the clock signal is input to the amplifier, the clock signal generates an output pulse having the same width as the pulse width of the clock signal. , The plurality of flip-flops are set / reset flip-flops, and the input of the switch means for controlling the input of the clock signal to the (i + k × M) -th (k ≧ 1) flip-flop is controlled. The output pulse generated by the switching is input to a reset terminal of the flip-flop at the i-th stage.

  Further, as described above, the shift register according to the present invention is turned on in response to a plurality of flip-flops to which a clock signal is input and an output signal of the i-th (i is an arbitrary value) flip-flop. Or a plurality of switch means for controlling the input of the clock signal to the (i + 1) -th flip-flop by being turned off, and the switch means is turned on by the output signal of the i-th flip-flop And the clock signal is input to the (i + 1) -th stage flip-flop via the switch means, and the clock signal generates an output pulse having the same width as the pulse width of the clock signal. The flip-flop is a set / reset type flip-flop, and is a (i + k × M) -th stage (k ≧ 1) flip-flop. The output signal of the-up is configured to be inputted to the reset terminal of the flip-flop in the i-th stage.

  Therefore, it is possible to provide a shift register in which the output pulses of the respective stages do not overlap, and the circuit configuration is simplified.

  Further, in the shift register of the present invention, M (M ≧ 2) types of clock signals are input to the plurality of flip-flops at intervals of (M−1). As a result, the frequency can be reduced, and when a clock signal is input from an external circuit, the voltage consumption of the external circuit can be reduced.

  Further, in the shift register according to the present invention, the plurality of flip-flops are set / reset flip-flops, and the input of the clock signal to the (i + k × M) -th (k ≧ 1) flip-flop is performed. The output pulse generated by switching the input of the switch means to be controlled is input to the reset terminal of the i-th flip-flop, whereby the pulse width of the signal output from each flip-flop Can be adjusted for a desired period.

  Further, in the shift register of the present invention, the flip-flops of the plurality of stages are set / reset flip-flops, and an output signal of the (i + k × M) -th stage (k ≧ 1) is an i-th stage flip-flop. With the configuration in which the signal is input to the reset terminal of the flip-flop of the eye, the pulse width of the signal output from each flip-flop can be adjusted to a desired period.

  Further, in the shift register of the present invention, the M types of clock signals have a phase such that their high-level periods do not overlap each other or a phase such that their low-level periods do not overlap each other. This produces an effect that an output signal that does not overlap with the output signal to be output can be obtained.

  Further, in the shift register of the present invention, the duty ratio of each of the M types of clock signals is set to be (100 × 1 / M)% or less so that the output signal from each stage does not overlap with an adjacent output signal. And the pulse width can be arbitrarily changed.

  Further, in the shift register of the present invention, when the switch means is turned off, the switch means is provided with input stabilizing means for stabilizing an input to the plurality of flip-flops when the switch means is turned off. Since the input to the flip-flop has a predetermined potential, the flip-flop can be prevented from malfunctioning.

  Further, the shift register of the present invention includes an inverter for inverting a clock signal selectively input by the switch means, and the switch is turned on when an output signal of the i-th flip-flop turns on the switch means. The output signal is generated by the clock signal being input to the inverter via a means and being output via the inverter.

  As described above, the image display device according to the present invention has a configuration in which at least one of the data signal line driving circuit and the scanning signal line driving circuit includes the above-described shift register of the present invention.

  Therefore, by using the shift register of the present invention, the circuit scale of the driving circuit can be reduced, and an image processing apparatus having a narrower frame can be provided.

  Further, in the image display device according to the present invention, at least one of the data signal line driving circuit and the scanning signal line driving circuit is formed over a substrate on which the pixels are formed, so that a This has the effect of saving labor and preventing an undesired increase in the capacitance of each signal line.

  Further, in the image display device according to the present invention, the switch element forming at least one of the data signal line driving circuit and the scanning signal line driving circuit is a polycrystalline silicon thin film transistor, so that the display area can be easily reduced. This has the effect of being able to expand.

  Further, in the image display device of the present invention, the switch element is formed at a temperature of 600 ° C. or less, so that an inexpensive glass substrate or the like can be used as a substrate, and the image display device can be provided at low cost. This has the effect that it becomes possible.

[Embodiment 1]
One embodiment of the present invention will be described below with reference to FIGS.

  The shift register of the present invention can be suitably used for a data signal line driving circuit and a scanning signal line driving circuit of an image display device, but can also be applied to devices other than the image display device. Hereinafter, a shift register according to an embodiment of the present invention applied to a data signal line driving circuit will be referred to as a first embodiment, and a shift register according to an embodiment of the present invention applied to a scanning signal line driving circuit will be described. Explanation will be given as 2.

  As shown in FIG. 1, the shift register 1 according to the present embodiment generally includes a switch unit 2, an input stabilizing unit 3, and a flip-flop unit 4, and includes, for example, an image shown in FIG. Used for the data signal line drive circuit 14 of the display device 11.

  As shown in FIG. 2, the image display device 11 includes a display unit 12, a scanning signal line driving circuit 13, a data signal line driving circuit 14, and a control circuit 15.

  The display unit 12 is arranged in a matrix with n scanning signal lines GL (GL1, GL2,... GLn) parallel to each other and n data signal lines SL (SL1, SL2,. (In the figure, PIX) 16. The pixel 16 is formed in a region surrounded by two adjacent scanning signal lines GL, GL and two adjacent data signal lines SL, SL. For convenience of explanation, the number of the scanning signal lines GL and the number of the data signal lines SL are also n, but it is needless to say that the numbers of the two lines may be different.

  The scanning signal line driving circuit 13 includes a shift register 17, which shifts the pixels 16 in each row based on two types of clock signals GCK 1 and GCK 2 input from the control circuit 15 and a start pulse GSP. The scanning signals to be applied to the connected scanning signal lines GL1, GL2,... Are sequentially generated. The circuit configuration of the shift register 17 will be described in detail in a second embodiment.

  The data signal line drive circuit 14 includes the shift register 1 and a sampling unit 18. Two types of clock signals SCK and SCKB having different phases from each other and a start pulse SSP are input from the control circuit 15 to the shift register 1, while a video signal DAT is input from the control circuit 15 to the sampling unit 18. . The data signal line driving circuit 14 samples the video signal DAT in the sampling unit 18 based on the signals S1 to Sn output from each stage of the shift register 1, and outputs the obtained video data to the pixels 16 in each column. Output to the connected data signal lines SL1, SL2,...

  The control circuit 15 is a circuit that generates various control signals for controlling operations of the scanning signal line driving circuit 13 and the data signal line driving circuit 14. As described above, the control signals include the clock signals GCK1, GCK2, SCK, SCKB, the start signals GSP, SSP, and the video signal DAT.

  Note that a switching element is provided in each of the scanning signal line driving circuit 13, the data signal line driving circuit 14, and the pixel 16 of the display unit 12 of the image display device 11, and a method of manufacturing these switching elements will be described. This will be described in detail in a third embodiment.

If the image display device 11 is an active matrix liquid crystal display device, the pixel 16, as shown in FIG. 3, a pixel transistor SW formed of field effect transistors, the pixel capacitance includes a liquid crystal capacitor C _L C _P ( And a storage capacitor C _S is added as necessary). In such a pixel 16, and one electrode of the data signal line SL and the pixel capacitor C _P is connected through the drain and source of the pixel transistor SW, the gate of the pixel transistor SW is connected to the scanning signal line GL, a pixel the other electrode of the capacitor C _P is connected to a common a common electrode line (not shown) to all pixels.

Here, when the pixel 16 connected to the i-th data signal line SLi and the j-th scanning signal line GLj is represented as PIX (i, j), (i, j is in the range of 1 ≦ i, j ≦ n) In the PIX (i, j), when the scanning signal line GLj is selected, the pixel transistor SW is turned on, and the voltage as video data applied to the data signal line SLi is changed to the pixel capacitance C _P. Applied to With such voltage to the liquid crystal capacitor C _L of the pixel capacitor C _P is applied, the liquid crystal of the transmittance or reflectance is modulated. Therefore, by selecting the scanning signal line GLj and applying a signal voltage corresponding to the video data to the data signal line SLi, the display state of the PIX (i, j) can be changed according to the video data.

  In the image display device 11, the scanning signal line driving circuit 13 selects the scanning signal line GL, and the video data to the pixel 16 corresponding to the selected combination of the scanning signal line GL and the data signal line SL is converted to the data signal line. The data is output to each data signal line SL by the drive circuit 14. As a result, the respective video data is written to the pixels 16 connected to the scanning signal line GL. Further, the scanning signal line driving circuit 13 sequentially selects the scanning signal lines GL, and the data signal line driving circuit 14 outputs video data to the data signal lines SL. As a result, the respective video data is written to all the pixels 16 of the display section 12, and an image corresponding to the video signal DAT is displayed on the display section 12.

  Here, between the control circuit 15 and the data signal line drive circuit 14, video data to each pixel 16 is transmitted as a video signal DAT in a time-division manner, and the data signal line drive circuit 14 A clock signal SCK having a predetermined period and a duty ratio of 50% or less (in this embodiment, a Low period is shorter than a High period) and a clock signal SCKB having a phase 180 ° different from the clock signal SCK (see FIG. 4) ) And the start pulse SSP, each video data is extracted from the video signal DAT.

  Specifically, the shift register 1 of the data signal line driving circuit 14 sequentially shifts a pulse corresponding to a half cycle of the clock by inputting the start pulse SSP in synchronization with the clock signals SCK and SCKB. Thus, output signals S1 to Sn having different timings by one clock are generated. The sampling unit 18 of the data signal line drive circuit 14 extracts video data from the video signal DAT at the timing of each of the output signals S1 to Sn.

  On the other hand, the shift register 17 of the scanning signal line drive circuit 13 sequentially shifts and outputs a pulse corresponding to a half cycle of the clock by receiving the start pulse GSP in synchronization with the clock signals GCK1 and GCK2. Thus, scanning signals having different timings by one clock are output to the scanning signal lines GL1 to GLn.

  Hereinafter, the configuration and operation of the shift register 1 of the present embodiment used for the data signal line driving circuit 14 will be described. Subsequently, in Embodiment 2, the configuration and operation of the shift register 17 used for the scanning signal line driving circuit 13 will be described. The operation will be described.

  Referring to FIG. 1, shift register 1 has n stages, and has a configuration in which, as described above, two types of clock signals SCK and SCKB having different phases from each other and start pulse SSP are input. The clock signals SCK and SCKB are alternately input to each stage, and the odd-numbered stages receive the clock signal SCK, while the even-numbered stages receive the clock signal SCKB.

  The shift register 1 includes a switch unit 2, an input stabilizing unit 3, and a flip-flop unit 4. The switch section 2 is provided with a switch means 21 for each stage, and the input stabilization section 3 is provided with a p-type transistor (input stabilization means) 22 for each stage. The flip-flop unit 4 is provided with a flip-flop (SR-FF in the figure) 23 which is a set / reset type flip-flop and an inverter 24 for each stage.

  For example, as shown in FIG. 5, the flip-flop 23 includes transistors 31, 34, and 35 that are p-type MOS transistors, transistors 32, 33, 36, and 37 that are n-type MOS transistors, and inverters 38 and 39. It can be realized by the configuration described above.

  Referring to FIG. 5, in flip-flop 23, transistors 31, 32, and 33 are connected in series between drive voltage Vcc and the ground level, and the gates of transistors 31 and 33 have negative logic. A set signal / S is applied. A positive logic reset signal R is applied to the gate of the transistor 32. Further, the drain potentials of the transistors 31 and 32 connected to each other are inverted by inverters 38 and 39, respectively, and output as an output signal Q.

  Between the drive voltage Vcc and the ground level, there are further provided transistors 34, 35, 36 and 37 connected in series. The drains of the transistors 35 and 36 are connected to the input of the inverter 38, and the gates of the transistors 35 and 36 are connected to the output of the inverter 38. Further, the reset signal R is applied to the gate of the transistor 34, and the set signal / S is applied to the gate of the transistor 37.

  In the flip-flop 23, when the set signal / S changes to active (low level) while the reset signal R is inactive (low level) as shown in FIG. Change the input to high level. As a result, the output signal Q of the flip-flop 23 changes to a high level.

  In the above state, the transistors 34 and 35 are turned on by the reset signal R and the output of the inverter 38. The transistors 32 and 36 are cut off by the reset signal R and the output of the inverter 38. Thus, even if the set signal / S changes to inactive, the input of the inverter 38 is maintained at the high level, and the output signal Q is maintained at the high level.

  Thereafter, when the reset signal R becomes active, the transistor 34 is turned off and the transistor 32 is turned on. Here, since the set signal / S remains inactive, the transistor 31 is turned off and the transistor 33 is turned on. Therefore, the input of inverter 38 is driven to low level, and output signal Q changes to low level.

  Referring again to FIG. 1, the output signal Q (Q1, Q2,...) Of each stage flip-flop 23 is inputted to the next stage switch means 21 and also inputted to the gate of the next stage p-type transistor 22. Is done. Each switch means 21 controls the input of the clock signal SCK or SCKB to each stage by opening and closing the switch means 21. While the output signal Q of the preceding flip-flop 23 is at a low level, the switch means 21 is opened (switched off), while the output signal is turned off. During the period when Q is at the high level, the switch is closed (switched on). The clock signal SCK or SCKB input to each stage is input to the flip-flop 23 as a set signal / S, and is also input to the inverter 24.

  The p-type transistor 22 is for stabilizing the input of the flip-flop 23 when the clock signal SCK / SCKB is not input to the flip-flop 23. In the p-type transistor 22, the source and the drain are non-conductive while the output signal Q is at the high level, and the source and drain are conductive while the output signal Q is at the low level.

  The flip-flop 23 is configured to transmit a start signal SSP having one clock cycle width to the next stage every time the clock signals SCK and SCKB fall. Specifically, the clock signals SCK and SCKB controlled by the switch means 21 which is opened and closed by the output signal Q of the preceding stage (the initial stage is the start signal SSP) are applied to the flip-flop 23 as the negative logic set signal / S. At the first stage, the output is output as the output S1 of the shift register 1 via the inverter 24. The output signal Q1 of the first-stage flip-flop 23 is applied as a switching signal of the next-stage switch means 21.

  Further, a signal delayed from the input signal to the subsequent stage by the pulse width transmitted as the output of the shift register 1 via the inverter 24 among the input signals to the subsequent stage is applied as the reset signal R. Since the shift register 1 transmits a pulse having a width of one clock cycle, the signal is delayed by one clock cycle, that is, switched by the switch means 21 two steps later, and the shift register 1 output from the inverter 24 of that stage is output. The output signal is applied as a positive logic reset signal R.

  The clock signal SCK is input to the odd-numbered switch means 21 so that the odd-numbered flip-flop 23 is set at the falling edge of the clock signal SCK. On the other hand, the clock signal SCKB is input to the even-numbered switch means 21 so that the even-numbered flip-flop 23 is set at the falling of the clock signal SCKB.

  Therefore, shift register 1 operates as follows.

  When the start signal SSP goes high, the connected first-stage switch means 21 switches accordingly, and the clock signal SCK is input to the flip-flop 23. At this time, since the start signal SSP is input to the gate of the first-stage p-type transistor 22 of the input stabilizing unit 3, the source-drain is in a non-conductive state. Therefore, the signal input by the switching of the first-stage switch means 21 becomes a sampling signal for extracting video data from the video signal DAT as the output S1 via the inverter 24.

  On the other hand, in response to the fall of the input clock signal SCK, the output signal Q1 of the first-stage flip-flop 23 goes high. The high-level output signal Q1 turns on the next-stage (second-stage) switch means 21 and receives the clock signal SCKB. The clock signal SCKB is input to the second-stage flip-flop 23 to generate an output signal Q2. One of the two is a sampling signal for extracting video data from the video signal DAT as an output S2 via the inverter 24. .

  Further, when the switch means 21 of the next stage (third stage) is turned on by the output signal Q2, the clock signal SCK is input to the stage. The clock signal SCK is input to the third-stage flip-flop 23 to generate an output signal Q3, and one of the two is a sampling signal for extracting video data from the video signal DAT as an output S3 via the inverter 24. .

  The third-stage signal S3 is input as the reset signal R of the first-stage flip-flop 23, and the output signal Q1 becomes low level. When the output signal Q1 becomes low level, the second-stage switch means 21 is turned off. At this time, in the p-type transistor 22 of the second stage, the conduction between the source and the drain becomes conductive, and the input portion of the flip-flop 23 of the second stage becomes high level and is stabilized.

  Here, in the case of the first-stage flip-flop 23, when the start signal SSP becomes low level, the first-stage switch means 21 is turned off, the input of the clock signal SCK is stopped, and the first-stage p-type transistor At 22, the connection between the source and the drain becomes conductive, and the input section of the flip-flop 23 of the first stage becomes high level and is stabilized.

  Hereinafter, by sequentially generating signals in the same manner as described above, it is possible to obtain output signals S1 to Sn that do not overlap each other based on the clock signals SCK and SCKB, as shown in FIG. This is because each switch means 21 is in a conductive state for a sufficiently long time for the pulse width of the output signals S1 to Sn, so that the rising or falling timing of the clock signal SCK or SCKB passes through the switch with almost no delay, As a result, the output signals S1 to Sn hardly overlap each other.

  On the other hand, in the conventional configuration shown in FIG. 17 in which an output pulse is generated by a logic element, a delay occurs at the rising or falling timing of the pulse due to a variation in the switching time of the transistors constituting each logic element. This may result in the disadvantage that the output pulses overlap each other.

  Note that, in the shift register 1 of the present embodiment, as shown in FIG. 1, a switch means 21x, a p-type transistor 22x, a flip-flop 23x, and an inverter 24x are provided at the last stage for dummy use. The output signal Sx from the inverter 24x is input to the reset terminal of the n-th stage flip-flop 23, and the output signal Qx of the flip-flop 23x itself is input to the reset terminal of the last stage flip-flop 23x. It has become. Therefore, the final-stage flip-flop 23x is set and reset at the same time when the output signal Qx is generated, and the output signal Qx has a waveform as shown in FIG.

  Note that the output signal Sx from the inverter 24x is not input to the reset terminal of the n-th flip-flop 23, and the output signal Qx of the last flip-flop 23x is It may be configured to be input to the reset terminal. In such a configuration, the inverter 24x becomes unnecessary.

  As described above, in the shift register 1 of the present embodiment, the output pulse of each stage does not overlap, and there is no need to provide a logic element or the like, so that the circuit configuration can be simplified. Further, by using such a shift register 1, it is possible to provide an image processing apparatus which realizes a narrow frame by simplifying a driving circuit.

  In this embodiment, two types of clock signals are input to the shift register 1. However, the present invention is not limited to this, and three or more types of clock signals may be used.

  The clock signal SCK / SCKB input to the shift register 1 has a low period shorter than the high period. However, the present invention is not limited to this, and the low period and the high period have the same length. A configuration in which a certain clock signal is input may be adopted.

  Further, the output signal from the inverter 24 after two stages is input to the reset terminal of each flip-flop 23 of the shift register 1, but the present invention is not limited to this. That is, assuming that M (M ≧ 2) kinds of clock signals are input and k is an arbitrary integer of 1 or more, the output pulse of the (i + k × M) -th stage (the output of the inverter 24 of the (i + k × M) -th stage) Signal) may be input to the reset terminal of the i-th stage flip-flop 23. For example, as in a shift register 25 shown in FIG. 7, a configuration may be employed in which an output signal from the inverter 24 after four stages is input to the reset terminal of each flip-flop 23.

  The shift register 1 shown in FIG. 1 has a configuration in which k = 1 and M = 2. For example, a configuration in which a reset terminal of the first-stage flip-flop 23 receives a third-stage output pulse. It is. On the other hand, the shift register 25 shown in FIG. 7 has a configuration in which k = 2 and M = 2. For example, an output pulse of the fifth stage is input to a reset terminal of the flip-flop 23 of the first stage. It is a configuration that is performed.

  FIG. 8 is a timing chart showing the operation of the shift register 25. As shown in FIG. 8, the output signal Q1 of the first-stage flip-flop 23 is reset by the fifth-stage output pulse S5, and The output signal Q2 of the flip-flop 23 is reset by the sixth-stage output pulse S6. Note that two set signals are input to the flip-flop 23 as in the output pulse S1, for example, but there is no effect on the operation of the flip-flop 23. Further, although the fifth-stage output pulse S5 is used to reset the first-stage flip-flop 23, even if the reset signal is input twice as described above, the operation of the flip-flop 23 is not hindered. .

  When the shift register 25 shown in FIG. 7 is used for the data signal line driving circuit 14, the video signal DAT can be sampled twice by the output pulse. That is, the first sampling can be used as the preliminary sampling, and the desired video signal DAT can be sampled on the data signal line in the second sampling. The preliminary sampling also has the effect of assisting the second charge.

  Further, in the shift register of the present invention, when M (M ≧ 2) types of clock signals are input and k is an arbitrary integer of 1 or more, the output signal of the (i + k × M) -th stage flip-flop 23 is A configuration in which the signal is input to the reset terminal of the i-th flip-flop 23 may be adopted. For example, like the shift register 26 shown in FIG. 9, a configuration may be employed in which the output signal of the flip-flop 23 after the next stage is input to the reset terminal of each flip-flop 23. Further, like the shift register 27 shown in FIG. 11, a configuration may be employed in which the output signal of the flip-flop 23 after the fourth stage is input to the reset terminal of each flip-flop 23.

  The shift register 26 shown in FIG. 9 has a configuration in which k = 1 and M = 2. For example, an output signal Q3 of the third-stage flip-flop 23 is connected to a reset terminal of the first-stage flip-flop 23. Is input. On the other hand, the shift register 27 shown in FIG. 11 has a configuration in which k = 2 and M = 2. For example, the reset terminal of the first-stage flip-flop 23 The configuration is such that the output signal Q5 is input.

  FIG. 10 is a timing chart showing the operation of the shift register 26. As shown in FIG. 10, the first-stage flip-flop 23 is reset by the output signal Q3 of the third-stage flip-flop 23, The flip-flop 23 is reset by the output signal Q4 of the fourth-stage flip-flop 23. FIG. 12 is a timing chart showing the operation of the shift register 27. As shown in FIG. 12, the first-stage flip-flop 23 is reset by the output signal Q5 of the fifth-stage flip-flop 23, The flip-flop 23 of the sixth stage is reset by the output signal Q6 of the flip-flop 23 of the sixth stage. With such a configuration, the shift registers 26 and 27 have the same effects as the shift registers 1 and 25 described above.

  7 to 12 showing the configuration and operation of the shift registers 25, 26, and 27, the last dummy stage is represented as the n-th stage. The shift register 25 has a configuration in which the output signal Sn from the last n-th stage inverter 24 is input to the reset terminal of the (n−1) -th stage flip-flop 23. The configuration is such that the output signal Qn of the flip-flop 23 of the stage is input to the reset terminal of the flip-flop 23 of the (n-1) th stage.

[Embodiment 2]
The second embodiment of the present invention will be described below with reference to FIGS. Note that, in the present embodiment, elements having the same functions as the elements in the above-described first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  The shift register 17 according to the present embodiment is a shift register used for the scanning signal line driving circuit 13 as described above, and receives two types of clock signals GCK1 and GCK2 as clock signals as shown in FIG. , Except that a start pulse GSP is input as a start signal.

  As shown in FIG. 14, the clock signals GCK1 and GCK2 have phases such that the low-level periods do not overlap with each other. Specifically, the clock signals GCK1 and GCK2 are out of phase with each other by 180 °. Further, the clock signals GCK1 and GCK2 have a sufficiently short low-level period compared to a high-level period.

  In the case of the scanning signal line driving circuit 13, when the scanning signals before and after overlap, display is significantly deteriorated on display. Therefore, conventionally, the scanning signals are generated so as not to overlap using the pulse width control signal PWC or the like.

  In the shift register 17 of the present embodiment, the clock signals GCK1 and GCK2 are used. In the same operation as the shift register 1 described above, the input of the clock signals GCK1 and GCK2 to each flip-flop 23 is controlled by each switch means 21 and the signals GL1 to GL1 are output from each stage via each inverter 24. GLn is output. Therefore, based on the clock signals GCK1 and GCK2, the output signals GL1 to GLn that do not overlap each other can be obtained as shown in FIG.

  In addition, the frame width can be easily reduced without requiring the pulse width control signal PWC or the logic circuit.

  It is needless to say that the input to the reset terminal of each flip-flop 23 in the shift register 17 may be changed like the shift registers 25, 26, and 27.

[Embodiment 3]
The following will describe the third embodiment of the present invention with reference to FIGS. In the present embodiment, the same reference numerals are given to the elements having the same functions as those in the first and second embodiments, and the description thereof will be omitted.

  The image display device according to the present embodiment has a configuration similar to that of the image display device 11 described in the first embodiment, except that the scanning signal line driving circuit 13 and the data signal line driving circuit 14 include a plurality of pixels 16. The part 12 is formed on the same substrate.

  That is, in the image display device of the present embodiment, the scanning signal line driving circuit 13 and the data signal line driving circuit 14 are formed together with the display section 12 on an insulating substrate, for example, a glass substrate 51 (driver monolithic structure). As the insulating substrate (substrate), a sapphire substrate, a quartz substrate, an alkali-free glass, or the like is often used.

  In this way, by forming the scanning signal line driving circuit 13 and the data signal line driving circuit 14 monolithically on the same glass substrate 51 as the display section 12, the labor and the wiring capacity at the time of manufacturing can be reduced. Further, the number of input terminals to the glass substrate 51 is smaller than that of an image display device using an external IC as a driver. As a result, it is possible to reduce the cost for mounting components on the glass substrate 51 and the occurrence of defects due to the mounting. Therefore, the manufacturing cost and the mounting cost of the driving circuit can be reduced, and the reliability of the driving circuit can be improved.

  Further, in the present image display device, a thin film transistor is used as the pixel transistor SW (see FIG. 3), and the scanning signal line driving circuit 13 and the data signal line driving circuit 14 include thin film transistors. Polycrystalline silicon thin film transistors are employed as these thin film transistors in order to integrate 16 and increase the display area.

  The polycrystalline silicon thin film transistor has a structure as shown in FIG. 15, for example. In this structure, a silicon oxide film 52 for preventing contamination is deposited on a glass substrate 51, and a field effect transistor is formed thereon. Have been.

  The thin film transistor described above includes a polycrystalline silicon thin film 53 including a channel region 53a, a source region 53b, and a drain region 53c formed on a silicon oxide film 52, and a gate insulating film 54, a gate electrode 55, and a gate insulating film 54 formed thereon. It is composed of an interlayer insulating film 56 and metal wirings 57.

  The above-mentioned polycrystalline silicon thin film transistor has a forward stagger (top gate) structure using a polycrystalline silicon thin film on an insulating substrate as an active layer. However, the present embodiment is not limited to this, and the present invention is not limited to this. The transistor may have another structure. Further, in the present image display device, a single crystal silicon thin film transistor, an amorphous silicon thin film transistor, or a thin film transistor formed of another material can be applied.

  By using the polycrystalline silicon thin film transistor as described above, the scanning signal line driving circuit 13 and the data signal line driving circuit 14 having practical driving capabilities are placed on the glass substrate 51 on which the display section 12 is formed. .. Can be manufactured in substantially the same manufacturing process.

  FIG. 16 is a process sectional view showing a process for manufacturing the polycrystalline silicon thin film transistor. In this manufacturing process, first, an amorphous silicon thin film a-Si is deposited on the glass substrate 51 shown in FIG. 16A (FIG. 16B). Next, the polycrystalline silicon thin film 53 is formed by irradiating the amorphous silicon thin film a-Si with an excimer laser (FIG. 16C). This polycrystalline silicon thin film 53 is patterned into a desired shape (FIG. 16D), and a gate insulating film 54 made of silicon dioxide is formed thereon (FIG. 16E).

  Further, the gate electrode 55 is formed of aluminum or the like (FIG. 16F). Thereafter, impurities (phosphorus in the n-type region and boron in the p-type region) are implanted into portions of the polycrystalline silicon thin film 53 that will become the source region 53b and the drain region 53c (FIGS. 16 (g) and (h)). When implanting an impurity into the n-type region, the p-type region is masked with a resist 58 (FIG. 16 (g)), and when implanting an impurity into the p-type region, the n-type region is masked with the resist 58. (FIG. 16 (h)).

  Then, an interlayer insulating film 56 made of silicon dioxide, silicon nitride or the like is deposited (FIG. 16 (i)), and contact holes 59 are formed in the interlayer insulating film 56 (FIG. 16 (j)). Finally, metal wires 57 such as aluminum are formed in the contact holes 59 (FIG. 16 (k)).

  The maximum temperature in the above process is 600 ° C. or less when forming the gate insulating film 54. Therefore, even when a normal glass substrate (a glass substrate having a strain point of 600 ° C. or lower) is used, warping or bending due to a process at or above the strain point does not occur. That is, it is not necessary to use an expensive quartz substrate having extremely high heat resistance as the insulating substrate, and it is possible to use inexpensive high heat resistant glass. Therefore, it is possible to provide the image display device at low cost.

  In the manufacture of the image display device, a transparent electrode (in the case of a transmissive liquid crystal display device) or a reflective electrode (reflective type) is formed on the thin film transistor manufactured as described above via a further interlayer insulating film. (In the case of a liquid crystal display device).

  By employing the above-described process, a polycrystalline silicon thin film transistor can be formed over a glass substrate which is inexpensive and can have a large area. Therefore, cost reduction and size increase of the image display device can be easily realized.

FIG. 2 is a circuit diagram schematically illustrating a configuration of a shift register according to one embodiment of the present invention. FIG. 2 is a diagram illustrating a schematic configuration of an image display device using the shift register. It is a figure showing composition of a pixel in the above-mentioned image display device. 4 is a timing chart illustrating an operation of the shift register. FIG. 3 is a circuit diagram illustrating a configuration of a set / reset type flip-flop used in the shift register. 5 is a timing chart showing an operation of the set / reset flip-flop. FIG. 4 is a circuit diagram showing a configuration example in which an input to a reset terminal of each flip-flop in the shift register is changed. 8 is a timing chart showing the operation of the shift register of FIG. FIG. 9 is a circuit diagram showing another configuration example in which an input to a reset terminal of each flip-flop in the shift register is changed. 10 is a timing chart showing the operation of the shift register of FIG. FIG. 9 is a circuit diagram showing still another configuration example in which the input to the reset terminal of each flip-flop in the shift register is changed. 12 is a timing chart illustrating the operation of the shift register of FIG. FIG. 9 is a circuit diagram schematically illustrating a configuration of a shift register according to another embodiment of the present invention. 4 is a timing chart illustrating an operation of the shift register. FIG. 3 is a cross-sectional view illustrating a structure of a polycrystalline silicon thin film transistor used in the image display device. (A) to (k) are cross-sectional views showing the structure at each stage in the manufacturing process of the polycrystalline silicon thin film transistor of FIG. FIG. 9 is a circuit diagram showing a configuration of a conventional shift register used in a data signal line driving circuit. 6 is a timing chart showing the operation of the conventional shift register. FIG. 9 is a circuit diagram illustrating an operation of a conventional shift register used in a scanning signal line driving circuit. 6 is a timing chart showing an operation of a shift register in the conventional scanning signal line driving circuit. 6 is a timing chart illustrating an operation of a D-type flip-flop.

Explanation of reference numerals

Reference Signs List 1 shift register 11 image display device 12 display unit 13 scanning signal line drive circuit 14 data signal line drive circuit 15 control circuit 16 pixel 17 shift register 21 switch means 22 p-type transistor (input stabilizing means)
23 set / reset type flip-flop 24 inverter 25-27 shift register

Claims (10)

A plurality of flip-flops to which a clock signal is input;
a plurality of switch means for controlling the input of the clock signal to the flip-flop of the (i + 1) -th stage by being turned on or off in accordance with the output signal of the flip-flop of the i-th (i is an arbitrary value) stage With
As the clock signal, M (M ≧ 2) types of clock signals are input to the plurality of flip-flops at intervals of (M−1).
When the switching means is turned on by the output signal of the i-th flip-flop, the clock signal is input to the (i + 1) -th flip-flop via the switching means, and the clock signal is supplied to the (i + 1) -th flip-flop. An output pulse with the same width as the pulse width of the signal is generated,
The plurality of stages of flip-flops are set / reset type flip-flops, and switch off an input of the switch means for controlling an input of the clock signal to the (i + k × M) -th stage (k ≧ 1). The shift register, wherein the output pulse generated by the replacement is input to a reset terminal of the flip-flop in the i-th stage. A plurality of flip-flops to which a clock signal is input;
a plurality of switch means for controlling the input of the clock signal to the flip-flop of the (i + 1) -th stage by being turned on or off in accordance with the output signal of the flip-flop of the i-th (i is an arbitrary value) stage With
When the switching means is turned on by the output signal of the i-th flip-flop, the clock signal is input to the (i + 1) -th flip-flop via the switching means, and the clock signal is supplied to the (i + 1) -th flip-flop. An output pulse with the same width as the pulse width of the signal is generated,
The plurality of flip-flops are set / reset flip-flops, and output signals of the (i + k × M) -th (k ≧ 1) flip-flop are supplied to a reset terminal of the i-th flip-flop. A shift register, which is inputted.   3. The shift register according to claim 1, wherein the M types of clock signals have phases such that their high-level periods do not overlap or phases of their low-level periods do not overlap. 4.   4. The shift register according to claim 3, wherein the duty ratio of each of the M types of clock signals is (100 × 1 / M)% or less.   5. The shift register according to claim 1, further comprising an input stabilizing unit configured to stabilize an input to the plurality of flip-flops when the switch unit is turned off. 6. . An inverter for inverting a clock signal selectively input by the switch means,
When the switch means is turned on by the output signal of the i-th flip-flop, the clock signal is input to the inverter via the switch means and output via the inverter, whereby the output pulse is output. The shift register according to claim 1, wherein the shift register is generated. A display portion including a plurality of pixels provided in a matrix, a data signal line driving circuit connected to a plurality of data signal lines and supplying video data to be written to the pixels to each data signal line, and a plurality of scanning signal lines A scanning signal line driving circuit that supplies a scanning signal for controlling the writing of the video data to the pixel to each scanning signal line.
7. An image display device comprising: the shift register according to claim 1 provided in at least one of the data signal line driving circuit and the scanning signal line driving circuit.   8. The image display device according to claim 7, wherein at least one of said data signal line driving circuit and said scanning signal line driving circuit is formed on a substrate on which said pixels are formed.   9. The image display device according to claim 7, wherein a switch element constituting at least one of the data signal line driving circuit and the scanning signal line driving circuit is a polycrystalline silicon thin film transistor. The image display device according to claim 9, wherein the switch element is formed at a temperature of 600 ° C. or less.

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